Open channel vector command execution

Abstract

The present invention provides a method and apparatus, which provide a solid-state drive controller, which is configured to analyze an input / output command from a host computing device to determine whether the command includes a vector or non-vector command, and is configured to generate multiple non-vector commands based on a physical address included in a vector command.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 16 / 459,183, filed on July 1, 2019, which is assigned to the assignee herein and is incorporated herein by reference in its entirety. Background Art Technical Field

[0003] Embodiments of the present disclosure are generally directed to systems and methods for executing vector commands on memory devices.

[0004] Description of Related Art

[0005] A solid-state drive (SSD) storage device is a data storage device that typically consists of a controller and SSD memory (e.g., non-volatile NAND flash memory). In all SSD storage devices, the controller sits between one or more host computing systems and the SSD memory. The SSD storage device interacts with the host using a flash translation layer (FTL).

[0006] Recently, a new class of SSDs has been developed, called open channel SSDs. Open channel SSDs differ from traditional SSDs in that they expose the internal mapping of the SSD memory structure to the host, allowing the host to perform data placement and data input / output (I / O) scheduling using physical addresses rather than traditional logical addresses. Therefore, open channel SSDs have the ability to leave certain aspects of the FTL for the host to handle. Additional commands such as vector commands can be used to enhance the functionality of the SSD as the host assumes additional responsibilities that exist once handed over to the storage device.

[0007] Therefore, as the demands on digital storage solutions continue to increase, new approaches are needed to support additional vector commands in order to not only meet the growing demands but also to improve and enhance the user experience. Summary of the invention

[0008] The present disclosure is generally directed to a method and apparatus that provides a solid-state drive controller that analyzes input / output commands from a host computing device to determine whether the commands include vector or non-vector commands and is configured to generate a plurality of non-vector commands based on physical addresses contained in vector commands.

[0009] In one embodiment, the present disclosure describes a device comprising a memory and a controller communicatively coupled to the memory, wherein the controller is configured to identify a set of physical addresses in a vector command obtained from a host computing device, wherein each physical address in the set of physical addresses corresponds to a location in the memory. In some embodiments, the controller is further configured to generate a set of non-vector commands, wherein each non-vector command in the set of non-vector commands corresponds to one of each physical address in the set of physical addresses. In some embodiments, the controller is further configured to execute the set of non-vector commands. In some embodiments, the controller is configured to generate a message indicating completion of the vector command to the host computing device in response to execution of the set of non-vector commands.

[0010] In another embodiment, the present disclosure describes a device that includes a memory and a controller communicatively coupled to the memory, wherein the controller is configured to receive an indication that the memory has executed a non-vector command, wherein the non-vector command is one of a plurality of non-vector commands corresponding to a vector command received from a host computing device. In some embodiments, the controller is further configured to determine whether the memory has executed all of the plurality of non-vector commands corresponding to the vector command. In some embodiments, the controller is further configured to generate a completion message indicating execution of the vector command if the memory has executed each of the plurality of non-vector commands. In some embodiments, the controller is further configured to transmit the completion message to the host computing device.

[0011] In another embodiment, the present disclosure describes an apparatus. In one example, the apparatus includes means for receiving a vector command from a host device, wherein the vector command includes a set of physical addresses. In another example, the apparatus includes means for generating a set of non-vector commands, wherein each non-vector command in the set of non-vector commands corresponds to one of each physical address in the set of physical addresses, and wherein each non-vector command in the set of non-vector commands is configured to be executed by an apparatus for storing digital data. In another example, the apparatus includes means for generating a message indicating completion of the vector command to a host computing device in response to execution of the non-vector command set by the apparatus for storing digital data. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Thus, a detailed understanding of the manner in which the above-described features of the present disclosure are understood, a more particular description of the present disclosure, the above brief overview, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0013] Figure 1 is a block diagram of a memory device communicatively coupled to a host computer system in accordance with certain aspects of the present disclosure.

[0014] Figure 2 is a block diagram illustrating a logical representation of the internal parallel organization of an open channel solid state drive (SSD) according to certain aspects of the present disclosure.

[0015] Figure 3 is a flow chart illustrating an exemplary process for executing vector commands in accordance with certain aspects of the present disclosure.

[0016] Figure 4 is a flow chart illustrating an example process for generating a vector command completion message in accordance with certain aspects of the present disclosure.

[0017] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0018] Hereinafter, reference is made to the embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the embodiments specifically described. On the contrary, any combination of the following features and elements (whether or not related to different embodiments) is considered to realize and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a specific advantage is achieved by a given embodiment is not a limitation to the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative, and are not considered to be elements or limitations of the appended claims, unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein, and should not be considered to be elements or limitations of the appended claims, unless explicitly stated in the claims.

[0019] The present disclosure relates to a method and apparatus that provide a solid-state drive controller that analyzes an input / output (I / O) command from a host computing device to determine whether the command includes a vector or non-vector command, and generates a plurality of non-vector commands based on a physical address contained in a vector command.

[0020] Figure 11 is a schematic diagram of one embodiment of a system 100 that includes a host computing system 102 communicatively coupled to a storage device 108. The storage device 108 includes a controller 110 and a non-volatile memory (NVM), such as a solid state drive (SSD) 134 comprised of one or more dies or planes of flash memory cells (e.g., single-level cells (SLC 136), multi-level cells (MLC), triple-level cells (TLC 138), etc.). The host 102 interfaces with the storage device 108 to issue I / O commands for memory operations at the SSD 134, including: read, write, copy, and reset (e.g., erase).

[0021] The storage device 108 may be an internal storage drive, such as a laptop hard drive or a desktop hard drive. The storage device 108 may be a removable mass storage device, such as, but not limited to, a handheld removable memory device, such as a memory card (e.g., a secure digital (SD) card, a micro secure digital (micro SD) card, or a multimedia card (MMC)) or a universal serial bus (USB) device. The storage device 108 may take the form of an embedded mass storage device (such as an eSD / eMMC embedded flash drive) embedded in the host 108. The storage device 108 may also be any other type of internal storage device, removable storage device, embedded storage device, external storage device, or network storage device.

[0022] Host 102 may include a wide variety of devices, such as computer servers, network attached storage (NAS) units, desktop computers, notebook (i.e., laptop) computers, tablet computers (i.e., "smart" tablets), set-top boxes, telephone handsets (i.e., "smart" phones), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, and automotive applications (i.e., mapping, autonomous driving). In certain embodiments, host 102 includes any device having a processing unit or any form of hardware capable of processing data, including a general-purpose processing unit, dedicated hardware (such as an application-specific integrated circuit (ASIC)), configurable hardware (such as a field programmable gate array (FPGA)), or any other form of processing unit configured by software instructions, microcode, or firmware.

[0023] In some configurations, the host 102 includes a central processing unit (CPU) 104 connected to a host memory 106, such as a DRAM or other main memory. Applications may be stored in the host memory 106 for execution by the CPU 104. For example, the host memory 106 may include a computer-readable medium storing computer-readable program code (e.g., software or firmware) that can be executed by the processor 104. The host 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flow charts.

[0024] The storage device 108 includes a physical (PHY) interface component 114 for entering communications from the host 102 to the storage device 108 and exiting communications from the storage device 108 to the host 102. The link between the storage device 108 and the host 102 may include any suitable link, such as a Peripheral Component Interconnect Express (PCIe) link. The PCIe link supports full-duplex communication between the storage device 108 and the host 102 via a dedicated unidirectional serial point-to-point connection or "channel". The PCIe link may include one to thirty-two channels, depending on the number of available PHYs 114 between the storage device 108 and the host 102.

[0025] The communication between the storage device 108 and the host 102 may be operated under a communication protocol such as a PCIe serial communication protocol or other suitable communication protocols. Other suitable communication protocols include Ethernet, Serial Attached SCSI (SAS), Serial AT Attachment (SATA), any protocol related to Remote Direct Memory Access (RDMA), such as Infiniband, iWARP or RDMA over Converged Ethernet (RoCE), and other suitable serial communication protocols. The storage device 108 may also be connected to the host 102 via a switch or bridge.

[0026] SSD 134 of storage device 108 may include non-volatile memory space configured for long-term storage of information after power on / off cycles. In some examples, SSD 134 may be composed of one or more dies or planes of NAND flash memory, electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and other solid-state memory.

[0027] The storage device 108 includes a controller 110 that manages the operation of the storage device 108, such as writing to and reading from the SSD 134. The controller 110 includes one or more processors 112, which may be multi-core processors. The processor 112 processes the components of the storage device 108 through firmware code.

[0028] The controller 110 may operate under the NVM Express (NVMe) protocol, but other protocols are also applicable. The NVMe protocol is a communication interface / protocol developed for SSDs to operate a host and a storage device linked through a PCIe interface (e.g., PHY 114). The NVMe protocol provides a command submission queue and a command completion queue for accessing data stored in the storage device 108 by the host 102. The storage device 108 may obtain, receive, or read the host 102 command from the command submission queue of the host queue stored in the host memory 106.

[0029] The controller 110 executes computer-readable program code (e.g., software and / or firmware) executable instructions (referred to herein as “instructions”). The instructions may be executed by various components of the controller 110, such as the processor 112, logic gates, switches, application specific integrated circuits (ASICs), programmable logic controllers, embedded microcontrollers, and other components of the controller 110.

[0030] The instructions are stored in a non-transitory computer-readable storage medium. In some embodiments, the instructions are stored in a non-transitory computer-readable storage medium of the storage device 108, such as in a read-only memory or in an SSD 134. The instructions stored in the storage device 108 can be executed without added input or instructions from the host 102. In other embodiments, the instructions are transmitted from the host 102. The controller 110 is configured with hardware and instructions to perform the various functions described herein and shown in the figures.

[0031] The storage device 102 may also include other components, such as a flash interface module 130, a direct memory access (DMA) module 126, a scheduler 128, a command executor 120, and a control path 124. The flash interface module 130 interacts with the SSD 134 for operations associated with various I / O commands for controlling and accessing an open channel SSD (e.g., SSD 134). The DMA module 126 is configured to control the actual data transfer between the host 102 and the storage device 108. The scheduler 128 is configured to activate and schedule the data transfer. Figure 1 . For example, the scheduler 128 controls data transfer, activates the control path 124 to obtain a physical page region (PRP), issues completion requests and interrupts, and activates DMA to perform actual data transfer between the host 102 and the storage device 108. The control path 124 is configured to transmit control information between the host 102 and the storage device 108, and provides completion requests to the vector completer 122. The command parser 118 is configured to parse and queue commands received from the vector command converter 116, and transmit the commands to the command executor 120. The command executor 120 is configured to arbitrate and execute commands received from the command parser 118.

[0032] The vector command converter 116 and the vector completer 122 may involve one or more of hardware, firmware, and / or software implementations on the device controller 110 for supporting vector type commands from the host 102. In some configurations, the vector command converter 116 monitors I / O commands received from the host 102. The vector command converter 116 may determine whether the I / O command is a vector command or a non-vector command. For example, the vector command converter 116 may identify the I / O command as a vector command based on whether the I / O command includes an additional field containing a list of scatter-gather logic block addresses. If the I / O command is not a vector command (e.g., does not contain a list of scatter-gather logic block addresses), the non-vector I / O command is transmitted to the command parser for execution. Otherwise, the vector command converter 116 obtains metadata for the vector command via the control path 124 and temporarily stops obtaining new commands from the host 102.

[0033] In some configurations, the vector command converter 116 generates multiple non-vector I / O commands based on a single vector command. In some cases, the entire set of multiple non-vector I / O commands is logically equivalent to a single vector command. In some examples, multiple non-vector I / O commands are generated by converting the pointer contained in the vector command into a physical address and generating a non-vector I / O command for each physical address. The vector command converter 116 can then queue the non-vector I / O command in the command parser 118 for execution. Once the non-vector I / O command is queued, the device controller 110 can resume acquiring new I / O commands from the host 102. As used herein, a vector command can be a list or set of commands generated by the host 102. Multiple physical addresses can be assigned to each vector command to specify multiple memory locations in the SSD. In some configurations, the vector command may include a pointer to metadata stored on the host memory 106. In this configuration, the metadata contains a list of physical addresses for accessing the SSD134.

[0034] In some configurations, the vector completer 122 collects all completion messages associated with the plurality of non-vector I / O commands generated by the vector command converter 116. Initially, the collected completion messages will not be provided to the host 102. Instead, once all completion messages associated with the plurality of non-vector I / O commands are received, the vector completer 122 generates a vector command completion message based on the contents of all completion requests associated with the plurality of non-vector I / O commands. That is, the vector command completion message is an indication that the vector command received from the host 102 and converted to the plurality of non-vector I / O commands has been completed. The vector completer 122 then provides the vector command completion message to the host 102.

[0035] In some configurations, the device controller 110 is responsible for processing I / O commands (including vector commands) received from the host 102, ensuring data integrity and valid storage, and managing the SSD 134. To perform these tasks, the controller 110 runs a flash translation layer (FTL) firmware. The FTL tasks can be performed by one or more processors 112 using one or more of the aforementioned components. The FTL can also perform many other functions, including: error code correction (i.e., using redundant data or parity data to recover messages with errors); garbage collection (i.e., identifying expired data in SSD 134 memory blocks / invalidating the expired data to delete free space for future writes); scheduling (i.e., controlling the order in which I / O commands from the host 102 are executed); over-provisioning (i.e., reserving memory for maintaining write speed); and wear leveling (i.e., spreading writes across the blocks of the SSD 134 as evenly as possible to ensure that all blocks of the device wear out at a roughly similar rate).

[0036] However, in some configurations, the host 102 may be responsible for some or all of the FTL tasks. For example, the SSD 134 may include a physically addressable SSD, such as an open channel SSD. In such a configuration, the open channel SSD may expose the internal parallel organization of the SSD 134 to the host 102, so that the SSD 134 may be directly managed by the host 102.

[0037] Figure 2 2 is a block diagram showing a logical representation of the internal parallel organization of an open channel SSD 202. The logical structure of the SSD 202 is divided by one or more groups 204a-204n, parallel units 206a-206n (e.g., NAND dies or planes), and blocks 208a-208b containing one or more logic blocks (not shown). Within the parallel units 206a-206n, there is a set of blocks representing the linear range of the logic blocks. In some examples, the groups 204a-204n may refer to a shared bus or physical channel for transmitting I / O commands to the parallel units 206a-206n, and the parallel units 206a-206n may refer to one or more NAND flash memory devices on the shared bus. In some examples, the blocks 208a-208b are the smallest addressable units for reading and writing, and the logic blocks are the smallest erasable units.

[0038] In some configurations, the host 102 is responsible for various aspects of the FTL. Therefore, the open channel SSD 202 may not receive instructions based on logical addresses from the host 102. Instead, the host 102 may directly manage the physical addresses of the open channel SSD 202 where data is stored. In some configurations, the responsibilities of the host 102 include data placement and I / O scheduling. For example, the host 102 may use physical addressing to control data mapping, as well as generate mapping tables and other metadata.

[0039] Thus, the host 102 may issue an I / O command using a vector type command that includes an additional field configured to transmit a scatter-gather logical block address list. Using vector commands, the host 102 is able to access separate parallel units 206a-206n simultaneously using a single I / O command. However, not all storage devices are capable of supporting vector commands. For example, non-vector I / O commands from the host 102 are typically directed to a single NAND plane for each command, while vector commands may be directed to several NAND planes in parallel in a single I / O command. According to certain aspects of the present disclosure, minimal hardware, software, and / or firmware changes may be applied to the storage device to configure the device controller 110 to support vector commands issued by the host 102.

[0040] Figure 3 is a flow chart illustrating an exemplary process 300 for receiving and executing vector commands. The process 300 may be executed, for example, by a storage device (e.g., such as Figure 1 Process 300 may be implemented as a software and / or firmware component stored on a memory device and executed on one or more processors (e.g., Figure 1 In addition, the system can be executed and run on the processor 112 of the system. ... Figure 1 's PHY 114) to enable transmission and reception of signals by the storage device 108 in the exemplary process 300.

[0041] At block 310, the storage device 108 receives a host I / O command. For example, the device controller 110 of the storage device 108 may receive the I / O command from the host 102 via the PHY 114 interface. In some configurations, the device controller 110 includes a command register that includes a plurality (e.g., 64, 256, 512, etc.) of 1-bit time slots. The device controller 110 may regulate the receipt of the I / O command from the host 102 based on whether the command register has any available time slots (e.g., time slots with binary "0").

[0042] For example, the device controller 110 may set one of the command register slots (e.g., with a binary "1") for each command received from the host 102. Thus, if a bit is set, the corresponding slot has the I / O command associated with that bit received by the device controller 110. If a bit is available, the slot is empty and the device controller 110 is available for a new command.

[0043] In some configurations, the processor 112 may determine whether the command register contains any available time slots before the device controller 110 retrieves a new I / O command. For example, the processor 112 may utilize a bitmap vector stored in the device controller 110 to determine whether the command register time slots are set before continuing to retrieve I / O commands from the host 102.

[0044] Therefore, in some configurations, the device controller 110 determines whether the command register contains at least one available time slot before retrieving an I / O command from the host 102. Once the device controller 110 determines that a time slot is available, the device controller 110 retrieves the I / O command and proceeds to set the available time slot. If the device controller 110 determines that there is no available time slot, the device controller 110 may disable retrieving I / O commands from the host 102 until a time slot becomes available.

[0045] At block 320, the device controller 110 determines whether the acquired I / O command is a vector command. If the I / O command is not a vector command, the process 300 moves to block 330, and the device controller 110 queues the command to the command parser 118 for execution. If the I / O command is a vector command, the process 300 moves to block 340, in which the device controller 110 determines the number of physical addresses contained in the vector command and sets the number of command time slots to be equal to or less than the number of physical addresses. For example, if there are fewer available time slots in the command register than the physical addresses contained in the vector command, the vector command converter 116 will continue to generate a number of non-vector I / O commands from the vector command that is only equal to the number of time slots, and the remaining non-vector I / O commands will be generated when one or more time slots become available (e.g., after the command corresponding to one of the time slots is completed).

[0046] For example, if the SSD device can hold up to 64 I / O commands from the host 102, 64 command time slots are implemented in the command register of the device controller 110. If all 64 command time slots are set, the device controller 110 will stop fetching host commands until at least one outstanding I / O command is completed, thereby clearing the corresponding time slot.

[0047] Similarly, if the storage device 108 is in an idle state and there are no outstanding commands in the device controller 110, the command register is 0. If the device controller 110 fetches 16 non-vector I / O commands from the host 102, bits 0 to 15 in the command register are set to indicate that command slots 0 to 15 are occupied. However, if the device controller 110 fetches a single vector command containing 32 physical addresses, 32 non-vector I / O commands must be generated. At this time, the device controller 110 sets 32 command slots (e.g., slots 16 to 47 in the command register). In some configurations, the device controller 110 will stop fetching new I / O commands until the non-vector commands are generated and queued for execution. In other configurations, the device controller 110 may continue to fetch up to 16 more commands based on command slot availability.

[0048] For example, if the device controller 110 acquires 15 new non-vector commands and 1 vector command from the host 102, and the vector command contains 21 physical addresses, the device controller sets the remaining 16 command time slots (i.e., 15 time slots for non-vector commands and 1 time slot for vector commands) and generates only one non-vector command corresponding to one of the physical addresses in the vector command. The device controller then stops acquiring I / O commands from the host 102 and waits until time slots become available before generating additional non-vector commands corresponding to the remaining 20 physical addresses in the vector command.

[0049] Thus, the device controller 110 may stop fetching additional I / O commands from the host 102 until a time slot in the command register has been set for each physical address included in the vector command and the command register contains an available time slot. In other configurations, if the command register does not contain an available time slot, the device controller 110 may continue to fetch new commands from the host 102, but will take into account the number of I / O commands to be generated. For example, the device controller 110 may continue to fetch new commands, identify the number of physical addresses in each command, and queue the vector command converter 116 to generate multiple I / O commands based on the vector commands as time slots become available.

[0050] At block 350, the device controller 110 obtains metadata for the vector command from the host 102. In some configurations, the metadata contains information needed to generate multiple I / O commands. For example, the metadata may include a list of physical addresses corresponding to pointers included in the vector command. In another example, the metadata may include pointers represented by physical region pages (PRPs) or scatter-gather lists (SGLs) according to the NVMe standard. The storage device obtains the pointers and may manipulate them in order to construct pointers for each non-vector command.

[0051] At block 360, the vector command converter 116 generates a plurality of non-vector I / O commands based on the vector command obtained from the host 102. In some configurations, the vector command converter 116 generates each of the non-vector I / O commands by appending one of the physical addresses of the vector command to each non-vector command. Thus, the plurality of non-vector I / O commands are equivalent to the original vector command.

[0052] In some configurations, a plurality of non-vector I / O commands are generated in an order according to metadata provided by the host 102. For example, the device controller 110 may obtain metadata from the host 102. In some examples, the metadata includes a list of physical addresses. Thus, the non-vector I / O commands may be generated sequentially in the order of the addresses on the list. In other configurations, the non-vector I / O commands are generated according to the structure and / or resource availability of the storage device. For example, the vector command converter 116 may generate the non-vector I / O commands in a priority order, where physical addresses associated with available parallel units are given a higher priority than physical addresses associated with busy parallel units. In this configuration, the quality of service and efficiency of the storage device 108 are improved.

[0053] At block 370 , the vector command converter 116 sends the plurality of non-vector commands to the command parser 118 to be queued for execution.

[0054] Figure 4 4 is a flow chart illustrating an exemplary process 400 for generating and sending command completions. Process 400 may be performed, for example, by a storage device (e.g., such as Figure 1 Process 400 may be implemented as a software and / or firmware component stored on a memory device and executed on one or more processors (e.g., Figure 1 In addition, the system can be executed and run on the processor 112 of the system. ... Figure 1 's PHY 114) to enable transmission and reception of signals by the storage device 108 in the exemplary process 400.

[0055] At block 410 , the vector completer 122 receives a completion request. In some configurations, the completion request is generated by the flash interface module 130 and communicated to the vector completer 122 via the control path 124 .

[0056] At step 420, vector completer 122 identifies whether the completion request corresponds to an independent non-vector I / O command or to one of a plurality of non-vector commands that are derived from a vector command. If the completion request corresponds to an independent non-vector I / O command, process 400 moves to block 430 where vector completer 122 generates a completion message and provides the completion message to host 102.

[0057] At step 420, if the vector completer 122 determines that the completion request corresponds to one of a plurality of non-vector commands that are derived from the vector command, then the process 400 moves to step 440, where the vector completer 122 determines whether the received completion request is the last request for the vector command. For example, the vector completer 122 may be configured to collect all completion requests associated with a particular vector command. If the received completion request is not the last request (i.e., the vector completer 122 has not yet collected all completion requests associated with each physical address of the vector command), then the process 400 moves to block 450, where the vector completer 122 holds the received completion request and waits until it receives the last completion request for the vector command.

[0058] At step 440 , if vector completer 122 determines that the received completion request is the last request for a vector command, process 400 moves to block 460 where vector completer 122 generates a vector command completion message based on all received completion requests associated with the vector command.

[0059] At block 470 , vector completer 122 clears all received completion requests associated with the vector command.

[0060] In summary, the present disclosure as a whole relates to systems, methods, and apparatus for receiving vectored I / O commands from a host 102 and executing the vectored commands on an open channel SSD (e.g., SSD 134) with minimal changes to the storage device 108. In particular, certain aspects of the present disclosure relate to methods and apparatus for supporting vectored commands so that the vectored commands are processed transparently to several components of the host 102 and the storage device 108. For example, the vector command converter 116 may be configured to generate multiple non-vectored I / O commands from a single vectored command and pass the multiple non-vectored I / O commands to other components of the storage device 108 for execution. In addition, the vector completer 122 may generate a vectored command completion message based on the completion of the multiple non-vectored I / O commands and pass the completion message to the host 102. Here, no indication of how to process the vectored commands may be provided to the host 102.

[0061] In some examples, the generation of multiple non-vector I / O commands from a single vector command by vector command converter 116 provides device controller 110 with the ability to intelligently schedule multiple non-vector I / O commands to improve the efficiency of storage device 108. In one example, vector command converter 116 can generate non-vector I / O commands in a priority order, where physical addresses associated with available parallel units receive a higher priority than physical addresses associated with busy parallel units. In this configuration, the quality of service and efficiency of storage device 108 are improved.

[0062] In one non-limiting embodiment, a device is disclosed, wherein the device includes a memory and a controller communicatively coupled to the memory. In some configurations, the controller is configured to identify a set of physical addresses in a vector command obtained from a host computing device, wherein each physical address in the set of physical addresses corresponds to a location in the memory. In some configurations, the controller is configured to generate a set of non-vector commands, wherein each non-vector command in the set of non-vector commands corresponds to one of each physical address in the set of physical addresses. In some configurations, the controller is configured to execute the set of non-vector commands. In some configurations, the controller is configured to generate a message to the host computing device indicating completion of the vector command in response to execution of the set of non-vector commands.

[0063] In one non-limiting embodiment, the controller is further configured to fetch a command from the host computing device and determine that the fetched command is a vector command, wherein the determination is based on whether the fetched command includes a field configured to convey a scatter-gather logic block address list.

[0064] In one non-limiting embodiment, the controller is further configured to obtain metadata from the host computing device, wherein the metadata includes a list of physical addresses.

[0065] In one non-limiting embodiment, the vector command includes a pointer configured to identify a set of physical addresses in a list of physical addresses in the metadata.

[0066] In one non-limiting embodiment, the set of physical addresses includes two or more physical addresses,

[0067] In one non-limiting embodiment, the controller includes a command register including a plurality of 1-bit time slots, wherein the controller is further configured to determine whether the command register includes an available time slot, and to retrieve a command from the host computing device if the command register includes an available time slot.

[0068] In one non-limiting embodiment, the controller is further configured to execute a non-vector command from the set of non-vector commands for each available time slot in the command register.

[0069] In one non-limiting embodiment, the memory comprises an open channel solid state drive (SSD) memory device.

[0070] In one non-limiting embodiment, a device is disclosed, wherein the device includes a memory and a controller communicatively coupled to the memory. In some configurations, the controller is configured to receive an indication that the memory has executed a non-vector command, wherein the non-vector command is one of a plurality of non-vector commands corresponding to a vector command received from a host computing device. In some configurations, the controller is configured to determine whether the memory has executed all of the plurality of non-vector commands corresponding to the vector command. In some configurations, the controller is configured to generate a completion message indicating execution of the vector command if the memory has executed each of the plurality of non-vector commands. In some additional configurations, the controller is configured to transmit the completion message to the host computing device.

[0071] In one non-limiting embodiment, the controller is further configured to store an indication that the memory has executed the non-vector command if the memory has not executed all of the plurality of non-vector commands corresponding to the vector command.

[0072] In one non-limiting embodiment, the controller is further configured to receive a plurality of indications that the memory has executed non-vector commands, wherein each indication in the plurality of indications corresponds to a non-vector command in the plurality of non-vector commands. In some configurations, the controller is configured to store the plurality of indications. In some configurations, the controller is configured to clear the stored plurality of indications after the completion message is transmitted to the host computing device.

[0073] In one non-limiting embodiment, each non-vector command in the plurality of non-vector commands includes a physical address in the plurality of physical addresses included in the vector command.

[0074] In one non-limiting embodiment, each of the physical addresses corresponds to a location in memory.

[0075] In one non-limiting embodiment, each non-vector command of the plurality of non-vector commands is configured to be executed by the memory in a sequential order.

[0076] In one non-limiting embodiment, each non-vector command of the plurality of non-vector commands shares at least one of a write, read, copy, or reset command with the vector command.

[0077] In one non-limiting embodiment, the memory comprises an open channel non-volatile memory.

[0078] In one non-limiting embodiment, an apparatus is disclosed. In some configurations, the apparatus includes means for receiving a vector command from a host device, wherein the vector command includes a set of physical addresses. In some configurations, the apparatus includes means for generating a set of non-vector commands, wherein each non-vector command in the set of non-vector commands corresponds to one of each of the physical addresses in the set of physical addresses, and wherein each non-vector command in the set of non-vector commands is configured to be executed by a means for storing digital data. In some configurations, the apparatus includes means for generating a message to a host computing device indicating completion of the vector command in response to execution of the non-vector command set by the means for storing digital data.

[0079] In one non-limiting embodiment, the apparatus includes means for obtaining metadata from a host computing device, wherein the metadata includes a list of physical addresses, and wherein the vector command includes a pointer configured to identify a set of physical addresses in the list of physical addresses in the metadata.

[0080] In one non-limiting embodiment, the apparatus includes means for determining whether a command register contains an available time slot, wherein the command register includes a plurality of 1-bit time slots. In some configurations, the apparatus includes means for obtaining a command from a host computing device if the command register contains an available time slot.

[0081] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be envisaged without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A device for executing a vector command, the device comprising: Memory; and a controller communicatively coupled to the memory, wherein the controller is configured to: Obtaining commands from a host computing device; determining that the acquired command is a vector command, wherein the determination is based on whether the acquired command includes a field configured to convey a scatter-gather logic block address list; identifying a set of physical addresses in the vector command obtained from the host computing device, wherein each physical address in the set of physical addresses corresponds to a location in the memory; generating a non-vector command set, wherein each non-vector command in the non-vector command set corresponds to a physical address in each of the physical addresses in the physical address set; executing the set of non-vector commands; and A message is generated to the host computing device in response to execution of the set of non-vector commands indicating completion of the vector commands.

2. The apparatus of claim 1, wherein each non-vector command in the set of non-vector commands shares at least one of a write, read, copy, or reset command with the vector command.

3. A device for executing a vector command, the device comprising: Memory; and a controller communicatively coupled to the memory, wherein the controller is configured to: obtaining metadata from a host computing device, wherein the metadata includes a list of physical addresses; identifying a set of physical addresses in a vector command obtained from the host computing device, wherein each physical address in the set of physical addresses corresponds to a location in the memory; generating a non-vector command set, wherein each non-vector command in the non-vector command set corresponds to a physical address in each of the physical addresses in the physical address set; executing the set of non-vector commands; and A message is generated to the host computing device in response to execution of the set of non-vector commands indicating completion of the vector commands. 4 . The apparatus of claim 3 , wherein the vector command comprises a pointer configured to identify the set of physical addresses in the list of physical addresses in the metadata. The apparatus of claim 3 , wherein the set of physical addresses comprises two or more physical addresses.

6. A device for executing a vector command, the device comprising: Memory; A command register containing multiple 1-bit time slots; as well as a controller communicatively coupled to the memory and the command register, wherein the controller is configured to: determining whether the command register contains an available time slot; if the command register contains the available time slot, obtaining a command from a host computing device; identifying a set of physical addresses in a vector command obtained from the host computing device, wherein each physical address in the set of physical addresses corresponds to a location in the memory; generating a non-vector command set, wherein each non-vector command in the non-vector command set corresponds to a physical address in each of the physical addresses in the physical address set; executing the set of non-vector commands; and A message is generated to the host computing device in response to execution of the set of non-vector commands indicating completion of the vector commands. 7 . The apparatus of claim 6 , wherein the controller is further configured to execute one non-vector command from the set of non-vector commands for each available time slot in the command register.

8. The device of claim 6, wherein the memory comprises an open channel solid state drive memory device (open channel SSD memory device).

9. A device for executing a vector command, the device comprising: Memory; and a controller communicatively coupled to the memory, wherein the controller is configured to: receiving an indication that the memory has executed a non-vector command, wherein the non-vector command is one of a plurality of non-vector commands corresponding to a vector command received from a host computing device; determining whether the memory has executed all of the plurality of non-vector commands corresponding to the vector command; storing the indication that the memory has executed the non-vector commands if the memory has not executed all of the plurality of non-vector commands corresponding to the vector commands; if the memory has executed each of the plurality of non-vector commands, generating a completion message indicating execution of the vector commands; and transmitting the completion message to the host computing device; The vector command includes a set of physical addresses, each physical address in the set of physical addresses corresponds to a location in the memory, and each non-vector command in the plurality of non-vector commands corresponds to one of the physical addresses in the set of physical addresses.

10. The apparatus of claim 9, wherein each non-vector command of the plurality of non-vector commands shares at least one of a write, read, copy, or reset command with the vector command.

11. The apparatus of claim 9, wherein the memory comprises an open channel non-volatile memory.

12. A device for executing a vector command, the device comprising: Memory; and a controller communicatively coupled to the memory, wherein the controller is configured to: receiving an indication that the memory has executed a non-vector command, wherein the non-vector command is one of a plurality of non-vector commands corresponding to a vector command received from a host computing device; receiving a plurality of indications that the memory has executed non-vector commands, wherein each indication of the plurality of indications corresponds to a non-vector command of the plurality of non-vector commands; storing the plurality of indications; determining whether the memory has executed all of the plurality of non-vector commands corresponding to the vector command; if the memory has executed each of the plurality of non-vector commands, generating a completion message indicating execution of the vector commands; transmitting the completion message to the host computing device; and clearing the stored plurality of indications after the completion message is transmitted to the host computing device; The vector command includes a set of physical addresses, each physical address in the set of physical addresses corresponds to a location in the memory, and each non-vector command in the plurality of non-vector commands corresponds to one of the physical addresses in the set of physical addresses. 13 . The apparatus of claim 12 , wherein the controller is further configured to hold completion requests until all requests in the vector command have been completed.

14. The apparatus of claim 12, wherein each non-vector command of the plurality of non-vector commands is configured to be executed by the memory in a sequential order.

15. An apparatus for executing a vector command, comprising: means for receiving a vector command from a host computing device, wherein the vector command comprises a set of physical addresses; means for obtaining metadata from the host computing device, wherein the metadata comprises a list of physical addresses, and wherein the vector command comprises a pointer configured to identify the set of physical addresses in the list of physical addresses in the metadata; means for generating a non-vector command set, wherein each non-vector command in the non-vector command set corresponds to one of each of the physical addresses in the set of physical addresses, and wherein each non-vector command in the non-vector command set is configured to be executed by means for storing digital data; as well as Means for generating a message to the host computing device indicating completion of the vector commands in response to execution of the set of non-vector commands by the means for storing digital data.

16. An apparatus for executing a vector command, comprising: means for determining whether a command register contains an available time slot, wherein the command register comprises a plurality of 1-bit time slots; means for obtaining a command from a host computing device if said command register contains said available time slot; means for receiving a vector command from a host computing device, wherein the vector command comprises a set of physical addresses; means for generating a non-vector command set, wherein each non-vector command in the non-vector command set corresponds to one of each of the physical addresses in the set of physical addresses, and wherein each non-vector command in the non-vector command set is configured to be executed by means for storing digital data; as well as Means for generating a message to the host computing device indicating completion of the vector commands in response to execution of the set of non-vector commands by the means for storing digital data.

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