Fan-out package with recesses

Abstract

A system to integrate a fan-out package including a first semiconductor die (120) with a second semiconductor die (110). In some embodiments, the fan-out package includes a first semiconductor die (120), a molding compound (305) covering the first semiconductor die on at least two sides, and electrical contacts on a lower surface of the first semiconductor die. The fan-out package can have a notch (315) along a portion of a lower edge of the fan-out package.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Provisional Application No. 62 / 770,500, filed November 21, 2018, entitled “FAN-OUT PACKAGE WITH RABBET,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more aspects of the embodiments of this disclosure relate to packaging, and more specifically to fan-out packages with slots. Background Technology

[0004] In applications that connect optoelectronic devices to electronic integrated circuits, especially in high-speed applications, it can be advantageous to position the components close together to minimize the electrical paths between them. This can be challenging, for example, if the package of the electronic integrated circuit has a much larger envelope than the die itself, and if there is potential mechanical interference between the optoelectronic device and the package of the electronic integrated circuit.

[0005] Therefore, there is a need for improved systems and methods for integrating optoelectronic devices and electronic integrated circuits. Summary of the Invention

[0006] According to an embodiment of the present invention, a system is provided comprising: a fan-out package including: a first semiconductor die; a molding compound covering the first semiconductor die on at least two sides; and electrical contacts on a lower surface of the first semiconductor die, the fan-out package having a notch along a portion of a lower edge of the fan-out package.

[0007] In some implementations, the vertical depth of the slot is between 10 micrometers and 500 micrometers.

[0008] In some implementations, the horizontal depth of the slot is between 10 micrometers and 500 micrometers.

[0009] In some embodiments, the fan-out package further includes a redistribution layer on the lower surface of the fan-out package.

[0010] In some implementations, a portion of the vertical surface of the slot is the edge surface of the redistribution layer.

[0011] In some implementations, the notch does not extend into the first semiconductor die.

[0012] In some embodiments, the system further comprises: a second semiconductor die; and a shared support element to which both the second semiconductor die and the fan-out package are fixed to an upper surface of the shared support element.

[0013] In some embodiments, the system further comprises a conductive path between the first semiconductor die and the second semiconductor die, a length of the conductive path being less than 200 microns.

[0014] In some embodiments, a gap between the second semiconductor die and the fan-out package is at least 2 microns.

[0015] In some embodiments, a gap between the second semiconductor die and the fan-out package is at most 100 microns.

[0016] In some embodiments, an upper edge of the second semiconductor die extends into the notch.

[0017] In some embodiments, the system further comprises a layer of underfill between the fan-out package and the shared support element, the layer of underfill extending horizontally to the second semiconductor die.

[0018] In some embodiments, the underfill does not extend further from the fan-out package than a portion of the second semiconductor die that is furthest from the fan-out package.

[0019] According to embodiments of the present invention, there is provided a method for manufacturing a fan-out package, the method comprising: manufacturing a carrier, the carrier comprising: a layer of molding compound; a plurality of semiconductor dies embedded in the molding compound; and a redistribution layer on the semiconductor dies and the molding compound; cutting a first channel in the carrier, the first channel having a first width and a first depth and extending between a first semiconductor die of the plurality of semiconductor dies and a second semiconductor die of the plurality of semiconductor dies; and cutting a second channel in the carrier within the first channel, the second channel having a second width that is less than the first width and a second depth that is greater than the first depth from an upper surface of the carrier.

[0020] In some embodiments, a depth of the second channel is equal to a thickness of the carrier and is used to separate a portion of the carrier on one side of the second channel from a portion of the carrier on another side of the second channel.

[0021] In some embodiments, a width of the first channel exceeds a width of the second channel by between 30 microns and 100 microns.

[0022] In some implementations, the depth of the first channel is between 30 micrometers and 100 micrometers.

[0023] In some embodiments, the method further includes: cutting a plurality of channels in the carrier to form a plurality of fan-out packages, the plurality of channels including the first channel and the second channel; forming a sub-assembly by: securing a first fan-out package of the plurality of fan-out packages to a shared support element; and securing a third semiconductor die to the shared support element, the sub-assembly including a conductive path between the first semiconductor die and the third semiconductor die, the conductive path having a length of less than 200 micrometers.

[0024] In some embodiments, the method further includes: distributing underfill between the first fan-out package and the shared support element; and blocking the underfill through the third semiconductor die during the distribution. Attached Figure Description

[0025] These and other features and advantages of this disclosure will be understood and appreciated by referring to the specification, claims and drawings, in which:

[0026] Figure 1 This is a side cross-sectional view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0027] Figure 2A This is a side cross-sectional view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0028] Figure 2B This is a side cross-sectional view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0029] Figure 2C This is a side cross-sectional view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0030] Figure 3 This is a side cross-sectional view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0031] Figure 4A This is a top view of a carrier having multiple semiconductor dies according to an embodiment of this disclosure;

[0032] Figure 4B This is a top view of a portion of a carrier having multiple semiconductor dies according to an embodiment of this disclosure;

[0033] Figure 4CThis is a bottom view of a fan-out package according to an embodiment of this disclosure;

[0034] Figure 5A This is a side cross-sectional view of the carrier according to the embodiments of this disclosure;

[0035] Figure 5B This is a side cross-sectional view of the carrier according to the embodiments of this disclosure;

[0036] Figure 5C This is a side cross-sectional view of the carrier according to the embodiments of this disclosure;

[0037] Figure 6A This is a perspective view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0038] Figure 6B This is a side cross-sectional view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0039] Figure 6C This is a top view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0040] Figure 7 This is a perspective view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0041] Figure 8 This is a perspective view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0042] Figure 9 This is a side view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure;

[0043] Figure 10 This is a side view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure; and

[0044] Figure 11 This is a perspective view of a fan-out package and a semiconductor die on a shared support element according to an embodiment of this disclosure. Detailed Implementation

[0045] The detailed description set forth below with reference to the accompanying drawings is intended as a description of an exemplary embodiment of a fan-out package with a slot provided according to this disclosure, and is not intended to represent the only form in which this disclosure may be constructed or utilized. This description, in conjunction with the illustrated embodiments, illustrates the features of this disclosure. However, it should be understood that the same or equivalent functions and structures may be implemented by different embodiments, which are also intended to be included within the scope of this disclosure. As indicated elsewhere herein, similar element numbers are intended to indicate similar elements or features.

[0046] refer to Figure 1 In a sub-assembly including a fan-out package 105 (which may include a first semiconductor die 120, e.g., a silicon CMOS chip) and a second semiconductor die 110 (e.g., an optoelectronic device, such as an electro-absorption modulator (EAM), a laser, or a photodetector) on a shared support element 115 or "bottom wafer" (e.g., a substrate or another semiconductor die, such as a photonic integrated optical path (PIC)) on a fan-out package 105, such as a fan-out package 105, the conductive path between the second semiconductor die 110 and the first semiconductor die 120 (e.g., a CMOS chip) in the fan-out package 105 is such that ... Figure 1 Minimizing the length (as indicated by the arrow in the image) can be advantageous. Such minimization can improve characteristic impedance, delay, electromagnetic interference (EMI), and electromagnetic compatibility (EMC). Figure 2A As shown, a large gap between the second semiconductor die 110 and the fan-out package 105 may be disadvantageous, as it could result in a long conductive path between the second semiconductor die 110 and the first semiconductor die 120 in the fan-out package 105.

[0047] Horizontally moving one or both of the second semiconductor die 110 and the fan-out package 105 to reduce the spacing between them can reduce the length of the conductive path, but (i) if the spacing is too small (e.g., less than 50 micrometers or comparable to part placement accuracy or package size tolerances), occasional contact between the parts may lead to a decrease in yield; and (ii) if sufficient spacing is maintained to avoid a decrease in yield, the length of the conductive path may remain undesirably large. Figure 2CAs shown, a fan-out package 105 can be suspended above the second semiconductor die 110. However, this configuration may require significant thinning of the second semiconductor die 110 or the high copper pillar bump 210, or both. Either of these can present manufacturing challenges and potentially lead to reduced yield. In particular, high aspect ratio (> 1:1) copper pillar bumps may be difficult to manufacture, and high copper pillar bumps (e.g., above 100 micrometers) may require a pitch greater than 150 micrometers (while system requirements may dictate a pitch of 100 micrometers or less). Thinning the second semiconductor die 110 to less than 50 micrometers can result in reduced yield, and using copper pillar bumps less than 50 micrometers from the edge of the package can also lead to reduced yield. Underfill (UF) overflow (or “bleed-out”) (discussed in further detail below) can cause III-V performance degradation.

[0048] refer to Figure 3 In some embodiments, in addition to the first semiconductor die 120, the fan-out package 105 also includes a molding compound 305 (e.g., epoxy molding compound (EMC)) and a redistribution layer (RDL) 310. A notch or notch 315 is cut into the lower edge of the fan-out package 105 to allow a portion of the fan-out package 105 to hang over the second semiconductor die 110 without using high copper pillar bumps. As a result, as shown, a portion of the molding compound 305 can be cantilevered over the second semiconductor die 110 (i.e., it can hang over the second semiconductor die 110). Solder connections 320 can be used to attach each copper pillar bump (CPB) to a metal mold in a shared support element 115. Similarly, standard soldering methods can be used to flip-chip bond the EAM to the support element 115. Figure 3 The second semiconductor die 110 of the embodiment can effectively act as a bottom filler dam (discussed in further detail below) because it can be more efficient than... Figure 2C The die shown is thicker and... Figure 2A and Figure 2B Compared to the die shown (“EAM” die), it also allows for a smaller bottom filler barrier zone (KOZ) because... Figure 3 The second semiconductor die 110 of the embodiment can be able to precisely block the bottom filler near the slot opening. Improved blocking of the bottom filler can reduce or prevent performance degradation of the second semiconductor die 110 due to leakage. The edge of the barrier area can be blocked by... Figure 3 The right edge of the second semiconductor die 110 in the middle is determined.

[0049] The molding compound 305 may include silica filler particles encapsulated in and bonded to the epoxy resin. The surface of the notch 315 may be rough and may have characteristics depending on the process used to form the notch 315. For example, if laser cutting is used, a rough surface may be formed above which some filler particles protrude above the surface of the epoxy resin, because the laser can have the effect of removing epoxy resin while leaving the filler particles undisturbed, except that the filler particles may also be removed if all or almost all of the epoxy resin binding any filler particles is removed. If a blade is used to form the notch, it may cut through some filler particles or tear some filler particles from the epoxy resin, thus leaving voids in the epoxy resin at the surface of the notch. In the terminology used herein, the surface of the notch is defined as a surface defining a volume into which no residual material of the molding compound 305 (i.e., neither epoxy resin nor silica filler) protrudes.

[0050] Figure 4A - Figure 4C The intermediate and final products during the manufacturing of the fan-out package 105 are shown. (Reference) Figure 4A Multiple first semiconductor dies 120 can be embedded in the molding compound 305 in a sheet 405. A redistribution layer (in...) Figure 4A - Figure 4C A carrier 410 is formed by depositing a transparent layer (shown in the figure, making the first semiconductor die 120 visible) onto a sheet 405 of molding compound 305 (and the first semiconductor die 120 embedded therein). In some embodiments, the carrier is square or rectangular, rather than circular as shown. Reference Figure 4B Multiple wide shallow channels 415 are formed in the top surface of the carrier (e.g., by laser ablation or sawing), and then multiple narrow deep channels 420 are formed in the wide shallow channels 415 (e.g., by laser cutting or blade cutting). The narrow deep channels 420 may extend all the way through the carrier to cut it into individual packages (or they may extend almost all the way through so that the packages can then be easily separated). Figure 4C The resulting fan-out package 105 is shown, which has a cantilevered position in the final assembly ( Figure 3 The EMC region 425 and the region 430, which are covered by the redistribution layer 310, are respectively located in the carrier 410. In this process, the top surface of the so-called carrier 410 becomes the bottom surface of the so-called fan-out package 105. Figure 5A A side cross-sectional view of the carrier 410 is shown; Figure 5B The carrier 410 is shown after the wide, shallow channel 415 has been cut, and Figure 5C The carrier 410 is shown after the narrow deep channel 420 has also been cut. Figure 5A - Figure 5CIn one embodiment, the conductors on the top surface of the carrier 410 (which form conductors on the bottom surface of the fan-out package 105 and are subsequently used to form a connection with the shared support element 115) are microbumps, which may be made of, for example, copper, solder, nickel or gold.

[0051] Figure 6A A perspective view of a subassembly including a fan-out package 105 and a second semiconductor die 110 on a shared support element 115 is shown. Figure 6B A side view of the subassembly is shown, in which underfill (UF) is applied to the gap between the fan-out package 105 and the shared support element 115. The underfill material may be NCP (non-conductive adhesive) or NCF (non-conductive film). The fan-out package 105 may be attached to the shared support element 115 using thermocompression bonding (TCB). The assembly process may include applying, for example, non-conductive adhesive to the fan-out package 105 or the shared support element 115, placing the fan-out package 105 onto the shared support element 115 (e.g., using a pick-and-place process), and using thermocompression bonding to attach copper or gold pillar bumps (located on the bottom surface of the fan-out package 105) to the shared support element 115. The thermocompression process may provide localized heating, which may also cure the non-conductive adhesive (or non-conductive film).

[0052] refer to Figure 6C In this process, in the fan-out type package 105 (in Figure 6C A second semiconductor die 110 exists at the edge (and extending into its slot 315) of the die marked "FOWLP". Figure 6CThe presence of the second semiconductor die 110 (referred to as "die 1") can be advantageous because it can act as a dam to limit the leakage of the bottom filler. Initially, after the fan-out package 105 is placed on the shared support element 115 and before heat is applied (as part of a thermoforming process), the presence of the second semiconductor die 110 can act as a dam to reduce the rate at which, for example, non-conductive adhesive flows out from under the fan-out package 105. Furthermore, once heat is applied and the temperature of the non-conductive adhesive rises, the viscosity of the non-conductive adhesive increases as it begins to cure, further slowing its flow out from under the fan-out package 105 and its dispersion away from the fan-out package 105. In systems where the second semiconductor die 110 is farther from or completely absent from the fan-out package 105, the non-conductive adhesive can flow out more rapidly from under the fan-out package 105 before heat is applied, and this portion of the non-conductive adhesive flowing out from under the fan-out package 105 before heat is applied can remain relatively cool after heat is applied, thus keeping its viscosity low and allowing it to spread over a larger area. If the top surface of the shared support element 115 is a surface where the non-conductive adhesive is easily wetted, the surface tension of the non-conductive adhesive can also accelerate its spread on the shared support element 115. In some embodiments, the underfill may not extend further from the fan-out package 105 than any of the distal edges of the second semiconductor die 110, such as... Figure 6C As shown, the dotted area represents the underfill. Limiting the underfill to extend beyond the fan-out package 105 may be advantageous because the underfill may shrink upon cooling, potentially adversely affecting certain components that are sensitive to the stresses exerted by the underfill during shrinkage.

[0053] In one implementation scheme Figure 7 - Figure 11 This is an additional perspective and side view of the sub-assembly including the fan-out package 105 and the second semiconductor die 110 on the shared support element 115. For one embodiment, Figure 7 - Figure 11 Each one in the image is drawn to scale. Figure 7 - Figure 11 Each scaling bar in the table indicates the scale used. It should be understood that the scale can be changed. Figure 7 - Figure 11 The dimensions and relative dimensions shown (e.g., the vertical and horizontal depths of the slot, the gap between the slot and the surface of the second semiconductor die 110, etc.) can be increased or decreased by up to two times (i.e., the value of the change factor is between 0.50 and 2.00) while retaining some or all of the benefits of the illustrated embodiment.

[0054] Some implementations can achieve high-speed signaling of 100 Gbps / ch or even higher while mitigating current packaging technology challenges. Process challenges such as thinning the second semiconductor die 110, manufacturing high aspect ratio CPBs, and high-tolerance package dimensions are reduced or mitigated. Using the second semiconductor die 110 as a bottom filler dam in the package during wafer assembly processes can lead to improvements in the component barrier entry area for UF permeation during higher-level assembly.

[0055] Spatial relative terms (such as "below," "below," "down," "lower," "above," "upper," etc.) may be used herein for ease of description to describe the relationship of one element or feature to another, as illustrated in the figures. It should be understood that such spatial relative terms are intended to include different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, then an element described as "below," "below," or "lower" to another element or feature would be oriented "above" to that element or feature. Thus, the exemplary terms "below" and "lower" can include both the upper and lower orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or otherwise), and the spatial relative descriptors used herein should be interpreted accordingly. Additionally, it should be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0056] Any numerical range described herein is intended to include all subranges of the same numerical precision contained within the described range. For example, the range “1.0 to 10.0” or “between 1.0 and 10.0” is intended to include all subranges between the referenced minimum value of 1.0 and the referenced maximum value of 10.0 (inclusive), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein.

[0057] Although exemplary embodiments of fan-out packages with slots have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that fan-out packages with slots constructed in accordance with the principles of this disclosure can be implemented in addition to those specifically described herein.

Claims

1. A system comprising: a fan-out package comprising: a first semiconductor die; a molding compound covering the first semiconductor die on at least two sides; and an electrical contact on a lower surface of the first semiconductor die, the fan-out package having a notch along a portion of a lower edge of the fan-out package, and an upper surface of the notch being higher than the lower surface of the first semiconductor die; a second semiconductor die, wherein an upper edge of the second semiconductor die extends into the notch; wherein a portion of the molding compound overhangs the second semiconductor die, wherein the fan-out package further comprises a redistribution layer on a lower surface of the fan-out package, and wherein a portion of a vertical surface of the notch is an edge surface of the redistribution layer.

2. The system of claim 1, wherein a vertical depth of the notch is between 10 microns and 500 microns.

3. The system of claim 1 or claim 2, wherein a horizontal depth of the notch is between 10 microns and 500 microns.

4. The system of claim 1, wherein the notch does not extend into the first semiconductor die.

5. The system of claim 1, further comprising: a shared support element, both the second semiconductor die and the fan-out package are fixed to an upper surface of the shared support element.

6. The system of claim 5, further comprising a conductive path between the first semiconductor die and the second semiconductor die, a length of the conductive path being less than 200 microns.

7. The system of claim 1, wherein a gap between the second semiconductor die and the fan-out package is at least 2 microns.

8. The system of claim 1, wherein a gap between the second semiconductor die and the fan-out package is at most 100 microns.

9. The system of claim 5, further comprising a layer of underfill between the fan-out package and the shared support element, the layer of underfill extending horizontally to the second semiconductor die.

10. The system of claim 9, wherein the underfill does not extend further from the fan-out package than a portion of the second semiconductor die that is furthest from the fan-out package.

11. A method for manufacturing the system of any one of claims 1-10, the method comprising: manufacturing a carrier, the carrier comprising: a layer of molding compound; a plurality of semiconductor dies embedded in the molding compound; and a redistribution layer on the semiconductor dies and the molding compound; cutting a first channel in the carrier, the first channel having a first width and a first depth, and extending between a first semiconductor die of the plurality of semiconductor dies and a second semiconductor die of the plurality of semiconductor dies; and cutting a second channel in the carrier within the first channel, the second channel having a second width that is less than the first width and a second depth that is greater than the first depth from an upper surface of the carrier.

11. The method of claim 10, wherein the second channel is cut to a depth that is at least 10 microns.

12. The method of claim 11, wherein a depth of the second channel is equal to a thickness of the carrier and is used to separate a portion of the carrier on one side of the second channel from a portion of the carrier on another side of the second channel.

13. The method of claim 11, wherein a width of the first channel exceeds a width of the second channel by between 30 microns and 100 microns.

14. The method of claim 11, wherein a depth of the first channel is between 30 microns and 100 microns.

15. The method of claim 11, further comprising: cutting a plurality of channels in the carrier to form a plurality of fan-out packages, the plurality of channels including the first channel and the second channel, forming a sub-assembly by: securing a first fan-out package of the plurality of fan-out packages to a shared support element, and securing a third semiconductor die to the shared support element, the sub-assembly including a conductive path between the first semiconductor die and the third semiconductor die, a length of the conductive path being less than 200 microns.

16. The method of claim 15, further comprising: dispensing underfill between the first fan-out package and the shared support element, and blocking the underfill by the third semiconductor die during the dispensing.

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