Advanced cell-aware fault models for yield analysis and physical failure analysis

Abstract

The present application relates to an advanced cell-aware fault model for yield analysis and physical fault analysis. To specifically identify a fault within a semiconductor cell, a SPICE netlist associated with a semiconductor cell design is retrieved, and one or more transistor characteristics are identified within the SPICE netlist. The advanced cell-aware fault model is executed for the semiconductor cell, and one or more fault testing methods of the advanced cell-aware fault model for the cell of the semiconductor chip design return results. The method for identifying a fault within the semiconductor cell is continued by correlating one or more faults detected as a result of the fault testing method with one or more transistor characteristics within the SPICE netlist, and a user interface for identifying one or more faulty transistors within the semiconductor chip design is generated.

Description

[0001] Related Applications

[0002] This patent application claims priority to U.S. Provisional Application No. 62 / 968,810, filed on January 31, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to yield analysis concepts related to semiconductor manufacturing. Background Art

[0004] As semiconductor manufacturing technology advances, transistor construction processes are becoming more complex and transistor dimensions are shrinking. Defects in transistors are becoming increasingly subtle and difficult for yield analysis engineers to identify yield limiting factors. These problems become more prevalent as semiconductor technology and transistor dimensions continue to shrink (for example) to 5nm technology and below.

[0005] Defects in transistors may affect the functionality or performance of the transistor. For example, some defects may cause the transistor to remain in the off state instead of switching between 0 and 1; some other defects may cause excessive leakage and make the signal transition much slower than expected. For yield analysis and physical failure analysis, it has become an important issue to quickly identify the defect location and find the root cause of transistor defects. Summary of the invention

[0006] A method is discussed herein, the method comprising: identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design; receiving results of one or more fault test models for a unit of the semiconductor chip design, the results being generated at one or more output pins of the unit of the semiconductor chip design based at least in part on inputs provided to input pins of the unit of the semiconductor chip design specified by the one or more fault test models, and wherein the one or more fault test models are executed based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design; correlating one or more detected faults with the one or more transistor characteristics within the netlist to identify one or more faulty transistors within the semiconductor chip design based at least in part on the results of the one or more fault test models; and providing, by a processor, a user interface for identifying the one or more faulty transistors within the semiconductor chip design.

[0007] In certain embodiments of the method, identifying one or more transistor characteristics includes: receiving user input of a transistor characteristic of interest; identifying the transistor characteristic of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristic of interest from the netlist associated with the semiconductor chip design. In addition, providing a user interface may include: providing data identifying the location of one or more faults within a cell of the semiconductor chip design within a graphical display, the graphical display overlaying the location of the one or more faults onto a cell layout.

[0008] The method may further include the following steps: generating at least one user interface, the at least one user interface uniquely identifying at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface uniquely identifying the at least one transistor includes data extracted from the netlist uniquely identifying the at least one transistor and data extracted from the netlist identifying the one or more transistor characteristics. Correlating the detected one or more faults with the one or more transistor characteristics within the netlist may include looking up results generated at the one or more output pins of the unit of the semiconductor chip design within a data structure identifying expected outputs of the unit of the semiconductor chip design. In some embodiments, identifying the one or more transistor characteristics within a netlist associated with the semiconductor chip design includes: identifying a library unit within the semiconductor chip design; and retrieving the one or more transistor characteristics of the library unit from a memory storage area. The method may further include: comparing one or more transistor characteristics of the one or more faulty transistors with one or more transistor characteristics of other transistors extracted from a netlist associated with the semiconductor chip design; determining whether one or more of the transistor characteristics of the one or more faulty transistors match one or more of the transistor characteristics of at least one of the other transistors; after determining that at least one of the transistor characteristics of the one or more faulty transistors matches at least one of the transistor characteristics of the at least one of the other transistors, determining whether one or more faults detected for the one or more faulty transistors are shared with the at least one of the other transistors; and after determining that at least one of the one or more faults is shared with at least one of the other transistors, identifying the at least one of the other transistors as a faulty transistor within a user interface.

[0009] A system is also described, the system including a memory storing instructions and a processor, the processor being coupled to the memory and executing the instructions, the instructions when executed causing the processor to: identify one or more transistor characteristics within a netlist associated with a semiconductor chip design; execute an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of cells of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design, and wherein providing the inputs to the input pins of the cells causes the cells to generate results at one or more output pins of the cells; correlating one or more detected faults with one or more transistor characteristics within the netlist to identify one or more faulty transistors within the semiconductor chip design based at least in part on the results of the one or more fault test models; and providing a user interface for identifying the one or more faulty transistors within the semiconductor chip design.

[0010] For certain embodiments of the system, identifying one or more transistor characteristics includes: receiving user input of the transistor characteristics of interest; identifying the transistor characteristics of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristics of interest from the netlist associated with the semiconductor chip design. In certain embodiments, providing a user interface includes: providing data identifying the location of one or more faults within a cell of the semiconductor chip design within a graphical display, the graphical display overlaying the location of the one or more faults onto the cell layout. In addition, the processor may be further configured to generate at least one user interface, the at least one user interface uniquely identifying at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface uniquely identifying the at least one transistor includes data extracted from the netlist uniquely identifying the at least one transistor and data identifying the one or more transistor characteristics extracted from the netlist.

[0011] Correlating the detected one or more faults with one or more transistor characteristics within the netlist may include looking up results generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying expected outputs of the cell of the semiconductor chip design.

[0012] For a particular system, identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design includes: identifying a library cell within the semiconductor chip design; and retrieving the one or more transistor characteristics of the library cell from a memory storage area. In addition, the processor may be further configured to determine whether one or more faults detected for the semiconductor chip design are shared with multiple transistors within the semiconductor chip design.

[0013] The present invention also discusses a non-transitory computer-readable medium comprising stored instructions that, when executed, cause the processor to: identify one or more transistor characteristics within a netlist associated with a semiconductor chip design; execute an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of cells of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design, and wherein providing the inputs to the input pins of the cells causes the cells to generate results at one or more output pins of the cells; correlate one or more detected faults with one or more transistor characteristics within the netlist to identify one or more faulty transistors within the semiconductor chip design based at least in part on the results of the one or more fault test models; and provide a user interface for identifying the one or more faulty transistors within the semiconductor chip design.

[0014] In some embodiments, identifying one or more transistor characteristics includes: receiving user input of a transistor characteristic of interest; identifying the transistor characteristic of interest within the netlist associated with the semiconductor chip design; and extracting the transistor characteristic of interest from the netlist associated with the semiconductor chip design. Providing a user interface may include: providing data identifying the location of one or more faults within a cell of the semiconductor chip design within a graphical display, the graphical display overlaying the location of the one or more faults onto a cell layout.

[0015] Specific embodiments of the non-transitory computer-readable medium further include stored instructions that, when executed by a processor, cause the processor to generate at least one user interface, the at least one user interface uniquely identifying at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface uniquely identifying the at least one transistor includes data extracted from the netlist uniquely identifying the at least one transistor and data extracted from the netlist identifying the one or more transistor characteristics. In certain embodiments, correlating the detected one or more faults with the one or more transistor characteristics within the netlist includes looking up results generated at the one or more output pins of the unit of the semiconductor chip design within a data structure identifying expected outputs of the unit of the semiconductor chip design. For specific embodiments, identifying the one or more transistor characteristics within a netlist associated with the semiconductor chip design includes: identifying a library unit within the semiconductor chip design; and retrieving the one or more transistor characteristics of the library unit from a memory storage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure will be more fully understood according to the detailed description given below and the drawings of the embodiments of the present disclosure. The drawings are used to provide an understanding and understanding of the embodiments of the present disclosure, and the scope of the present disclosure is not limited to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0017] Figure 1 is a flow chart illustrating an example operation of an advanced cell-aware fault model.

[0018] Figure 2 An example SPICE netlist for a semiconductor chip design is shown.

[0019] Figure 3 Shows the parameters of an example fault test model.

[0020] Figure 4 An example user interface for providing information about a fault detected within a semiconductor unit is shown.

[0021] Figure 5 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure.

[0022] Figure 6 An abstract diagram depicting an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0023] Aspects of the present disclosure relate to advanced cell-aware fault models for yield analysis and physical failure analysis. The described aspects augment cell-aware fault modeling for semiconductor manufacturing with detailed transistor physical features that can be identified and extracted from SPICE netlists. By leveraging data of detailed transistor physical features, the cell-aware fault modeling process predicts how a properly functioning cell should operate, and how a malfunctioning cell will operate for multiple possible malfunction types. The method thereby enables detection of faulty transistors within a physical semiconductor chip. The advanced cell-aware fault model demonstrates its benefits, namely, helping yield analysis and physical failure analysis engineers quickly identify transistor defects that are yield limiting factors.

[0024] This article discusses an advanced cell-aware fault model 100 and implementation methods thereof that take into account physical characteristics of transistors. The advanced cell-aware fault model 100 identifies and extracts data indicating characteristics of transistors within a cell design from a SPICE netlist when executed, such as physical characteristics of transistors within the cell design. The identified and extracted data enables the advanced cell-aware fault model 100 to predict how a cell should operate under proper functionality, and predict how a specific malfunctioning transistor may affect the functionality of the overall cell design. The transistor characteristics for extraction may be identified based on user-specified data indicating various parameters, based on automated configuration for identifying feature-specific data within a SPICE netlist (e.g., based on a generated database, and / or based on the results of machine learning-based analysis of data reflecting historical cell designs trained to identify defects within a specific cell), etc. The extracted data indicating the physical characteristics of the transistors is used in logic diagnosis to identify candidate defects as specific transistors or specific regions within the cell design. Based on the physical characteristics of the diagnostic candidates, yield analysis and physical failure analysis engineers can quickly identify the location and root cause of systematic defects that affect product yield. Thus, the use of the advanced cell-aware fault model 100 enables identification and ultimate resolution of systematic defects within a cell, such as defects attributable to a single transistor, a single type of transistor (even if covering multiple individual transistors), or within a specific region of a cell, with reduced use of processing resources for defect analysis because exhaustive test criteria that may involve redundant or inefficient test strategies do not have to be executed to specifically identify those systematic defects. Furthermore, because the fault test model does not require very exhaustive test criteria to accurately and precisely identify the root cause of defects within a cell, production yields can be increased over time because cell failure analysis requires less time to complete.

[0025] Many modern SOC (system on chip) designs are based on standard library cells. Faults in these standard library cells are often identified at the cell boundary pins. For example, "stuck-on" fault models on cell pins (e.g., identifying defects that do not allow the transistor to change output value) and "transition fault" models (e.g., identifying transition time faults) have detected most defects in library cells. However, as transistor size continues to decrease and standard library cells continue to increase in complexity, detection of specific faults in standard library cells based on boundary pin analysis has become more difficult.

[0026] Advanced cell-aware testing utilizes the characteristics of physical transistors within standard library cells to generate fault test models that are intended to predict the fault behavior of the overall library cells based on specific malfunctioning transistors, even as the size of the library cells decreases and the complexity of those library cells increases, and the advanced cell-aware testing can be used to identify and / or target defects within the standard library cells. Cell-aware test methods and models are generated with advanced cell-aware fault models. Once the cell-aware fault models are generated, the cell-aware fault models can be used in the fault test model generation process to target defects within complex cells.

[0027] The advanced cell-aware fault model 100 contains defect data indicating the behavior of a specific defect within a library cell. The defect data includes identification data that can be used to identify the specific defect to which the defect data applies. The defect data for a specific defect also identifies the standard library cell to which it applies, the transistor (or transistors) within the standard library cell to which it applies (e.g., based on data that uniquely identifies the transistor (or transistors) extracted from a SPICE netlist of the cell design), the type of defect of the transistor (or transistors), and data indicating the behavior of the standard library cell when the specific transistor (or transistors) malfunctions according to the identified defect type. For example, the defect data identifies the input pin values ​​used to distinguish between non-defective cells and cells affected by the defect. The defect is simulated using a SPICE simulator, and its behavior is captured and stored in a cell-aware fault model file as part of the defect data. The stored defect data is used to generate a fault test model, such as via an input / output truth table (e.g., from Synopsys's TestMax ATPG tool) to generate a test pattern that targets the defect behavior (e.g., by generating pin input combinations that can be used to distinguish between properly and improperly functioning transistors). These fault test models are implemented by providing inputs to the input pins of the cell according to an input-output truth table, and the results of the fault test models are received at the output pins of the cell, which can be compared against the expected results within the identified input-output truth table to identify the root cause of the defect. The defect data also guides a logic diagnostic tool (such as TestMax Diagnosis) to diagnose the failed chip by identifying the type of defect and the location of the defect within the failed chip. The location of the defect can be specified via a generated graphical display, such as Figure 4 An example graphical display 402 is reflected in and discussed in greater detail herein.

[0028] Aspects of the present disclosure relate to an advanced cell-aware fault model 100 that identifies and describes transistor defects within standard library cells, thereby enabling systematic defects within the cell that reduce manufacturing yield to be corrected with minimal processing resource utilization for testing the cell and identifying the defect. The cell-aware fault model 100 contains transistor characteristics that identify detailed transistor physical features associated with specific defects, which are reflected in the input-output truth table of the standard library cell that distinguishes between properly functioning and improperly functioning cell designs, and are used to distinguish the defect location within the improperly functioning cell design. These physical features can be identified and extracted from the SPICE netlist description of the library cell, for example, via text-based extraction techniques that are used to identify relevant text and to extract the relevant text reflected in the SPICE netlist as a text file. The detailed transistor physical features reflected in the advanced cell-aware fault model 100 are used in logic diagnostics (e.g., TestMax Diagnosis from Synopsys) and can effectively identify the root cause of the defect within the identified defective cell.

[0029] Semiconductor manufacturing technology has evolved from planar FETs (field effect transistors) to FinFETs, and now to gate-all-around (GAA) FETs or MBCFETs (multi-bridge channel field effect transistors) at 5nm and below. With each generation of technology, transistor construction has become more complex. Defects in transistors have always affected the functionality, drive strength, or leakage of transistors.

[0030] During technology development or product yield ramp-up, manufacturers or fabless design companies need to quickly identify yield limiting factors of cell designs. Fault model-based logical diagnosis can facilitate defect localization for yield analysis and physical analysis. Specific fault models can include stuck-at fault models and transition fault models.

[0031] The advanced cell-aware fault model 100 of certain embodiments contains defect data indicative of the behavior of a defect. For example, the defect data for a particular defect contains input pin values ​​that distinguish the different responses between non-defective cells and cells affected by the defect. The captured defect behavior is used for fault test model generation to generate test patterns that precisely target the defect behavior, and / or to diagnose the chip where the fault occurs, for example by supplementing the data utilized by logic diagnostic tools (e.g., TestMax Diagnosis from Synopsys).

[0032] The advanced cell-aware fault model 100 includes defect data such as physical information of the characteristics of the cell defect. For example, the advanced cell-aware fault model 100 generates data defining a bounding box around the defect (the bounding box is visually reflected via a graphical display, such as Figure 4402), and data identifying the layer of the defect to identify the location of the defect within the cell. The advanced cell-aware fault model 100 augments the transistor characteristics of the identified cell defect with detailed physical features of the transistor extracted from the SPICE netlist of the cell. The extracted physical features are used in logic diagnostic reports and / or fed to yield analysis tools to quickly identify yield limiting factors as discussed herein.

[0033] Figure 1 An example flow chart is shown that illustrates the steps of building and executing an example advanced cell-aware fault model 100. The advanced cell-aware fault model 100 identifies and extracts transistor physical features from a SPICE netlist, such as Figure 1 As indicated at blocks 101-102 of FIG. 1 (the example SPICE netlist 200 is shown in FIG. Figure 2 The data extraction may identify and extract data indicative of physical characteristics of the transistors based at least in part on user input identifying particular parameters of interest and / or automatically identified parameters (e.g., generated via a computing system based at least in part on analysis of various SPICE netlists, etc.). In addition to identifying the particular parameters of each transistor, the data extraction may additionally identify and extract data that uniquely identifies each transistor (e.g., such as the location of the transistor within the cell and the SPICE netlist, or some other data that uniquely distinguishes each transistor from other transistors within the cell and as reflected in the SPICE netlist). As just one example, data extracted from the SPICE netlist may be automatically identified as being relevant to identifying a particular defect within the cell. The SPICE netlist may be provided as a text file (e.g., as a Figure 2 ), and extraction of these features may include text recognition and extraction of text strings reflected in the SPICE netlist that are identified as relevant to uniquely identifying a particular transistor during later analysis and / or identified as relevant to defect identification within the cell. For each transistor instance, the SPICE netlist contains data identifying the transistor instance, as well as a list of parameters associated with the transistor instance and their corresponding values. These parameters are related to the physical characteristics of each transistor instance in the cell layout. Different instances of the same type of transistor may have the same values ​​for some parameters, but they may have different values ​​for other parameters. The difference in values ​​shows the different physical characteristics of each individual transistor, which affects the functionality of the transistor within the cell layout. An example of the data content of the SPICE netlist is reflected in the figure, with individual parameters emphasized. See FIG. Figure 2 , which shows a fragment of a SPICE netlist 200 for three transistor examples, identifying (in Figure 2 ) and extracting data that uniquely identifies each transistor instance, and similarly identifies (in Figure 2) and extract individual parameters determined to be relevant to defect detection (e.g., based on manual identification and / or automatic identification). As just one example, text-based data identification and extraction continues through an advanced cell-aware fault model that identifies specific text strings reflected within a memory storage area associated with the advanced cell-aware fault model 100 as being relevant to uniquely identifying specific transistors and / or distinguishing defects. The relevant text strings within the SPICE netlist and adjacent text (e.g., a defined number of characters or text between the identified relevant text strings and a delimiter within the text) that indicates values ​​associated with those relevant text strings are extracted for further analysis.

[0034] The following is an example description of several transistors in a SPICE netlist file ( Figure 2 Instance data is also shown in the ):

[0035] XMPA1 I1:F1109 A1:F1108 VDD:F1107 VBP pch_svt_mac ad=0.00203p as=0.00406p

[0036] +dfm_flag=1edgeflag=0l=0.02u matchingflag=0nfin=2nrd=0nrs=0ojh=0

[0037] +pd=0.128u ploda1=2e-08 ploda2=0 ploda3=0 plodb1=0 plodb2=0 plodb3=0

[0038] +…

[0039] +spobl1=3.26e-07 spobl2=1.39e-07 spobr1=1.39e-07 spobr2=3.26e-07 nfin_a_ddb=1 nfin_b_ddb=0

[0040] +spot=4.3e-08 spotl1=4.3e-08 spotl2=4.3e-08 spotr1=4.3e-08 spotr2=4.3e-08 nfin_a_sdb2=3nfin_b_sdb2=2$angle=90

[0041] XMPA2 I1:F1109 A2:F1112 VDD:F1113 VBP pch_svt_mac ad=0.00203p as=0.00406p

[0042] +dfm_flag=1edgeflag=0l=0.02u matchingflag=0nfin=2nrd=0nrs=0ojh=0

[0043] +pd=0.128u ploda1=0 ploda2=0 ploda3=0 plodb1=2e-08 plodb2=0plodb3=0

[0044] +…

[0045] +spob=3.26e-07 spobl1=1.39e-07 spobl2=1.39e-07 spobr1=3.26e-07nfin_a_ddb=0 nfin_b_ddb=1

[0046] +spobr2=1.39e-07 spot=4.3e-08 spotl1=4.3e-08 spotl2=4.3e-08spotr1=4.3e-08

[0047] +spotr2=4.3e-08nfin_a_sdb2=3nfin_b_sdb2=3$angle=90

[0048] XMPI1 X:F1115 I1:F1116 VDD:F1117 VBP pch_svt_mac ad=0.01078p as=0.01078p

[0049] +dfm_flag=1edgeflag=0l=0.02u matchingflag=0nfin=4nrd=0nrs=0ojh=0

[0050] +pd=0.448u ploda1=0 ploda2=0 ploda3=0 plodb1=0 plodb2=0 plodb3=0 ppitch=0

[0051] +…

[0052] +sodxb4=5.92454e-08 sodyb=1.34e-07 sodyt=1.70115e-07 spob=3.26e-07 nfin_a_ddb=0nfin_b_ddb=0

[0053] +spobl1=4.3e-08 spobl2=3.26e-07 spobr1=4.3e-08 spobr2=4.3e-08spot=4.3e-08

[0054] +spotl1=4.3e-08 spotl2=4.3e-08 spotr1=4.3e-08 spotr2=4.3e-08 nfin_a_sdb2=3 nfin_b_sdb2=2$angle=90

[0055] In the above example, there are three transistors of the same type "pch_svt_mac". For the parameter "nfin" (which specifies the number of fins per metal gate finger of the transistor and varies between transistors), the transistors have values ​​of 2, 2, and 4, respectively; thereby reflecting only one instance parameter, which varies between transistors and which is determined in the example shown to indicate the presence of a defect within the operation of the transistor). The differences in the nfin parameters between transistors cause the transistors to operate differently under certain conditions, and therefore these differences can be utilized by the advanced cell-aware fault model 100 as only one of multiple parameters that reflect differences in transistor characteristics that lead to different fault behaviors of the cell (based on which transistor is defective). The different values ​​of the nfin parameter represent different physical characteristics of each of these transistors. For another parameter "angle" (which is also indicated as being related to the fault test model determining the presence of a defect in the cell, as Figure 2 ), all three transistors have the same value 90. It should be noted that there are several parameters in the transistor description of the SPICE netlist, but some parameters may not be relevant to accurately identify the root cause of the defect in the cell, and therefore the advanced cell-aware fault model 100 only identifies and extracts those parameters related to distinguishing the defect type, so as to minimize the processing resources required for analyzing all parameters known to all transistors in the cell. Each parameter shows a different aspect of the physical layout. By examining these parameters, an embodiment selects and extracts transistor characteristics that are considered to be relevant to distinguishing the defect type and / or defect location in the cell, such as transistor models, parameters and their values. These extracted transistor characteristics can be used to construct a fault test model to distinguish between properly functioning transistors and malfunctioning transistors in the cell. It should be understood that certain parameters may be considered to be relevant to identifying the defect location in one library cell design, but may not be relevant to identifying the defect location in another library cell design. As an example, identifying and extracting transistor characteristics that are considered to be relevant to defect identification and location can be a two-step process:

[0056] Step 1: Identify transistor characteristics ( Figure 1101 of the embodiment of the present invention). The advanced cell-aware fault model 100 includes a generation tool to automatically identify and extract relevant transistor characteristics. For individual transistors within a cell to be analyzed for possible faults and / or yield limiting factors, these transistor characteristics are identified as relevant and extracted. The generation tool of the advanced cell-aware fault model 100 extracts specific transistor characteristics that are manually identified by a user, and / or the generation tool of the advanced cell-aware fault model 100 extracts specific transistor characteristics that are automatically identified as being relevant to distinguishing properly functioning transistors from malfunctioning transistors (e.g., based on a library of data that associates specific transistor characteristics with defect identification). If the user knows which transistor characteristics are of interest, the user can input these characteristics (e.g., via user input) into the advanced cell-aware fault model 100 for use by the generation tool, and the generation tool then focuses on the transistor characteristics specified by the user. In many cases, the user may not know the exact transistor characteristics of interest, or there may be too many parameters in the SPICE netlist for the user to manually select the specific transistor characteristics of interest. In this case, the unit-aware fault test model generation tool investigates all transistors in the SPICE netlist file and compares the parameters and their values ​​of all transistors. These parameters can be classified or grouped based on whether all transistors of the same type have the same value or different values. The similarity (or dissimilarity) of these physical characteristic values ​​can be used to enhance the unit-aware fault model.

[0057] Step 2: Extract physical features and create a physical feature data structure (e.g., data table) to be included in the unit-aware fault test model file ( Figure 1 Once the physical features are identified (or specified by the user), the cell-aware fault test model generation tool extracts the parameters and their corresponding values ​​and adds this information to the cell-aware fault model file. A physical layout data structure is then constructed to contain characteristics indicating the physical data of all transistors, as reflected at box 103. The enhanced cell-aware fault model 100 then generates a logical diagnostic report (as shown at box 104) that provides an indication of whether the identified parameters indicate a possible defect (e.g., based on a comparison with a library of data used to identify defects of the advanced cell-aware fault model), and / or provides the generated physical layout data structure to a yield analysis tool to identify systematic defects within the cell, as reflected at box 105. For example, when the physical layout data structure is utilized via the yield analysis tool, the enhanced cell-aware fault model 100 generates one or more cell input-output truth tables (as shown at box 105) to be used as test criteria for the fault test model, at least in part based on the physical layout data structure. Figure 1Because the physical characteristics of transistors indicate how the transistors will react to specific inputs, the enhanced cell-aware fault model 100 predicts how individual faulty transistors affect the operation of even complex cells based on the physical characteristics of the individual transistors as reflected in the input-output truth table generated and used as test criteria for the fault test model. Thus, the truth table specifies the expected outputs (detectable at the cell output pins) for a given set of inputs (provided at the cell input pins). For example, for a given input to the overall cell, the advanced cell-aware fault model 100 predicts how the input will behave as signals flow through and between the various components (e.g., transistors) of the cell for a properly functioning cell (e.g., as signals flow from one transistor to another, as an input to a first transistor becomes an output of the first transistor used as an input to a second transistor). The advanced cell-aware fault model 100 provides the inputs of the input-output truth table to the cell as part of the fault test model, as indicated at block 107, and monitors the outputs of the cell based on the inputs provided according to the test criteria of the fault test model and the input-output truth table, as reflected in block 108. After identifying a deviation from an expected output for a given cell, the advanced cell-aware fault model 100 identifies the defect within the cell, for example, by generating a defect report containing the identification of the defect, as reflected at block 109. The specific defect is precisely identified so as to indicate an area within the cell (e.g., at a specific transistor location), thereby enabling downstream processes and / or cell designers utilizing the advanced cell-aware fault model to remediate the identified defect. Further, as reflected herein, the defect report may include a graphical display that provides a visual overlay on a displayed indication of the cell layout, such that a user is provided with a visual indication of the location of the defect within the cell layout. In certain embodiments, the graphical display may be interactive, enabling a user to selectively zoom in / out on the layout to obtain additional details about the location of the detected defect. Because a truth table is specifically generated for identifying a specific fault, the advanced cell-aware fault model 100 does not have to perform exhaustive testing of all possible inputs to the cell to identify a specific source of the defect, thereby reducing the amount of processing resources necessary for defect identification. Similarly, utilizing precisely adapted truth tables specifically provided for identifying specific faults within a library cell, the exact location of a fault within a cell can be accurately identified without the need to individually analyze each transistor within the cell to confidently determine the location of the fault. By identifying similarities between a defect of a particular cell and defects detected for other cells that share one or more physical characteristics (e.g., portions of the cell's transistor layout), specific information about the defect is determined and included in the defect report.For example, based on determined similarities between defects detected for different cells and / or defects detected for different input combinations for a single cell, the advanced cell-aware fault model 100 correlates specific defects with specific physical characteristics of the cell, thereby providing a specific indication of a specific faulty portion of the cell.

[0058] Based on the predicted outputs of various library cell designs and the determined similarities between the cell designs and the detected defects, the cell input-output truth table identifies the pin inputs of the test criteria of the cell's fault test model that distinguish between properly functioning cells and improperly functioning cells, wherein specific input combinations within the test criteria of the fault test model are used to distinguish specific fault types. As a simplified example, the input-output truth table of the fault test model may specify that an input "1" on a first input pin should produce an output "1" on a first output pin. If the tested cell produces an output "0" on the first output pin, this output may indicate a fault. A combination of multiple input-output combinations is then used to specifically identify the source of the fault, and thereby distinguish multiple possible faults to identify a specific fault type of the cell, which is then reflected in the defect report. According to the above example, where the presence of a fault in a cell has been identified (based on an incorrect output on a first output pin), an input-output table is referenced to specify an input "0" on a second input pin as part of the test criteria of the fault test model, the corresponding expected output on the second output pin is "0" for the first fault type, and the expected output on the same second output pin is "1" for the second fault type. When additional combinations of expected inputs and outputs are considered, the advanced cell-aware fault model 100 is able to distinguish between multiple fault types within a complex cell, thereby enabling the advanced cell-aware fault model to specifically identify a faulty transistor within the complex cell, and reflect the specifically identified faulty transistor within a defect report (e.g., via data uniquely identifying the faulty transistor extracted from a SPICE netlist).

[0059] As mentioned above, the extracted physical information may be provided in a data structure having a table format, such as within a table in a cell-aware fault model file. An example cell-aware fault model 100 having physical features extracted from a SPICE netlist is shown below (this data is also provided by Figure 3 The example depicted in ( ):

[0060] Transistor_and_subcell_layout_data:

[0061] -[Table,Device]

[0062] -[Name,Type,llx,lly,urx,ury,layers,Active_Device, Related_Pin,device_model,device_feature]

[0063] -[XMPA1,transistor,80,432,100,432,pgate_mac tpdiff,XMPA1,,pch_svt_mac, nfin=2 nfin_b_sdb2=2 angle=90]

[0064] -[XMPA2,transistor,170,432,190,432,pgate_mac tpdiff,XMPA2,,pch_svt_mac, nfin=2 nfin_b_sdb2=3 angle=90]

[0065] -[XMPI1,transistor,80,144,100,144,ngate_mac tndiff,XMPI1,,pch_svt_mac, nfin=4 nfin_b_sdb2=2 angle=90]

[0066] In the above example, the first row shows the physical features extracted by the generation tool of the advanced cell-aware fault model 100, and each subsequent row shows the feature value of each transistor. Each column corresponds to a physical feature of the transistor, for example, the column "device_model" shows the type of transistor, and the column "device_feature" shows the physical feature of each transistor (e.g., number of fins, transistor angle, etc.). The data in this data structure can later be included in a logic diagnostic report, or imported into a yield analysis tool to identify defects within the cell.

[0067] In certain embodiments, the extracted data may be used to identify similarities (or dissimilarity) between transistors included within a design. For example, after identifying an error or failure within a design, such as that attributable to a faulty transistor, identifying similarities and / or dissimilarity between transistors includes determining whether one or more transistor characteristics match across multiple transistors (e.g., one or more parameters are shared between multiple transistors). The identified similarities and / or dissimilarity between transistor parameters may be used to determine whether the identified failure is shared between all transistors having a given parameter, or whether the failure is isolated to a single transistor (or multiple unrelated transistors). For example, a particular failure may be indicated as being caused by a particular transistor parameter (or a particular combination of transistor parameters), such that the determination of whether a particular failure is shared between multiple parameters includes identifying all other transistors that share parameters with the faulty transistor identified as being associated with the transistor failure. When the faulty transistor is displayed within a graphical display, the graphical display is then updated to reflect the locations (and / or other characteristics) of those transistors that are identified as sharing parameters with the initially identified faulty transistor.

[0068] In addition, data indicating various transistor parameters can be compared with Figure 4 4 and / or 500, which may be shared with the diagnostic and / or yield explorer system 401 reflected in FIG. 4 (e.g., executed via shared processing resources and / or via separate computing entities) that may provide additional data regarding yield and / or detected failures within the cell, such that additional transistor parameters may supplement data provided via such systems (e.g., such as Figure 4 In some embodiments, these additional systems may be configured to utilize data indicative of various physical parameters to modify the displayed output (e.g., by showing identified similar transistors within a graphical display, by annotating displayed transistors within a display, etc.). Figure 4 An example graphical display is shown at that illustrates a graphical overlay indicating the locations of various defects detected via application of an advanced cell-aware fault model within a graphical illustration of a cell layout.

[0069] As part of the overall cell design and fabrication process, the advanced cell-aware fault model 100 may be utilized. For example, after constructing a netlist for a new cell design, the advanced cell-aware fault model identifies and extracts transistor characteristic data for transistors within the cell design (e.g., all transistors within the cell design). Based on the physical characteristics of the transistors as identified within the transistor characteristic data, the advanced cell-aware fault model generates an input-output data table or other such data structure that identifies how a particular transistor, if faulty, affects the operation of the overall cell. The advanced cell-aware fault model identifies specific input combinations within the input-output data table that can be used to distinguish between properly functioning cells and malfunctioning cells and for distinguishing between types of faults within a cell, which enables the advanced cell-aware fault model to specifically identify individual faulty transistors within the constructed cell.

[0070] During testing of a constructed cell (e.g., after fabrication), and / or when modeling the expected operation of the cell, the advanced cell-aware fault model 100 executes one or more fault test models that include specifically identified input combinations to the cell to determine whether the cell operates properly, and to distinguish between various fault types so as to enable the advanced cell-aware fault model to specifically identify faulty transistors within the fabricated (or simulated) cell.

[0071] By executing the one or more fault test models, the advanced cell-aware fault model 100 causes the cell to generate an output at the output pin of the cell. The advanced cell-aware fault model 100 then compares the generated output with the data stored in the input-output data table for the utilized data inputs to see if the output of the fault test model indicates a faulty transistor, and determines which transistor(s) within the cell are faulty by correlating the output received from the cell for a given set of inputs with the corresponding entry in the input-output data table that identifies the specific fault of the cell.

[0072] An input-output data table may be generated separately for each semiconductor chip design. For example, an input-output table may be generated for each cell within a semiconductor chip design as part of the semiconductor chip design process. However, the input-output data table of a standard library cell may be stored in a memory for retrieval when constructing a fault test model for a newly developed semiconductor chip design that includes one or more standard library cells. During the design of a semiconductor chip, standard library cells included in the semiconductor chip design are identified, and the advanced cell-aware fault model retrieves the relevant input-output data table of the standard library cell, and the retrieved input-output data table is then utilized during testing of the semiconductor cell design.

[0073] Figure 5A set of example processes 700 for transforming and verifying design data and instructions representing an integrated circuit used during the design, verification, and fabrication of an article such as an integrated circuit are shown. Each of these processes can be constructed and implemented as multiple modules or operations. The term "EDA" stands for the term "electronic design automation". These processes begin with creating a product concept 710 with information provided by a designer, which is transformed to create an article using a set of EDA processes 712. When the design is complete, the design is taped out 734, at which time the work (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor die are fabricated 736, and packaging and assembly processes 738 are performed to produce a finished integrated circuit 740.

[0074] The specification of a circuit or electronic structure can vary from a low-level transistor material layout to a high-level description language. High-level abstractions can be used to design circuits and systems using hardware description languages ​​("HDLs") such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic level register transfer level ("RTL") description, a gate level description, a layout level description, or a mask level description. Each lower level of abstraction, which is a less abstract description, adds more useful details to the design description, such as more details of the modules that contain the description. The lower level of abstraction, which is a less abstract description, can be computer-generated, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of abstraction language for specifying a more detailed description is SPICE, which is used for detailed descriptions of circuits with many analog components. The description at each level of abstraction is enabled for use by the corresponding tools (e.g., formal verification tools) at that layer. The design process can use Figure 5 The sequence depicted in . The described process is enabled by an EDA product (or tool).

[0075] During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or codeline), and cost reduction. Partitioning the design into different types of modules or components may be done at this stage.

[0076] During logic design and functional verification 716, modules or components in a circuit are specified in one or more description languages ​​and the functional accuracy of the specifications is checked. For example, the components of the circuit can be checked to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal checkers. In some embodiments, special systems of components called "emulators" or "prototyping systems" are used to accelerate functional verification.

[0077] During synthesis and test design 718, the HDL code is transformed into a netlist. In some embodiments, the netlist can be a curved structure where the edges of the curved structure represent components of the circuit and where the nodes of the curved structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify that the integrated circuit works according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit can be tested to verify that the integrated circuit meets the requirements of the specification.

[0078] During netlist verification 720, the netlist is checked for compatibility with timing constraints and correspondence with the HDL code. During design planning 722, the overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level placement.

[0079] During layout or physical implementation 724, physical placement (e.g., positioning of circuit components such as transistors or capacitors) and routing (connection of circuit components by multiple conductors) are performed, and selection of cells from a library to enable a specific logic function may be performed. As used herein, the term "cell" may specify a group of transistors, other components, and interconnects that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (e.g., a flip-flop or latch). As used herein, a circuit "block" may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or components, and are enabled as both physical and analog structures. Parameters such as size are specified for the selected cell (based on a "standard cell"), and the parameters are made accessible in a database for use by the EDA product.

[0080] During analysis and extraction 726, circuit functionality is verified at the layout level, which permits improvements to the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints such as DRC constraints, electrical constraints, lithography constraints, etc. are correct and that the circuit system functionality matches the HDL design specifications. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0081] During tape-out, data is created for use in producing lithography masks (after applying lithography enhancements where appropriate).During mask data preparation 732, the "tape-out" data is used to generate lithography masks for use in producing finished integrated circuits.

[0082] Computer systems (e.g. Figure 6 The storage subsystem of the computer system 900) may be used to store programs and data structures used by some or all of the EDA products described herein and products for developing libraries and units of physical and logical design that use the libraries.

[0083] Figure 6 An example machine of computer system 900 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., connected to a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment as a peer machine in a peer-to-peer (or distributed) network environment or as a server or a client machine in a cloud computing infrastructure or environment.

[0084] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be taken to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0085] The example computer system 900 includes a processing device 902, a main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 906 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 918, which communicate with each other via a bus 930.

[0086] Processing device 902 represents one or more processors, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 902 may be configured to execute instructions 926 for performing the operations and steps described herein.

[0087] The computer system 900 may further include a network interface device 908 to communicate over a network 920. The computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generating device 916 (e.g., a speaker), a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

[0088] The data storage device 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methods or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and / or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media.

[0089] In some embodiments, the instructions 926 include instructions that implement functionality corresponding to the present disclosure. Although the machine-readable storage medium 924 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing the one or more instruction sets. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode an instruction set for machine execution and cause the machine and processing device 902 to perform any one or more methods of the present disclosure. The term "machine-readable storage medium" should be considered to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0090] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations that produce a desired result. Operations are those that require physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals that are capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0091] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated as apparent from the present disclosure, it should be understood that throughout the description, specific terms refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0092] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for a given purpose, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including a floppy disk, an optical disk, a CD-ROM and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0093] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0094] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0095] In the above disclosure, the embodiments of the present disclosure have been described with reference to their specific example embodiments. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the drawings, and similar elements are marked with similar reference numerals. Therefore, the present disclosure and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method for semiconductor chip design, the method comprising: identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design, wherein the transistor characteristics include physical features of the one or more transistors within the semiconductor chip design; receiving results of one or more fault test models for a cell of the semiconductor chip design, the results being generated at one or more output pins of the cell of the semiconductor chip design based at least in part on inputs provided to input pins of the cell of the semiconductor chip design specified by the one or more fault test models, and wherein the one or more fault test models are executed based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design; correlating one or more detected faults with one or more transistor characteristics within the netlist to identify one or more faulty transistors within the semiconductor chip design based at least in part on the results of the one or more fault test models; as well as A user interface is provided, by a processor, that identifies the one or more faulty transistors within the semiconductor chip design.

2. The method of claim 1 , wherein identifying one or more transistor characteristics comprises: receiving user input of a transistor characteristic of interest; identifying the transistor characteristic of interest within the netlist associated with the semiconductor chip design; as well as The transistor characteristics of interest are extracted from the netlist associated with the semiconductor chip design.

3. The method of claim 1 , wherein providing a user interface comprises: Data identifying locations of one or more failures within the cell of the semiconductor chip design is provided within a graphical display that overlays the locations of the one or more failures onto a cell layout.

4. The method according to claim 1, further comprising: At least one user interface is generated, the at least one user interface uniquely identifying at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface uniquely identifying the at least one transistor includes data extracted from the netlist uniquely identifying the at least one transistor and data extracted from the netlist identifying the one or more transistor characteristics.

5. The method of claim 1 , wherein correlating one or more detected faults with one or more transistor characteristics within the netlist comprises looking up results generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying expected outputs of the cell of the semiconductor chip design.

6. The method of claim 1 , wherein identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design comprises: identifying library cells within the semiconductor chip design; as well as One or more transistor characteristics of the library cell are retrieved from a memory storage area.

7. The method according to claim 1, further comprising: comparing one or more transistor characteristics of the one or more faulty transistors with one or more transistor characteristics of other transistors extracted from the netlist associated with the semiconductor chip design; determining whether one or more of the transistor characteristics of the one or more faulty transistors matches one or more of the transistor characteristics of at least one of the other transistors; after determining that at least one of the transistor characteristics of the one or more faulty transistors matches at least one of the transistor characteristics of the at least one of the other transistors, determining whether one or more faults detected for the one or more faulty transistors are shared with the at least one of the other transistors; as well as Upon determining that at least one of the one or more faults is shared with at least one of the other transistors, the at least one of the other transistors is identified within the user interface as a faulty transistor.

8. A semiconductor chip design system, comprising: a memory storing instructions; as well as a processor coupled to the memory and executing instructions that, when executed, cause the processor to: identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design, wherein the transistor characteristics include physical features of the one or more transistors within the semiconductor chip design; executing an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of cells of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design, and wherein providing the inputs to the input pins of the cells causes the cells to generate results at one or more output pins of the cells; correlating one or more detected faults with one or more transistor characteristics within the netlist to identify one or more faulty transistors within the semiconductor chip design based at least in part on the results of the one or more fault test models; as well as A user interface is provided that identifies the one or more faulty transistors within the semiconductor chip design.

9. The semiconductor chip design system of claim 8, wherein identifying one or more transistor characteristics comprises: receiving user input of a transistor characteristic of interest; identifying the transistor characteristic of interest within the netlist associated with the semiconductor chip design; as well as The transistor characteristics of interest are extracted from the netlist associated with the semiconductor chip design.

10. The semiconductor chip design system according to claim 8, wherein providing a user interface comprises: Data identifying locations of one or more failures within the cell of the semiconductor chip design is provided within a graphical display that overlays the locations of the one or more failures onto a cell layout.

11. The semiconductor chip design system of claim 8 , wherein the processor is further configured to generate at least one user interface, wherein the at least one user interface uniquely identifies at least one transistor and one or more transistor characteristics of the at least one transistor identified in the netlist, wherein the user interface uniquely identifying the at least one transistor includes data extracted from the netlist that uniquely identifies the at least one transistor and data that identifies the one or more transistor characteristics extracted from the netlist.

12. A semiconductor chip design system according to claim 8, wherein correlating one or more detected faults with one or more transistor characteristics within the netlist includes looking up results generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying expected outputs of the cell of the semiconductor chip design.

13. The semiconductor chip design system of claim 8, wherein identifying one or more transistor characteristics within a netlist associated with the semiconductor chip design comprises: identifying library cells within the semiconductor chip design; as well as One or more transistor characteristics of the library cell are retrieved from a memory storage area. 14 . The semiconductor chip design system of claim 8 , wherein the processor is further configured to determine whether one or more faults detected for a semiconductor chip design are shared with a plurality of transistors within the semiconductor chip design.

15. A non-transitory computer readable medium comprising stored instructions that, when executed by a processor, cause the processor to: identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design, wherein the transistor characteristics include physical features of the one or more transistors within the semiconductor chip design; executing an advanced cell-aware fault model for the semiconductor chip design to provide inputs specified within one or more fault test models to input pins of cells of the semiconductor chip design, wherein the one or more fault test models are identified based at least in part on the one or more transistor characteristics within the netlist associated with the semiconductor chip design, and wherein providing the inputs to the input pins of the cells causes the cells to generate results at one or more output pins of the cells; correlating one or more detected faults with one or more transistor characteristics within the netlist to identify one or more faulty transistors within the semiconductor chip design based at least in part on the results of the one or more fault test models; as well as A user interface is provided that identifies the one or more faulty transistors within the semiconductor chip design.

16. The non-transitory computer readable medium of claim 15, wherein identifying one or more transistor characteristics comprises: receiving user input of a transistor characteristic of interest; identifying the transistor characteristic of interest within the netlist associated with the semiconductor chip design; as well as The transistor characteristics of interest are extracted from the netlist associated with the semiconductor chip design.

17. The non-transitory computer-readable medium of claim 15, wherein providing a user interface comprises: Data identifying locations of one or more failures within the cell of the semiconductor chip design is provided within a graphical display that overlays the locations of the one or more failures onto a cell layout.

18. The non-transitory computer-readable medium of claim 15, further comprising stored instructions that, when executed by a processor, cause the processor to generate at least one user interface that uniquely identifies at least one transistor and one or more transistor characteristics of the at least one transistor identified within the netlist, wherein the user interface that uniquely identifies the at least one transistor includes data extracted from the netlist that uniquely identifies the at least one transistor and data that identifies the one or more transistor characteristics extracted from the netlist.

19. The non-transitory computer-readable medium of claim 15, wherein correlating one or more detected faults with one or more transistor characteristics within the netlist comprises looking up results generated at the one or more output pins of the cell of the semiconductor chip design within a data structure identifying expected outputs of the cell of the semiconductor chip design.

20. The non-transitory computer readable medium of claim 15, wherein identifying one or more transistor characteristics within a netlist associated with a semiconductor chip design comprises: identifying library cells within the semiconductor chip design; as well as One or more transistor characteristics of the library cell are retrieved from a memory storage area.

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