Semiconductor-on-insulator substrate, semiconductor structure and method for forming the same

Abstract

A semiconductor-on-insulator (SOI) substrate includes: a handle substrate; a charge trapping layer located on the handle substrate and comprising nitrogen-doped polysilicon; an insulating layer located on the charge trapping layer; and a semiconductor material layer located on the insulating layer. Nitrogen atoms in the charge trapping layer inhibit grain growth during an annealing process for forming the SOI substrate and during a subsequent high-temperature process for forming a semiconductor device on the semiconductor material layer. The slowing of grain growth reduces deformation of the SOI substrate and facilitates overlap of lithographic patterns during fabrication of the semiconductor device. The charge trapping layer inhibits the formation of a parasitic surface conduction layer and reduces capacitive coupling of the semiconductor device with the handle substrate during high frequency operation (e.g., operation in the gigahertz range).

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor-on-insulator substrate, a semiconductor structure and a method for forming the same. Background Art

[0002] A semiconductor-on-insulator (SOI) substrate includes a thin layer of semiconductor material layer, which is attached to a handle substrate via an intermediate insulating material layer. A shallow trench isolation structure formed through the semiconductor material layer can contact the insulating layer, thereby providing electrical isolation between semiconductor devices. In addition, the insulating layer provides electrical isolation between the semiconductor material layer and the handle substrate. However, there is capacitive coupling between the semiconductor material layer and the handle substrate. To reduce capacitive coupling, a high resistivity semiconductor layer can be used for the handle substrate. Summary of the invention

[0003] According to some embodiments of the present disclosure, a semiconductor-on-insulator substrate includes: a processing substrate; a nitrogen-doped polysilicon layer located on the processing substrate; an insulating layer located on the nitrogen-doped polysilicon layer; and a semiconductor material layer located on the insulating layer.

[0004] In some embodiments, a semiconductor structure includes: a semiconductor-on-insulator substrate, including a stack from bottom to top comprising a processing substrate, a nitrogen-doped polysilicon layer, an insulating layer, and a semiconductor material layer; and at least one semiconductor device located within or on the semiconductor material layer.

[0005] In some embodiments, a method for forming a semiconductor structure includes: depositing a polysilicon material layer on the top surface of a processing substrate; converting the polysilicon material layer into a nitrogen-doped polysilicon layer; forming an insulating layer on top of the nitrogen-doped polysilicon layer; attaching a semiconductor material layer to the top surface of the insulating layer; and forming at least one semiconductor device in or on the semiconductor material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1Ais a vertical cross-sectional view of an exemplary structure including a handle substrate for forming a radio frequency semiconductor-on-insulator (RFSOI) semiconductor structure according to an embodiment of the present disclosure.

[0008] Figure 1B is a vertical cross-sectional view of an exemplary structure after forming a collector region of an optional bipolar transistor according to an embodiment of the present disclosure.

[0009] Figure 1C is a vertical cross-sectional view of an exemplary structure after depositing a layer of polysilicon material on a top surface of a handle substrate according to an embodiment of the present disclosure.

[0010] Figure 1D is a vertical cross-sectional view of an exemplary structure after an optional thinning process to thin the polysilicon material layer according to an embodiment of the present disclosure.

[0011] Figure 1E is a vertical cross-sectional view of an exemplary structure after an ion implantation process of implanting nitrogen ions into a polysilicon material layer to form a charge trapping layer according to an embodiment of the present disclosure.

[0012] Figure 1F is a vertical cross-sectional view of an exemplary structure after an annealing process of annealing a charge trap layer according to an embodiment of the present disclosure.

[0013] Figure 2 is a graph schematically illustrating the effect of implanted nitrogen atoms in a charge trap layer on suppressing grain size growth during a subsequent annealing process according to an embodiment of the present disclosure.

[0014] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming an insulating layer by thermally oxidizing an upper portion of a charge trap layer according to an embodiment of the present disclosure.

[0015] Figure 4A is Figure 1F Schematic diagram of the polycrystalline grain structure near the top surface of the charge trapping layer after the process steps shown.

[0016] Figure 4B is Figure 3 Schematic diagram of a polycrystalline grain structure at the interface with an insulating layer after the process steps shown.

[0017] Figure 5A is a vertical cross-sectional view of an exemplary structure after an optional step of thinning the insulating layer according to an embodiment of the present disclosure.

[0018] Figure 5B is a vertical cross-sectional view of an exemplary structure after forming an extrinsic base region of an optional bipolar transistor according to an embodiment of the present disclosure.

[0019] Figure 5C is a vertical cross-sectional view of an exemplary structure after forming a base cavity of an optional bipolar transistor according to an embodiment of the present disclosure.

[0020] Figure 5D is a vertical cross-sectional view of an exemplary structure after forming an epitaxial base region and a polycrystalline base material region of an optional bipolar transistor according to an embodiment of the present disclosure.

[0021] Figure 5E is a vertical cross-sectional view of an exemplary structure after forming an emitter region of an optional bipolar transistor according to an embodiment of the present disclosure.

[0022] Figure 6 FIG. 4 is a vertical cross-sectional view of a source substrate including a semiconductor material layer and a hydrogen implantation layer according to an embodiment of the present disclosure.

[0023] Figure 7 is a vertical cross-sectional view of an exemplary structure after transferring a layer of semiconductor material from a source substrate to an assembly of a handle substrate, a charge trapping layer, and an insulating layer according to an embodiment of the present disclosure.

[0024] Figure 8 is a vertical cross-sectional view of an exemplary structure after optional thinning and / or planarization of the semiconductor material layer according to an embodiment of the present disclosure.

[0025] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a shallow trench isolation structure according to an embodiment of the present disclosure.

[0026] Fig.10 is a vertical cross-sectional view of an exemplary structure after forming a complementary metal-oxide-semiconductor (CMOS) transistor according to an embodiment of the present disclosure.

[0027] Fig.11 is a vertical cross-sectional view of an exemplary structure after forming passive devices, contact-level dielectric layers, and contact via structures according to an embodiment of the present disclosure.

[0028] Fig.12is a vertical cross-sectional view of an exemplary structure after forming an interconnect-level dielectric layer, metal interconnect structures, and additional passive devices according to an embodiment of the present disclosure.

[0029] Fig.13 is a process flow diagram showing steps of forming a RFSOI semiconductor structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The present disclosure relates generally to semiconductor devices, and more particularly to a radio frequency semiconductor-on-insulator (RFSOI) semiconductor structure including a nitrogen-doped charge trapping layer and a method of manufacturing the same.

[0031] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed "above" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed in itself.

[0032] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0033] Reference Figure 1A , Figure 1A A handle substrate 10 is shown for forming a semiconductor on insulator (SOI) substrate of the present disclosure. The handle substrate 10 may have a high resistivity. The high resistivity may be used to reduce capacitive coupling between the handle substrate 10 and a semiconductor material layer that may be subsequently formed on the handle substrate 10. The DC resistivity of the semiconductor material (e.g., single crystal silicon) in the handle substrate 10 may range from 3.0×10 2 Ω-cm to 3.0×10 4Ω-cm range (e.g. from 1.0×10 3 Ω-cm to 1.0×10 4 Ω-cm range), but lower DC resistivity and higher DC resistivity may also be used. DC resistivity refers to the resistivity of a material under direct current (DC) electrical bias conditions. Such high DC resistivity of the handle substrate 10 may be provided by using a single crystal semiconductor material with a very low electrical doping level. For example, the handle substrate 10 may include a single crystal semiconductor material with a doping level ranging from 3.0×10 11 / cm 3 to 3.0×10 13 / cm 3 range (e.g. from 1.0×10 12 / cm 3 to 1.0×10 13 / cm 3 The present invention relates to single crystal silicon with an electrical dopant (which may be a p-type dopant or an n-type dopant) having an atomic concentration of about 100 to about 1000 Å (in the range of about 100 to about 1000 Å), but lower atomic concentrations of electrical dopants and higher atomic concentrations of electrical dopants may also be used. The electrical dopant may be a p-type electrical dopant (e.g., boron) or an n-type electrical dopant (e.g., phosphorus, arsenic, and / or antimony). Other dopants may be used consistent with the intended scope of the present disclosure.

[0034] The thickness of the handle substrate 10 may be selected to provide adequate mechanical support for the layers and structures that may be subsequently formed on the handle substrate 10. In one embodiment, the thickness of the handle substrate 10 may range from 100 microns to 2 mm, but lesser and greater thicknesses of handle substrates may be used. In one embodiment, the entire handle substrate 10 may be single crystalline. In one embodiment, the handle substrate 10 may include and / or may consist of single crystalline silicon. The conductivity type of the handle substrate 10 is referred to herein as the first conductivity type, which may be p-type or n-type. In one embodiment, the handle substrate 10 may include and / or may consist of a commercial silicon substrate having a diameter of, for example, 200 mm, 300 mm, or 450 mm and having a diameter ranging from 3.0×10 2 Ω-cm to 3.0×10 4 The DC resistivity may be in the range of Ω-cm, but lower DC resistivities and higher DC resistivities may also be used.

[0035] When the SOI substrate is subsequently to be used in applications requiring high device isolation levels (e.g., radio frequency devices) or high Q factor passive components (e.g., resonance circuits), it may be desirable to use a high DC resistivity material when forming the handle substrate 10. The high DC resistivity of the handle substrate 10 also enables the fabrication of various hybrid devices, including complementary metal oxide semiconductor (CMOS) devices, bipolar devices, and / or passive devices (e.g., resistors, diodes, thyristors, capacitors, varactors, inductors, antennas, etc.).

[0036] The high DC resistivity of the handle substrate 10 may be provided by a low level of electrical dopants in the handle substrate 10. The high DC resistivity of the handle substrate 10 may provide adequate electrical decoupling from semiconductor devices that may be subsequently formed in the semiconductor material layer. However, at high frequencies, different mechanisms may contribute to increasing the capacitive coupling between the handle substrate 10 and semiconductor devices that may be subsequently formed in or above the overlying semiconductor material layer. Specifically, a parasitic surface conduction layer may be formed at a surface portion of the handle substrate 10 adjacent to an interface with an insulating layer that may be subsequently formed. In other words, when the insulating layer is formed in a subsequent process step, a surface layer of free charge carriers may be formed below the interface between the handle substrate 10 comprising a single crystalline semiconductor material and the insulating layer. The insulating layer typically comprises silicon oxide, and the formation of fixed oxide charges in the insulating layer may cause the formation of a parasitic surface conduction layer at high frequencies (e.g., 1 GHz or above). The parasitic surface conduction layer may dominate the conductivity of the handle substrate 10 at high frequencies (e.g., 1 GHz or above) and limit the effective resistivity of the handle substrate 10 to below 200 Ω-cm, regardless of the DC resistivity of the handle substrate 10. High performance of radio frequency semiconductor-on-insulator (RFSOI) devices requires higher effective resistivity of the handle substrate.

[0037] The parasitic surface conduction layer may act as an accumulation layer or an inversion layer depending on the type of charge present in the overlying insulating layer. High frequency voltage signals that may be generated in a semiconductor device that may subsequently be formed in a semiconductor material layer overlying the insulating layer interact with the parasitic surface conduction layer to generate eddy currents. Such interactions may cause device crosstalk and / or nonlinear distortion, resulting in radio frequency signal loss. Such crosstalk and signal loss may be significant in a frequency range above 1 GHz (e.g., a frequency range from 1 GHz to 100 GHz).

[0038] According to an embodiment of the present disclosure, a charge trapping layer that may be subsequently formed provides charge trapping for free charges generated in the processing substrate 10. By keeping the free charges in the processing substrate immobile, the charge trapping layer of the present disclosure can reduce the capacitive coupling between the semiconductor device subsequently formed in the semiconductor material layer and the processing substrate 10. Therefore, the signal fidelity of the subsequently formed semiconductor device can be improved. According to another embodiment of the present disclosure, nitrogen atoms can be implanted into the charge trapping layer. By implanting nitrogen ions into the charge trapping layer, grain growth in the charge trapping layer can be suppressed during a subsequent annealing process. Suppressing grain growth during a subsequent annealing process reduces structural deformation (e.g., warping of the SOI substrate) and enables various device features to be photolithographically patterned within a reduced overlap deviation relative to a previously patterned structure in a subsequent process step.

[0039] Reference Figure 1B , in embodiments where it may be desirable to form a bipolar transistor, the process steps may be optionally performed. For example, a patterned implant mask layer 13 (e.g., a photolithographically patterned photoresist layer) may be formed over the top surface of the handle substrate 10. The patterned implant mask layer 13 includes an opening located in an area where the collector region 12 may subsequently be formed. In embodiments where the handle substrate 10 includes a dopant of a first conductivity type, a dopant of a second conductivity type may be implanted into a surface region of the handle substrate 10 located below the opening in the patterned implant mask layer 13. The second conductivity type is opposite to the first conductivity type. For example, the first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The collector region 12 may be formed below the opening in the patterned implant mask layer 13. Although the present disclosure is explained using an embodiment in which only a single collector region 12 is shown, it should be understood that the patterned implant mask layer 13 may be a photoresist layer patterned in a lithography step having multiple lithography exposure fields, each lithography exposure field including a pattern of at least one semiconductor die (which may be a single semiconductor die or multiple semiconductor dies), and each pattern of semiconductor dies may include a pattern of a single collector region 12 or a pattern of multiple collector regions 12. As such, multiple repetitions of each illustrative pattern in the drawings of the present application on the same handle substrate 10 are expressly contemplated.

[0040] The depth of the pn junction formed between the collector region 12 and the semiconductor material of the first conductivity type in the handle substrate 10 may be in the range of from 300 nm to 2,000 nm (e.g., from 600 nm to 1,200 nm), although smaller depths or greater depths may also be used. The average dopant concentration of the second conductivity type dopant in the collector region 12 may be in the range of from 3×10 15 / cm3 to 3×10 18 / cm 3 The range of the average dopant concentration of the second conductivity type may be within the range of the average dopant concentration of the second conductivity type, but smaller average dopant concentrations and larger average dopant concentrations may also be used. The vertical distribution of the atomic concentration of the dopant of the second conductivity type may be optimized to enhance the performance of the subsequently formed bipolar transistor. The patterned implant mask layer 13 may then be removed, for example, by ashing. The area of ​​ion implantation may be limited to the area in which the collector region 12 is formed to minimize the formation of a highly conductive material region in the handle substrate 10.

[0041] Reference Figure 1C , a polysilicon material layer 22 may be formed on the top surface of the handle substrate 10. The polysilicon material layer 22 may be formed by a conformal deposition process or a non-conformal deposition process. In one embodiment, the polysilicon material layer 22 may be formed by a chemical vapor deposition process using a silicon-containing precursor gas (e.g., silane, disilane, and / or dichlorosilane). For example, the polysilicon material layer 22 may be formed by a low pressure chemical vapor deposition (LPCVD) process, a rapid thermal chemical vapor deposition (RTCVD) process, or a plasma-enhanced chemical vapor deposition (PECVD) process. Depending on the silicon-containing precursor gas used in the deposition process and depending on the partial pressure of the silicon-containing precursor gas, the deposition temperature of the chemical vapor deposition process may be in a range from 550 degrees Celsius to 700 degrees Celsius. In an illustrative example, in the case of using silane as a silicon-containing precursor gas, the deposition temperature may be in the range of from 600 degrees Celsius to 670 degrees Celsius, but lower deposition temperatures and higher deposition temperatures may also be used. In general, the polycrystalline silicon material layer 22 may be deposited at a temperature at which polycrystalline silicon is deposited. In other words, since the amorphous silicon may be converted into polycrystalline silicon having an average grain size larger than that of the polycrystalline silicon material deposited as the polycrystalline silicon material, the deposition of amorphous silicon may be avoided, and the amorphous silicon may be subsequently annealed, which incidentally increases the average grain size. The initial thickness t0 of the polycrystalline silicon material layer 22 may be in the range of from 550 nm to 4,000 nm (e.g., from 750 nm to 3,500 nm), but smaller thicknesses and larger thicknesses may also be used.

[0042] In one embodiment, the polysilicon material layer 22 may be substantially free of electrical dopants (e.g., p-type dopants and n-type dopants), or may have low levels of electrical dopants. In one embodiment, the polysilicon material layer 22 may be deposited as an undoped polysilicon material layer, i.e., a polysilicon material layer without any intentional doping. Therefore, during the deposition process, any electrical dopants in the polysilicon material layer 22 are unintentionally introduced as impurities. If the collector region 12 is present, some autodoping may occur in the portion of the polysilicon material layer 22 adjacent to the collector region 12. In one embodiment, the average atomic concentration of the electrical dopants in the polysilicon material layer 22 may be less than 3.0×10 13 / cm 3 For example, the average atomic concentration of the electrical dopant in the polysilicon material layer 22 may be in the range of 1.0×10 10 / cm 3 to 3.0×10 13 / cm 3 In the range (e.g. from 1.0×10 11 / cm 3 to 1.0×10 13 / cm 3 range), but smaller average atomic concentrations of electrical dopants or larger average atomic concentrations of electrical dopants may also be used.

[0043] The polycrystalline silicon material layer 22 may include crystal grains having a mixed crystal orientation. The grain boundaries generally extend along the growth direction (i.e., the vertical direction). The average grain size of the polycrystalline silicon material layer 22 may be determined by obtaining a horizontal cross-sectional view of the polycrystalline silicon material layer, counting the number of grains in a region with a statistically significant number of grains (e.g., 1,000 or more than 1,000), calculating the average grain area by dividing the area of ​​the region by the total number of grains, and calculating the diameter of a circle having the same area as the average grain area. In one embodiment, the average grain size of the polycrystalline silicon material layer 22 may be in the range from 20 nm to 100 nm, but smaller average grain sizes and larger average grain sizes may also be used. In one embodiment, the average grain size of the polycrystalline silicon material layer 22 may gradually increase with the vertical distance from the processing substrate 10, for example, by about 20% relative to the thickness of the polycrystalline silicon material layer 22.

[0044] The grain boundaries in the polysilicon material layer 22 provide localized states for charge carriers of the semiconductor material of the polysilicon material layer 22. Therefore, free charge carriers diffusing from the handle substrate 10 toward the polysilicon material layer 22 occupy localized electron states at the grain boundaries and are trapped within the polysilicon material layer 22. Therefore, the polysilicon material layer 22 acts as a charge trapping layer for free charge carriers in the handle substrate 10, and thus has the effect of depleting free charge carriers from the handle substrate 10.

[0045] Reference Figure 1D The polysilicon material layer 22 may be optionally thinned, for example, by a chemical mechanical planarization (CMP) process. A touch-up polishing process may be used to provide a smooth top surface for the polysilicon material layer 22. In this document, the thickness of the polysilicon material layer 22 after the planarization process is referred to as a first thickness t1, which is less than the initial thickness t0. The first thickness t1 may be in a range from 550 nm to 3,250 nm (e.g., from 750 nm to 3,000 nm), but smaller thicknesses and larger thicknesses may also be used.

[0046] Reference Figure 1E , nitrogen ions may be implanted into the polysilicon material layer 22. Hereinafter, the polysilicon material layer 22 having the implanted nitrogen ions therein is referred to as the charge trapping layer 20. The total dose of nitrogen ions during the nitrogen ion implantation process may be selected such that the average atomic concentration of nitrogen atoms in the charge trapping layer 20 is between 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3 In the range (e.g. from 1.0×10 17 / cm 3 to 5.0×10 19 / cm 3 ), but a smaller average atomic concentration of nitrogen atoms or a larger average atomic concentration of nitrogen atoms may also be used. The dose of the implanted nitrogen ions may be selected so that a sufficient number of nitrogen ions are present in the charge trapping layer 20 to prevent grain growth in the nitrogen-doped polysilicon material of the charge trapping layer 20 during a subsequent high temperature process (e.g., an annealing process). In an embodiment in which the charge trapping layer 20 has a thickness in a range from 500 nm to 3,800 nm, the total dose of nitrogen ions during the nitrogen ion implantation process may be in a range from 5.0×10 11 / cm 3 to 3.8×10 16 / cm 3The total dose of nitrogen atoms may be within the following range: Subsequently, the range may prevent the grain size of the polycrystalline material in the charge trapping layer 20 from being significantly changed during a subsequent annealing process. The energy of the implanted nitrogen ions may be within the range from 0.5 MeV to 50 MeV, but smaller implant energies and larger implant energies may also be used. The nitrogen ion implantation process may include multiple implantation steps with different target depths and therefore different implantation energies to provide relatively uniform nitrogen atom doping throughout the charge trapping layer 20. In one embodiment, the target depth and dose of each of the multiple implantation steps in the nitrogen ion implantation process may be selected so that the overall variation of the atomic concentration of nitrogen ions within the charge trapping layer 20 as a function of the vertical distance from the processing substrate 10 is within 50% (e.g., within 30% and / or within 20%) of the average atomic concentration of nitrogen atoms in the charge trapping layer 20. In one embodiment, the atomic concentration of nitrogen atoms in the charge trapping layer is within a range from 70% of the average atomic concentration of nitrogen atoms to 130% of the average atomic concentration of nitrogen atoms.

[0047] In one embodiment, the charge trapping layer 20 may consist essentially of silicon atoms and nitrogen atoms. In this case, the charge trapping layer 20 does not contain electrical dopants, or contains electrical dopants at a trace level (e.g., an atomic concentration of less than one part per million). Thus, the charge trapping layer consists essentially of silicon atoms and nitrogen atoms, but may contain electrical dopants at a trace level. In one embodiment, the atomic concentration of all other elements in the charge trapping layer 20 other than silicon atoms and nitrogen atoms may be less than 3.0×10 13 / cm 3 The substantial absence of electrical dopants within the charge trapping layer 20 has the beneficial effect of removing a source of free charge carriers and, therefore, has the effect of increasing the resistivity of the charge trapping layer 20. As a result, capacitive coupling between the charge trapping layer 20 and semiconductor devices subsequently formed in or on a layer of semiconductor material formed above the charge trapping layer 20 may be reduced.

[0048] Optionally, in addition to nitrogen ions, additional non-electrical dopants other than nitrogen atoms may be implanted. Such non-electrical dopants may help the implanted nitrogen atoms suppress grain growth in the charge trapping layer during subsequent high temperature process steps. Such optional non-electrical dopants may include carbon atoms, argon atoms, chlorine atoms, and / or bromine atoms. A single type of additional non-electrical dopant or multiple types of additional non-electrical dopants may be used. The total atomic concentration of the additional non-electrical dopants may range from 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3 In the range (e.g. from 1.0×10 17 / cm3 to 5.0×10 19 / cm 3 ), but smaller atomic concentrations or larger atomic concentrations may also be used. In one embodiment, the average atomic concentration of nitrogen atoms in charge trapping layer 20 may be greater or less than the average atomic concentration of the additional non-electrical dopant in charge trapping layer 20.

[0049] Reference Figure 1F , an annealing process may be performed at a high temperature to stabilize the polycrystalline grain structure in the charge trapping layer 20 during a subsequent high temperature annealing process. The high temperature may be in a range from 600 degrees Celsius to 1,050 degrees Celsius (e.g., from 800 degrees Celsius to 1,025 degrees Celsius). In one embodiment, the high temperature may be in a range from 900 degrees Celsius to 1,000 degrees Celsius. The duration of the annealing process performed at a high temperature may be in a range from 30 minutes to 60 hours, but shorter annealing durations and longer annealing durations may also be used. In one embodiment, the annealing temperature may be selected to be approximately the same as the highest annealing temperature employed in a subsequent process step. In such an embodiment, the subsequent annealing process is performed under operating parameters that do not introduce any further changes in the grain structure of the charge trapping layer 20. Generally speaking, a higher annealing temperature is maintained for a shorter annealing process duration, and a lower annealing temperature is maintained for a longer annealing process duration. The purpose of subjecting the charge trap layer 20 to the annealing process in this process step is to induce possible structural changes in this process step that would otherwise occur in the subsequent high-temperature process step. In other words, the annealing process can accelerate the structural changes in the charge trap layer 20 and the warping of the processed substrate accompanying this process step, rather than causing such changes to occur in a later process step.

[0050] According to one aspect of the present disclosure, the presence of nitrogen atoms in the charge trap layer 20 may have the effect of suppressing grain growth during the annealing process. Figure 2 , curve 210 schematically illustrates the ratio of the average grain size after annealing of the undoped polysilicon material to the average grain size during deposition. Curve 220 schematically illustrates the ratio of the average grain size after annealing of the nitrogen-doped polysilicon material of the charge trapping layer 20 that can be used in various embodiments to the average grain size during deposition. For each annealing process, the annealing duration at the annealing temperature is approximately 40 minutes. The undoped polysilicon material of curve 210 is substantially composed of silicon atoms in polycrystalline form. As the annealing temperature increases, the grain size can increase by nearly 4 times. The nitrogen-doped polysilicon material of curve 220 shows that the grain size growth can be less than 20% even after annealing at approximately 900 degrees Celsius. Although Figure 2The graph shown is intended only to illustrate the general trend of average grain size change, however it is apparent that the implanted nitrogen is effective in suppressing grain growth in the charge trap layer 20 .

[0051] Reference Figure 3 , a thermal oxidation process may be performed to oxidize a surface portion of the charge trapping layer 20 into an insulating layer 30 comprising thermal silicon oxide. Thermal silicon oxide is a stoichiometric silicon oxide substantially free of hydrogen atoms. In embodiments where the additional implanted ions in the charge trapping layer 20 do not include carbon atoms, the thermal silicon oxide of the insulating layer 30 may be substantially free of carbon atoms. A wet oxidation process or a dry oxidation process may be performed to convert a surface portion of the charge trapping layer 20 into the insulating layer 30. The temperature of the oxidation process may be in a range from 800 degrees Celsius to 1,100 degrees Celsius. The temperature of the oxidation process may be selected to be approximately the same as the highest processing temperature in a subsequent process step to prevent subsequent grain size changes in the charge trapping layer 20 in a subsequent process step.

[0052] The thickness of the insulating layer 30 may be in the range of from 50 nm to 600 nm (e.g., from 100 nm to 500 nm), but smaller thicknesses and larger thicknesses may also be used. In this article, the thickness of the charge trapping layer 20 thinned by the oxidation process is referred to as the second thickness t2. The second thickness t2 may be in the range of from 500 nm to 3,000 nm, but smaller thicknesses and larger thicknesses may also be used. The thermal oxidation process has the incidental effect of providing further annealing to the nitrogen-doped polysilicon material in the charge trapping layer 20, and thus stabilizing the microcrystalline structure of the nitrogen-doped polysilicon material in the charge trapping layer 20. Generally speaking, before forming a semiconductor device (e.g., a field effect transistor) on the semiconductor material layer, the charge trapping layer 20 may be annealed at a high temperature in the range of from 900 degrees Celsius to 1,100 degrees Celsius for a duration in the range of from 10 seconds to 120 minutes in a dedicated annealing process or a thermal oxidation process that incidentally provides an annealing process.

[0053] Figure 4A and Figure 4B The microstructural changes of the topmost portion of the charge trapping layer 20 during the thermal oxidation process of forming the insulating layer 30 are shown. Figure 4A Shown in Figure 1F The polycrystalline grain structure near the top surface of the charge trapping layer after the process steps are shown. Figure 4B Shown in Figure 3 Polycrystalline grain structure at the interface with the insulating layer after the process steps are shown.

[0054] Generally speaking, Figure 3During the thermal oxidation process shown, oxygen atoms diffuse along the grain boundaries of the charge trapping layer 20. Therefore, in addition to the generally horizontal interface between the charge trapping layer 20 and the insulating layer 30, which can be used to define the thickness of the charge trapping layer 20 and the thickness of the insulating layer 30, the interface between the insulating layer 30 and the charge trapping layer 20 includes a downwardly protruding thermally oxidized silicon portion extending toward the handle substrate 10 along the grain boundary. Thermal annealing generally reduces the grain boundaries in the polysilicon material by silicon-silicon self-interstitial diffusion and generates tensile stresses on the surrounding material portions. The thermally oxidized silicon formed by thermal oxidation of silicon expands the volume of the conversion portion by introducing oxygen atoms and thus applies a compressive element to the surrounding material portions. Therefore, the interface between the thermally oxidized silicon and the nitrogen-free polysilicon material that is prone to grain growth will provide an unstable interface that is prone to further oxidation and further grain growth due to the complementary stresses in the thermally oxidized silicon and the undoped polysilicon material.

[0055] According to an embodiment of the present disclosure, nitrogen atoms in the charge trapping layer can inhibit grain growth in the charge trapping layer 20. Therefore, the charge trapping layer 20 implanted with nitrogen can prevent the mutual influence of complementary stresses between the thermal silicon oxide material and the nitrogen-doped polysilicon material. Therefore, the interface between the thermal silicon oxide and the nitrogen-doped polysilicon material of the charge trapping layer 20 can be stabilized. To avoid being bound by any particular theory, the implanted nitrogen atoms are believed to accumulate at the grain boundaries in the nitrogen-doped polysilicon material of the charge trapping layer 20 and delay the inter-grain oxidation of the nitrogen-doped polysilicon material. Therefore, in the charge trapping layer 20 of the present disclosure, the vertical extent of the downwardly protruding thermal silicon oxide portion extending along the grain boundaries toward the processing substrate 10 can be smaller than the vertical extent in an undoped polysilicon material layer having the same thickness and subjected to the same thermal oxidation process.

[0056] Reference Figure 5A The insulating layer 30 comprising and / or consisting essentially of thermal silicon oxide may be optionally thinned, for example, by polishing and / or by etching (e.g., wet etching or dry etching). After this process step, the thickness of the insulating layer 30 may be in the range from 50 nm to 500 nm (e.g., from 100 nm to 400 nm), although smaller thicknesses and larger thicknesses may also be used.

[0057] Reference Figure 5BA patterned implant mask layer 23 (e.g., a photolithographically patterned photoresist layer) may be optionally formed over the insulating layer 30. The patterned implant mask layer 23 includes an opening in an area within the periphery of the collector region 12. Dopants of the first conductivity type may be implanted into the underlying portion of the charge trapping layer 20 through the openings in the patterned implant mask layer 23 to form a doped semiconductor region having the first conductivity type doping, the doped semiconductor region serving as an optional bipolar transistor non-intrinsic base region 26. The non-intrinsic base region 26 may or may not contact the top surface of the collector region 12. The atomic concentration of the dopant of the first conductivity type in the non-intrinsic base region 26 may be between 5.0×10 19 / cm 3 to 1.0×10 20 / cm 3 The dopant concentration of the implant mask layer 23 may be removed by ashing, for example.

[0058] Reference Figure 5C A patterned etch mask layer 27 (e.g., a photolithographically patterned photoresist layer) may be optionally formed over the insulating layer 30. The patterned etch mask layer 27 may include openings in an area within the periphery of the extrinsic base region 26. An anisotropic etch process may be performed to etch through the insulating layer 30 and the unmasked portions of the extrinsic base region 26 and physically expose the top surface of the collector region 12. A base cavity 21 extending from the top surface of the insulating layer 30 to the top surface of the collector region 12 may be formed through the insulating layer 30 and the charge trapping layer 20. In one embodiment, the base cavity 21 may have vertical sidewalls or tapered sidewalls. The patterned etch mask layer 27 may then be removed, for example, by ashing.

[0059] Reference Figure 5D, a semiconductor epitaxy process may be performed to grow a doped semiconductor material having a first conductivity type doping from the physically exposed semiconductor surfaces of the collector region 12 and the charge trapping layer 20. The semiconductor epitaxy process is a growth process for depositing a single crystal semiconductor material on a physically exposed semiconductor surface. The semiconductor epitaxy process deposits a polycrystalline semiconductor material on a physically exposed polycrystalline semiconductor surface. The semiconductor epitaxy process may be a selective semiconductor epitaxy process or a non-selective semiconductor epitaxy process. The selective semiconductor epitaxy process is a semiconductor deposition process that grows a single crystal semiconductor material from a physically exposed single crystal semiconductor surface while suppressing the growth of semiconductor material from a physically exposed dielectric surface. In such an embodiment, an etchant (e.g., gaseous hydrogen chloride) may be flowed into the process chamber from an insulating surface (e.g., the surface of insulating layer 30) at a rate that etches the nucleated semiconductor material, while or in lieu thereof, a reactant (e.g., silane or disilane) is flowed into the process chamber from an insulating surface (e.g., the surface of insulating layer 30) at a rate that etches the nucleated semiconductor material. A non-selective semiconductor epitaxial process is a semiconductor deposition process that deposits single crystalline semiconductor material from physically exposed single crystalline semiconductor surfaces while simultaneously depositing polycrystalline semiconductor material on polycrystalline semiconductor surfaces and dielectric surfaces.

[0060] The semiconductor epitaxial process may form an epitaxial base region 25 epitaxially aligned with the collector region 12 on the physically exposed top surface of the collector region 12, and form a polycrystalline base material layer 24L on the physically exposed surface of the charge trapping layer 20. If the semiconductor epitaxial process is a non-selective semiconductor epitaxial process, the polycrystalline base material layer 24L grows from the physically exposed sidewalls of the charge trapping layer 20 and from the physically exposed surface of the insulating layer. If the semiconductor epitaxial process is a selective semiconductor epitaxial process, the polycrystalline material may grow only from the physically exposed surface of the charge trapping layer 20, while inhibiting the polycrystalline material from growing from the physically exposed surface of the insulating layer 30. Although the present disclosure is explained using the example of a non-selective semiconductor epitaxial process, embodiments in which a selective semiconductor epitaxial process is used are expressly contemplated herein.

[0061] The thickness of epitaxial base region 25 may be in the range of 40 nm to 300 nm (e.g., 60 nm to 150 nm), although smaller thicknesses and larger thicknesses may also be used. The average atomic concentration of the first conductivity type dopant in epitaxial base region 25 may be in the range of 1.0×10 15 / cm3 to 3.0×10 17 / cm 3 , but a smaller average atomic concentration and a larger average atomic concentration of the first conductivity type dopant may be used in the epitaxial base region 25. The vertical distribution of the first conductivity type dopant in the epitaxial base region 25 may be optimized for the performance of the bipolar transistor.

[0062] Dielectric spacers may be formed on the sidewalls of the polycrystalline base material layer 24L by conformal deposition of a dielectric material layer and subsequent anisotropic etching of horizontal portions of the dielectric material layer. The remaining tubular portion of the dielectric material layer includes dielectric spacers, which are referred to herein as emitter pedestal spacers 28. The emitter pedestal spacers 28 may include a dielectric material such as silicon oxide and / or silicon nitride.

[0063] Reference Figure 5E , a doped semiconductor material having a second conductivity type doping may be deposited in the remaining volume of the base cavity 21. A surface oxide having a thickness ranging from 0.3 nm to 1.0 nm may be formed at the interface between the epitaxial base region 25 and the deposited doped semiconductor material. In one embodiment, the deposited doped semiconductor material may include doped polysilicon having a thickness ranging from 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 The atomic concentration within the range of includes dopants of the second conductivity type, but smaller atomic concentrations and larger atomic concentrations may also be used. Excess portions of the deposited doped semiconductor material and polycrystalline base material layer 24L may be removed from above a horizontal plane including the top surface of the insulating layer 30 by a planarization process, which may use chemical mechanical planarization and / or recess etching. The remaining portion of the doped semiconductor material located in the base cavity 21 and laterally surrounded by the emitter base spacer 28 includes an emitter region 32. The remaining tubular portion of the polycrystalline base material layer 24L includes the polycrystalline base material region 24. The emitter base spacer 28 prevents direct contact between the emitter region 32 and the polycrystalline base material region 24, thereby reducing leakage current.

[0064] The combination of the collector region 12, the epitaxial base region 25, the polycrystalline base material region 24, the extrinsic base region 26, and the emitter region 32 comprises a bipolar transistor 122. The bipolar transistor 122 may include the collector region 12 formed within the handle substrate 10, the epitaxial base region 25 in contact with the top surface of the collector region 12 and formed within the charge trapping layer 20, and the emitter region 32 in contact with the top surface of the epitaxial base region 25 and laterally surrounded by the charge trapping layer 20. Forming the bipolar transistor 122 in the combination of the handle substrate 10, the charge trapping layer 20, and the insulating layer 30 may be useful for some RFSOI devices, but may be omitted for some other RFSOI devices to reduce production costs.

[0065] Reference Figure 6 , Figure 6 A source substrate 110 is shown, which includes a semiconductor material layer 40 to be transferred to a combination of a handle substrate 10, a charge trapping layer 20, and an insulating layer 30. Specifically, the source substrate 110 may include a carrier substrate 120, the semiconductor material layer 40, and a hydrogen implantation layer 130 located at a boundary between the carrier substrate 120 and the semiconductor material layer 40. The source substrate 110 may be formed by providing a single crystal semiconductor substrate (e.g., a commercial single crystal silicon wafer), and implanting hydrogen through a front surface of the single crystal semiconductor substrate at a dose sufficient to form the hydrogen implantation layer 130. A lower portion (i.e., a bulk portion) of the single crystal semiconductor substrate located below the hydrogen implantation layer 130 includes the carrier substrate 120, and an upper portion (i.e., a surface portion) of the single crystal semiconductor substrate overlying the hydrogen implantation layer 130 includes the semiconductor material layer 40, which may include and / or consist of a single crystal semiconductor material (e.g., single crystal silicon). The depth of the hydrogen implanted layer 130 may range from 10 nm to 300 nm, although lesser thicknesses and greater thicknesses may also be used.

[0066] Reference Figure 7 , the semiconductor material layer 40 may be bonded to the top surface of the insulating layer 30 by semiconductor-oxide bonding. For example, the source substrate 110 may be disposed to the top surface of the insulating layer 30 so that the semiconductor material layer 40 contacts the top surface of the insulating layer 30. The first annealing process may be performed at a first high temperature to promote semiconductor-oxide bonding between the semiconductor material of the semiconductor material layer 40 and the silicon oxide material of the insulating layer 30. The first high temperature may be in a range from 150 degrees Celsius to 400 degrees Celsius (e.g., from 250 degrees Celsius to 350 degrees Celsius). Optionally, pressure may be applied to press the assembly of the handle substrate 10, the charge trap layer 20, and the insulating layer 30 toward the source substrate 110.

[0067] Subsequently, a second annealing process may be performed at a second high temperature to cause the hydrogen-filled cavities within the hydrogen implantation layer 130 to merge into a continuous cavity. The second high temperature may be in the range of 400 degrees Celsius to 600 degrees Celsius. A process generally referred to as a "Smart Cut process" may be used. The source substrate 110 may be divided into two separate parts, a carrier substrate 120 and a semiconductor material layer 40. The carrier substrate 120 may be removed, and the carrier substrate 120 may be reused as another source substrate when another hydrogen implantation layer is formed in the carrier substrate 120. The semiconductor material layer 40 is bonded to the insulating layer 30 to provide a semiconductor on an insulator (SOI) substrate (10, 20, 30, 40). The semiconductor material layer 40 may include and / or be composed of single crystal silicon, and may have a thickness in the range of 10 nm to 300 nm, but a smaller thickness or a larger thickness may also be used. In general, the thickness of the semiconductor material layer 40 may be selected so that a suitable semiconductor device can be formed on the semiconductor material layer 40. In one embodiment, the thickness of the semiconductor material layer 40 may range from 30 nm to 100 nm, although smaller thicknesses and larger thicknesses may also be used.

[0068] Reference Figure 8 The semiconductor material layer 40 of the SOI substrate (10, 20, 30, 40) may be optionally thinned, for example, by polishing. The root-mean-square (RMS) roughness of the top surface of the semiconductor material layer 40 may be reduced by the thinning process. After the thinning process, the thickness of the semiconductor material layer 40 may be in the range from 50 nm to 500 nm, but smaller thicknesses and larger thicknesses may also be used.

[0069] Reference Fig. 9, various shallow trench isolation structures 140 may be formed in the semiconductor material layer 40. For example, shallow trenches extending in the vertical direction to the top surface of the insulating layer 30 through the semiconductor material layer 40 may be formed at the boundaries of various semiconductor device regions. For example, the shallow trenches may be formed to laterally surround each combination of the body region, source region, and drain region of the subsequently formed field effect transistor. In addition, shallow trenches may be formed at each periphery of the bipolar transistor and the subsequently formed passive devices. A dielectric material (e.g., silicon oxide) may be deposited in the shallow trenches, and excess portions of the dielectric material may be removed from above the horizontal plane including the top surface of the semiconductor material layer 40. The remaining portions of the dielectric material include the shallow trench isolation structures 140. The shallow trench isolation structures 140 may laterally enclose discrete patterned portions of the semiconductor material layer 40 and may contact the top surface of the insulating layer 30. P-type dopants and / or n-type dopants may be implanted into respective discrete patterned portions of semiconductor material layer 40 to form at least one p-well 42 and / or at least one n-well 44 in a complementary metal oxide semiconductor (CMOS) device region.

[0070] Reference Fig.10 , a gate dielectric layer may be formed, for example, by thermally oxidizing a surface portion of the semiconductor material layer 40 (including a surface portion of the p-well 42 and the n-well 44). A gate electrode material layer (which may include polysilicon and / or at least one metal material) may be deposited over the gate dielectric layer. In an embodiment in which the gate electrode material layer includes polysilicon, a material region of the polysilicon material used as the gate electrode may be appropriately implanted with a p-type dopant or an n-type dopant. The gate electrode material layer and the gate dielectric layer may then be patterned, for example, by applying a photoresist layer over the gate electrode material layer and patterning the photoresist layer into a pattern of a gate electrode, and anisotropically etching the unmasked portions of the gate electrode material layer and the gate dielectric layer. Each patterned portion of the gate dielectric layer includes a gate dielectric 52, and each patterned portion of the gate electrode material layer includes a gate electrode 54.

[0071] Gate spacers 56 may be formed on the sidewalls of each gate structure (52, 54) including gate dielectric 52 and gate electrode 54. P-type dopants may be implanted into portions of n-well 44 not masked by gate structures (52, 54) before and / or after forming gate spacers 56 to form p-doped active regions 64 including p-doped source regions and p-doped drain regions. N-type dopants may be implanted into portions of p-well 42 not masked by gate structures (52, 54) before and / or after forming gate spacers 56 to form n-doped active regions 62 including n-doped source regions and n-doped drain regions. NPN transistors 162 and PNP transistors 164 may be formed in the CMOS device region.

[0072] Compared to comparative exemplary samples using nitrogen-free polysilicon as the charge trapping layer, wafer deformation measurements of samples including the charge trapping layer 20 including nitrogen-doped polysilicon of the disclosed embodiments showed that wafer warpage was significantly reduced by about 80%. The reduction in wafer warpage can be attributed to the suppression of grain growth in the charge trapping layer 20 and the reduction of stress generated by the charge trapping layer 20 and applied to the semiconductor material layer 40. In addition, testing of field effect transistors using the methods of the disclosed embodiments showed tighter threshold voltage distributions for various field effect transistors, which is attributed to enhanced registration of the photolithographic patterns and pre-existing alignment patterns used to pattern the gate structures of the field effect transistors.

[0073] Reference Fig.11 , a contact-level dielectric layer 70 may be formed over the field effect transistors (162, 164), and the contact-level dielectric layer 70 may be planarized to provide a level top surface. Contact via structures (78, 178) may be formed to various nodes of the optional bipolar transistor 122 and the field effect transistors (162, 164). For example, the contact via structures (78, 178) may include CMOS device contact via structures 78 contacting various nodes of the field effect transistors (162, 164) and bipolar device contact via structures 178 contacting various nodes of the optional bipolar transistor 122. An insulating liner 176 may be used to electrically isolate each bipolar device contact via structure 178 from surrounding conductive material portions or semiconductor material portions, which may include a semiconductor material layer 40 and a charge trapping layer 20. Passive devices 66 (e.g., resistors, diodes, and thyristors) may be formed in, on, or over the semiconductor material layer.

[0074] Reference Fig.12 , an interconnect-level dielectric layer 80 may be formed above the contact-level dielectric layer 70. A metal interconnect structure 88 may be formed in the interconnect-level dielectric layer 80. The interconnect-level dielectric layer may include, from bottom to top, a first line-level dielectric layer, a first via-level dielectric layer, a second line-level dielectric layer, a second via-level dielectric layer, a third line-level dielectric layer, a third via-level dielectric layer, and the like. The metal interconnect structure 88 may include a first metal line formed in the first line-level dielectric layer, a first via structure formed in the first via-level dielectric layer, a second metal line formed in the second line-level dielectric layer, a second via structure formed in the second via-level dielectric layer, a third metal line formed in the third line-level dielectric layer, a third via structure formed in the third via-level dielectric layer, and the like. A bonding structure (e.g., a metal pad) may be formed at the topmost level of the interconnect-level dielectric layer 80.

[0075] Additional passive devices (92, 94) may be formed within the interconnect level dielectric layer 80. The additional passive devices (92, 94) may include, for example, capacitors, varactors, inductors, and antennas. Specifically, inductors and capacitors may be provided to enable a resonant circuit to operate with an antenna.

[0076] In general, at least one semiconductor device may be formed on and / or in the semiconductor material layer 40. The at least one semiconductor device may include a field effect transistor configured to operate in a frequency range from 1 GHz to 100 GHz. In addition, the at least one semiconductor device may include a radio frequency circuit including at least one capacitor and at least one inductor and configured to operate in a frequency range from 1 GHz to 100 GHz. The atomic concentration of nitrogen atoms in the charge trapping layer 20 may be substantially uniform. For example, in the final device, the atomic concentration of nitrogen atoms in the charge trapping layer 20 may be in a range from 70% of the average atomic concentration of nitrogen atoms in the charge trapping layer 20 to 130% of the average atomic concentration of nitrogen atoms. In one embodiment, in the final device, the atomic concentration of nitrogen atoms in the charge trapping layer 20 may be in a range from 85% of the average atomic concentration of nitrogen atoms in the charge trapping layer 20 to 115% of the average atomic concentration of nitrogen atoms.

[0077] Reference Fig.13 , a flow chart shows the process steps of the embodiment of the present disclosure that can be used to form an RFSOI semiconductor structure according to the embodiment of the present disclosure. Referring to step 1310, a polysilicon material layer 22 can be deposited on the top surface of the handle substrate 10. Referring to step 1320, nitrogen ions can be implanted into the polysilicon material layer 22 to form a charge trapping layer 20 including nitrogen-doped polysilicon. Referring to step 1330, an insulating layer 30 can be formed on the charge trapping layer 20. Referring to step 1340, a semiconductor material layer 40 can be attached to the top surface of the insulating layer 30. Referring to step 1350, at least one semiconductor device can be formed in or on the semiconductor material layer 40.

[0078] With reference to all drawings and according to various embodiments of the present disclosure, a semiconductor-on-insulator (SOI) substrate (10, 20, 30, 40) is provided, the semiconductor-on-insulator substrate (10, 20, 30, 40) comprising: a handle substrate 10; a charge trapping layer 20 (which is a nitrogen-doped polysilicon layer), located on the handle substrate 10 and comprising nitrogen-doped polysilicon; an insulating layer 30, located on the charge trapping layer 20; and a semiconductor material layer 40, located on the insulating layer 30.

[0079] According to another embodiment of the present disclosure, a semiconductor structure is provided, which includes: a semiconductor on insulator (SOI) substrate (10, 20, 30, 40), including, from bottom to top, a stack of a processing substrate 10, a charge trapping layer 20 including nitrogen-doped polysilicon (which is a nitrogen-doped polysilicon layer), an insulating layer 30, and a semiconductor material layer 40; and at least one semiconductor device located in or on the semiconductor material layer 40.

[0080] According to another embodiment of the present disclosure, a method for forming a semiconductor structure is provided. The embodiment method may include the step of depositing a polysilicon material layer on the top surface of a processing substrate 10. The method also includes the steps of: converting the polysilicon material layer into a nitrogen-doped polysilicon charge trapping layer 20; forming an insulating layer 30 on the nitrogen-doped polysilicon charge trapping layer 20; attaching a semiconductor material layer 40 on the top surface of the insulating layer 30; and forming at least one semiconductor device in or on the semiconductor material layer 40.

[0081] Various embodiments of the present disclosure pin free charge carriers in the handle substrate 10 at the grain boundaries of the charge trapping layer 20. In addition, the charges in the charge trapping layer 20 can be trapped in localized states at the grain boundaries. Thus, free charges that can respond to high frequency electric fields can be removed from under the insulating layer 30, and the effective resistivity of the combination of the handle substrate 10 and the charge trapping layer 20 can be between 3.0×10 2 Ω-cm to 3.0×10 4 The range of Ω-cm is not only for DC device characteristics, but also for operating frequencies above 1 GHz (e.g., in the range from 1 GHz to 100 GHz). By reducing the free charge carriers in the process substrate 10 and the charge trapping layer 20, the eddy currents in the process substrate 10 and the charge trapping layer 20 can be significantly reduced. The crosstalk and nonlinear distortion of the signals in the semiconductor device can be minimized, and the signal fidelity in the semiconductor circuit on the semiconductor material layer 40, especially the signal fidelity of high frequency operation, can be enhanced. In addition, by implanting nitrogen ions into the charge trapping layer 20, the grain growth in the charge trapping layer 20 during the subsequent annealing process can be suppressed. Suppressing grain growth during the subsequent annealing process reduces structural deformation (e.g., warping of the SOI substrate), and enables the photolithographic patterning of various device features within a reduced overlay deviation relative to the previously patterned structure in the subsequent process steps. Thus, the SOI may be thermally stable and may reduce structural deformation, such as warping (bow) of the SOI substrate, which may occur during subsequent process steps that subject the substrate to higher thermal temperatures.

[0082] According to some embodiments of the present disclosure, a semiconductor-on-insulator substrate includes: a processing substrate; a nitrogen-doped polysilicon layer located on the processing substrate; an insulating layer located on the nitrogen-doped polysilicon layer; and a semiconductor material layer located on the insulating layer.

[0083] In some embodiments, the nitrogen-doped polysilicon layer has a thickness between 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3 In some embodiments, the nitrogen-doped polysilicon layer has an atomic concentration of nitrogen atoms in a range from 70% of the average atomic concentration of the nitrogen atoms to 130% of the average atomic concentration of the nitrogen atoms. In some embodiments, the handle substrate includes a single crystal silicon layer having an average atomic concentration of from 3.0×10 2 Ω-cm to 3.0×10 4 In some embodiments, the insulating layer comprises thermal silicon oxide and has a thickness in the range of 50 nm to 500 nm; and the semiconductor material layer comprises single crystal silicon and has a thickness in the range of 10 nm to 300 nm. In some embodiments, the interface between the insulating layer and the nitrogen-doped polysilicon layer comprises a downwardly protruding thermal silicon oxide portion extending toward the handle substrate along a grain boundary.

[0084] In some embodiments, a semiconductor structure includes: a semiconductor-on-insulator substrate, including a stack from bottom to top comprising a processing substrate, a nitrogen-doped polysilicon layer, an insulating layer, and a semiconductor material layer; and at least one semiconductor device located within or on the semiconductor material layer.

[0085] In some embodiments, the nitrogen-doped polysilicon layer has a thickness between 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3 In some embodiments, the nitrogen-doped polysilicon layer has a thickness ranging from 500 nm to 3,000 nm. In some embodiments, the handle substrate includes a single crystal silicon layer having a thickness ranging from 3.0×10 2 Ω-cm to 3.0×10 4In some embodiments, the at least one semiconductor device comprises a field effect transistor configured to operate in a frequency range from 1 GHz to 100 GHz. In some embodiments, the at least one semiconductor device comprises a radio frequency circuit, the radio frequency circuit comprising at least one capacitor and at least one inductor and configured to operate in a frequency range from 1 GHz to 100 GHz. In some embodiments, a bipolar transistor is also included, which includes a collector region formed in the processing substrate, an epitaxial base region that contacts the top surface of the collector region and is formed in the nitrogen-doped polysilicon layer, and an emitter region that contacts the top surface of the epitaxial base region and is laterally surrounded by the nitrogen-doped polysilicon layer.

[0086] In some embodiments, a method for forming a semiconductor structure includes: depositing a polysilicon material layer on the top surface of a processing substrate; converting the polysilicon material layer into a nitrogen-doped polysilicon layer; forming an insulating layer on top of the nitrogen-doped polysilicon layer; attaching a semiconductor material layer to the top surface of the insulating layer; and forming at least one semiconductor device in or on the semiconductor material layer.

[0087] In some embodiments, converting the polysilicon material layer into a nitrogen-doped polysilicon layer comprises: implanting nitrogen ions into the polysilicon material layer. In some embodiments, the total dose of the nitrogen ions implanted into the polysilicon material layer is selected so that the nitrogen-doped polysilicon layer has a total dose of between 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3The method further comprises: annealing the nitrogen-doped polysilicon layer at a high temperature ranging from 900 degrees Celsius to 1,100 degrees Celsius for a duration ranging from 10 seconds to 120 minutes before forming the at least one semiconductor device in or on the semiconductor material layer. In some embodiments, the insulating layer is formed by thermally oxidizing a top portion of the nitrogen-doped polysilicon layer into a thermally oxidized silicon layer.

[0088] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor-on-insulator substrate, characterized in that include: processing substrates; a nitrogen-doped polysilicon layer located on the handle substrate; an insulating layer over the nitrogen-doped polysilicon layer, wherein an atomic concentration of nitrogen atoms in the nitrogen-doped polysilicon layer varies as a function of vertical distance from the handle substrate, the atomic concentration varying within 30% of an average atomic concentration of the nitrogen atoms in the nitrogen-doped polysilicon layer; and The semiconductor material layer is located on the insulating layer.

2. The semiconductor-on-insulator substrate according to claim 1, wherein the nitrogen-doped polysilicon layer has a thickness between 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3 The average atomic concentration in the range includes nitrogen atoms.

3. The semiconductor-on-insulator substrate according to claim 1, wherein the handle substrate comprises a single-crystal silicon layer having a thickness ranging from 3.0×10 2 Ω-cm to 3.0×10 4 The handle substrate has a DC resistivity in the range of Ω-cm, and the handle substrate has a thickness in the range of from 100 μm to 2 mm.

4. The semiconductor-on-insulator substrate according to claim 1, wherein: The insulating layer comprises thermal silicon oxide and has a thickness ranging from 50 nm to 500 nm; and The semiconductor material layer includes single crystal silicon and has a thickness ranging from 10 nm to 300 nm. 5 . The semiconductor-on-insulator substrate of claim 4 , wherein an interface between the insulating layer and the nitrogen-doped polysilicon layer comprises a downwardly protruding thermal silicon oxide portion extending along a grain boundary toward the handle substrate.

6. A semiconductor structure, characterized in that include: A semiconductor-on-insulator substrate comprises, from bottom to top, a stack of a handle substrate, a nitrogen-doped polysilicon layer, an insulating layer, and a semiconductor material layer; as well as at least one semiconductor device located in or on the semiconductor material layer, The semiconductor structure also includes a bipolar transistor, which includes a collector region formed in the processing substrate, an epitaxial base region that contacts the top surface of the collector region and is formed in the nitrogen-doped polysilicon layer, and an emitter region that contacts the top surface of the epitaxial base region and is laterally surrounded by the nitrogen-doped polysilicon layer.

7. The semiconductor structure according to claim 6, wherein the nitrogen-doped polysilicon layer has a thickness between 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3 The average atomic concentration in the range includes nitrogen atoms.

8. The semiconductor structure of claim 6, wherein the nitrogen-doped polysilicon layer has a thickness ranging from 500 nm to 3,000 nm.

9. The semiconductor structure according to claim 6, wherein the handle substrate comprises a single crystal silicon layer having a thickness ranging from 3.0×10 2 Ω-cm to 3.0×10 4 The handle substrate has a DC resistivity in the range of Ω-cm, and the handle substrate has a thickness in the range of from 100 μm to 2 mm.

10. The semiconductor structure of claim 6, wherein: The insulating layer comprises thermal silicon oxide and has a thickness ranging from 50 nm to 500 nm; The semiconductor material layer comprises single crystal silicon and has a thickness ranging from 10 nm to 300 nm; and An interface between the insulating layer and the nitrogen-doped polysilicon layer includes a downwardly protruding thermal silicon oxide portion extending along a grain boundary toward the handle substrate.

11. The semiconductor structure of claim 6, wherein the at least one semiconductor device comprises a field effect transistor configured to operate in a frequency range from 1 GHz to 100 GHz.

12. The semiconductor structure of claim 6, wherein the at least one semiconductor device comprises a radio frequency circuit comprising at least one capacitor and at least one inductor and configured to operate in a frequency range from 1 GHz to 100 GHz.

13. A method for forming a semiconductor structure, characterized in that include: depositing a layer of polysilicon material on a top surface of a handle substrate; converting the layer of polysilicon material into a nitrogen-doped polysilicon layer, wherein an atomic concentration of nitrogen atoms in the nitrogen-doped polysilicon layer varies as a function of vertical distance from the handle substrate, the atomic concentration varying within 30% of an average atomic concentration of nitrogen atoms in the nitrogen-doped polysilicon layer; forming an insulating layer on the nitrogen-doped polysilicon layer; Laminating a semiconductor material layer on the top surface of the insulating layer; as well as At least one semiconductor device is formed in or on the semiconductor material layer.

14. The method for forming a semiconductor structure according to claim 13, wherein converting the polysilicon material layer into a nitrogen-doped polysilicon layer comprises: Nitrogen ions are implanted into the polysilicon material layer.

15. The method for forming a semiconductor structure according to claim 14, wherein the total dose of nitrogen ions implanted into the polysilicon material layer is selected so that the nitrogen-doped polysilicon layer has a total dose of between 1.0×10 16 / cm 3 to 1.0×10 20 / cm 3 The average atomic concentration in the range includes nitrogen atoms. 16 . The method for forming a semiconductor structure according to claim 14 , wherein the nitrogen ions are implanted into the polysilicon material layer using a plurality of nitrogen implantation processes having different average ion implantation depths.

17. The method for forming a semiconductor structure according to claim 13, further comprising: Prior to forming the at least one semiconductor device in or on the semiconductor material layer, the nitrogen-doped polysilicon layer is annealed at an elevated temperature ranging from 900 degrees Celsius to 1,100 degrees Celsius for a duration ranging from 10 seconds to 120 minutes. 18 . The method for forming a semiconductor structure according to claim 13 , wherein the insulating layer is formed by thermally oxidizing a top portion of the nitrogen-doped polysilicon layer into a thermal silicon oxide layer.

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