Integrated circuit design method, device and equipment

Abstract

The present application provides an integrated circuit design method, device and equipment, which relates to the field of integrated circuit technology. The method includes: laying out and routing the target integrated circuit to obtain the layout information and routing information of the target integrated circuit; performing timing analysis on the layout information and routing information of the target integrated circuit to obtain the timing analysis result, and the timing analysis result includes the hold time between multiple devices in the target integrated circuit; when the hold time violation between the first device and the second device among the multiple devices is determined, and the number of repairs i corresponding to the hold time violation between the first device and the second device obtained by the counter is less than a preset threshold, inserting a delay module between the first device and the second device; wherein the component model library includes a delay module and a counter, and the use state of the delay module is an unused state. According to the embodiment of the present application, the occupation of routing resources can be reduced, and the deterioration of hold time violations in integrated circuits can be avoided.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit design method, device and equipment. Background Art

[0002] In integrated circuit design, the main factors that determine the operating speed and design area of ​​the integrated circuit are the following: production process, code writing style, and the physical implementation process from code to layout. In the physical implementation process from code to layout, timing analysis is one of the most important key steps. Timing analysis can determine whether there is a hold time violation between the devices of the integrated circuit. If the hold time is violated, the function of the integrated circuit will be wrong, so the hold time violation between the devices needs to be repaired.

[0003] At present, buffers are usually inserted in the target area of ​​the integrated circuit to repair the hold time violation. However, since the design process of the integrated circuit includes: netlist generation and layout, layout timing optimization, clock tree construction, hold time repair, routing and post-routing timing optimization, layout output and other stages. Therefore, inserting buffers to repair hold time violations is performed before the clock tree is built. At this time, the integrated circuit has been optimized many times, and the routing resources of the critical timing part are tight, resulting in insufficient space to insert buffers during the hold time repair stage, or the newly inserted buffer can only be placed far away from the target area, which will occupy more routing resources, and the winding or long routing is more susceptible to coupling noise, resulting in worsening of hold time violations in the integrated circuit. Summary of the invention

[0004] The embodiments of the present application provide an integrated circuit design method, device and equipment, which can reduce the occupation of routing resources and avoid the deterioration of hold time violations in the integrated circuit.

[0005] In a first aspect, an embodiment of the present application provides an integrated circuit design method, which is applied to an integrated circuit design platform, wherein the integrated circuit design platform includes a component model library;

[0006] Placing and routing the target integrated circuit to obtain layout information and routing information of the target integrated circuit;

[0007] Performing timing analysis on layout information and routing information of the target integrated circuit to obtain a timing analysis result, wherein the timing analysis result includes a hold time between multiple devices in the target integrated circuit;

[0008] When a hold time violation between a first device and a second device among multiple devices is determined, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by a counter is less than a preset threshold, a delay module is inserted between the first device and the second device to repair the hold time violation between the first device and the second device; wherein the component model library includes a delay module and a counter, and the usage state of the delay module is an unused state.

[0009] In a possible implementation, inserting a delay module between the first device and the second device includes:

[0010] Calculating a target number of delay modules required for holding time violation repair according to a holding time between the first device and the second device, a preset holding time threshold, and a delay value of the delay module;

[0011] When it is detected that the number of delay modules is not less than the target number, the target number of delay modules is inserted between the first device and the second device.

[0012] In a possible implementation, the method further includes:

[0013] In a case where it is detected that the number of delay modules is less than the target number, a distance between the first device and the second device is increased.

[0014] In a possible implementation manner, after increasing the distance between the first device and the second device, the method further includes:

[0015] Update layout information;

[0016] Based on the updated layout information, update the wiring information;

[0017] Based on the updated layout information and the updated routing information, the process jumps to performing timing analysis on the layout information and the routing information of the target integrated circuit to obtain a timing analysis result until the hold time violation between the first device and the second device is repaired.

[0018] In a possible implementation manner, after inserting a target number of delay modules between the first device and the second device, the method further includes:

[0019] Update layout information;

[0020] Based on the updated layout information, update the wiring information;

[0021] Based on the updated layout information and the updated routing information, the process jumps to performing timing analysis on the layout information and the routing information of the target integrated circuit to obtain a timing analysis result until the hold time violation between the first device and the second device is repaired.

[0022] In a possible implementation, after inserting a target number of delay modules between the first device and the second device, the method further includes:

[0023] The update and repair times i is i+1.

[0024] In a possible implementation, after performing timing analysis on the layout information and routing information of the target integrated circuit to obtain the timing analysis result, the method further includes:

[0025] When a hold time violation between a first device and a second device among multiple devices is determined, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is not less than a preset threshold, a prompt message is generated, and the prompt message is used to prompt a user to manually modify the layout and wiring of the target integrated circuit.

[0026] In a possible implementation, the method further includes:

[0027] The use status corresponding to the delay module inserted between the first device and the second device is updated to a used status.

[0028] In a second aspect, an embodiment of the present application provides an integrated circuit design device, which is applied to an integrated circuit design platform, the integrated circuit design platform includes a component model library, and the device includes:

[0029] A design module, used for layout and routing of a target integrated circuit, and obtaining layout information and routing information of the target integrated circuit;

[0030] An analysis module, used to perform timing analysis on the layout information and routing information of the target integrated circuit to obtain a timing analysis result, wherein the timing analysis result includes a hold time between multiple devices in the target integrated circuit;

[0031] A repair module is used to insert a delay module between the first device and the second device to repair the hold time violation between the first device and the second device when a hold time violation between a first device and a second device among multiple devices is determined and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by a counter is less than a preset threshold value; wherein the component model library includes a delay module and a counter, and the use state of the delay module is an unused state.

[0032] In a possible implementation, the repair module is used to:

[0033] Calculating a target number of delay modules required for holding time violation repair according to a holding time between the first device and the second device, a preset holding time threshold, and a delay value of the delay module;

[0034] When it is detected that the number of delay modules is not less than the target number, the target number of delay modules is inserted between the first device and the second device.

[0035] In a possible implementation, the device further includes:

[0036] The increasing module is used to increase the distance between the first device and the second device when it is detected that the number of the delay modules is less than the target number.

[0037] In a possible implementation manner, the device further includes a first updating module, configured to:

[0038] Update layout information;

[0039] Based on the updated layout information, update the wiring information;

[0040] Based on the updated layout information and the updated routing information, the process jumps to performing timing analysis on the layout information and the routing information of the target integrated circuit to obtain a timing analysis result until the hold time violation between the first device and the second device is repaired.

[0041] In a possible implementation manner, the device further includes a second updating module, configured to:

[0042] Update layout information;

[0043] Based on the updated layout information, update the wiring information;

[0044] Based on the updated layout information and the updated routing information, the process jumps to performing timing analysis on the layout information and the routing information of the target integrated circuit to obtain a timing analysis result until the hold time violation between the first device and the second device is repaired.

[0045] In a possible implementation, the device further includes:

[0046] The update and repair times i is i+1.

[0047] In one possible implementation, the device also includes a generation module for generating a prompt message when a hold time violation between a first device and a second device among multiple devices is determined and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is not less than a preset threshold, wherein the prompt message is used to prompt a user to manually modify the layout and routing of the target integrated circuit.

[0048] In a possible implementation manner, the apparatus further includes a fourth updating module, configured to update a usage status corresponding to the delay module inserted between the first device and the second device to a used status.

[0049] In a third aspect, an embodiment of the present application provides a computer device, including:

[0050] at least one memory for storing a program;

[0051] At least one processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method in the first aspect or any possible implementation of the first aspect.

[0052] In a fourth aspect, an embodiment of the present application provides a computer storage medium, in which instructions are stored. When the instructions are executed on a computer, the computer executes the method in the first aspect or any possible implementation of the first aspect.

[0053] The integrated circuit design method, device and equipment provided by the embodiment of the present application are applied to an integrated circuit design platform, the integrated circuit design platform includes a component model library, the target integrated circuit is laid out and routed, and the layout information and routing information of the target integrated circuit are obtained; the layout information and routing information of the target integrated circuit are subjected to timing analysis to obtain timing analysis, and the timing analysis results include the hold time between multiple devices in the target integrated circuit; when the hold time violation between the first device and the second device among the multiple devices is determined, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is less than a preset threshold, a delay module is inserted between the first device and the second device to repair the hold time violation between the first device and the second device; wherein the component model library includes a delay module and a counter, and the use state of the delay module is an unused state. In this way, the occupation of routing resources is reduced, and the deterioration of the hold time violation in the integrated circuit is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic diagram of a flow chart of an integrated circuit design method provided in an embodiment of the present application is shown;

[0055] Figure 2 A schematic diagram showing a flow chart of another integrated circuit design method provided by an embodiment of the present application is shown;

[0056] Figure 3 A schematic diagram of the structure of an integrated circuit design device provided in an embodiment of the present application is shown;

[0057] Figure 4 A schematic diagram of the structure of a computer device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0059] In the description of the embodiments of the present application, words such as "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a concrete way.

[0060] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "multiple" means two or more. For example, multiple systems refers to two or more systems, and multiple screen terminals refers to two or more screen terminals.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprises", "has" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0062] In integrated circuit design, the main factors that determine the operating speed and design area of ​​the integrated circuit are the following: production process, code writing style, and the physical implementation process from code to layout. In the physical implementation process from code to layout, timing analysis is one of the most important key steps. Timing analysis can determine whether there is a hold time violation between the devices of the integrated circuit. If the hold time is violated, the function of the integrated circuit will be wrong, so the hold time violation between the devices needs to be repaired.

[0063] At present, buffers are usually inserted in the target area of ​​the integrated circuit to repair the hold time violation. However, since the design process of the integrated circuit includes: netlist generation and layout, layout timing optimization, clock tree construction, hold time repair, routing and post-routing timing optimization, layout output and other stages. Therefore, inserting buffers to repair hold time violations is performed before the clock tree is built. At this time, the integrated circuit has been optimized many times, and the routing resources of the critical timing part are tight, resulting in insufficient space to insert buffers during the hold time repair stage, or the newly inserted buffer can only be placed far away from the target area, so that the scan path will occupy more routing resources, increase the setup time violation of the functional path, and the winding or long routing is more susceptible to coupling noise, resulting in worsening of the hold time violation in the integrated circuit.

[0064] Based on this, the embodiments of the present application provide an integrated circuit design method, device and equipment, which can reduce the occupation of routing resources and avoid the deterioration of hold time violations in the integrated circuit.

[0065] The integrated circuit design method provided by the embodiment of the present application is applied to an integrated circuit design platform, wherein the integrated circuit design platform can design and wire the integrated circuit, etc., wherein the integrated circuit design platform includes a component model library, and the component model library includes a variety of component models, so that the design of the integrated circuit can be completed using the component model. After the design of the integrated integrated circuit is performed, the integrated circuit design platform will save the layout information and wiring information of the integrated circuit, so as to facilitate the timing analysis of the designed integrated circuit, and then determine whether there is a hold time violation phenomenon in the integrated circuit. If there is a hold time violation phenomenon in the integrated circuit, it is also necessary to repair the hold time violation of the integrated circuit. In order to improve the efficiency of the hold time violation repair and avoid excessive occupation of computing resources in the process of the hold time violation repair, it is also necessary to use the counter in the component model library to count the number of hold time violation repairs to avoid the number of hold time violation repairs exceeding the preset threshold. After the timing analysis is performed, the integrated circuit design platform provided by the embodiment of the present application can execute the integrated circuit design method provided by the embodiment of the present application.

[0066] In some embodiments, the integrated circuit design platform provided in the embodiments of the present application may be a computer device capable of performing integrated circuit design, or may be an application installed on the computer device.

[0067] The above is an introduction to the integrated circuit design platform provided in the embodiment of the present application. Figure 1 , the integrated circuit design method designed in the embodiment of the present application is introduced in detail.

[0068] Figure 1Schematic diagram of a flow chart of an integrated circuit design method provided in an embodiment of the present application. Figure 1 As shown, the integrated circuit design method provided in the embodiment of the present application may include S101-S103.

[0069] S101: Place and route a target integrated circuit to obtain layout information and routing information of the target integrated circuit.

[0070] Here, the integrated circuit design platform can automatically perform layout and routing of the target integrated circuit, thereby generating layout information and routing information of the target integrated circuit.

[0071] S102: Performing timing analysis on the layout information and routing information of the target integrated circuit to obtain a timing analysis result, wherein the timing analysis result includes a retention time between multiple devices in the target integrated circuit.

[0072] After the target integrated circuit is designed, the layout information and wiring information of the target integrated circuit can be generated according to the design of the target integrated circuit. Here, the layout information and wiring information of the target integrated circuit can be saved or cached. In order to measure the performance of the target integrated circuit, the layout information and wiring information of the target integrated circuit can also be subjected to timing analysis. For example, dynamic timing analysis and static timing analysis.

[0073] For example, static timing analysis is performed on the target integrated circuit. Specifically, all timing paths of the target integrated circuit can be extracted based on the layout information and wiring information of the target integrated circuit. Then, it is calculated whether there are errors that violate the timing constraints during the transmission of the signal on the timing path, such as setup time violation, hold time violation, etc., and then the result of the timing analysis is obtained. The setup time refers to the time when the data is stable before the rising edge of the trigger clock signal (assuming the rising edge sampling) arrives; the hold time refers to the time when the data is stable after the rising edge of the trigger clock signal (assuming the rising edge sampling) arrives (the data remains unchanged so that it can be stably read).

[0074] The timing analysis results may include the hold time between any two devices in the target integrated circuit and the devices with hold time violations. If there are hold time violations between devices, the hold time violations between the devices need to be repaired.

[0075] S103: When a hold time violation between a first device and a second device among multiple devices is determined, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is not less than a preset threshold, a prompt message is generated, and the prompt message is used to prompt a user to manually modify the layout and wiring of the target integrated circuit.

[0076] It can be determined whether the timing analysis result includes a hold time violation between devices in the target integrated circuit. When it is determined that the timing analysis result includes a hold time violation between the first device and the second device, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter, that is, the value i corresponding to the current counter is less than a preset threshold, a delay module is inserted between the first device and the second device where the hold time violation occurred. In this way, it is only necessary to insert a cache module between the first device and the second device after performing the timing analysis and determining that the timing analysis result includes a hold time violation between devices in the target integrated circuit, without the need to optimize the layout timing and build a clock tree, and even without inserting a buffer, to repair the hold time violation, reduce the occupation of routing resources, and avoid the deterioration of the hold time violation in the integrated circuit.

[0077] In some embodiments, the timing analysis results also include the hold time between multiple devices. In order to accurately repair the hold time violation, in S103, the target number of delay modules required for the hold time violation repair can also be calculated according to the hold time between the first device and the second device, the preset hold time threshold and the delay value of the delay module in the component model library; then, it is detected whether the number of delay modules in the component model library is greater than the target number. When it is detected that the number of unused delay modules in the component model library is not less than the target number, the target number of delay modules is inserted between the first device and the second device. Specifically, the difference between the hold time between the first device and the second device and the preset hold time threshold is calculated, and the quotient of the difference and the delay value of the delay module in the component model library is calculated to obtain the target number of delay modules required for the hold time violation repair. For example, if the target number is calculated to be 3, 3 delay modules are inserted between the first device and the second device. Among them, the delay module can be an input / output delay module or a display look-up table (LUT).

[0078] In some embodiments, after S103, the layout information of the target integrated circuit may be updated, and the target integrated circuit may be wired based on the updated layout information, and the wiring information of the target integrated circuit may be updated based on the rewired target integrated circuit. Then, the process jumps to S101, and S101-S103 are executed in a loop until the timing analysis result includes that the hold time between the first device and the second device meets the timing requirement.

[0079] In some embodiments, the number of delay modules in the component model library may also be less than the target number. In this case, the distance between the first device and the second device can be increased to repair the hold time violation between the first device and the second device. Specifically, after increasing the distance between the first device and the second device, the layout information and wiring information of the target integrated circuit can also be updated. First, the layout information of the target integrated circuit is updated, and then the wiring information of the target integrated circuit is updated based on the updated layout information. Finally, based on the updated layout information and the updated wiring information, jump to S101, and execute S101-S103 in a loop until the timing analysis results include that the hold time between the first device and the second device meets the timing requirements.

[0080] In some embodiments, in the case of a hold time violation between a first device and a second device, the hold time violation can be repaired by inserting a delay module between the first device and the second device. However, in order to avoid too many hold time violation repairs and occupying computing resources, the number of hold time violation repairs can be recorded by a counter. When the value recorded by the counter is greater than or equal to a preset threshold, the number of hold time violation repairs between the first device and the second device is too many, and the hold time violation between the first device and the second device still exists in the timing analysis result, then a prompt message is generated, and the prompt message is used to prompt the user to manually modify the layout and routing of the target integrated circuit, so as to repair the hold time violation between the first device and the second device.

[0081] Based on the above embodiments, the integrated circuit design scheme in the embodiments of the present application is exemplarily introduced below. In this example, the integrated circuit design scheme is Figure 1 The corresponding embodiments are corresponding. Figure 2 As shown, the integrated circuit design scheme provided in the embodiment of the present application includes S201-S211.

[0082] S201: Layout the target integrated circuit.

[0083] S202: Generate layout information of the target integrated circuit according to the layout of the target integrated circuit.

[0084] S203: wiring the target integrated circuit to obtain wiring information of the target integrated circuit.

[0085] S204: Performing timing analysis on the layout information and routing information of the target integrated circuit to obtain a timing analysis result.

[0086] S205: Determine whether there is a hold time violation in the timing analysis result. If there is a hold time violation, execute S206. If there is no hold time violation, the function of the target integrated circuit is normal.

[0087] S206: Check whether the value of the counter is less than a preset threshold, if so, execute S207, if not, execute S210.

[0088] S207: Calculate a target number of delay modules required for hold time violation repair according to the hold time between the first device and the second device in the timing analysis result, a preset hold time threshold, and delay values ​​of delay modules in the component model library.

[0089] S208: Determine whether the number of unused delay modules in the component model library is not less than the target number. If so, execute S209; if not, execute S211.

[0090] S209: inserting a target number of delay modules between the first device and the second device, and executing S202.

[0091] Here, jumping from S209 to S202 actually updates the layout information of the target integrated circuit based on the original layout information of the target integrated circuit, thereby obtaining new layout information.

[0092] S210: Generate prompt information, where the prompt information is used to prompt the user to manually modify the layout and routing of the target integrated circuit.

[0093] S211: Increase the distance between the first device and the second device, and execute S202.

[0094] Here, jumping from S211 to S202 actually updates the layout information of the target integrated circuit based on the original layout information of the target integrated circuit, thereby updating the distance between the first device and the second device into the layout information of the target integrated circuit to obtain new layout information of the target integrated circuit.

[0095] The integrated circuit design method provided by the embodiment of the present application is applied to an integrated circuit design platform, the integrated circuit design platform includes a component model library, the target integrated circuit is laid out and routed, and the layout information and routing information of the target integrated circuit are obtained; the layout information and routing information of the target integrated circuit are subjected to timing analysis to obtain timing analysis, and the timing analysis result includes the hold time between multiple devices in the target integrated circuit; when the hold time violation between the first device and the second device among the multiple devices is determined, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is less than a preset threshold, a delay module is inserted between the first device and the second device to repair the hold time violation between the first device and the second device; wherein the component model library includes a delay module and a counter, and the use state of the delay module is an unused state. In this way, the occupation of routing resources is reduced, and the deterioration of the hold time violation in the integrated circuit is avoided.

[0096] Based on the integrated circuit design method in the above embodiment, an embodiment of the present application also provides an integrated circuit design device. Figure 3 is a schematic diagram of the structure of an integrated circuit design device 300 provided in an embodiment of the present application, such as Figure 3 As shown, the integrated circuit design device 300 is applied to an integrated circuit design platform, and the integrated circuit design platform includes a component model library. The device 300 may include a design module 301 , an analysis module 302 , and a repair module 303 .

[0097] Design module 301, used for layout and routing of target integrated circuit, and obtaining layout information and routing information of the target integrated circuit;

[0098] An analysis module 302 is used to perform a timing analysis on the layout information and the routing information of the target integrated circuit to obtain a timing analysis result, wherein the timing analysis result includes a hold time between multiple devices in the target integrated circuit;

[0099] A repair module 303 is used to insert a delay module between a first device and a second device among the multiple devices to repair the hold time violation between the first device and the second device when a hold time violation between the first device and the second device obtained by a counter is less than a preset threshold value; wherein the component model library includes the delay module and the counter, and the usage state of the delay module is an unused state.

[0100] In a possible implementation, the repair module 303 is used to:

[0101] Calculating a target number of the delay modules required for holding time violation repair according to a holding time between the first device and the second device, a preset holding time threshold, and a delay value of the delay module;

[0102] In a case where it is detected that the number of the delay modules is not less than the target number, the target number of delay modules is inserted between the first device and the second device.

[0103] In a possible implementation, the device further includes:

[0104] The increasing module is used to increase the distance between the first device and the second device when it is detected that the number of the delay modules is less than the target number.

[0105] In a possible implementation manner, the device further includes a first updating module, configured to:

[0106] updating the layout information;

[0107] Based on the updated layout information, updating the wiring information;

[0108] Based on the updated layout information and the updated routing information, the process jumps to timing analysis of the layout information and the routing information of the target integrated circuit to obtain timing analysis results until the hold time violation between the first device and the second device is repaired.

[0109] In a possible implementation manner, the device further includes a second updating module, configured to:

[0110] updating the layout information;

[0111] Based on the updated layout information, updating the wiring information;

[0112] Based on the updated layout information and the updated routing information, the process jumps to timing analysis of the layout information and the routing information of the target integrated circuit to obtain timing analysis results until the hold time violation between the first device and the second device is repaired.

[0113] In a possible implementation, the device further includes:

[0114] Update the repair times i to i+1.

[0115] In one possible implementation, the device also includes a generation module for generating a prompt message when a hold time violation between a first device and a second device among the multiple devices is determined and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is not less than a preset threshold, wherein the prompt message is used to prompt a user to manually modify the layout and routing of the target integrated circuit.

[0116] In a possible implementation manner, the apparatus further includes a fourth updating module, configured to update a usage status corresponding to a delay module inserted between the first device and the second device to a used status.

[0117] The integrated circuit design device provided by the embodiment of the present application is applied to an integrated circuit design platform, the integrated circuit design platform includes a component model library, the target integrated circuit is laid out and routed, and the layout information and routing information of the target integrated circuit are obtained; the layout information and routing information of the target integrated circuit are subjected to timing analysis to obtain the timing analysis result, and the timing analysis result includes the hold time between multiple devices in the target integrated circuit; when the hold time violation between the first device and the second device among the multiple devices is determined, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is less than a preset threshold, a delay module is inserted between the first device and the second device to repair the hold time violation between the first device and the second device; wherein the component model library includes a delay module and a counter, and the use state of the delay module is an unused state. In this way, the occupation of routing resources is reduced, and the deterioration of the hold time violation in the integrated circuit is avoided.

[0118] A computer device provided in an embodiment of the present application is introduced below.

[0119] Figure 4 Schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 4 As shown, the computer device provided in the embodiment of the present application can be used to implement the integrated circuit design method described in the above method embodiment.

[0120] The computer device may include a processor 401 and a memory 402 storing computer program instructions.

[0121] Specifically, the processor 401 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0122] Memory 402 may include a large capacity memory for data or instructions. By way of example and not limitation, memory 402 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, memory 402 may include a removable or non-removable (or fixed) medium. In appropriate cases, memory 402 may be inside or outside of an integrated gateway disaster recovery device. In a specific embodiment, memory 402 is a non-volatile solid-state memory.

[0123] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods in the present application.

[0124] The processor 401 implements any one of the integrated circuit design methods in the above embodiments by reading and executing computer program instructions stored in the memory 402 .

[0125] In one example, the electronic device may further include a communication interface 404 and a bus 410. Figure 4 As shown, the processor 401, the memory 402, and the communication interface 404 are connected via a bus 410 and communicate with each other.

[0126] The communication interface 404 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0127] Bus 410 includes hardware, software or both, and the parts of electronic equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 410 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.

[0128] In addition, in combination with the above embodiments, the embodiments of the present application may provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any one of the integrated circuit design methods in the above embodiments is implemented.

[0129] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0130] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0131] The above reference is according to the method of the embodiment of the present application, the flow chart of the device (system) and the computer program product and / or the block diagram described various aspects of the present application.It should be understood that each square box in the flow chart and / or the block diagram and the combination of each square box in the flow chart and / or the block diagram can be realized by computer program instructions.These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the realization of the function / action specified in one or more square boxes of the flow chart and / or the block diagram.Such a processor can be but is not limited to a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit.It can also be understood that each square box in the block diagram and / or the flow chart and the combination of the square boxes in the block diagram and / or the flow chart can also be realized by the dedicated hardware that performs the specified function or action, or can be realized by the combination of dedicated hardware and computer instructions.

[0132] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. An integrated circuit design method, applied to an integrated circuit design platform, characterized in that: The integrated circuit design platform includes a component model library, and the method includes: Placing and routing the target integrated circuit to obtain layout information and routing information of the target integrated circuit; Performing timing analysis on the layout information and routing information of the target integrated circuit to obtain a timing analysis result, wherein the timing analysis result includes a hold time between multiple devices in the target integrated circuit; When a hold time violation between a first device and a second device among the multiple devices is determined, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is less than a preset threshold, a delay module is inserted between the first device and the second device to repair the hold time violation between the first device and the second device; wherein the component model library includes the delay module and the counter, and the usage state of the delay module is unused.

2. The method according to claim 1, characterized in that The inserting a delay module between the first device and the second device comprises: Calculating a target number of the delay modules required for holding time violation repair according to a holding time between the first device and the second device, a preset holding time threshold, and a delay value of the delay module; In a case where it is detected that the number of the delay modules is not less than the target number, the target number of delay modules is inserted between the first device and the second device.

3. The method according to claim 2, characterized in that The method further comprises: In case that it is detected that the number of the delay modules is less than the target number, a distance between the first device and the second device is increased.

4. The method according to claim 3, characterized in that After increasing the distance between the first device and the second device, the method further includes: updating the layout information; Based on the updated layout information, updating the wiring information; Based on the updated layout information and the updated routing information, the process jumps to timing analysis of the layout information and the routing information of the target integrated circuit to obtain timing analysis results until the hold time violation between the first device and the second device is repaired.

5. The method according to claim 2, characterized in that: After inserting the target number of delay modules between the first device and the second device, the method further includes: updating the layout information; Based on the updated layout information, updating the wiring information; Based on the updated layout information and the updated routing information, the process jumps to timing analysis of the layout information and the routing information of the target integrated circuit to obtain timing analysis results until the hold time violation between the first device and the second device is repaired.

6. The method according to claim 2, characterized in that After inserting the target number of delay modules between the first device and the second device, the method further includes: Update the repair times i to i+1.

7. The method according to claim 1, characterized in that After performing timing analysis on the layout information and routing information of the target integrated circuit to obtain the timing analysis result, the method further includes: When a hold time violation between a first device and a second device among the multiple devices is determined, and the number of repair times i corresponding to the hold time violation between the first device and the second device obtained by the counter is not less than a preset threshold, a prompt message is generated, and the prompt message is used to prompt a user to manually modify the layout and wiring of the target integrated circuit.

8. The method according to claim 2, characterized in that: After inserting the target number of delay modules between the first device and the second device, the method further includes: The usage status corresponding to the delay module inserted between the first device and the second device is updated to a used status.

9. An integrated circuit design device, applied to an integrated circuit design platform, characterized in that: The integrated circuit design platform includes a component model library, and the device includes: A design module, used for layout and routing of a target integrated circuit, and obtaining layout information and routing information of the target integrated circuit; An analysis module, configured to perform timing analysis on the layout information and routing information of the target integrated circuit to obtain a timing analysis result, wherein the timing analysis result includes a hold time between multiple devices in the target integrated circuit; A repair module for inserting a delay module between a first device and a second device among the plurality of devices to repair the hold time violation between the first device and the second device when a hold time violation between the first device and the second device obtained by a counter and corresponding to the repair number i of the hold time violation between the first device and the second device is less than a preset threshold; wherein the component model library includes the delay module and the counter, and the use state of the delay module is an unused state.

10. A computer device, characterized in that: include: at least one memory for storing a program; At least one processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method according to any one of claims 1 to 8.

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