Volatility storage device and data sensing method thereof

Abstract

A volatile storage device and a data sensing method thereof are provided. The volatile storage device includes: a first sense amplifier connected to a first storage cell via a first bit line and configured to sense 2 bits of data stored in the first storage cell; a second sense amplifier connected to a second storage cell via a second bit line and configured to sense 2 bits of data stored in the second storage cell, wherein the length of the second bit line is greater than the length of the first bit line; and a drive voltage supply circuit configured to supply a first drive voltage to the first sense amplifier and supply a second drive voltage to the second sense amplifier, wherein the voltage level of the second drive voltage is different from the voltage level of the first drive voltage.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0013733, filed on February 5, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to volatile storage devices and data sensing methods thereof, and more specifically, to volatile storage devices including a plurality of sense amplifiers and methods of operating the volatile storage devices. Background Technology

[0004] Dynamic Random Access Memory (DRAM) operates by writing and reading data based on the charge stored in the cell capacitors of the memory cells. With the increasing demand for high-capacity DRAM, there is a need to investigate storing at least two bits of data in a single DRAM cell, i.e., developing multi-level cells that store multiple bits of data. To realize multi-level cell DRAM, a readout amplifier capable of sensing the charge stored in the cell capacitors as multiple bits of data is required. Summary of the Invention

[0005] Embodiments of the present invention provide a volatile memory device capable of compensating for differences in sensing characteristics between sense amplifiers caused by length differences between bit lines, and a data sensing method for the volatile memory device.

[0006] According to one aspect of the embodiments, a volatile storage device is provided, comprising: a first sense amplifier connected to a first storage cell via a first bit line and configured to sense 2 bits of data stored in the first storage cell; a second sense amplifier connected to a second storage cell via a second bit line and configured to sense 2 bits of data stored in the second storage cell, wherein the length of the second bit line is greater than the length of the first bit line; and a drive voltage supply circuit configured to supply a first drive voltage to the first sense amplifier and supply a second drive voltage to the second sense amplifier, wherein the voltage level of the second drive voltage is different from the voltage level of the first drive voltage.

[0007] According to another aspect of the embodiments, a data sensing method for a volatile storage device is provided. The data sensing method includes: pre-charging a first bit line using a first pre-charge voltage; sensing first 2-bit data via a first sense amplifier connected to the first bit line, the first 2-bit data being stored in a first memory cell connected between the first bit line and a selected word line; pre-charging a second bit line using a second pre-charge voltage different from the first pre-charge voltage, the second bit line having a length greater than the first bit line; and sensing second 2-bit data via a second sense amplifier connected to the second bit line, the second 2-bit data being stored in a second memory cell connected between the second bit line and the selected word line.

[0008] According to another aspect of the embodiments, a data sensing method for a storage device is provided, the storage device including volatile storage cells storing unit data. The data sensing method includes: in a sensing operation of a first storage cell connected to a first storage cell having a first bit line of a first length, pre-charging the first bit line with a first pre-charging voltage; sensing first 1-bit data stored in the first storage cell; in a sensing operation of a second storage cell connected to a second storage cell having a second bit line of a second length longer than the first length, pre-charging the second bit line with a second pre-charging voltage; and sensing second 1-bit data stored in the second storage cell.

[0009] According to another aspect of the embodiments, a data sensing method for a storage device is provided, the storage device including volatile storage cells storing unit data. The data sensing method includes: in a sensing operation of a first storage cell connected to a first bit line, pre-charging the first bit line with a first pre-charge voltage; sensing first 1-bit data stored in the first storage cell; in a sensing operation of a second storage cell connected to a second bit line, pre-charging the second bit line with the first pre-charge voltage; boosting the voltage level of the second bit line to a second pre-charge voltage; and sensing second 1-bit data stored in the second storage cell.

[0010] According to another aspect of the present invention, a method for configuring sensing settings of a storage device is provided, the storage device including a first sense amplifier and a second sense amplifier. The method includes: performing test sensing on the first sense amplifier and the second sense amplifier based on various cell voltages; obtaining a first fault cell distribution with respect to the first sense amplifier and a second fault cell distribution with respect to the second sense amplifier based on the test sensing results; and determining a voltage level for a first drive voltage for the first sense amplifier and a voltage level for a second drive voltage for the second sense amplifier based on the first fault cell distribution and the second fault cell distribution. Attached Figure Description

[0011] The embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 A storage device according to an embodiment is shown;

[0013] Figure 2 A memory cell and a sense amplifier with an open bit line structure are shown according to an embodiment;

[0014] Figure 3 This is a diagram according to an embodiment for describing multi-bit data of a memory cell sensed by a sense amplifier;

[0015] Figure 4 A readout amplifier according to an embodiment is shown;

[0016] Figures 5A to 5D This is a flowchart illustrating the sequential operation of the readout amplifier according to an embodiment;

[0017] Figure 6 This is a timing diagram of the signal from the readout amplifier that senses the 2-bit data "00" according to an embodiment;

[0018] Figure 7 A storage device according to an embodiment is shown;

[0019] Figure 8 This is a diagram illustrating the qualified and faulty units in a readout amplifier according to an embodiment;

[0020] Figure 9 This is a diagram illustrating the types of driving voltages according to an embodiment;

[0021] Figure 10 This is a flowchart of the sensing operation of the storage device according to an embodiment;

[0022] Figure 11 This is a flowchart of the sensing operation of the storage device according to an embodiment;

[0023] Figure 12 This is a flowchart of the sensing operation of the storage device according to an embodiment;

[0024] Figure 13 This is a flowchart of the sensing operation of the storage device according to an embodiment;

[0025] Figure 14 This is a timing diagram of the signals of the storage device according to an embodiment;

[0026] Figure 15 This is a flowchart of a method for setting a drive voltage in a storage device according to an embodiment;

[0027] Figure 16 A readout amplifier according to an embodiment is shown;

[0028] Figure 17 This is a flowchart of the sequential operation method of the readout amplifier according to an embodiment;

[0029] Figure 18 This is a timing diagram of signals during sensing and pre-charging operations on the in-line according to an embodiment;

[0030] Figure 19 This is a timing diagram of signals during sensing and pre-charging operations on the in-line according to an embodiment. Detailed Implementation

[0031] In the following description, embodiments will be illustrated with reference to the accompanying drawings. Note that all embodiments described herein are exemplary embodiments.

[0032] Figure 1 A storage device 10 according to an embodiment is shown. Storage device 10 may include dynamic random access memory (DRAM) that senses the cell voltage Vcell stored in the storage cell MC as multi-bit data. Storage device 10 may be referred to as multi-level DRAM. For example, multi-level DRAM can be applied to memories such as synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, low power DDR SDRAM (LPDDR SDRAM), graphics DDR SDRAM (GDDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, etc.

[0033] Storage device 10 can output data DQ in response to commands CMD and addresses received from external devices such as a central processing unit (CPU) or a memory controller. Storage device 10 may include a memory cell array 100, a first sense amplifier 200_1, a second sense amplifier 200_2, a command decoder 300, an address buffer 400, an address decoder 500, control circuitry 600, and data input / output (I / O) circuitry 700.

[0034] The memory cell array 100 includes a plurality of memory cells MC in a two-dimensional (2D) matrix of rows and columns. The memory cell array 100 includes multiple word lines WL and bit lines BL connected to the memory cells MC. Each memory cell MC includes a cell transistor CT and a cell capacitor CC. The gate of the cell transistor CT is connected to one of the word lines WL arranged in the row direction of the memory cell array 100. One end of the cell transistor CT is connected to one of the bit lines BL arranged in the column direction of the memory cell array 100. The other end of the cell transistor CT is connected to the cell capacitor CC. The cell capacitor CC can store various amounts of charge corresponding to multiple bits of data, such as 2 bits. The cell capacitor CC can be restored to the amount of charge corresponding to the amount of multiple bits of data, i.e., the cell voltage Vcell. Alternatively, the cell capacitor CC can store the amount of charge corresponding to a single-bit data. The cell capacitor CC can be restored to the amount of charge corresponding to the amount of single-bit data, i.e., the cell voltage Vcell.

[0035] The storage cell MC can store a cell voltage Vcell with a specified 2-bit data value. The cell voltage Vcell can be represented as 2-bit data including the most significant bit (MSB) and the least significant bit (LSB). According to an embodiment, the storage cell MC can store multi-bit data or unit data including at least "n" bits (where "n" is a natural number greater than 2).

[0036] Command decoder 300 can determine the command CMD by referring to the chip select signal / CS, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE, etc., received from an external device. Command decoder 300 can generate control signals corresponding to the command CMD. Command CMD may include activation command, read command, write command, precharge command, etc.

[0037] Address buffer 400 receives address ADDR from an external device. Address ADDR includes row address and column address, where row address addresses rows of memory cell array 100 and column address addresses columns of memory cell array 100. Address buffer 400 can send the row address and column address to address decoder 500.

[0038] Address decoder 500 may include a row decoder and a column decoder, which select the word line WL and bit line BL of the memory cell MC to be accessed, respectively, in response to address ADDR. The row decoder decodes the row address and enables the word line WL of the memory cell MC corresponding to that row address. The column decoder decodes the column address and provides a column select signal to select the bit line BL of the memory cell MC corresponding to that column address.

[0039] The control circuit 600 can control the first sense amplifier 200_1 and the second sense amplifier 200_2 under the control of the command decoder 300. The control circuit 600 can control the operation of the first sense amplifier 200_1 when it senses the cell voltage Vcell of the memory cell MC, and control the operation of the second sense amplifier 200_2 when it senses the cell voltage Vcell of the memory cell MC. The control circuit 600 can control the first sense amplifier 200_1 and the second sense amplifier 200_2 to sequentially perform a pre-charge operation, an offset cancellation operation, an MSB sensing operation, an LSB sensing operation, and a recovery operation. The control circuit 600 can selectively turn on or off operations corresponding to either the first sense amplifier 200_1 or the second sense amplifier 200_2, such as... Figure 4 The first latch 210 and the second latch 220, as well as multiple switches SWA, SWb, SW10 and SW1 to SW6.

[0040] Both the first sense amplifier 200_1 and the second sense amplifier 200_2 can sense the charge stored in the corresponding memory cell MC as 2-bit data. Both the first sense amplifier 200_1 and the second sense amplifier 200_2 can sense the LSB and MSB of the 2-bit data, and can recover the bit line voltage generated by combining the MSB and LSB data in the corresponding memory cell MC as the cell voltage. Both the first sense amplifier 200_1 and the second sense amplifier 200_2 can also send the sensed 2-bit data to the data I / O circuit 700, so that the sensed 2-bit data is output from the memory device 10 through one or more data pads.

[0041] The first readout amplifier 200_1 can be connected to the first bit line BL1, and the second readout amplifier 200_2 can be connected to the second bit line BL2. According to an embodiment, as... Figure 2 As shown, complementary bit lines can be connected to each of the first sense amplifier 200_1 and the second sense amplifier 200_2 in a memory device with an open bitline structure.

[0042] The data I / O circuit 700 can receive data DQ to be written to the memory cell MC from an external source and send the data DQ to the memory cell array 100. The data I / O circuit 700 can output 2-bit data sensed by the first sense amplifier 200_1 or the second sense amplifier 200_2 to the outside of the memory device 10 via data pads. According to an embodiment, when outputting the sensed 2-bit data, the data I / O circuit 700 can serially output MSB data and LSB data via a single data pad. Conversely, it can serially output LSB data and MSB data via a single data pad. According to an embodiment, the data I / O circuit 700 can output the sensed 2-bit data in parallel via two data pads. For example, MSB data can be output via the first data pad, and LSB data can be output via the second data pad.

[0043] In the storage device 10, the length of the first bit line BL1 connected to the first sense amplifier 200_1 may differ from the length of the second bit line BL2 connected to the second sense amplifier 200_2. Therefore, the capacitance of the first bit line BL1 may differ from the capacitance of the second bit line BL2. Consequently, the sensing characteristics of the first sense amplifier 200_1 may differ from the sensing characteristics of the second sense amplifier 200_2. This difference in sensing characteristics may refer to a difference in sensing margin. For example, even when performing a sensing operation on memory cells with the same cell voltage Vcell, the first sense amplifier 200_1 may perform correct sensing, but the second sense amplifier 200_2 may perform incorrect sensing. Therefore, a method is desired to compensate for the difference in sensing characteristics caused by the length difference between the bit lines.

[0044] According to an embodiment, to compensate for the difference in sensing characteristics caused by the length difference between the first bit line BL1 and the second bit line BL2, the storage device 10 can use different drive voltages to drive the first sense amplifier 200_1 and the second sense amplifier 200_2 respectively. For example, the storage device 10 can provide a first drive voltage VD_1 to the first sense amplifier 200_1 and a second drive voltage VD_2 to the second sense amplifier 200_2. In an embodiment, the drive voltage may include at least one of a pre-charge voltage, a first latch drive voltage, and a second latch drive voltage. In other words, in an embodiment, different pre-charge voltages can be used to charge the first bit line BL1 and the second bit line BL2 respectively during the pre-charge operation period of the sensing operation. In an embodiment, during the MSB sensing operation, the first latch of the first sense amplifier 200_1 can be driven by a first latch drive voltage having a first voltage level, and the first latch of the second sense amplifier 200_2 can be driven by a first latch drive voltage having a second voltage level different from the first voltage level. In an embodiment, during an MSB sensing operation or an LSB sensing operation, the second latch of the first sense amplifier 200_1 can be driven by a second latch drive voltage having a third voltage level, and the second latch of the second sense amplifier 200_2 can be driven by a second latch drive voltage having a fourth voltage level different from the third voltage level. Specific embodiments will now be described in detail with reference to the accompanying drawings.

[0045] According to this embodiment, the storage device 10 can provide a first driving voltage VD_1 to a first sense amplifier 200_1 connected to the first bit line BL1, and can provide a second driving voltage VD_2 to a second sense amplifier 200_2 connected to the second bit line BL2. Therefore, the difference in sensing characteristics caused by the length difference between the first bit line BL1 and the second bit line BL2 can be compensated.

[0046] Figure 2 A plurality of memory cells MC and a sense amplifier 200 having an open bit line structure are shown according to an embodiment. Figure 2 The readout amplifier 200 can correspond to Figure 1 Either the first sense amplifier 200_1 or the second sense amplifier 200_2. (To be referenced together) Figure 1 To describe Figure 2 .

[0047] Reference Figure 2The sense amplifier 200 can be connected to the memory cell MC via paired bit lines (e.g., bit line BL and complementary bit line BLB). Specifically, the sense amplifier 200 can have an open bit line configuration and can be connected to the memory cell MC. In the open bit line configuration, the paired bit line BL and complementary bit line BLB are respectively located in master cell blocks 110 and 120 adjacent to the sense amplifier 200. In the open bit line configuration, when the word line WL of the memory cell MC included in master cell block 110 is enabled, data can be read from or written to the memory cell MC via the selected bit line BL. At this time, while accessing the memory cell MC via the selected bit line BL, since there is no selected memory cell connected to the complementary bit line BLB in master cell block 120, the complementary bit line BLB can be maintained at the level of the precharge voltage VPRE, which serves as a reference voltage level. Therefore, the sense amplifier 200 can sense the cell voltage Vcell of the memory cell MC using the shared charge via the bit line BL.

[0048] The sense amplifier 200 can sense the cell voltage Vcell stored in the memory cell MC in the master cell block 110 as the MSB and LSB of 2-bit data, and can recover the cell voltage Vcell corresponding to the sensed MSB and LSB in the memory cell MC. The sense amplifier 200 can use the cell capacitance of the memory cell MC, the bit line capacitance of the bit line pairs (e.g., BL and BLB), and the holding bit line pairs (e.g., ... Figure 4 The bit line capacitance of the hold bit line HBL and complementary hold bit line HBLB, and the first sensing bit line pair (e.g. Figure 4 The bit line capacitance of the first sensing bit line SBL1 and the first complementary sensing bit line SBLB1 shown, and the second sensing bit line pair (e.g. Figure 4 The bit line capacitances of the second sensing bit line (SBL2) and the second complementary sensing bit line (SBLB2) shown, and the changes in these capacitances, are used to perform the first to third charge-sharing operations. The sense amplifier 200 can sense the MSB and LSB of 2-bit data by performing the first to third charge-sharing operations, and can recover the cell voltage Vcell corresponding to the sensed MSB and LSB data in the memory cell MC. The first to third charge-sharing operations of the sense amplifier 200 will be described below.

[0049] In the sense amplifier 200, a first charge-sharing operation can occur between the charge stored in the cell capacitor CC, which has a cell capacitance, and the charge stored in the bit line BL and the holding bit line HBL, both of which have bit line capacitance. The sense amplifier 200 can sense the MSB data of the memory cell MC by performing the first charge-sharing operation.

[0050] In the sense amplifier 200, the second charge-sharing operation may include charge sharing between the charge stored in bit line BL and hold bit line HBL and the charge stored in the first sense bit line SBL1, and charge sharing between the charge stored in complementary bit line BLB and complementary hold bit line HBLB and the charge stored in the first complementary sense bit line SBLB1. The sense amplifier 200 can sense the LSB data of the memory cell MC by performing the second charge-sharing operation.

[0051] In the sense amplifier 200, a third charge-sharing operation can occur between the charge stored in bit line BL of the memory cell MC, the charge stored in hold bit line HBL storing LSB data of the memory cell MC, the charge stored in second complementary sensing bit line SBLB2 storing MSB data of the memory cell MC, the charge stored in first complementary sensing bit line SBLB1, the charge stored in complementary bit line BLB and complementary hold bit line HBLB, and the charge stored in first sensing bit line SBL1. The sense amplifier 200 can combine the sensed MSB data with the sensed LSB data by performing the third charge-sharing operation. The sense amplifier 200 can recover the cell voltage Vcell generated in the memory cell MC by the combination of the sensed MSB and LSB data.

[0052] In the read mode of the storage device 10, the sense amplifier 200 can electrically connect a second sense bit line pair (e.g., SBL2 and SBLB2) and a bit line pair (e.g., BL and BLB) to the data I / O circuit 700 in response to a column select signal. The second sense bit line pair (e.g., SBL2 and SBLB2) stores the MSB data of the memory cell MC sensed in the first and second charge-sharing operations, and the bit line pair (e.g., BL and BLB) stores the LSB data of the memory cell MC sensed in the first and second charge-sharing operations. The data I / O circuit 700 can serially output the MSB data and LSB data via a single data pad, or in parallel via two data pads.

[0053] Figure 3 This is a diagram illustrating multi-bit data of a memory cell sensed by a sense amplifier, according to an embodiment. It will be referred to together with other diagrams. Figure 1 and Figure 2 To describe Figure 3 .

[0054] Reference Figure 3The cell voltage Vcell of a memory cell MC can be represented as the MSB and LSB of 2 bits of data. The cell voltage Vcell can be represented as a bit combination, i.e., "00", "01", "10", or "11". For example, a cell voltage Vcell with voltage level V00 can indicate the bit combination "00", a cell voltage Vcell with voltage level V01 can indicate the bit combination "01", a cell voltage Vcell with voltage level V10 can indicate the bit combination "10", and a cell voltage Vcell with voltage level V11 can indicate the bit combination "11".

[0055] When a first charge-sharing operation is performed between the charge stored in the cell capacitor CC and the charge stored in the bit line BL and the holding bit line HBL in the sense amplifier 200 for the MSB data of the sense memory cell MC, the bit line BL and the holding bit line HBL are captured as the MSB voltage V_MSB. The bit line BL can transition from the level of the precharge voltage VPRE to the MSB voltage V_MSB. At this time, the complementary bit line BLB can be held at the level of the precharge voltage VPRE.

[0056] For example, due to a first charge-sharing operation on a cell voltage Vcell with voltage level V00, the voltage level of bit line BL can be captured as the MSB voltage V_MSB at voltage level VM00. For example, due to a first charge-sharing operation on a cell voltage Vcell with voltage level V01, the voltage level of bit line BL can be captured as the MSB voltage V_MSB at voltage level VM01. For example, due to a first charge-sharing operation on a cell voltage Vcell with voltage level V10, the voltage level of bit line BL can be captured as the MSB voltage V_MSB at voltage level VM10. For example, due to a first charge-sharing operation on a cell voltage Vcell with voltage level V11, the voltage level of bit line BL can be captured as the MSB voltage V_MSB at voltage level VM11. At this time, the complementary bit line BLB can be maintained at the level of the pre-charge voltage VPRE.

[0057] When a second charge-sharing operation is performed in the sense amplifier 200 of the LSB data in the sense storage unit MC, including charge sharing between the charge stored in bit line BL and hold bit line HBL and the charge stored in the first sense bit line SBL1, and charge sharing between the charge stored in complementary bit line BLB and complementary hold bit line HBLB and the charge stored in the first complementary sense bit line SBLB1, the selected bit line BL is captured as the LSB voltage V_LSB. The selected bit line BL can be converted from MSB voltage V_MSB to LSB voltage V_LSB.

[0058] For example, due to the second charge-sharing operation, the voltage level of bit line BL, which has an MSB voltage V_MSB at voltage level VM00, can be captured as an LSB voltage V_LSB at voltage level VL00. For example, due to the second charge-sharing operation, the voltage level of bit line BL, which has an MSB voltage V_MSB at voltage level VM01, can be captured as an LSB voltage V_LSB at voltage level VL10. For example, due to the second charge-sharing operation, the voltage level of bit line BL, which has an MSB voltage V_MSB at voltage level VM10, can be captured as an LSB voltage V_LSB at voltage level VL10. For example, due to the second charge-sharing operation, the voltage level of bit line BL, which has an MSB voltage V_MSB at voltage level VM11, can be captured as an LSB voltage V_LSB at voltage level VL11.

[0059] When the sense amplifier 200 senses the cell voltage Vcell of the memory cell MC as a 2-bit combination of MSB and LSB data, the voltage levels of the hold bit line HBL and bit line BL with LSB voltage levels are used as a self-reference with a specific voltage difference from the voltage levels of the complementary bit line BLB and complementary hold bit line HBLB.

[0060] Figure 4 A readout amplifier 200 according to an embodiment is shown. Figure 4 The readout amplifier 200 can correspond to Figure 1 The first readout amplifier 200_1 or the second readout amplifier 200_2 will be referenced together. Figure 1 To describe Figure 4 .

[0061] Reference Figure 4 The readout amplifier 200 includes a first latch 210, a second latch 220, and a switching circuit, which includes a bit line switch SWa, a complementary bit line switch SWb, a power switch SW10, and first switches SW1 to sixth switches SW6.

[0062] The first latch 210 is connected to the first latch pull-up drive signal LA1 and the first latch pull-down drive signal LAB1, and includes a first P-type metal-oxide-semiconductor (PMOS) transistor P11 and a second P-type metal-oxide-semiconductor (PMOS) transistor P12, as well as a first N-type MOS (NMOS) transistor N11 and a second N-type MOS (NMOS) transistor N12. The control circuit 600 (in which the operation of the sense amplifier 200 is controlled) can... Figure 1 Under the control of ( ), the power supply voltage VINTA, ground voltage VSS, or precharge voltage VPRE is applied to the first latch pull-up drive signal LA1 and the first latch pull-down drive signal LAB1.

[0063] One end of the first PMOS transistor P11 is connected to the line of the first latch pull-up drive signal LA1, the other end of the first PMOS transistor P11 is connected to the first sensing bit line SBL1, and the gate of the first PMOS transistor P11 is connected to the first complementary sensing bit line SBLB1. One end of the second PMOS transistor P12 is connected to the line of the first latch pull-up drive signal LA1, the other end of the second PMOS transistor P12 is connected to the first complementary sensing bit line SBLB1, and the gate of the second PMOS transistor P12 is connected to the first sensing bit line SBL1.

[0064] One end of the first NMOS transistor N11 is connected to the power switch SW10, the other end of the first NMOS transistor N11 is connected to the first sensing bit line SBL1, and the gate of the first NMOS transistor N11 is connected to the hold bit line HBL. One end of the second NMOS transistor N12 is connected to the power switch SW10, the other end of the second NMOS transistor N12 is connected to the first complementary sensing bit line SBLB1, and the gate of the second NMOS transistor N12 is connected to the complementary hold bit line HBLB.

[0065] Bit line switch SWA is connected between bit line BL and holding bit line HBL, and is turned on or off under the control of control circuit 600. Complementary bit line switch SWb is connected between complementary bit line BLB and complementary holding bit line HBLB, and is turned on or off under the control of control circuit 600. Power switch SW10 is connected between the corresponding terminals of the first NMOS transistor N11 and the second NMOS transistor N12 and the line of the first latch pull-down drive signal LAB1, and is turned on or off under the control of control circuit 600.

[0066] The first switch SW1 is connected between the holding bit line HBL and the first sensing bit line SBL1, and is turned on or off under the control of the control circuit 600. The second switch SW2 is connected between the complementary holding bit line HBLB and the first complementary sensing bit line SBLB1, and is turned on or off under the control of the control circuit 600. The third switch SW3 is connected between the holding bit line HBL and the first complementary sensing bit line SBLB1, and is turned on or off under the control of the control circuit 600. The fourth switch SW4 is connected between the complementary holding bit line HBLB and the first sensing bit line SBL1, and is turned on or off under the control of the control circuit 600.

[0067] The second latch 220 is connected to the second latch pull-up drive signal LA2 and the second latch pull-down drive signal LAB2, and includes a third PMOS transistor P21 and a fourth PMOS transistor P22, as well as a third NMOS transistor N21 and a fourth NMOS transistor N22.

[0068] One end of the third PMOS transistor P21 is connected to the line of the second latch pull-up drive signal LA2, the other end of the third PMOS transistor P21 is connected to the second sensing bit line SBL2, and the gate of the third PMOS transistor P21 is connected to the second complementary sensing bit line SBLB2. One end of the fourth PMOS transistor P22 is connected to the line of the second latch pull-up drive signal LA2, the other end of the fourth PMOS transistor P22 is connected to the second complementary sensing bit line SBLB2, and the gate of the fourth PMOS transistor P22 is connected to the second sensing bit line SBL2.

[0069] One end of the third NMOS transistor N21 is connected to the line of the second latch pull-down drive signal LAB2, the other end of the third NMOS transistor N21 is connected to the second sensing bit line SBL2, and the gate of the third NMOS transistor N21 is connected to the second complementary sensing bit line SBLB2. One end of the fourth NMOS transistor N22 is connected to the line of the second latch pull-down drive signal LAB2, the other end of the fourth NMOS transistor N22 is connected to the second complementary sensing bit line SBLB2, and the gate of the fourth NMOS transistor N22 is connected to the second sensing bit line SBL2.

[0070] The fifth switch SW5 is connected between the first sensing bit line SBL1 and the second sensing bit line SBL2, and is turned on or off under the control of the control circuit 600. The sixth switch SW6 is connected between the first complementary sensing bit line SBLB1 and the second complementary sensing bit line SBLB2, and is turned on or off under the control of the control circuit 600.

[0071] Figures 5A to 5D This is a flowchart of the sequential operation of the readout amplifier according to an embodiment.

[0072] Reference Figures 2 to 4 And according to Figure 5A In operation S110, the sense amplifier 200 can perform a precharge operation. The sense amplifier 200 can precharge the bit line BL, the hold bit line HBL, the complementary bit line BLB, the complementary hold bit line HBLB, the first sense bit line SBL1, the first complementary sense bit line SBLB1, the second sense bit line SBL2, the second complementary sense bit line SBLB2, the first latch pull-up drive signal LA1, the first latch pull-down drive signal LAB1, the second latch pull-up drive signal LA2, and the second latch pull-down drive signal LAB2 using the precharge voltage VPRE.

[0073] In operation S120, the readout amplifier 200 can perform offset cancellation operation. (Referring to...) Figure 2In the described sense amplifier 200 with an open bit-line structure, noise such as process variations, temperature, or threshold voltage differences between transistors may manifest differently between a pair of bit lines (i.e., bit line BL and complementary bit line BLB). This difference in noise between bit line BL and complementary bit line BLB can act as offset noise during sensing operation of the sense amplifier 200, thereby reducing the effective sensing margin. Therefore, the sense amplifier 200 performs an offset cancellation operation before sensing operation to increase the effective sensing margin.

[0074] In operation S130, the sense amplifier 200 may perform a first sensing operation to sense the MSB, which indicates the 2-bit combination of the cell voltage Vcell stored in the memory cell MC. This MSB sensing operation may include a first charge sharing operation between the charge stored in the memory cell MC and the charge stored in the bit line BL and the holding bit line HBL.

[0075] The first charge-sharing operation occurs between the charge stored in the unit capacitor CC (which has a unit capacitance) and the charge stored in the bit line BL and the holding bit line HBL (both have bit line capacitances). As a result of the first charge-sharing operation, the voltage levels of the bit line BL and the holding bit line HBL can be expressed as the MSB voltage V_MSB corresponding to the bit combination "00", "01", "10", or "11". Figure 3 (in the middle). The sense amplifier 200 can sense and amplify the MSB voltage V_MSB and the complementary bit line voltage V_MSB of the complementary bit line BLB. BLB The difference between them can be latched, and the MSB data can be latched with a logic "1" at the level of the power supply voltage VINTA or a logic "0" at the level of the ground voltage VSS.

[0076] In operation S140, the sense amplifier 200 may perform a second sensing operation to sense the LSB indicating a 2-bit combination of cell voltage Vcell stored in the memory cell MC. The LSB sensing operation may include a second charge-sharing operation.

[0077] The second charge sharing operation may include charge sharing between the charge stored in bit line BL and hold bit line HBL and the charge stored in first sense bit line SBL1, and charge sharing between the charge stored in complementary bit line BLB and complementary hold bit line HBLB and the charge stored in first complementary sense bit line SBLB1.

[0078] As a result of the second charge-sharing operation, the voltage levels of bit line BL and hold bit line HBL can be expressed as LSB voltage V_LSB corresponding to bit combinations "00", "01", "10", or "11". Figure 3(in the middle). The sense amplifier 200 can sense and amplify the LSB voltage V_LSB and the complementary bit line voltage V_LSB. BLB and complementary hold bit line voltage V HBLB The difference between each of them, and can latch LSB data with a logic "1" at the level of the power supply voltage VINTA or a logic "0" at the level of the ground voltage VSS.

[0079] In operation S150, the sense amplifier 200 can perform a recovery operation by rewriting the cell voltage Vcell to the memory cell MC, which is generated by combining sensed MSB data with sensed LSB data. The recovery operation may include a third charge-sharing operation.

[0080] As a result of sensing MSB and LSB data in operations S130 and S140, LSB data with corresponding logic levels are stored in bit line BL and hold bit line HBL, and MSB data with corresponding logic levels are stored in first sensing bit line SBL1, complementary bit line BLB, complementary hold bit line HBLB and first complementary sensing bit line SBLB1.

[0081] A third charge-sharing operation can be performed using the cell capacitance of the memory cell MC, the bit line capacitance of the bit line pairs (e.g., BL and BLB), the bit line capacitance of the holding bit line pairs (e.g., HBL and HBLB), and the bit line capacitance of the first sensing bit line pairs (e.g., SBL1 and SBLB1), as well as variations in these capacitances. The MSB data and LSB data sensed through the third charge-sharing operation can be combined. The sense amplifier 200 can recover the cell voltage Vcell in the memory cell MC, which is generated by combining the sensed MSB data with the sensed LSB data.

[0082] For ease of description, we will combine Figure 6 To describe Figures 5B to 5D Detailed flowchart.

[0083] Figure 6 This is a timing diagram of the signal of the sense amplifier that senses the 2-bit data "00" according to an embodiment. For ease of description, the operation of the sense amplifier that senses the 2-bit data "00" will be described in detail.

[0084] 1. Pre-charge operation

[0085] Reference Figure 5A as well as Figure 6At time point T0, during operation S110, the readout amplifier 200 precharges the bit line BL, hold bit line HBL, complementary bit line BLB, complementary hold bit line HBLB, first sensing bit line SBL1, first complementary sensing bit line SBLB1, second sensing bit line SBL2, second complementary sensing bit line SBLB2, first latch pull-up drive signal LA1, first latch pull-down drive signal LAB1, second latch pull-up drive signal LA2, and second latch pull-down drive signal LAB2 using the precharge voltage VPRE.

[0086] The precharge voltage VPRE can be set to half the level of the supply voltage VINTA. For example, when the supply voltage VINTA is 1V, the precharge voltage VPRE can be set to 0.5V. According to an embodiment, the sense amplifier 200 may further include a precharge circuit that can precharge the hold bit line HBL, the complementary hold bit line HBLB, the first sense bit line SBL1, the first complementary sense bit line SBLB1, the second sense bit line SBL2, the second complementary sense bit line SBLB2, the first latch pull-up drive signal LA1, the first latch pull-down drive signal LAB1, the second latch pull-up drive signal LA2, and the second latch pull-down drive signal LAB2 with the precharge voltage VPRE.

[0087] During the precharge operation, the first latch 210 and the second latch 220 can be in the off state, the bit line switch SWA, the complementary bit line switch SWb, and the power switch SW10 are in the on state, and the first switch SW1 to the sixth switch SW6 are in the off state. When the first latch 210 is in the off state, the precharge voltage VPRE is applied to the first latch pull-up drive signal LA1 and the first latch pull-down drive signal LAB1. When the second latch 220 is in the off state, the precharge voltage VPRE is applied to the second latch pull-up drive signal LA2 and the second latch pull-down drive signal LAB2.

[0088] 2. Offset cancellation operation

[0089] Reference Figure 5A as well as Figure 6 At time point T1, during operation S120, the readout amplifier 200 performs an offset cancellation operation. For example... Figure 2 As shown, the sense amplifier 200 has an open bit line configuration, such that the sense amplifier 200 is connected to a pair of bit lines BL and complementary bit lines BLB located in adjacent cell blocks 110 and 120, respectively. In the open bit line configuration, offset noise relative to the noise in the bit lines BL and complementary bit lines BLB may be maximized during the sensing operation of the sense amplifier 200, thereby reducing the effective sensing margin of the sense amplifier 200.

[0090] To increase the effective sensing margin of the sense amplifier 200, the sense amplifier 200 turns on the first latch 210 and the first switch SW1 and the second switch SW2 to perform an offset cancellation operation. The power supply voltage VINTA is applied to the first latch pull-up drive signal LA1 of the first latch 210, and the ground voltage VSS is applied to the first latch pull-down drive signal LAB1 of the first latch 210.

[0091] Due to the offset noise of the bit line pairs (i.e., BL and BLB) in the first latch 210, the complementary bit line BLB can rise or fall to a certain level compared to the bit line BL, and therefore, a voltage difference exists between the bit line BL and the complementary bit line BLB. This voltage difference can be interpreted as an offset voltage caused by the offset noise. When the bit line BL and the complementary bit line BLB are set to have a difference corresponding to the offset voltage, the offset noise of the sense amplifier 200 is removed. In other words, the sense amplifier 200 can compensate for the offset through an offset cancellation operation.

[0092] 3. First charge sharing operation

[0093] Reference Figure 5B as well as Figure 6 At time T2, during operation 132, the sense amplifier 200 performs a first charge sharing operation between the memory cell MC and the bit line BL. The sense amplifier 200 disconnects the first latch 210 and the first switch SW1 and the second switch SW2. At this time, the word line WL connected to the memory cell MC is enabled, and charge sharing occurs between the charge stored in the cell capacitor CC of the memory cell MC and the charge stored in the bit line BL and the holding bit line HBL.

[0094] When a cell voltage Vcell of 0V is stored in the memory cell MC, the voltage levels of bit line BL and hold bit line HBL can drop by a specific level from the level of the precharge voltage VPRE. At this time, the complementary bit line BLB and the complementary hold bit line HBLB can remain at the level of the precharge voltage VPRE.

[0095] 4. Charge retention operation

[0096] Reference Figure 5B as well as Figure 6 At time point T3, in operation S134, the readout amplifier 200 holds the charge of bit line BL and bit line HBL, which is generated through the first charge sharing operation. The readout amplifier 200 then disconnects bit line switch SWA and complementary bit line switch SWb.

[0097] 5. MSB Sensing Operation

[0098] Reference Figure 5B as well as Figure 6 At time T4, in operation S136, the sense amplifier 200 performs an MSB sensing operation by sensing the MSB of the 2-bit combination of the cell voltage Vcell stored in the memory cell MC. The sense amplifier 200 turns on the first latch 210 and the third switch SW3 and the fourth switch SW4 to perform the MSB sensing operation. The power supply voltage VINTA is applied to the first latch pull-up drive signal LA1 of the first latch 210, and the ground voltage VSS is applied to the first latch pull-down drive signal LAB1 of the first latch 210. The hold bit line HBL is connected to the first complementary sense bit line SBLB1 via the third switch SW3, and the complementary hold bit line HBLB is connected to the first sense bit line SBL1 via the fourth switch SW4.

[0099] The first latch 210 can increase the voltage of the first sensing bit line SBL1 to a logic "1" level and decrease the voltage of the first complementary sensing bit line SBLB1 to a logic "0" level. The voltage of the complementary holding bit line HBLB connected to the first sensing bit line SBL1 can rise to a logic "1" level, and the voltage of the holding bit line HBL connected to the first complementary sensing bit line SBLB1 can fall to a logic "0" level.

[0100] 6. First MSB latch operation

[0101] Reference Figure 5B as well as Figure 6 At time T5, in operation S138, the sense amplifier 200 performs a first MSB latch operation by latching the MSB of 2 bits of data. The sense amplifier 200 disconnects the first latch 210 and the power switch SW10, and turns on the second latch 220, as well as the fifth switch SW5 and the sixth switch SW6, to perform the first MSB latch operation. The power supply voltage VINTA is applied to the second latch pull-up drive signal LA2 of the second latch 220, and the ground voltage VSS is applied to the second latch pull-down drive signal LAB2 of the second latch 220. The first sensing bit line SBL1 is connected to the second sensing bit line SBL2 via the fifth switch SW5, and the first complementary sensing bit line SBLB1 is connected to the second complementary sensing bit line SBLB2 via the sixth switch SW6. The power switch SW10 can be disconnected to block the leakage current path, which interrupts the operation of the second latch 220 when it is in the on state.

[0102] The second latch 220 can perform sensing based on the voltage difference between the second sensing bit line SBL2 and the second complementary sensing bit line SBLB2, and can increase the voltage of the second sensing bit line SBL2 to a logic "1" level and decrease the voltage of the second complementary sensing bit line SBLB2 to a logic "0" level. The voltages of the first sensing bit line SBL1 and the complementary holding bit line HBLB connected to the second sensing bit line SBL2 can become logic "1" levels. The voltages of the first complementary sensing bit line SBLB1 and the holding bit line HBL connected to the second complementary sensing bit line SBLB2 can become logic "0" levels.

[0103] 7. Second MSB latch operation

[0104] Reference Figure 5B as well as Figure 6 At time T6, in operation 139, the sense amplifier 200 performs the second MSB latch operation. The sense amplifier 200 disconnects switches SW3 through SW6 to perform the second MSB latch operation. The voltage of the second sensing bit line SBL1 can be maintained at logic "1", the voltage of the second complementary sensing bit line SBLB2 can be maintained at logic "0", the voltage of the first sensing bit line SBL1 can be maintained at logic "1", the voltage of the first complementary sensing bit line SBLB1 can be maintained at logic "0", the voltage of the holding bit line HBL can be maintained at logic "0", and the voltage of the complementary holding bit line HBLB can be maintained at logic "1".

[0105] A logic "0" level can be latched as MSB data of the storage cell MC into the second complementary sensing bit line SBLB2 of the second latch 220.

[0106] 8. Second charge sharing operation

[0107] Reference Figure 5C as well as Figure 6 At time point T7, in operation 142, the sense amplifier 200 performs a second charge-sharing operation between the first sensing bit line SBL1, the holding bit line HBL, and the bit line BL, and between the first complementary sensing bit line SBLB1, the complementary holding bit line HBLB, and the complementary bit line BLB. The sense amplifier 200 turns on the bit line switch SWA, the complementary bit line switch SWb, and the first switch SW1 and the second switch SW2.

[0108] Bit line BL, hold bit line HBL, and first sensing bit line SBL1 are connected to each other via bit line switch SWa and first switch SW1. Complementary bit line BLB, complementary hold bit line HBLB, and first complementary sensing bit line SBLB1 are connected to each other via complementary bit line switch SWb and second switch SW2.

[0109] Charge sharing occurs among the charges stored in bit line BL, the charges stored in holding bit line HBL, and the charges stored in first sensing bit line SBL1. Charge sharing also occurs among the charges stored in complementary bit line BLB, complementary holding bit line HBLB, and first complementary sensing bit line SBLB1.

[0110] 9. LSB Sensing Operation

[0111] Reference Figure 5C as well as Figure 6 At time T8, in operation 144, the sense amplifier 200 performs an LSB sensing operation by sensing the LSB of the 2-bit combination of the cell voltage Vcell stored in the memory cell MC. The sense amplifier 200 turns on the first latch 210, the power switch SW10, and the third switch SW3 and the fourth switch SW4, and turns off the first switch SW1 and the second switch SW2 to perform the LSB sensing operation.

[0112] The first power supply voltage VINTA1 is applied to the first latch pull-up drive signal LA1 of the first latch 210, and the ground voltage VSS is applied to the first latch pull-down drive signal LAB1 of the first latch 210. Bit line BL, hold bit line HBL, and first complementary sensing bit line SBLB1 are connected to each other through bit line switch SWA and third switch SW3. Complementary bit line BLB, complementary hold bit line HBLB, and first sensing bit line SBL1 are connected to each other through complementary bit line switch SWb and fourth switch SW4.

[0113] The first latch 210 can increase the voltage of the first sensing bit line SBL1 to a logic "1" level and decrease the voltage of the first complementary sensing bit line SBLB1 to a logic "0" level.

[0114] The voltages connected to the complementary bit line BLB and the complementary hold bit line HBLB of the first sensing bit line SBL1 can rise to a logic "1" level. The voltages connected to the bit line BL and the hold bit line HBL of the first complementary sensing bit line SBLB1 can fall to a logic "0" level.

[0115] A logic "0" level can be latched as LSB data of the storage cell MC into the bit line BL of the first latch 210.

[0116] 10. Combined operations of MSB and LSB

[0117] Reference Figure 5D as well as Figure 6At time point T9, during operation 152, the sense amplifier 200 can combine the MSB data and LSB data of the sensed memory cell MC. The sense amplifier 200 can disconnect the first latch 210, the power switch SW10, and the third switch SW3, and turn on the second switch SW2 and the sixth switch SW6 to combine the sensed MSB data and the sensed LSB data.

[0118] The second complementary sensing bit line SBLB2 of the second latch 220 latches the MSB data at a logic "0" level, and the first complementary sensing bit line SBLB1 of the first latch 210 latches the LSB data at a logic "0" level.

[0119] The second complementary sensing bit line SBLB2, the first sensing bit line pair (i.e., SBL1 and SBLB1), the complementary hold bit line HBLB, and the complementary bit line BLB can be connected to each other via the complementary bit line switch SWb and the second switch SW2, the fourth switch SW4, and the sixth switch SW6. The voltage of the first sensing bit line pair (i.e., SBL1 and SBLB1), the complementary hold bit line HBLB, and the complementary bit line BLB connected to the second complementary sensing bit line SBLB2 can drop to a logic "0" level. At this time, the voltage of bit line BL and hold bit line HBL can be maintained at a logic "0" level.

[0120] 11. Third charge sharing operation

[0121] Reference Figure 5D as well as Figure 6 At time point T10, in operation 154, the sense amplifier 200 performs a third charge-sharing operation between the first sense bit line pair (i.e., SBL1 and SBLB1), the hold bit line pair (i.e., HBL and HBLB), and the bit line pair (i.e., BL and BLB). The sense amplifier 200 can disconnect the first latch 210 and the sixth switch SW6, and turn on the first switch SW1 and the third switch SW3 to perform the third charge-sharing operation.

[0122] Bit line pairs (i.e., BL and BLB), holding bit line pairs (i.e., HBL and HBLB), and first sensing bit line pairs (i.e., SBL1 and SBLB1) can be connected to each other via bit line switch SWA, complementary bit line switch SWb, and first switches SW1 to fourth switches SW4.

[0123] The sense amplifier 200 can perform a third charge-sharing operation using the cell capacitance of the memory cell MC, the bit line capacitance of the bit line pairs (i.e., BL and BLB), the bit line capacitance of the holding bit line pairs (i.e., HBL and HBLB), the bit line capacitance of the first sensing bit line pairs (i.e., SBL1 and SBLB1), and changes in these capacitances. As a result of the third charge-sharing operation, the voltages of the bit line pairs (i.e., BL and BLB), the holding bit line pairs (i.e., HBL and HBLB), and the first sensing bit line pairs (i.e., SBL1 and SBLB1) become the level of the ground voltage VSS. The voltage of the bit line BL, which has the level of the ground voltage VSS, is restored to the cell voltage Vcell in the memory cell MC.

[0124] As described above, the sense amplifier 200 senses the 0V cell voltage Vcell stored in the memory cell MC as MSB and LSB bits "00", and restores the 0V of the bit line BL corresponding to the sensed MSB and LSB bits "00" in the memory cell MC as the cell voltage Vcell.

[0125] Figure 7 A storage device 10 according to an embodiment is shown. The storage device 10 may include a first sense amplifier 200_1, a second sense amplifier 200_2, a first drive voltage supply circuit 810, and a second drive voltage supply circuit 820.

[0126] The first sense amplifier 200_1 can be connected to the first bit line BL1 and the first complementary bit line BL1B, and the second sense amplifier 200_2 can be connected to the second bit line BL2 and the second complementary bit line BL2B.

[0127] The length of the first bit line BL1, corresponding to the length from the memory cell to the first sense amplifier 200_1, can be shorter than the length of the second bit line BL2, corresponding to the length from the memory cell to the second sense amplifier 200_2. This length difference between the bit lines results in a capacitance difference between them, which in turn leads to a difference in sensing characteristics between the sense amplifiers. To compensate for the difference in sensing characteristics caused by the length difference between the bit lines, the first sense amplifier 200_1 and the second sense amplifier 200_2 can be driven with different drive voltages.

[0128] For this operation, the first drive voltage supply circuit 810 can generate a first drive voltage VD_1 and supply it to the first sense amplifier 200_1. See below for reference. Figure 9 The first drive voltage VD_1 described herein may include at least one of a first pre-charge voltage VPRE_1, a first power supply voltage VINTA1_1 at a first level, and a second power supply voltage VINTA2_1 at a third level. In an embodiment, the first drive voltage supply circuit 810 may be configured to supply the first drive voltage. Figure 1 Under the control of the control circuit 600, the first driving voltage VD_1 is provided to the first sense amplifier 200_1.

[0129] Similarly, the second drive voltage supply circuit 820 can generate a second drive voltage VD_2 and supply it to the second sense amplifier 200_2. See below for reference. Figure 9 The described second drive voltage VD_2 may include at least one of a second pre-charge voltage VPRE_2, a first power supply voltage VINTA1_2 at a second level, and a second power supply voltage VINTA2_2 at a fourth level. In an embodiment, the second drive voltage supply circuit 820 may be... Figure 1 Under the control of the control circuit 600, the second driving voltage VD_2 is provided to the second sense amplifier 200_2.

[0130] The second driving voltage VD_2 can have one or more values ​​different from the first driving voltage VD_1. The difference between the first driving voltage VD_1 and the second driving voltage VD_2 can correspond to the level used to compensate for the length difference between the first bit line BL1 and the second bit line BL2. Therefore, the designer of the memory device 10 can test the distribution of faulty cells in each bit line relative to the cell voltage and set the difference between the first driving voltage VD_1 and the second driving voltage VD_2 based on the distribution of faulty cells. (Refer to the following...) Figure 8 and Figure 13 This will be described in detail.

[0131] Despite Figure 7 The first drive voltage supply circuit 810 and the second drive voltage supply circuit 820 are shown as separate blocks, but the embodiment is not limited thereto. According to an embodiment, the first drive voltage supply circuit 810 and the second drive voltage supply circuit 820 can be integrated into a single drive voltage supply circuit that generates and provides the first drive voltage VD_1 and the second drive voltage VD2.

[0132] According to this embodiment, the storage device 10 uses voltages with different levels to drive the sense amplifiers that are respectively connected to bit lines with different lengths, thereby compensating for the difference in sensing characteristics caused by the length difference between the bit lines.

[0133] Figure 8 This is a diagram illustrating the qualified and faulty units in a readout amplifier according to an embodiment. Figure 8The diagram shows the recovery voltage levels RVL00_1, RVL01_1, RVL10_1, RVL11_1, RVL00_2, RVL01_2, RVL10_2, and RVL11_2 in the four states "00", "01", "10", and "11" of the readout amplifier, as well as the first to third fault regions FA1_1, FA1_2, FA2_1, FA2_2, FA3_1, and FA3_2 in the intermediate region of the storage device sensing multi-bit data. (See also...) Figure 7 To describe Figure 8 .exist Figure 8 The distribution of qualified and faulty cells in each state shown is only an example and does not represent the overall trend.

[0134] like Figure 8 As shown, the sensing characteristics between the first sense amplifier 200_1 and the second sense amplifier 200_2 may be different. The difference in sensing characteristics between the first sense amplifier 200_1 and the second sense amplifier 200_2 may be caused by the length difference between the bit lines connected to the first sense amplifier 200_1 and the second sense amplifier 200_2, respectively.

[0135] For example, the first fault region FA1_1 of the first sense amplifier 200_1 may differ from the first fault region FA1_2 of the second sense amplifier 200_2, wherein the first fault regions FA1_1 and FA1_2 are between "00" data and "01" data. The second fault region FA2_1 of the first sense amplifier 200_1 may differ from the second fault region FA2_2 of the second sense amplifier 200_2, wherein the second fault regions FA2_1 and FA2_2 are between "01" data and "10" data. The third fault region FA3_1 of the first sense amplifier 200_1 may differ from the third fault region FA3_2 of the second sense amplifier 200_2, wherein the third fault regions FA3_1 and FA3_2 are between "10" data and "11" data.

[0136] Here, the first fault region FA1_1, the second fault region FA2_1, or the third fault region FA3_1 of the first sense amplifier 200_1 being different from the first fault region FA1_2, the second fault region FA2_2, or the third fault region FA3_2 of the second sense amplifier 200_2 indicates that the distribution of faulty memory cells with respect to the first sense amplifier 200_1 in the memory cell array 100 is different from the distribution of faulty memory cells with respect to the second sense amplifier 200_2. For example, the location (with respect to the first sense amplifier 200_1) and size of at least one of the first fault region FA1_1, the second fault region FA2_1, or the third fault region FA3_1 may be different from the location (with respect to the second sense amplifier 200_2) and size of at least one of the first fault region FA1_2, the second fault region FA2_2, or the third fault region FA3_2.

[0137] Furthermore, regarding the first readout amplifier 200_1 and the second readout amplifier 200_2 respectively, the recovery voltage levels RVL00_1 and RVL00_2 of "00" data can be different from each other, the recovery voltage levels RVL01_1 and RVL01_2 of "01" data can be different from each other, the recovery voltage levels RVL10_1 and RVL10_2 of "10" data can be different from each other, and the recovery voltage levels RVL11_1 and RVL11_2 of "11" data can be different from each other.

[0138] To compensate for the aforementioned differences in sensing characteristics, namely, at least one of the position of the sensing area, the size of the sensing area, and the recovery voltage level of the state, the storage device may apply different driving voltages to the first sense amplifier 200_1 and the second sense amplifier 200_2, respectively.

[0139] For example, refer to Figure 10 Different precharge voltages can be used to perform precharge operations in the first sense amplifier 200_1 and the second sense amplifier 200_2, respectively. For example, refer to Figure 11 In MSB sensing operation, different drive voltages can be applied to the first sense amplifier 200_1 and the second sense amplifier 200_2, respectively. For example, refer to... Figure 12 In LSB sensing operation, different drive voltages can be applied to the first sense amplifier 200_1 and the second sense amplifier 200_2, respectively. For example, refer to... Figure 13 During the recovery operation, different drive voltages can be applied to the first sense amplifier 200_1 and the second sense amplifier 200_2, respectively. An embodiment of the above example will now be described in detail with reference to the accompanying drawings.

[0140] During the design phase, such as Figure 8As shown, designers of storage devices can test the sensing characteristics of the readout amplifier. For example, based on tests such as... Figure 8 Given the fault memory cell distribution shown, the designer can determine at least one of the level of the first drive voltage VD_1 to be applied to the first sense amplifier 200_1 and the level of the second drive voltage VD_2 to be applied to the second sense amplifier 200_2. As described above, when the voltages driving the sense amplifiers are set differently based on the sensing characteristics determined for each sense amplifier, the differences in sensing characteristics caused by the length difference between the bit lines can be compensated.

[0141] Figure 9 This is a diagram illustrating the types of drive voltages (e.g., a first drive voltage VD_1 and a second drive voltage VD_2) according to an embodiment. It will be referred to together with... Figure 7 To describe Figure 9 .

[0142] The first drive voltage VD_1 applied to the first sense amplifier 200_1 may include at least one of a first precharge voltage VPRE_1, a first power supply voltage VINTA1_1 at a first level, and a second power supply voltage VINTA2_1 at a third level. The second drive voltage VD_2 applied to the second sense amplifier 200_2 may include at least one of a second precharge voltage VPRE_2, a first power supply voltage VINTA1_2 at a second level, and a second power supply voltage VINTA2_2 at a fourth level.

[0143] At this time, the first pre-charge voltage VPRE_1 and the second pre-charge voltage VPRE_2 can correspond to the pre-charge voltage VPRE. The first power supply voltage VINTA1_1 and the second power supply voltage VINTA1_2 at the first level can correspond to... Figure 6 The first power supply voltage VINTA1. The third-level second power supply voltage VINTA2_1 and the fourth-level second power supply voltage VINTA2_2 can correspond to... Figure 6 The second power supply voltage VINTA2.

[0144] The following will describe in detail, with reference to the accompanying drawings, an embodiment for driving a sense amplifier using drive voltages with different voltage levels.

[0145] Figure 10 This is a flowchart of the sensing operation of the storage device according to an embodiment. It will be referred to together with the above. Figure 7 and Figure 9 To describe Figure 10 .

[0146] In operation S210, during the pre-charge operation period of the sensing operation performed on the memory cell connected to the first bit line BL1, the memory device 10 can pre-charge the first bit line BL1 using the first pre-charge voltage VPRE_1. For this operation, the first drive voltage supply circuit 810 can supply the first pre-charge voltage VPRE_1 to the first sense amplifier 200_1.

[0147] In operation S220, the storage device 10 can perform multi-bit sensing on the storage cells connected to the first bit line BL1 via the first sense amplifier 200_1 connected to the first bit line BL1. Operation S220 may include... Figure 5A The series of processes corresponding to operations S120 to S150.

[0148] In operation S230, during the pre-charge operation period of the sensing operation performed on the memory cell connected to the second bit line BL2, the memory device 10 can pre-charge the second bit line BL2 using the second pre-charge voltage VPRE_2. For this operation, the second drive voltage supply circuit 820 can supply the second pre-charge voltage VPRE_2 to the second sense amplifier 200_2.

[0149] In an embodiment, the second pre-charge voltage VPRE_2 may have a different voltage level than the first pre-charge voltage VPRE_1, and the difference between the first pre-charge voltage VPRE_1 and the second pre-charge voltage VPRE_2 may correspond to a level used to compensate for the difference in sensing characteristics caused by the difference between the length of the first bit line BL1 and the length of the second bit line BL2.

[0150] In operation S240, the storage device 10 can perform multi-bit sensing on the storage cells connected to the second bit line BL2 via the second sense amplifier 200_2 connected to the second bit line BL2. Operation S240 may include... Figure 5A The series of processes corresponding to operations S120 to S150.

[0151] Despite Figure 10 Operations S230 and S240 are executed sequentially after operations S210 and S220, but the embodiment is not limited to this. For example, operations S230 and S240 can be executed simultaneously with operations S210 and S220. In other words, operations S230 and S240 can be executed in parallel with operations S210 and S220.

[0152] Figure 11 This is a flowchart of the sensing operation of the storage device according to an embodiment. It will be referred to together with the above. Figure 7 and Figure 9 To describe Figure 11 .

[0153] In operation S310, during the MSB sensing operation and / or LSB sensing operation of the first sense amplifier 200_1 connected to the first bit line BL1, the storage device 10 can apply a first power supply voltage VINTA1_1 of a first level to the first sense amplifier 200_1. In an embodiment, during the MSB sensing operation and / or LSB sensing operation of the first sense amplifier 200_1, the first power supply voltage VINTA1_1 of a first level can be applied to a first latch pull-up drive signal in the first latch of the first sense amplifier 200_1.

[0154] In operation S320, during the MSB sensing operation and / or LSB sensing operation of the second sense amplifier 200_2 connected to the second bit line BL2, the storage device 10 can apply a first power supply voltage VINTA1_2 of the second level to the second sense amplifier 200_2. In an embodiment, during the MSB sensing operation and / or LSB sensing operation of the second sense amplifier 200_2, the first power supply voltage VINTA1_2 of the second level can be applied to a first latch pull-up drive signal in the first latch of the second sense amplifier 200.

[0155] In an embodiment, the first power supply voltage VINTA1_2 of the second level may have a different voltage level than the first power supply voltage VINTA1_1 of the first level, and the difference between the first power supply voltage VINTA1_1 of the first level and the first power supply voltage VINTA1_2 of the second level may correspond to a level used to compensate for the difference in sensing characteristics caused by the difference between the length of the first bit line BL1 and the length of the second bit line BL2.

[0156] Despite Figure 11 Operation S320 is executed sequentially after operation S310, but the embodiment is not limited to this. For example, operation S310 can be executed simultaneously with operation S320. In other words, operation S310 can be executed in parallel with operation S320.

[0157] Figure 12 This is a flowchart of the sensing operation of the storage device according to an embodiment. It will be referred to together with the above. Figure 7 and Figure 9 To describe Figure 12 .

[0158] In operation S410, during the MSB sensing operation of the first sense amplifier 200_1 connected to the first bit line BL1, the storage device 10 can apply a third-level second power supply voltage VINTA2_1 to the first sense amplifier 200_1. In an embodiment, during the MSB sensing operation of the first sense amplifier 200_1, the third-level second power supply voltage VINTA2_1 can be applied to the second latch pull-up drive signal in the second latch of the first sense amplifier 200_1.

[0159] In operation S420, during the MSB sensing operation of the second sense amplifier 200_2 connected to the second bit line BL2, the storage device 10 can apply a fourth-level second power supply voltage VINTA2_2 to the second sense amplifier 200_2. In an embodiment, during the MSB sensing operation of the second sense amplifier 200_2, the fourth-level second power supply voltage VINTA2_2 can be applied to the second latch pull-up drive signal in the second latch of the second sense amplifier 200_2.

[0160] In an embodiment, the second power supply voltage VINTA2_2 of the fourth level may have a different voltage level than the second power supply voltage VINTA2_1 of the third level, and the difference between the second power supply voltage VINTA2_1 of the third level and the second power supply voltage VINTA2_1 of the fourth level may correspond to a level used to compensate for the difference in sensing characteristics caused by the difference between the length of the first bit line BL1 and the length of the second bit line BL2.

[0161] Figure 13 This is a flowchart of the sensing operation of the storage device according to an embodiment. It will be referred to together with the above. Figure 7 and Figure 9 To describe Figure 13 .

[0162] In operation S510, during the recovery operation of the first sense amplifier 200_1 connected to the first bit line BL1, the storage device 10 can apply a second power supply voltage having a first recovery level to the first sense amplifier 200_1. In an embodiment, during the recovery operation of the first sense amplifier 200_1, the second power supply voltage having a first recovery level can be applied to the second latch pull-up drive signal in the second latch of the first sense amplifier 200_1.

[0163] In operation S520, during the recovery operation of the second sense amplifier 200_2 connected to the second bit line BL2, the storage device 10 can apply a second power supply voltage having a second recovery level to the second sense amplifier 200_2. In an embodiment, during the recovery operation of the second sense amplifier 200_2, a second power supply voltage having a second recovery level can be applied to a second latch pull-up drive signal in the second latch of the second sense amplifier 200_2.

[0164] In an embodiment, the second power supply voltage having a second recovery level may have a different voltage level than the second power supply voltage having a first recovery level, and the difference between the first recovery level and the second recovery level may correspond to a level used to compensate for the difference in sensing characteristics caused by the difference between the length of the first bit line BL1 and the length of the second bit line BL2.

[0165] Figure 14 This is a timing diagram of the signals of the storage device according to an embodiment. As described above, Figure 14 A variation of an embodiment is shown, in which different drive voltages are used for the first sense amplifier 200_1 and the second sense amplifier 200_2. (See also...) Figure 7 as well as Figures 10 to 13 To describe Figure 14 .

[0166] Reference Figure 10 and Figure 14 During the precharge operation period, the precharge voltage VPRE used for precharging the bit line can be different between the first sense amplifier 200_1 and the second sense amplifier 200_2.

[0167] Reference Figure 11 and Figure 14 During the MSB sensing operation period and / or LSB sensing operation period, the first power supply voltage VINTA1 of the first latch pull-up drive signal LA1 applied to the first latch can be different between the first sense amplifier 200_1 and the second sense amplifier 200_2.

[0168] Reference Figure 12 and Figure 14 During the MSB sensing operation period, the second power supply voltage VINTA2 applied to the second latch pull-up drive signal LA2 in the second latch can be different between the first sense amplifier 200_1 and the second sense amplifier 200_2.

[0169] Reference Figure 13 and Figure 14During the recovery operation period, the second power supply voltage and the second pull-down voltage applied to the second latch pull-up drive signal LA2 and the second latch pull-down drive signal LAB2 in the second latch can be different between the first readout amplifier 200_1 and the second readout amplifier 200_2.

[0170] The method for compensating for differences in sensing characteristics caused by length differences between bit lines can be referred to above. Figures 10 to 13 The variations described can be used simultaneously in the embodiments. Figures 10 to 13 At least two methods are involved. In other words, according to the embodiment, the level of the pre-charge voltage and the level of the first power supply voltage may be different between the first sense amplifier 200_1 and the second sense amplifier 200_2.

[0171] Figure 15 This is a flowchart of a method for setting a drive voltage in a storage device according to an embodiment. (To be referenced together) Figure 7 To describe Figure 15 .

[0172] In operation S610, the designer of the storage device can perform test sensing on multiple sense amplifiers, including the first sense amplifier 200_1 and the second sense amplifier 200_2, for various cell voltages Vcell.

[0173] In operation S620, the designer can obtain the fault cell distribution based on the test sensing performed in operation S610. The designer can obtain the fault cell distribution with respect to the first sense amplifier 200_1 and the fault cell distribution with respect to the second sense amplifier 200_2. In an embodiment, the obtained fault cell distribution can be as follows: Figure 8 As shown.

[0174] In operation S630, the designer can determine the level of the first drive voltage VD_1 and the level of the second drive voltage VD_2 based on the fault cell distribution obtained in operation S620.

[0175] In operation S640, the designer can set the determined level of the first drive voltage VD_1 and the level of the second drive voltage VD_2 in the storage device 10. The storage device 10 can drive the first sense amplifier 200_1 based on the set level of the first drive voltage VD_1, and drive the second sense amplifier 200_2 based on the set level of the second drive voltage VD_2.

[0176] When the driving voltage setting method according to this embodiment is used, the difference in sensing characteristics caused by the difference between the length of the first bit line and the length of the second bit line can be effectively compensated.

[0177] Figure 16 A readout amplifier 200 according to an embodiment is shown. Figure 16 A sense amplifier 200 capable of performing sensing operations on unit data is shown. (See also...) Figure 7 To describe Figure 16 .

[0178] and Figure 4 Compared to the 200 readout amplifier, Figure 16 The sense amplifier 200 can include only one latch because the sense amplifier 200 needs to sense a single bit. The latch operates similarly to... Figure 4 The operation of the first latch in the code will be omitted in its detailed description.

[0179] Each of the first readout amplifier 200_1 and the second readout amplifier 200_2 can correspond to Figure 16 The readout amplifier 200. At this time, the difference in sensing characteristics caused by the difference between the length of the first bit line BL1 and the length of the second bit line BL2 still exists.

[0180] To compensate for this difference in sensing characteristics caused by the length difference between bit lines, similar to the description given above with reference to the accompanying drawings, different pre-charge voltages can be applied to the sense amplifier 200 that performs sensing operations on unit data. A representative embodiment will now be described with reference to the accompanying drawings.

[0181] Figure 17 This is a flowchart of the sequential operation method of the readout amplifier according to an embodiment. It will be referred to together with... Figure 7 and Figure 16 To describe Figure 17 .

[0182] In operation S710, during the pre-charge operation period of the sensing operation performed on the memory cell connected to the first bit line BL1, the memory device 10 can pre-charge the first bit line BL1 using the first pre-charge voltage VPRE_1. For this operation, the first drive voltage supply circuit 810 can supply the first pre-charge voltage VPRE_1 to the first sense amplifier 200_1.

[0183] In operation S720, the storage device 10 can perform unit sensing on the storage cells connected to the first bit line BL1 via the first sense amplifier 200_1 connected to the first bit line BL1. Operation S720 may include a series of processes for sensing unit data from the storage cells.

[0184] In operation S730, during the pre-charge operation period of the sensing operation performed on the memory cell connected to the second bit line BL2, the memory device 10 can pre-charge the second bit line BL2 using the second pre-charge voltage VPRE_2. For this operation, the second drive voltage supply circuit 820 can supply the second pre-charge voltage VPRE_2 to the second sense amplifier 200_2.

[0185] In an embodiment, the second pre-charge voltage VPRE_2 may have a different voltage level than the first pre-charge voltage VPRE_1, and the difference between the first pre-charge voltage VPRE_1 and the second pre-charge voltage VPRE_2 may correspond to a level used to compensate for the difference in sensing characteristics caused by the difference between the length of the first bit line BL1 and the length of the second bit line BL2.

[0186] In operation S740, the storage device 10 can perform unit sensing on the memory cells connected to the second bit line BL2 via the second sense amplifier 200_2 connected to the second bit line BL2. Operation S740 may include a series of processes for sensing unit data from the memory cells.

[0187] In an embodiment, Figure 18 The long bit line Long BL in the memory can correspond to the readout amplifier located at the edge of the memory device 10.

[0188] Figure 18 This is a timing diagram of signals during sensing and pre-charging operations on bit lines (e.g., Short BL and Long BL) according to an embodiment. It will be referred to together with... Figure 7 To describe Figure 18 .

[0189] During the sensing operation period between time points T1 and T2, the long bit line BL can be driven using a second driving voltage VINTA_2, which is higher than the first driving voltage VINTA_1 corresponding to the short bit line BL. Therefore, during the operation period between time points T3 and T4, the voltage level of the long bit line BL is substantially the same as the voltage level of the short bit line BL.

[0190] According to an embodiment, during the time period between time points T2 and T3, the pre-charge voltage VPRE may be different between the long bit line (Long BL) and the short bit line (Short BL). However, the embodiment is not limited to this, and the pre-charge voltage VPRE may be the same between the long bit line (Long BL) and the short bit line (Short BL).

[0191] Figure 19It is a timing diagram of signals in sensing and pre-charging operations of on-bit lines (e.g., short bit lines and long bit lines) according to an embodiment. Figure 19 It shows the relationship with Figure 18 Similar to, but different from, the embodiments.

[0192] Reference Figure 19 The first drive voltage VINTA_1 can be used to precharge both the long bit line (Long BL) and the short bit line (Short BL) during the sensing operation period between time points T1 and T2.

[0193] However, during the period between time point T2 and time point T2', boosting can be performed only on the long bit line (Long BL). At this time, the voltage level of the long bit line (Long BL) can rise to the voltage level of the second drive voltage (VINTA_2). Therefore, it is possible to occur... Figure 18 The embodiments using different drive voltages achieve essentially the same effect. Therefore, during the operating period between time points T3 and T4, the voltage level of the long bit line (Long BL) is essentially the same as the voltage level of the short bit line (Short BL).

[0194] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A volatile storage device, the volatile storage device comprising: A first sense amplifier is connected to a first memory cell via a first bit line and is configured to sense 2 bits of data stored in the first memory cell; A second sense amplifier is connected to a second memory cell via a second bit line and is configured to sense 2 bits of data stored in the second memory cell, wherein the length of the second bit line is greater than the length of the first bit line. and A drive voltage supply circuit is configured to supply a first drive voltage to the first sense amplifier and a second drive voltage to the second sense amplifier, wherein the voltage level of the second drive voltage is different from the voltage level of the first drive voltage. The driving voltage supply circuit is further configured as follows: During at least one of the most significant bit sensing operation period and the least significant bit sensing operation period of the sensing operation on the first memory cell, a first power supply voltage having a first voltage level is supplied to the first sense amplifier to drive the pull-up terminal of the first latch, which is included in the first sense amplifier as a first latch and a second latch. and During at least one of the most significant bit sensing operation period and the least significant bit sensing operation period of the sensing operation on the second memory cell, the first power supply voltage having a second voltage level is supplied to the second sense amplifier to drive the pull-up terminal of the third latch, which is included in the third latch and the fourth latch in the second sense amplifier.

2. The volatile storage device according to claim 1, wherein, The drive voltage supply circuit is further configured as follows: The first bit line is precharged using the first precharge voltage by supplying a first precharge voltage during the precharge period of the sensing operation on the first memory cell; and The second bit line is precharged using the second precharge voltage by supplying a second precharge voltage during the precharge period of the sensing operation on the second memory cell; The second pre-charge voltage is different from the first pre-charge voltage.

3. The volatile storage device according to claim 2, wherein, The difference between the first pre-charge voltage and the second pre-charge voltage corresponds to the difference between the capacitance of the first bit line and the capacitance of the second bit line.

4. The volatile storage device according to claim 1, wherein, The first latch is configured to sense the least significant bit of the 2-bit data stored in the first memory cell and latch the least significant bit to the first sensing bit line pair; and The second latch is configured to sense the most significant bit of the 2-bit data stored in the first memory cell and latch the most significant bit to the second sensing bit line pair, and in, The third latch is configured to sense the least significant bit of the 2-bit data stored in the second memory cell and latch the least significant bit to the third sensing bit line pair; and The fourth latch is configured to sense the most significant bit of the 2-bit data stored in the second memory cell and latch the most significant bit to the fourth sense bit line pair.

5. The volatile storage device according to claim 1, wherein, The difference between the first voltage level and the second voltage level corresponds to the difference between the length of the first bit line and the length of the second bit line.

6. The volatile storage device according to claim 4, wherein, The drive voltage supply circuit is further configured as follows: During the most significant bit sensing operation period of the sensing operation of the first memory cell, a first power supply voltage with a first voltage level is supplied to the first sense amplifier to drive the pull-up terminal of the second latch. and During the most significant bit sensing operation period of the sensing operation on the second memory cell, the first power supply voltage with a second voltage level is supplied to the second sense amplifier to drive the pull-up terminal of the fourth latch.

7. The volatile storage device according to claim 6, wherein, The difference between the first voltage level and the second voltage level corresponds to a voltage level used to compensate for the difference between the sensing characteristics of the first sense amplifier and the sensing characteristics of the second sense amplifier.

8. The volatile storage device according to claim 4, wherein, The drive voltage supply circuit is further configured as follows: During the recovery operation period of the sensing operation of the first memory cell, a first power supply voltage with a first voltage level is supplied to the first sense amplifier to drive the pull-up terminal of the second latch. and During the recovery operation period of the sensing operation of the second memory cell, the first power supply voltage with a second voltage level is supplied to the second sense amplifier to drive the pull-up terminal of the fourth latch.

9. The volatile storage device according to claim 8, wherein, The drive voltage supply circuit is further configured to: During the recovery operation period of the sensing operation of the first memory cell, a first pull-down voltage having a third voltage level is supplied to the first sense amplifier to drive the pull-down terminal of the second latch. and During the recovery operation period of the sensing operation of the second memory cell, the first pull-down voltage having a fourth voltage level is supplied to the second sense amplifier to drive the pull-down terminal of the fourth latch.

10. A data sensing method for a volatile storage device, the data sensing method comprising: The first bit line is precharged using the first precharge voltage; The first 2 bits of data are sensed by a first sense amplifier connected to the first bit line, and the first 2 bits of data are stored in a first memory cell connected between the first bit line and the selected word line; The second bit line is precharged using a second precharge voltage different from the first precharge voltage, and the length of the second bit line is greater than the length of the first bit line. and A second 2-bit data is sensed by a second sense amplifier connected to the second bit line, and the second 2-bit data is stored in a second memory cell connected between the second bit line and the selected word line. The difference between the first precharge voltage and the second precharge voltage is determined based on the distribution of fault cells that occurs when multiple cell voltages are applied to each of the first sense amplifier and the second sense amplifier.

11. The data sensing method according to claim 10, wherein, The difference between the first precharge voltage and the second precharge voltage corresponds to a level used to compensate for the difference between the sensing characteristics of the first sense amplifier and the sensing characteristics of the second sense amplifier.

12. The data sensing method according to claim 10, wherein, Sensing the first 2 bits of data includes: The most significant bit of the first two bits of data is sensed using a first latch driven by a first power supply voltage; and The most significant bit of the first two bits of data is latched in a second latch driven by a second power supply voltage, and Sensing the second 2-bit data includes: A third latch driven by a third power supply voltage is used to sense the most significant bit of the second 2-bit data; and The most significant bit of the second 2-bit data is latched in a fourth latch driven by a fourth power supply voltage.

13. The data sensing method according to claim 12, wherein, The voltage level of the first power supply voltage is different from the voltage level of the third power supply voltage, and Wherein, the difference between the voltage level of the first power supply voltage and the voltage level of the third power supply voltage corresponds to the difference between the capacitance of the first bit line and the capacitance of the second bit line.

14. The data sensing method according to claim 12, wherein, The voltage level of the second power supply voltage is different from the voltage level of the fourth power supply voltage, and The difference between the voltage level of the second power supply voltage and the voltage level of the fourth power supply voltage corresponds to the difference between the length of the first bit line and the length of the second bit line.

15. The data sensing method according to claim 10, further comprising: Based on the first pull-up drive voltage and the first pull-down drive voltage, the sensed first 2-bit data is recovered in the first memory cell; and Based on the second pull-up drive voltage and the second pull-down drive voltage, the sensed second 2-bit data is recovered in the second memory cell; Wherein, the first pull-up drive voltage is different from the second pull-up drive voltage, and the first pull-down drive voltage is different from the second pull-down drive voltage.

16. A data sensing method for a storage device, the storage device comprising a volatile storage unit storing 1 bit of data, the data sensing method comprising: In a sensing operation on a first memory cell connected to a first bit line having a first length, the first bit line is precharged with a first precharge voltage. Sensing the first 1-bit data stored in the first storage unit; In a sensing operation on a second memory cell connected to a second bit line having a second length longer than the first length, the second bit line is precharged with a second precharge voltage different from the first precharge voltage. Sensing the second 1-bit data stored in the second storage unit; Based on the first pull-up drive voltage and the first pull-down drive voltage, the sensed first 2-bit data is recovered in the first memory cell; and Based on the second pull-up drive voltage and the second pull-down drive voltage, the sensed second 2-bit data is recovered in the second memory cell; Wherein, the first pull-up drive voltage is different from the second pull-up drive voltage, and the first pull-down drive voltage is different from the second pull-down drive voltage.

17. The data sensing method according to claim 16, wherein, The voltage level of the second pre-charge voltage is higher than the voltage level of the first pre-charge voltage.

18. The data sensing method according to claim 17, wherein, The difference between the first pre-charge voltage and the second pre-charge voltage corresponds to the difference between the first length and the second length.

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