Fault-tolerant error correction layout for memory subsystems

Abstract

A codeword of an error correction code may be received. The codeword may be divided into a plurality of segments. The segments of the codeword may be distributed across a plurality of dies in an error correction layout, wherein at least a portion of the error correction layout constitutes a Latin Square (LS) layout.

Description

Technical Field

[0001] The present disclosure relates generally to memory subsystems, and more particularly to an improved error correction layout with higher tolerance to die failures in a memory subsystem. Background Art

[0002] The memory subsystem may be a storage system, such as a solid state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0004] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is shown.

[0005] Figure 2 The general layout of an ECC-XOR system is shown.

[0006] Figure 3A An initial mapping of code fields on multiple dies before final mapping to a partial Latin square (LS) ECC-XOR layout is shown according to some embodiments of the present disclosure.

[0007] Figure 3B The final mapping of the code fields after applying the appropriate shift amount to the initial mapping to create a partial LS layout according to some embodiments of the present disclosure is shown.

[0008] Figure 4A The initial mapping of code fields on multiple dies before final mapping into a full LS ECC-XOR layout according to some embodiments of the present disclosure is shown.

[0009] Figure 4B The final mapping of the code fields after applying the appropriate shift amount to the initial mapping to create a complete LS layout is shown according to some embodiments of the present disclosure.

[0010] Figure 5 is a flowchart of an example method of creating an LS layout according to an embodiment of the present disclosure.

[0011] Figure 6 is a system design flow chart illustrating the difference between a complete LS layout and a partial LS layout according to an embodiment of the present disclosure.

[0012] Figure 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to designing improved layouts for error correction schemes of memory subsystems. A memory subsystem is also referred to as a "memory device" hereinafter. An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to a CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), etc. In some embodiments, a memory subsystem may be a hybrid memory / storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0014] Error Correction Code (ECC) is a technique for controlling errors in data stored in a memory subsystem. ECC involves generating parity values ​​for error detection and correction during transmission so that the correct data can be reconstructed by using a decoder without the need for retransmission. Exclusive OR (XOR) is a Boolean logic operation that generates a parity value for a pair of bits. A codeword is an element of an ECC whose length is equal to the length of the original data (payload) plus the length of the parity bits. If C1, C2, ..., C n-1 are codewords of the same linear code (e.g., Bose-Chaudhuri-Hocquenghem (BCH)), then the resulting XOR value (i.e., parity value) is It can be regarded as another valid codeword with error correction capability.

[0015] In a conventional ECC-XOR scheme, a single codeword is assigned to a single die. Multiple codewords from the corresponding die are then grouped together to calculate an XOR value, which is also stored in the single die. Since each codeword and XOR value are stored in the corresponding single die, the disadvantage of the conventional ECC-XOR scheme is that only shorter codewords can be used, which means lower error correction capability. Conventional ECC designs are limited by the worst quality die, not by the average quality of the die.

[0016] Aspects of the present disclosure address the above and other deficiencies by assigning a single ECC codeword to multiple die. Each codeword is divided into multiple segments distributed across multiple die. Multiple codewords are grouped together to calculate an XOR value. The XOR value is also segmented. The codeword field and the XOR segment are stored in different die in a Latin Square (LS) layout. Generally speaking, an LS is an arrangement of letters or symbols, each letter or symbol having its own space in n 2 The LS layout is an arrangement of memory cells where each memory cell stores a segment of a codeword that is not repeated along the same column or row. Even if a die or a portion of the die (including one or more memory cells) fails, the data can be reconstructed by decoding the remaining segments of the same codeword retrieved from intact memory cells, i.e., without physical damage or other failures.

[0017] Thus, the improved ECC-XOR layout described herein is generally more capable of handling faults. The advantages of the present disclosure include, but are not limited to, the ability to use longer codewords, because the probability of failure of the entire ECC-XOR scheme is greatly reduced. Longer codewords mean more powerful error correction capabilities. Since the ECC-XOR layout design adapts to the average quality of the die rather than the worst quality of the die, enhanced error correction capabilities can be utilized, because the limitations caused by the worst quality die can be largely compensated by the higher quality die. Therefore, in the improved ECC-XOR layout, the possible demand for data recovery is much lower. As an illustrative example, for a system with 16 die, a conventional ECC-XOR scheme uses a 64-byte ECC codeword. The improved ECC-XOR scheme described herein can construct a much longer 1024-byte codeword on 16 available die by a 64-byte segment. The ECC-XOR scheme using 1024-byte ECC codewords is much more capable of error correction than the conventional scheme using 64-byte codewords. The ECC codewords of the improved scheme need to handle the average error behavior from 16 dies, because the lower quality dies with higher errors can be averaged out by the higher quality dies with lower errors. That is, the improved ECC-XOR layout improves the error statistics observed by the ECC code. The LS layout also enhances parallel operation at the die level because the codewords are distributed among multiple dies. In addition, the memory subsystem utilizing the stronger ECC-XOR scheme can improve the error correction operation for the data stored at the memory subsystem. Therefore, the reliability of the data stored at the memory subsystem is improved because stronger error correction can be utilized.

[0018] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is shown. The memory subsystem 110 may include media, such as memory components 112A to 112N. The memory components 112A to 112N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0019] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110, so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including, for example, electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fiber Channel, a Serial Attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0020] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A to 112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more bits (e.g., a data block) of data used by the host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point (XP) array of non-volatile memory cells (including a three-dimensional cross-point (3DXP) array). The cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, the cross-point non-volatile memory may perform write-in-place operations, where the non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. In addition, the memory cells of the memory components 112A to 112N may be grouped into memory pages or data blocks, which may refer to cells of a memory component for storing data. Those skilled in the art will readily appreciate that the scope of the ECC-XOR scheme described in this disclosure is not limited by the type of memory technology used.

[0021] The memory system controller 115 (hereinafter referred to as the "controller") can communicate with the memory components 112A to 112N to perform operations, such as reading data, writing data, or erasing data at the memory components 112A to 112N, and other such operations. The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communications between the memory subsystem 110 and the host system 120). In some embodiments, the local memory 119 may include memory registers that store memory pointers, extracted data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a controller 115, but instead relies on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0022] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical block addresses and physical block addresses associated with the memory components 112A to 112N. The controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory components 112A to 112N, and convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0023] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A to 112N.

[0024] The memory subsystem 110 includes an error correction component 113 that implements an ECC-XOR code. In some embodiments, the controller 115 includes at least a portion of the error correction component 113. For example, the controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the error correction component 113 is part of a host system 120, an application, or an operating system. The error correction component 113 includes one or more of a circuit system, dedicated logic, programmable logic, firmware, etc. to perform the operations described herein. The error correction component 113 can generate an ECC-XOR layout. For example, a Latin square (LS) ECC-XOR layout can be implemented as described in further detail below.

[0025] Figure 2 A conventional ECC-XOR layout is shown. As described above, codewords C1, C2, C3, ..., C m-1 are all elements of the same linear code (e.g., BCH code). Each die stores a complete codeword. For example, die 1 stores all bits of codeword C1, die 2 stores all bits of codeword C2, and so on. Each codeword in the codeword can be designed as C i =[n,k i ], where k is the length of the data (payload), and n is the length of the data including the ECC, and i = 1, 2, ..., (m-1). All (m-1) codewords are then grouped to perform an XOR operation, and the result of the XOR is stored in another die (die m ). This scheme creates some tolerance to failures by creating XOR values ​​(i.e., parity bits of length n) and storing the XOR values ​​in an additional die. However, since the design is limited by the quality of the worst die, conventional error correction schemes produce suboptimal results. Therefore, additional data recovery schemes are needed to improve error correction results.

[0026] Figure 3A-3B and Figure 4A-4BThe proposed Latin Square (LS) ECC-XOR layout is shown to support a stronger ECC scheme designed for average quality dies (rather than the worst quality dies) to produce optimal error correction results. The layout disclosed herein tolerates single die failure by segmenting each codeword and storing the codewords separately in different storage cells distributed across multiple dies. Specifically, Figure 3A-3B Partial LS layout involving ECC-XOR, and Figure 4A-4B Full LS layout involving ECC-XOR. In both partial and full LS layouts, XOR is performed by grouping all codewords, and the resulting XOR values ​​are also segmented. Depending on whether all XOR segments are stored in a single die or distributed across all dies, the layout is called partial LS or full LS. This is further explained below.

[0027] Return to reference Figure 3A , each codeword is divided into an equal number of segments and initially mapped to different memory cells on multiple dies. For example, codeword C1 is divided into (m-1) segments distributed across (m-1) dies. Similarly, codeword C2 is also divided into (m-1) segments distributed across the same (m-1) dies. In general, (m-1) codewords that are segmented and distributed across (m-1) dies create a table 305 of dimensions (m-1) by (m-1), such as Figure 3A Each cell in table 305 indicates a physical memory cell 310 that can store a number of bits of a code field. The numerical values ​​shown within the cells of table 305 indicate the segment index of the codeword (i.e., the i-th segment of the codeword), not the index of the codeword itself. Initially, the i-th segment of each codeword is associated with the i-th die. For example, the first segment of C1, the first segment of C2, and so on. m-1 The first segment of C1 is associated with die 1 along the first column of the table. Therefore, each cell in the first column shows an index of 1. Similarly, the second segment of C1, the second segment of C2, and so on. m-1 The second segment of C1 is associated with die 2. Following the same pattern, segment (m-1) of C1, segment (m-1) of C2, and so on. m-1 The (m-1)th segment of the chip (m-1) Associated.

[0028] But before the proper shift amount is applied, the initial mapping of the code fields across multiple dies shown in table 305 is not in Latin square format. Figure 3AThe applicable shift amount along each row is listed (shown on the right side of table 305) to create an LS format for the ECC-XOR layout. The appropriate shift amount can be equal to zero. For example, the first row of table 305 is not shifted. The second row is shifted right by one segment, the third row is shifted right by two segments, the fourth row is shifted right by three segments, etc., until the (m-1)th row is shifted by (m-2) segments. It should be noted that shifting segments to the left or other shifting schemes are also within the scope of the present disclosure. For example, the i-th row can be shifted right or left or up or down by (ij) segments, where j can be any number. The result of the shifted segment may not always be an LS layout, but it will still improve the fault tolerance relative to the conventional layout. In an embodiment where the result of the shifted segment is an (complete or partial) LS layout, each code field with the same segment index appears exactly once in each column, but the order of different segments along the columns within a single die is not necessarily continuous. In fact, the ordering along the columns within a single die can be any arrangement of '(m-1)' elements in a partial LS layout, or any arrangement of 'm' elements in a full LS layout.

[0029] Figure 3B Shown according to Figure 3A The shifting scheme shown applies a modified mapping of the code fields after a variable shift amount. The entire layout 320 has two parts: a part 350 in LS format with dimensions (m-1) by (m-1), and a part 360 beyond the LS. Since the LS part 350 does not span the entire layout 320, this layout is referred to as a partial LS. The part 350 of the layout 320 contains memory cells where data information is stored by corresponding ECC code fields. The XOR value is calculated by grouping all code words, i.e. XOR value C m is also segmented into (m-1) segments. Although all segments of the XOR value are stored in different storage cells along a single column in portion 360 of layout 320, all segments are stored in a single die (die m )middle.

[0030] Within the LS portion 350 of the layout, the first row has all the segments of C1, but the segments are not shifted to the right. Thus, the first segment of C1 is stored in Die 1, the second segment of C2 is stored in Die 2, etc. The second row has all the segments of C2, but the segments are shifted to the right by one die position. Thus, the first segment of C2 is stored in Die 2, the second segment of C2 is stored in Die 3, etc. The third row has all the segments of C3, but the segments are shifted to the right by two die positions. Thus, the first segment of C3 is stored in Die 3, the second segment of C3 is stored in Die 4, etc. In a similar manner, the (m-1)th row within the LS portion 350 of the layout has C2. m-1 but shifted to the right by (m-2) die positions. Therefore, Cm-1 The first segment is stored in the die m-1 In, C m-1 The second segment is stored in die 1 and so on.

[0031] Figure 4A An initial mapping table 405 for creating an 'm×m' LS layout of a code field is shown. Here, the XOR value generated by grouping the first (m-1) codewords is considered as the mth codeword. Each of the codewords containing the XOR value codeword is divided into m segments, which are stored on m dies. Figure 4A For the scheme shown, the appropriate shift amount on the right side of table 405 is applied to this initial mapping.

[0032] Figure 4B Shown according to Figure 4A The shifting scheme shown applies a modified mapping of the code fields after a variable shift amount. The entire layout 420 is in LS format (of dimensions m×m). The layout 420 has two parts: part 450, and part 460, which together constitute the LS. Since the LS part spans the entire layout 420, this layout is referred to as a full LS. Part 450 of the layout 420 contains memory cells in which data information is stored by corresponding ECC code fields. As previously mentioned, the XOR value is calculated by grouping (m-1) code words, i.e. C m is itself a codeword and is divided into m segments. Each segment of XOR values ​​is stored in a corresponding die in portion 460 distributed over the m dies.

[0033] In the complete LS layout 420, the first row has all the segments of C1, but the segments are not shifted to the right. Therefore, the first segment of C1 is stored in Die 1, the second segment of C2 is stored in Die 2, etc. The second row has all the segments of C2, but the segments are shifted to the right by one die position. Therefore, the first segment of C2 is stored in Die 2, the second segment of C2 is stored in Die 3, etc. The third row has all the segments of C3, but the segments are shifted to the right by two die positions. Therefore, the first segment of C3 is stored in Die 3, the second segment of C3 is stored in Die 4, etc. In a similar manner, the (m-1)th row in the LS layout 420 has C1. m-1 but shifted to the right by (m-2) die positions. Therefore, C m-1 The first segment is stored in the die m-1 In, C m-1 The second segment of is stored in die 1, etc. And, finally, the mth row within LS layout 420 has XOR (ie, codeword C m ), but shifted right by (m-1) die positions. m The first segment is stored in the diem In, C m The second segment is stored in die 1 and so on.

[0034] Figure 3B and 4B The arrangement shown is only one embodiment in which all segments of a single codeword are stored in the same row. This embodiment may be easy to implement, but does not limit the scope of the present disclosure. Different segments of a single codeword can be stored in different rows as long as the characteristic LS property of non-repeating units along each column and each row is retained.

[0035] Figure 5 5 is a flow chart of an example method 500 for creating an ECC-XOR layout according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 may be performed by a processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, a hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Figure 1 The error correction component 113 of the embodiment of the present invention performs the method 500. Although shown in a specific order or sequence, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0036] At operation 510, processing logic obtains a set of codewords. As previously described, these codewords are elements of a linear code such as BCH. Any number of codewords may be used. When a host system provides user data to be stored at a memory subsystem, a set of codewords may be obtained. Error control operations utilized by the memory subsystem may generate a set of codewords by encoding the user data. At operation 520, processing logic assigns a set of dies to each codeword. The total number of codewords is equal to the number of dies.

[0037] At operation 530, processing logic divides each codeword into multiple segments. The code fields are to be distributed across a set of dies. If there are (m-1) dies assigned to each codeword, then each of the codewords is divided into (m-1) segments.

[0038] At operation 540, the processing logic calculates an XOR value based on the codeword set. All (m-1) codewords are grouped together to calculate the XOR value. The XOR value has error correction capabilities and is therefore equivalent to another codeword (i.e., the mth codeword). The XOR value is also divided into multiple segments. The XOR value can be regarded as a parity check value for the codeword set.

[0039] At step 550, the appropriate shift amount is applied to each of the code fields to arrange the code fields in the ECC-XOR LS layout, as described with respect to Figure 3A-3B and Figure 4A-4B For example, the code fields may be stored on a die by applying any shift to each of the code fields.

[0040] Figure 6 is a system design flow chart showing the difference between a full LS layout and a partial LS layout according to an embodiment of the present disclosure. Both the partial LS layout and the full LS layout can handle a variety of die qualities. As shown in block 650, the memory subsystem selects a partial LS or a full LS based on system design parameters (e.g., number of channels, code field size, host access capability, etc.).

[0041] For some LS layouts, the calculated XOR value (for example, in Figure 5 All bits of the XOR bits (the value calculated in operation 540 of method 500 in ) are stored in a single die, as described in operation 655. For example, as shown in box 655, the memory subsystem stores all XOR bits in multiple memory cells of a single die. It should be noted that although all XOR bits are stored in a single die, the die can have multiple memory cells. The die storing the XOR bits is usually the die with the worst quality, that is, the die with the highest probability of failure. However, in terms of potential data recovery, it is wiser to store the XOR bits in the die with the worst quality than to store the code field in the die with the worst quality. The data bits for the ECC codeword are stored in other available storage cells in other dies arranged in a partial LS layout, and the quality of the other dies is better than the quality of the die storing the XOR bits.

[0042] For the full LS layout, the calculated XOR value (for example, in Figure 5 The bits of the XOR segment (the value calculated in operation 540 of method 500 in FIG. 5 ) are evenly distributed across all the dies so that each die stores the bits of one XOR segment. For example, as shown in block 660, the memory subsystem evenly distributes the XOR bits across all the dies so that each die stores one XOR segment. Since the XOR bits are evenly distributed across the dies, the overall probability of failure due to a single die failure is reduced. The data bits for the ECC codeword are stored in other available storage cells in other dies.

[0043] Figure 7 An example machine of computer system 700 is shown, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 11) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the embodiment of the present invention may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the form of a server or a client machine in a client-server network environment, or in the form of a server or a client machine in a cloud computing infrastructure or environment.

[0044] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is shown, the term "machine" should also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0045] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0046] Processing device 702 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. Processing device 702 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 to communicate via a network 720.

[0047] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to Figure 1 Memory subsystem 110.

[0048] In one embodiment, the instructions 726 include instructions for implementing a corresponding pre-read adjustment component (eg, Figure 1 The machine-readable storage medium 724 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0049] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively communicate the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that result in a desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, quantities, etc.

[0050] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device to manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and transform the data into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0051] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or the apparatus may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0052] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0053] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory component, etc.

[0054] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method performed by a memory subsystem, the method comprising: receiving a plurality of codewords of an error correction code for the memory subsystem; dividing the plurality of codewords of the error correction code into a plurality of segments, wherein the plurality of segments are distributed across a plurality of dies of the memory subsystem; Calculate an XOR value based on the multiple code words; applying respective shifts to the plurality of segments of the plurality of codewords such that the plurality of segments are arranged in a Latin Square (LS) layout across the plurality of dies in the memory subsystem, wherein a number of codewords in the plurality of codewords is equal to a number of dies in the plurality of dies, and wherein code fields along columns or rows of the LS layout are not repeated; and An error correction layout distribution is formed on the plurality of dies, wherein at least a portion of the error correction layout constitutes the LS layout.

2. The method of claim 1, wherein each codeword of the plurality of codewords is divided into an equal number of segments. 3 . The method of claim 2 , wherein the number of segments in each codeword is equal to the number of dies in the plurality of dies.

4. The method of claim 3, wherein each die of the plurality of dies includes a plurality of memory cells.

5. The method of claim 4, wherein the number of memory cells in each die is equal to the number of segments in each codeword.

6. The method according to claim 1, further comprising: The XOR value is stored in an additional die outside the LS layout and within the error correction layout.

7. The method according to claim 1, further comprising: The XOR values ​​are stored within the LS layout spanning an entire error correction layout, wherein the XOR values ​​are evenly distributed across the plurality of dies.

8. A method performed by a memory subsystem, the method comprising: obtaining a plurality of codewords, wherein each codeword is an element of an error correction code (ECC) for the memory subsystem; assigning a plurality of dies of the memory subsystem to each codeword in the plurality of codewords, wherein a number of codewords in the plurality of codewords is equal to a number of dies in the plurality of dies; dividing each codeword of the plurality of codewords into a plurality of segments, wherein the plurality of segments are distributed across the plurality of dies of the memory subsystem; Calculate an XOR value based on the multiple code words; applying corresponding shifts to the plurality of segments of the plurality of codewords so that the plurality of segments are arranged in a distributed Latin square LS layout across the plurality of dies, wherein code fields along columns or rows of the LS layout are not repeated; as well as The plurality of segments of the plurality of codewords and the calculated XOR values ​​are stored in an error correction layout on the plurality of dies, wherein the LS layout constitutes at least a portion of the error correction layout.

9. The method of claim 8, wherein the number of memory cells in each die of the plurality of dies is equal to the number of segments in each codeword.

10. The method of claim 9, wherein each memory cell along a column of the error correction layout corresponds to one of the plurality of dies, and each memory cell along a row of the error correction layout corresponds to a different one of the plurality of dies. The method of claim 10 , wherein the error correction layout is larger than the LS layout.

12. The method of claim 11, wherein the error correction layout further comprises another die in addition to the plurality of dies in the LS layout.

13. The method according to claim 12, further comprising: dividing the XOR value into a plurality of segments; Each of the segments of XOR values ​​is stored in the other die within the error correction layout that is larger than the LS layout. The method of claim 11 , wherein the LS layout spans an entire error correction layout.

15. The method according to claim 14, further comprising: dividing the XOR value into a plurality of segments; The segments of the XOR values ​​are evenly distributed among the plurality of dies along rows of the LS layout.

16. A memory subsystem, the memory subsystem comprising: Memory components; as well as a processing device operatively coupled to the memory component for: receiving a plurality of codewords of an error correction code; dividing the plurality of codewords of the error correction code into a plurality of segments, wherein the plurality of segments are distributed across a plurality of dies of the memory subsystem; Calculate an XOR value based on the multiple code words; applying respective shifts to the plurality of segments of the plurality of codewords such that the plurality of segments are arranged in a Latin square LS layout across a plurality of dies, wherein a number of codewords in the plurality of codewords is equal to a number of dies in the plurality of dies, and wherein code fields along columns or rows of the LS layout are not repeated; and An error correction layout is formed on the plurality of dies, wherein at least a portion of the error correction layout constitutes the LS layout.

17. The memory subsystem of claim 16, wherein the processing device is further configured to: The XOR value is stored in an additional die outside the LS layout and within the error correction layout.

18. The memory subsystem of claim 16, wherein the processing device is further configured to: The XOR values ​​are stored within the LS layout spanning an entire error correction layout, wherein the XOR values ​​are evenly distributed across the plurality of dies.

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