Command / address channel for configuration memory

Abstract

The present application is directed to configuring a command / address channel of a memory. The configuration of a command / address C / A channel may be dynamically adapted based on energy saving considerations, control information execution latency, or both. Configuring the C / A channel may include determining a number of pins, or a number of cycles, or both, for communicating control information through the C / A channel. In some cases, the number of pins may be determined based on previous control information transmissions, characteristics of a memory device, or predicted control information transmissions, or any combination thereof. The determined number of pins, number of cycles, or both may be indicated to other devices (e.g., devices using the C / A channel) either explicitly or implicitly.

Description

[0001] Cross Reference

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 062500, filed on November 20, 2019, entitled “CONFIGURING COMMAND / ADDRESS CHANNEL FOR MEMORY,” filed by Richter et al., which claims priority to U.S. Patent Application No. 16 / 674,987, filed on November 5, 2019, entitled “CONFIGURING COMMAND / ADDRESS CHANNEL FOR MEMORY,” and U.S. Patent Application No. 16 / 674,987, filed on November 26, 2018, entitled “CONFIGURING COMMAND / ADDRESS CHANNEL FOR MEMORY,” filed by Richter et al. MEMORY)" each of which is assigned to the assignee of the present invention and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to command / address channels for configuring memories. Background Art

[0004] The following relates generally to operating a memory device, and more specifically, to configuring a command / address (C / A) channel.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of memory cells. For example, a binary device has two states, usually represented by a logical "1" or a logical "0". In other systems, more than two states can be stored. To access the stored information, a component of the electronic device can read or sense the stored states in the memory device. To store information, a component of the electronic device can write or program states in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM, PCM, RRAM) can maintain its stored logic state for an extended period of time even in the absence of an external power source. Volatile memory devices (e.g., DRAM) can lose their stored state over time unless they are periodically refreshed by an external power source.

[0007] Control information for operating / accessing the memory device may be passed between the external controller and the memory device. In some cases, the channel between the host device and the memory device may use one or more pins for communication. Summary of the invention

[0008] A method may include: determining a first number of pins of a channel for receiving one or more commands from a host device and a first number of cycles for receiving the one or more commands from the host device; configuring a component coupled to the channel based at least in part on the first number of pins and the first number of cycles, the component comprising a receiver or a decoder or both; and receiving commands through the channel based at least in part on configuring the component.

[0009] An apparatus may include: a first receiver comprising a plurality of pins configured to receive one or more commands over a first channel; a first decoder coupled to the first receiver and configured to decode the one or more commands received over the first channel; and a register coupled to the first receiver and the first decoder and programmable to configure a width of the first channel based at least in part on the one or more commands received over the first channel.

[0010] A method may include: determining a first number of pins of a channel configured to transmit one or more commands to a memory device and a first number of cycles for transmitting the one or more commands to the memory device; configuring a component coupled to the channel based at least in part on the first number of pins of the channel for transmitting the one or more commands and the first number of cycles, the component comprising a driver or an encoder or both; and transmitting commands to the memory device through the channel based at least in part on configuring the component.

[0011] A device may include: a first driver comprising a plurality of pins configured to transmit one or more commands over a first channel; a first encoder coupled to the first driver and configured to encode the one or more commands transmitted over the first channel; and a register coupled to the first driver and the first encoder and programmable to configure a width of the first channel based at least in part on the one or more commands transmitted over the first channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1

[0013] Aspects of an exemplary system that supports configuring a command / address (C / A) channel are described as disclosed herein.

[0013] Figure 2 Aspects of an exemplary memory device that supports configuring a C / A channel are described as disclosed herein.

[0014] Figure 3

[0066] Aspects of an exemplary system that supports configuring a C / A channel are described as disclosed herein.

[0015] Figure 4A and 4B

[0066] Aspects of an exemplary host device that supports configuring a C / A channel are described as disclosed herein.

[0016] Figure 5A and 5B Aspects of an exemplary device controller that supports configuring a C / A channel are described as disclosed herein.

[0017] Figures 6A to 6C An exemplary timing diagram for configuring a C / A channel is illustrated as disclosed herein.

[0018] Figure 7 A process flow for configuring a C / A channel is described as disclosed herein.

[0019] Figure 8 A block diagram representing aspects of a controller that supports configuring a C / A channel as disclosed herein is illustrated.

[0020] Fig. 9 and 10 A flow chart illustrating one or more methods for configuring a C / A channel as disclosed herein. DETAILED DESCRIPTION

[0021] Data and control information may be communicated in a system that supports processing and storing data. In some cases, the data may include information about operating a user application, such as data about a word processing application. For memory access operations, control information may be used to enable storage and reading of data in a memory array.

[0022] In some cases, control information is generated at an external controller (or "host device") to access (e.g., read or write) a memory array, for example, in response to receiving a request from a user application to access or store data in the memory array. In some cases, the generated control information includes commands for accessing the memory array. Some commands for accessing the memory array include an activate ("ACT") command, a read ("RD") command, a write ("WR") command, and a precharge ("PRE") command. The generated control information may also include a memory address, which indicates a memory cell or group of memory cells subject to the corresponding command. The memory address may include a bank address, a row address, and / or a column address. Commands associated with a row address may be referred to as "row commands", and commands associated with a column address may be referred to as "column commands". In some cases, the size of certain command / address (C / A) combinations is larger than the size of other C / A combinations, for example, a row ACT command may be larger than a column read command.

[0023] After the control information is generated, an information signal representing the control information may be generated at the external controller. In order to deliver the signal to the memory array, the external controller may apply the information signal to a pin (or "node") located at the external controller. The pin may provide an interface between the interior of the external controller and a transmission path that connects the external controller to other devices (e.g., memory devices) in the system. That is, the pin may be used to distribute the internally generated signal from one device to another. In some instances, multiple pins may be used to transmit information signals that simultaneously convey multiple information bits. In some cases, as the number of pins used to transmit information signals increases, the number of information bits that can be conveyed within a particular time period also increases. However, the footprint (or physical size) of the device typically increases as the number of pins at the device increases.

[0024] In some examples, to avoid increasing the footprint of the device, the device may be configured with a reduced number of pins for transmitting information signals. Additionally, power consumption at the device may be reduced by using fewer pins. However, as described above, reducing the number of pins may reduce the number of information bits that can be communicated in a particular time period. Thus, larger pieces of information (e.g., a row ACT command) may be communicated in multiple time periods (or "cycles"), for example, because all bits included in the row ACT command cannot be sent in a single cycle via the reduced number of pins. And increasing the duration of information transmission may introduce latency into the memory system and / or reduce the throughput of the memory system, for example, by delaying the execution of other commands.

[0025] In some cases, control information is signaled serially over the C / A channel, e.g., a row ACT command may be sent, followed by a PRE command, and so on. In such cases, the increase in the transmission time of one command may delay the transmission of one or more subsequent commands. In some cases, the serially transmitted commands may be otherwise processed in parallel (e.g., simultaneously) at the memory device; thus, delaying the transmission of subsequent commands may introduce additional latency into the memory system. In some examples, the transmission delay of commands may be reduced by simultaneously transmitting row commands over the row C / A channel and column commands over the column C / A channel. That is, some delay in transmitting commands may be maintained, e.g., between consecutive row and / or column commands.

[0026] Furthermore, when larger commands (such as row ACT commands) are sent at a high rate, the latency introduced into the memory system by increasing the command issuance time may be compounded. The rate at which row ACT commands are issued may be referred to as a "page hit rate" - a high page hit rate is associated with a low rate of ACT commands. Thus, reducing the pins used at a device may save power at the device but introduce latency to the transmission of information from the device, while increasing the pins used at a device may reduce the latency of information transmission but increase the footprint and power consumption of the device.

[0027] To reduce power consumption at the device while mitigating latency in the transmission and execution of sequential control information, the number of pins and / or cycles used to communicate control information may be dynamically configured.

[0028] In some cases, the number of pins and / or cycles used to communicate control information may be configured based on previously observed information. For example, the external memory controller may activate additional pins after identifying that the number of control information waiting to be sent has exceeded a threshold, or by counting unused command slots over a past period of time. After or simultaneously with activating the additional pins, the external memory controller may also reduce the number of cycles used to transmit control information. By reducing the amount of time used to transmit individual control information fragments, the backlog of control information in the queue may be reduced. Similarly, after identifying that the number of control information waiting to be sent is below a threshold, the external memory controller may deactivate certain pins and increase the number of cycles used to transmit control information.

[0029] In some cases, the number of pins and / or cycles used to communicate control information may be adjusted based on current observation information. For example, an external memory controller may deactivate a certain number of pins after recognizing that the temperature of the memory device is below a threshold, e.g., because fewer refresh commands may be sent at lower temperatures.

[0030] In some cases, the number of pins and / or cycles used to communicate control information is adjusted based on the prediction information. For example, the external memory controller may deactivate a certain number of pins after identifying that a page hit rate of the memory device exceeds a threshold. The page hit rate may be associated with the number of times a row of memory cells in a memory bank is accessed before another row of memory cells in the same memory bank is accessed.

[0031] Regardless, the external memory controller may indicate to the memory device how many and / or which pins to activate at the memory controller, and the memory device may similarly activate those pins to receive control information from the memory controller. In some cases, the external memory controller or the controller on the memory die may determine the number of pins and / or cycles to use to transmit a command based on previously observed information, currently observed information, or predicted information, or a combination thereof.

[0032] In some cases, dedicated components are used to support dynamic adjustment of the number of pins and / or cycles for transmitting control information (which may also be referred to as "C / A channel configuration"). For example, a bus width configuration component may be included in an external memory controller. The bus width configuration component may be configured to determine the number of pins and / or cycles used for subsequent transmission of control information to the memory device, for example based on the backward and / or forward information. The bus width configuration component may be further configured to indicate the determined number of pins and / or cycles to an encoder at the external memory controller. For example, the bus width configuration component may be configured to signal a value corresponding to a specific number of pins to the encoder, and the encoder may generate a command based on the received value. The bus width configuration component may also indicate the determined number of pins and / or cycles to a transmitter at the external memory controller, and the transmitter may activate / deactivate a specific driver corresponding to a specific pin at the external memory controller.

[0033] Similarly, a second bus width configuration component may be included in the memory device. The second bus width configuration component may be configured to store the number of pins and / or cycles for subsequent transmission of control information to the memory device, for example based on backward and / or forward information, received configuration information, or receiving an indication of which pins have been disabled after reset. The second bus width configuration component may be further configured to indicate the number of determined pins and / or cycles to a decoder at the memory device. For example, the second bus width configuration component may be configured to signal a value corresponding to a specific number of pins to the decoder, and the decoder may decode the received signal based on the received value. The second bus width configuration component may also indicate the number of determined pins and / or cycles to a receiver at the memory device, and the receiver may activate / deactivate a specific driver coupled to a pin corresponding to a specific pin at the memory device.

[0034] Below is Figures 1 to 3 Features of the present disclosure are described in the context of a memory system in FIG. Figures 4A to 7 Features of the present disclosure are described in the context of circuit diagrams, timing diagrams, and process flows. Figures 8 to 10 These and other features of the present disclosure are further illustrated and described. Figures 8 to 10 Contains equipment diagrams and flow charts related to configuring C / A channels.

[0035] Figure 1

[0066] Aspects of an exemplary system utilizing one or more memory devices that support configuring C / A channels are described as disclosed herein.

[0036] System 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 and the memory device 110. System 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0037] System 100 may include aspects of an electronic device, such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop, a tablet, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. Memory device 110 may be a component of the system configured to store data about one or more other components of system 100. In some examples, system 100 is configured for two-way wireless communication with other systems or devices using a base station or access point. In some examples, system 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0038] At least a portion of the system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to perform a process, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a graphics processing unit (GPU), a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, etc. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as a host device or a host device. In some examples, the system 100 may be a graphics card. The host device may include multiple drivers and multiple channels that link the host device to the memory device.

[0039] In some cases, memory device 110 may be a standalone device or component that is configured to communicate with other components of system 100 and provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes used to modulate signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0040] The memory device 110 may be configured to store data about the components of the system 100. In some cases, the memory device 110 may act as a slave-type device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. In some cases, the access command may be a command that prompts the memory device to store or read data from one or more storage units. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) to support the desired or specified data storage capacity. The memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0041] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may be coupled or in electronic communication with each other using a bus 140.

[0042] The processor 120 may be configured to control at least a portion of the system 100. The processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, the processor 120 may be an example of a central processing unit (CPU), a GPU, a general purpose graphics processing unit (GPGPU), or a system on a chip (SoC), among other examples.

[0043] In some cases, the processor 120 may be incorporated into or be part of the external memory controller 105. In some cases, the processor 120 may be a GPU. The processor 120 may perform aspects of configuring bus transmission lines (e.g., data bus transmission lines) as described herein. For example, the processor 120 may divide the data bus into two groups of transmission lines: a first group to transmit control signals and a second group to transmit data signals. If the amount of data and control signals to be transmitted changes, the processor 120 may reassign or reconfigure the transmission lines from one group to another to improve efficiency and use of the bus.

[0044] BIOS component 125 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0045] Peripheral component 130 may be any input device or output device, or an interface to such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components that one of ordinary skill in the art would understand to be a peripheral device.

[0046] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripherals that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0047] Input device 145 may represent a device or signal external to system 100 that can provide information, signals, or data to system 100 or its components. This may include a user interface or interfacing with or between other devices. In some cases, input device 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0048] Output device 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output device 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output device 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0049] The components of system 100 may be composed of general or special purpose circuitry designed to implement its functions. This may include output driver circuitry and various other circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements, configured to implement the functions described herein.

[0050] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Figure 2 , further describing the characteristics of memory array 170 and / or memory cells.

[0051] The memory array 170 may be an example of a two-dimensional (2D) memory cell array, or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a platform, a level, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). This may increase the number of memory cells that may be positioned on a substrate, as compared to a single 2D memory device, which in turn may reduce production costs, improve the performance of the memory array, or both. In some 3D memory devices, different platforms may share at least one common access line, such that some platforms may share at least one of a word line, a digit line, and / or a plate line.

[0052] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. As such, the device memory controller 155 may include hardware, firmware, and software that enable the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information related to the memory device 110. The device memory controller 155 may perform or facilitate aspects of configuring the transmission lines of a data bus as described herein. For example, the device memory controller 155 may receive control and data signals on multiple different sets of transmission lines that may be part of a data bus. When two sets of transmission lines are reconfigured, the device memory controller 155 may receive control and / or data signals through the reconfigured transmission lines.

[0053] The local memory controller 155 may be configured to communicate with the external memory controller 105, one or more memory dies 160, or the processor 120. In some cases, the memory device 110 may receive data and / or control signals (e.g., commands and addresses) from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 is to store certain data on behalf of a component of the system 100 (e.g., the processor 120) or a read command indicating that the memory device 110 is to provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include: a receiver for demodulating signals received from the external memory controller 105, an encoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, etc.

[0054] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. In addition, the local memory controller 165 may be configured to communicate with the device memory controller 155 (e.g., receive and transmit data and / or commands). The local memory controller 165 may support the device memory controller 155 to control the operation of the memory device 110 described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. As such, the local memory controller 165 may be configured to communicate with the device memory controller 155, other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0055] The external memory controller 105 may be configured to enable communication of information, data, commands, and / or addresses between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110 so that the components of the system 100 may not need to know the details of the operation of the memory device. The components of the system 100 may make requests (e.g., read commands or write commands) to the external memory controller 105, which the external memory controller 105 satisfies. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal. The data clock signal may provide timing for a multi-level signal sent over the channel 115. For example, the data clock may provide timing information for determining the duration of a symbol period of the multi-level signal.

[0056] In some cases, the processor 120 may implement the external memory controller 105 or other components of the system 100, or the functions thereof described herein. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is described as being external to the memory device 110, in some cases, the external memory controller 105 or the functions thereof described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120, while other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120).

[0057] Components of system 100 may exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to function as part of a channel. In some cases, a pin or pad of a terminal may be part of a signal path of channel 115.

[0058] Additional signal paths may be coupled to the terminals of the channels for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths internal to memory device 110 or a component thereof, such as signal paths internal to memory die 160) that route signals from terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170). The signal paths may be implemented using one or more types of transmit lines, including differential transmit lines and single-ended transmit lines.

[0059] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying a particular type of information. In some cases, channel 115 may be an aggregate channel and, therefore, may include multiple individual channels. For example, data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc.

[0060] In some cases, the channel 115 may include one or more C / A channels 186. The C / A channels 186 may be configured to communicate commands between the external memory controller 105 and the memory device 110 including control information associated with the commands (e.g., address information). For example, the C / A channel 186 may include a read command with the address of the desired data. In some cases, the C / A channel 186 may register on a rising clock signal edge or a falling clock signal edge using a technique that may be referred to as single data rate (SDR) signaling, or register to both a rising clock signal edge and a falling clock signal edge using a technique that may be referred to as double data rate (DDR) signaling. In some cases, the C / A channel 186 may include eight or nine signal paths.

[0061] In some cases, the channel 115 may include a row C / A channel and a column C / A channel. The row C / A channel may be configured to communicate row commands, such as activate and precharge commands, between the external memory controller 105 and the memory device 110. The column C / A channel may be configured to communicate column commands, such as read and write commands, between the external memory controller 105 and the memory device 110. In some cases, the row C / A channel may be larger than the column C / A channel to accommodate larger row commands that convey more information than the column commands. In such cases, the row C / A channel may be configured to include more pins and / or signal paths than the column C / A channel.

[0062] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channel 188 may be configured to pass one or more clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to adjust (e.g., oscillate) between a high state and a low state and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal), and the signal path of the CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. The CK channel 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., a CK_t signal and a CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110, or for other system-wide operations of the memory device 110. The clock signal CK may therefore be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, and the data clock may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0063] In some cases, the channel 115 may include one or more data (DQ) channels 190. For example, the channel 115 may include data channels 190-1 to 190-n. Each data channel may be associated with or include one or more transmission lines. The data channels 190 may be configured to communicate data and / or control information between the external memory controller 105 and the memory device 110. For example, the data channels 190 may communicate information to be written to the memory device 110 (e.g., bidirectional) or information to be read from the memory device 110. The data channels 190 may communicate signals that may be modulated using a variety of different modulation schemes, such as non-return-to-zero (NRZ) signaling, or pulse amplitude modulation (PAM) signaling.

[0064] In some cases, the channel 115 may include one or more other channels 192 that may be dedicated for other purposes. These other channels 192 may include any number of signal paths. In some cases, the other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write," the write clock signal WCK (e.g., the WCK_t signal and the WCK_c signal) may provide a timing reference for access operations commonly used for the memory device 110 (e.g., a timing reference for both read operations and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK.

[0065] The WCK channel may be configured to pass a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., a WCK_t signal and a WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (e.g., an oscillator, a crystal, a logic gate, a transistor, etc.).

[0066] In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels may be configured to convey error detection signals, such as checksums, to improve system reliability. EDC channels may include any number of signal paths.

[0067] The channel 115 may couple the external memory controller 105 with the memory device 110 using a variety of different architectures. Examples of the various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0068] The signals communicated over the channel 115 (and its associated transmission lines) may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to 2. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical "1" or a logical "0"). Examples of binary symbol modulation schemes include, but are not limited to, NRZ, unipolar encoding, bipolar encoding, Manchester encoding, PAM with two symbols (e.g., PAM2), and / or others.

[0069] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

[0070] Data and control information may be passed within system 100. For example, data and control information may be passed between an external controller (e.g., external memory controller 105) and a memory device (e.g., memory device 110). Data may include information created by a user application and may be communicated in data signaling.

[0071] Control information may include information that supports data flow within system 100 and may be communicated in control signaling. In some cases, control information includes commands that instruct the memory device to perform certain operations at the memory device. Memory operations may refer to operations that manipulate one or more memory cells, access lines (e.g., word lines, digit lines, or plate lines), or memory banks. Access operations may refer to a subset of memory operations that involve or result in data being written to or read from memory cells in the memory device. Possible commands include precharge, row activate, read, and write commands.

[0072] The control information may also include a storage address (e.g., a row or column address) that identifies a particular memory cell or group of memory cells. As discussed herein, the address of one or more memory cells may be represented in a signal by a number of address bits that indicate a block address, a column address, and / or a row address. For example, when the memory device 310 includes sixteen (16) memory banks, and each of those memory banks includes one hundred twenty-eight (128) columns and 16,384 rows (e.g., as in a 16Gb GDDR6 architecture or an 8Gb GDDR5 architecture), the bank address may be represented by four address bits, the column address may be represented by seven address bits, and the row address may be represented by fourteen address bits. In some cases, a row of memory cells may be referred to as a memory page. In another example (e.g., in a 16Gb DDR4x16 architecture), the memory device 310 may include eight (8) banks, and each of those banks includes 1024 columns and 131072 rows, in which case the bank address may be represented by three address bits, the column address may be represented by ten address bits, and the row address may be represented by 17 address bits. However, these are illustrative examples, and other numbers of address bits may be used and are specifically contemplated.

[0073] A control signal including both a command and a memory address may indicate that the command applies to a memory cell or a group of memory cells identified by the address. In some cases, a control signal including both a command and a memory address is referred to as a C / A signal. In one example, a C / A signal including an activate (ACT) command and a row address may indicate to a memory device that a row of memory cells is to be activated in preparation for or in conjunction with another memory operation (e.g., a read or write operation). Activating a memory cell may cause a word line corresponding to the memory cell to be excited. When an ACT command is transmitted to a memory device, the ACT command may include or be followed by a number of address bits indicating a memory bank targeted for an upcoming read or write operation and a row to be activated within the memory bank. Thus, the transmitted ACT command may include or be followed by a memory bank and row address associated with an upcoming memory operation. When the ACT command includes a row address, the ACT command may be referred to as a row command. An external controller may transmit an ACT command whenever a new row in a memory bank is targeted for a read or write operation. In some cases, when the rate of ACT commands decreases as the page hit rate increases, for example, when there are consecutive requests to access the same row.

[0074] In an example of an access operation, a read command may indicate to a memory device that one or more memory cells are to undergo a read operation so that their stored information (e.g., as represented by a logic state) may be transmitted to an external controller. Reading a memory cell may refer to the process of applying a voltage across a memory cell so that the memory cell discharges onto a digital line for sensing. When a read command is transmitted to a memory device, the read command may include or be followed by a bank address and a column address of a memory cell targeted for the read operation. When a read command includes a column address, the read command may be referred to as a column command. In some cases, the read command may also indicate the number of memory cells to be read starting at an initial address point. The number of memory cells to be read in response to a read command may be referred to as a read burst length.

[0075] In another example of an access operation, a write command may indicate to the memory device that one or more memory cells are to undergo a write operation so that information from an external controller may be stored in one of the memory banks of the memory device. Writing to a memory cell may refer to the process of applying a voltage across a memory cell so that the memory cell charges to indicate a state of logic 1 or 0. When a write command is transmitted to the memory device, the write command may include or be followed by a memory bank address and a column address of a memory cell targeted for the write operation. When a write command includes a column address, the write command may be referred to as a column command. In some cases, the write command may also indicate the number of memory cells to be written starting at an initial address point. The number of memory cells to be written in response to a write command may be referred to as a write burst length.

[0076] To communicate data and / or control information within system 100, data and control information may be signaled via one or more channels (e.g., channel 115) that electrically connect devices within the memory system. In some cases, one of the one or more channels may include multiple signal paths (or transmit paths). A device may access one or more channels via pins located at the device, where the pins may serve as a conductive interface between the device and the channel. For example, to communicate information between two devices, such as external memory controller 105 and memory device 110, a signal path may be coupled to a first set of pins located at external memory controller 105 and a second set of pins located at memory device 110. In some cases, a grouping of signal paths and pins may be referred to as a "bus."

[0077] In some cases, to signal data and / or control information between two devices, the first device may apply an internally generated signal to a first set of pins located at the first device. In some cases, the internally generated signal is composed of one or more voltages (e.g., multiple parallel and / or series voltages), and the first set of pins may be coupled to a set of signal paths of a channel connecting the two devices. In some examples, the external memory controller 105 may signal data and / or control information to the memory device 110 by applying the one or more voltages of the signal to a first set of pins at the external memory controller 105 coupled to the channel 115 connecting the external memory controller 105 and the memory device 110. In some cases, all of the one or more voltages are applied simultaneously in a single time period. In other cases, a subset of the one or more voltages are applied sequentially over multiple time periods. The memory device 110 may receive the one or more voltages of the signal at a second set of pins located at the memory device 110, and may decode the signal to determine the signaled data and / or control information. Similarly, the memory device 110 may signal data to the external memory controller 105 by applying one or more voltages to the second set of pins.

[0078] In some cases, data and control information may be signaled via separate data and control channels that electronically connect devices within a memory system via pins located at the devices. For example, data may be signaled via a channel (e.g., DQ channel 190) dedicated to data ("data channel"), and control information may be signaled via a channel (e.g., C / A channel 186) dedicated to control information ("control channel"). When data and control information are signaled via separate channels, a first set of signal paths for the data channel may be coupled to a first set of pins located at a first device and a first set of pins located at a second device. And a second set of signal paths for the control channel may be coupled to a second set of pins located at the first device and a second set of pins located at the second device. In some cases, when separate channels are used to signal data and control information, control information and data may be signaled according to a timing or protocol that indicates which control information corresponds to which data.

[0079] In some cases, the number of pins and the number of signal paths used to signal control information may be based on the number of information bits used to convey the maximum type of control information (e.g., the maximum C / A combination) and / or the number of cycles used to transmit different types of control information. In some cases, the number of pins and signal paths may be the same. In some examples, the number of pins and signal paths (or the size of the bus) used to signal control information may be reduced by reducing the size of the maximum type of control information (e.g., by encoding the control information). In some examples, the number of pins and signal paths (or the size of the bus) used to signal control information may be reduced by increasing the number of cycles used to transmit the maximum type of control information, or vice versa.

[0080] In some cases, commands are signaled over the control channel in a serial manner. That is, a first command may be sent, then a second command may be sent, then a third command may be sent, and so on. However, in some cases, the memory device may be able to perform operations triggered by different commands in parallel, for example, the memory device may perform a read operation on a memory cell at a first column address in a first memory bank while performing a row activation operation on a memory cell located in a different memory bank. By processing two commands in parallel, the throughput of the memory device may be increased.

[0081] In some cases, multiple control channels may be used to communicate parallel control information streams. For example, a first channel may be used to communicate row commands ("row control channel"), and a second channel may be used to communicate column commands ("column control channel"). In such cases, the number of pins used to transmit row control information may be based on the size of the largest type of row control information (e.g., the largest row C / A combination) and / or the number of cycles used to transmit different types of row control information. And the number of pins used to transmit column control information may be based on the size of the largest type of column control information (e.g., the largest column C / A combination) and / or the number of cycles used to transmit different types of row control information.

[0082] As the number of pins used to signal control information increases, the size (or footprint) of the memory die and / or the power consumption of the memory die may also increase. In some cases, to reduce the reflectivity and power consumption of the memory die, the number of pins used to signal control information may be reduced, and the number of cycles used for high-speed control information may be increased. However, increasing the number of cycles used to transmit control information may result in delays in command execution. That is, by increasing the number of cycles used to transmit control information, the transmission of discrete control information may take longer, thereby delaying the manner of subsequent control information.

[0083] To reduce power consumption at the memory die without introducing latency into the execution of consecutive commands, the number of pins and / or cycles used to communicate control information can be dynamically adjusted.

[0084] In some cases, the number of pins and / or cycles used to communicate control information is adjusted based on previously observed information. For example, an external memory controller (e.g., external memory controller 105) may activate additional pins after identifying that the number of control information waiting to be sent (e.g., in a queue) has exceeded a threshold. After or simultaneously with activating the additional pins, the external memory controller may also reduce the number of cycles used to transmit control information. By reducing the amount of time used to transmit individual control information fragments, the backlog of control information in the queue may be reduced. Similarly, after identifying that the number of control information waiting to be sent is below a threshold, the external memory controller may deactivate certain pins.

[0085] In some cases, the number of pins and / or cycles used to communicate control information is adjusted based on the prediction information. For example, an external memory controller (e.g., external memory controller 105) may deactivate a certain number of pins after identifying that a page hit rate of a memory device exceeds a threshold. The page hit rate may be associated with the number of times a row of memory cells in a memory bank is accessed before another row of memory cells in the memory bank is accessed. A higher page hit rate may correspond to a command mode with a reduced rate of activate commands (which are typically longer commands).

[0086] In some cases, a dedicated component is used to support dynamic adaptation of the number of pins and / or cycles used to transmit control information. For example, a bus width configuration component may be implemented using at least a portion of one or more memory controllers (e.g., external memory controller 105, device memory controller 155, local memory controller 165 or 260, or a combination thereof) and / or registers. The bus width configuration component may be configured to determine the number of pins and / or cycles used for subsequent transmission of control information to the memory device, for example based on backward-looking and / or forward-looking information. The bus width configuration component may be further configured to indicate the number of determined pins and / or cycles to an encoder at the external memory controller. For example, the bus width configuration component may be configured to signal a value corresponding to a specific number of pins to the encoder, and the encoder may generate a command based on the received value. The bus width configuration component may also indicate the number of determined pins and / or cycles to a transmitter at the external memory controller, and the transmitter may activate / deactivate a specific driver corresponding to a specific pin at the external memory controller.

[0087] Similarly, a second bus width configuration component may be included in the memory device. The second bus width configuration component may be configured to determine the number of pins and / or cycles for subsequent transmission of control information to the memory device, for example based on backward and / or forward information, received configuration information, or determining which pins have been disabled. The second bus width configuration component may be further configured to indicate the determined number of pins and / or cycles to a decoder at the memory device. For example, the second bus width configuration component may be configured to signal a value corresponding to a specific number of pins to the decoder, and the decoder may decode the received signal based on the received value. The second bus width configuration component may also indicate the determined number of pins and / or cycles to a receiver at the memory device, and the receiver may activate / deactivate a specific circuit coupled to a pin corresponding to a specific pin at the memory device.

[0088] Figure 2 Various aspects of an exemplary memory device that supports configuring a C / A channel are described as disclosed herein. The memory device 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory device 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory device 200 may include one or more memory cells 205 that may be programmed to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, a memory cell 205 may be configured to store one bit of digital logic (e.g., a logic 0 and a logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., a logic 00, a logic 01, a logic 10, or a logic 11) at a time.

[0089] Memory cell 205 may store a charge representing a programmable state in a capacitor. In a dynamic random access memory (DRAM) architecture, a memory cell such as memory cell 205 may include a capacitor that includes a dielectric material to store a charge representing a programmable state. In other memory architectures, other storage devices and components are also possible. For example, nonlinear dielectric materials may be employed.

[0090] By activating or selecting access lines such as word lines 210 and / or digit lines 215, operations such as reading and writing can be performed on memory cells 205. In some cases, digit lines 215 may also be referred to as bit lines. References to access lines, word lines, and digit lines, or the like, may be interchanged without loss of understanding or operation. Activating or selecting word lines 210 or digit lines 215 may include applying a voltage to the respective lines.

[0091] The memory device 200 may include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid-like pattern. Memory cells 205 may be located at the intersections of the word lines 210 and digit lines 215. By biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersections. The memory device 200 may include a number of memory banks, at least some of which, if not every memory bank, may have unique addresses, and may include multiple rows and columns.

[0092] Access to the memory cells 205 in the memory bank may be controlled by the row decoder 220 and the column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word line 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and may activate the digit line 215 based on the received column address. For example, the memory device 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, by activating the word lines 210 and digit lines 215 (e.g., WL_1 and DL_3), the memory cells 205 at their intersections may be accessed. The intersection of the word lines 210 and digit lines 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205.

[0093] Memory cell 205 may include a logic storage component, such as capacitor 230 and switch component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switch component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 is ground, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switch component 235 may be an example of a transistor or any other type of switching device that selectively establishes or disconnects (e.g., stops) electronic communication between two components.

[0094] Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switch component 235. Capacitor 230 may be in electronic communication with digit line 215 using switch component 235. For example, when switch component 235 is deactivated, capacitor 230 may be isolated from digit line 215, and when switch component 235 is activated, capacitor 230 may be coupled to digit line 215. In some cases, switch component 235 may be or include a transistor, and its operation may be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source may be greater than or less than the threshold voltage of the transistor. In some cases, switch component 235 may be or include a p-type transistor or an n-type transistor. Word line 210 may be in electronic communication with the gate of switch component 235, and switch component 235 may be activated / deactivated based on applying a voltage to word line 210.

[0095] The word line 210 may be a conductive line in electronic communication with a memory cell 205 that may be used to perform access operations on the memory cell 205. In some architectures, the word line 210 may be in electronic communication with a gate of a switching element 235 of the memory cell 205 and may be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with a node of a capacitor of the memory cell 205 and the memory cell 205 may not include a switching element.

[0096] The digit line 215 can be a conductive line that connects the memory cell 205 to the sensing component 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switch component 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 from the digit line 215. In some architectures, the memory cell 205 can be in electronic communication with the digit line 215.

[0097] The sensing component 245 can be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be small. As such, the sensing component 245 can include one or more sense amplifiers to amplify the signal output by the memory cell 205. The sense amplifier can detect small changes in the charge of the digit line 215 during a read operation and can generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge.

[0098] During a read operation, the capacitor 230 of the memory cell 205 may output a signal (e.g., a discharged charge) to its corresponding digit line 215. The signal may cause a voltage change of the digit line 215. The sensing component 245 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the stored state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a voltage higher than the reference signal 250, the sensing component 245 may determine that the stored state of the memory cell 205 is a logic 1, and if the digit line 215 has a voltage lower than the reference signal 250, the sensing component 245 may determine that the stored state of the memory cell 205 is a logic 0.

[0099] The sensing component 245 may include various transistors or amplifiers to detect and amplify the difference in the signal. In some cases, the sensing component 245 may be part of another component (e.g., column decoder 225, row decoder 220). In some cases, the sensing component 245 may be in electronic communication with the row decoder 220 or the column decoder 225.

[0100] As one example, the detected logic state of the memory cell 205 determined by the sense component 245 can be output by the column decoder 225 as an output 255. The output 255 can pass the detected logic state to one or more intermediate components (e.g., a local memory controller) for transmission through one or more channels (e.g., transmission through one or more transmission lines). Thus, the detected logic state of the memory cell 205 can be communicated to devices or components external to the memory device 200. For example, the detected logic state can be transmitted via one or more transmission lines (e.g., to the external memory controller 105).

[0101] The local memory controller 260 may control the operation of the memory cell 205 through various components (eg, the row decoder 220, the column decoder 225, and the sensing component 245). The local memory controller 260 may be a reference Figure 1 1. In some cases, one or more of the row decoder 220, column decoder 225, and sense component 245 may be co-located with the local memory controller 260. The local memory controller 260 may be configured to receive data from the external memory controller 105 (or reference 106). Figure 1The device memory controller 155 described above receives commands and / or data, translates the commands and / or data into information that can be used by the memory device 200, performs one or more operations on the memory device 200, and passes data from the memory device 200 to the external memory controller 105 (or the device memory controller 155) in response to performing the one or more operations. In some cases, the local memory controller 260 may be configured to receive data and control information through different channels. In some cases, the local memory controller 260 may be configured to receive different types of commands through different channels. For example, the local memory controller 260 may be configured to receive row commands through a first command channel and column commands through a second command channel.

[0102] As discussed herein, the memory device 200 may receive commands at different times through a variable number of pins. In some cases, the local memory controller 260 may determine the number of pins used to receive one or more commands. For example, the local memory controller 260 may determine the number of pins used to signal the one or more commands based on determining that a second number of pins used for command transmission is set to a particular voltage. In another example, the local memory controller 260 may determine the number of pins used to signal the one or more commands based on receiving an indication of which or how many pins are to be used. Additionally or alternatively, the local memory controller 260 may determine the number of cycles used to receive the one or more commands. In some cases, the local memory controller 260 may determine the number of cycles used to receive the one or more commands based on determining the number of pins used to transmit the one or more commands. For example, the local memory controller 260 may be configured to determine that a particular command (e.g., a row activation command) spans a certain number of cycles (e.g., 2) based on first determining that the particular command is transmitted through six (6) pins. After determining the number of pins and / or the number of cycles, the local memory controller 260 may configure the receiver and / or decoder to receive and process the command accordingly.

[0103] The memory device 200 may send data to and receive data from one or more external devices via a bus (e.g., a data bus) including a plurality of transmission lines. As described herein, the memory device 200 may use different combinations of transmission lines to transmit control signals and data signals. The memory device 200 may modify the combination of transmission lines (e.g., based on the amount of content to be transmitted) so that some transmission lines previously used or previously configured to transmit data may be used or configured to transmit control signals, and vice versa. The number of transmission lines selected to transmit a type of content (e.g., control content or data content) may be related to (e.g., proportional to) the amount of content.

[0104] The local memory controller 260 may generate row and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 may also generate and control various voltages or currents used during operation of the memory device 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed in operating the memory device 200.

[0105] In some cases, the local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory device 200. The write operation may be for data received from an external device. During the write operation, the memory cells 205 of the memory device 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cell 205 on which the write operation is performed. The local memory controller 260 may identify the target word line 210 and the target digit line 215 (e.g., the address of the target memory cell 205) in electronic communication with the target memory cell 205. The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. Local memory controller 260 may apply a first signal (eg, voltage) to digit line 215 during a write operation to store a first state (eg, charge) in capacitor 230 of memory cell 205, and the particular state (eg, charge) may indicate a desired logic state.

[0106] In some cases, the local memory controller 260 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory device 200. The read operation may be for data requested by an external device or for data of an external device. During the read operation, the logic state stored in the memory cell 205 of the memory device 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cell 205 on which the read operation is performed. The local memory controller 260 may identify the target word line 210 and the target digit line 215 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205.

[0107] The target memory cell 205 may transmit a signal to the sensing component 245 in response to biasing the access line. The sensing component 245 may amplify the signal. The local memory controller 260 may activate the sensing component 245 (e.g., latch the sensing component) and thus compare the signal received from the memory cell 205 with the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. The local memory controller 260 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155) as part of a read operation.

[0108] In some memory architectures, accessing the memory cell 205 may degrade or destroy the logic state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. The local memory controller 260 may perform a rewrite operation or a refresh operation to return the memory cell to its original logic state. The local memory controller 260 may rewrite the logic state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered as part of the read operation. In addition, activating a single access line, such as a word line 210, may disturb the state stored in some memory cells that are in electronic communication with the access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed.

[0109] Figure 3

[0013] According to various aspects of the present disclosure, aspects of an exemplary system that supports configuring a C / A channel are described.

[0110] System 300 can be used as a reference Figure 1 3. The system 300 may include a controller 305, a memory device 310, and a transmission line 315. In some cases, the controller 305 may be an example of an external memory controller 105 (also referred to as a host device, a host device controller, or a host device) or a processor 120 (e.g., a GPU, a GPGPU, a CPU), as described in reference to FIG. Figure 1 In some cases, memory device 310 may be an example of memory device 110, memory die 160, device memory controller 155, local memory controller 165, or storage device 200, as described in reference to Figure 1 and 2 described.

[0111] The controller 305 can be configured to determine the number of pins and / or the number of cycles used to transmit one or more commands to a memory device, such as the memory device 310. The controller 305 can include a controller transceiver 320.

[0112] The controller transceiver 320 may be configured to transmit command, address, and data signaling to other devices, such as the memory device 310. In some cases, the controller transceiver 320 may transmit C / A signaling based on the number of pins and cycles determined by the controller 305 for transmitting the command. In some cases, the controller transceiver 320 uses multi-level signaling techniques such as PAM4 signaling and / or other signaling techniques to increase the communication rate such as DDR signaling—when DDR signaling is used, the first information may be signaled at the rising edge of the clock pulse and the second information may be signaled at the falling edge of the clock pulse. The controller transceiver 320 may include and / or be in electronic communication with the controller pin 335.

[0113] Controller pins 335 may be configured to provide an interface between the transmit and receive components of controller 305 and transmit line 315. In some cases, a pin located at controller 305 (e.g., controller pin 1a ("CP_1a")) may correspond to a pin located at memory device 310 (e.g., memory device pin 1a ("MDP_1a")). In some cases, controller pins 335 may be referred to as nodes, pads, terminals, transmit line interfaces, interface components, or connection points. In some cases, controller pins 335 may be made of a conductive material capable of transferring current or voltage to and from transmit line 315 and controller 305.

[0114] The controller transceiver 320 may transmit command, address, and data signaling using the controller pins 335. That is, the controller transceiver 320 may apply various aspects of a signal to the controller pins 335 to transmit the signal to the memory device 310. In some cases, the controller transceiver 320 transmits command, address, and data signaling over different buses. For example, the controller transceiver 320 may transmit C / A signaling through the controller pins 335 included in the C / A bus 325, and may transmit data signaling through the controller pins 335 included in the data bus 330. In some cases, the C / A signaling transmitted over the C / A bus 325 includes information that enables the memory device 310 to process the corresponding data signaling received over the data bus 330. For example, the C / A signaling transmitted over the C / A bus 325 may indicate that the information included in the corresponding data signaling transmitted over the data bus 330 is to be stored in (e.g., in the case of a signaled write command) or read from a particular memory cell (e.g., in the case of a signaled read command). In some cases, the controller transceiver 320 may include an encoder configured to generate a set of information bits for a particular command. In some cases, the controller transceiver 320 may be configured to receive command, address, and / or data signaling from other devices (eg, memory device 310).

[0115] Memory device 310 may store information in memory cells of one or more memory banks (eg, in memory banks 0 to x). Figure 2 As described, memory cells may be configured in a memory bank in multiple groups of rows and columns. Dividing the memory array into one or more memory banks allows a degree of parallelism when accessing the memory array, which can increase the overall bandwidth of the memory device. Therefore, in order to target a particular memory cell as a storage operation, the memory device 310 may need to identify or target the memory bank, column, and row of the memory cell in question. The memory bank, column, and row associated with the memory cell may be indicated or represented by an address. For example, a memory bank including a memory cell may be associated with a memory bank address, a column including a memory cell may be associated with a column address, and a row including a memory cell may be indicated by a row address. The memory device 310 may be configured to determine the number of pins and the number of cycles used to receive one or more commands from a host device such as a controller 305. The memory device 310 may include a memory device transceiver 340.

[0116] The memory device transceiver 340 may be configured to receive command, address, and data signaling from another device, such as the controller 305. In some cases, the memory device transceiver 340 may receive C / A signaling based on the number of pins and cycles determined by the memory device 310. In some cases, the memory device transceiver 340 may be configured to receive signaling according to a particular modulation scheme, such as NRZ, PAM2, or PAM4, and / or using a single data rate (SDR) or DDR technology. The memory device transceiver 340 may include and / or be in electronic communication with device pins 345. In some cases, the memory device transceiver 340 may be configured to transmit command, address, and / or data signaling to other devices, such as the controller 305. In some cases, the C / A bus 325 may be configured to support the transmission of commands and address information from the controller 305 to the memory device 310, but not from the memory device 310 to the controller 305 (e.g., the C / A bus 325 may be unidirectional). In other cases, the C / A bus 325 may support bidirectional communication between the controller 305 and the memory device 310.

[0117] Device pins 345 may be configured to provide an interface between the transmit and receive components of memory device 310 and transmit line 315. In some cases, a pin located at memory device 310 (e.g., device pin 1a ("MDP_1a")) may correspond to a pin located at controller 305 (e.g., controller pin 1a ("CP_1a")). In some cases, device pins 345 may be referred to as nodes, pads, terminals, transmit line interfaces, interface components, or connection points. In some cases, device pins 345 may be made of a conductive material capable of transferring current or voltage to and from transmit line 315 and memory device 310.

[0118] The memory device transceiver 340 may receive command, address, and data signaling using the device pins 345. That is, the memory device transceiver 340 may receive various aspects of a signal through the device pins 345, and may combine various aspects of the signal to reconstruct a transmitted signal. For example, the memory device transceiver 340 may receive C / A signaling through the device pins 345 included in the C / A bus 325, and receive data signaling through the device pins 345 included in the data bus 330. In some cases, the C / A signaling received via the C / A bus 325 provides information for receiving corresponding data signaling through the data bus 330. For example, the C / A signaling received through the C / A bus 325 may instruct the memory device 310 to store (e.g., if a write command is received) information included in the corresponding data signaling received through the data bus 330 at a particular memory cell, e.g., based on an address received in the C / A signaling. In another example, C / A signaling received via C / A bus 325 may instruct memory device 310 to read data from (e.g., if a read command is signaled) a specific memory cell, e.g., based on the command and address received in the C / A signaling. In some cases, memory device transceiver 340 may include a decoder configured to recognize a specific command corresponding to a command, address, or data signal received via device pin 345.

[0119] Transmission line 315 may be configured to electronically connect controller 305 and memory device 310. As shown in system 300, transmission line 315 may originate from one component (e.g., controller 305) and terminate at another component (e.g., memory device 310), which may or may not be within the same device. Transmission line 315 may be a wire or trace. In some cases, transmission line 315 provides a one-to-one mapping between controller pins 335 and device pins 345. In some cases, transmission line 315 includes a reference pin, such as a reference pin. Figure 1For example, transmission lines 1a through M may be included in a control channel (eg, C / A channel 185), and transmission lines 1b through N may be included in a data channel (eg, DQ channel 190-1).

[0120] The C / A bus 325 can be configured to communicate C / A signaling between the controller 305 and the memory device 310. In some cases, the C / A bus 325 includes a subset of controller pins 335 (e.g., CP_1a to CP_M), a subset of device pins 345 (e.g., MDP_1a to MDP_M), and a subset of transmission lines 315 (e.g., TL_1a to TL_M). In other cases, the C / A bus 325 is defined to include the set of transmission lines 315 and is equivalent to a channel, such as reference Figure 1 115 described. In some cases, the C / A bus 325 is further divided into a row C / A bus and a column C / A bus. The row C / A bus can be configured to communicate row commands and row addresses to the memory device 310, and the column C / A bus can be configured to communicate column commands and column addresses to the memory device 310. In some examples, more bits of information are used to convey row commands than column commands, such as when the memory array is configured so that there are more rows than columns, and the row C / A bus can include more pins than the column C / A bus.

[0121] The data bus 330 may be configured to communicate data signaling between the controller 305 and the memory device 310. In some cases, the data bus 330 includes a subset of controller pins 335 (e.g., CP_1b to CP_N), a subset of device pins 345 (e.g., MDP_1b to MDP_N), and a subset of transmission lines 315 (e.g., TL_1b to TL_N). In some cases, the data signal communicated through the data bus 330 corresponds to the C / A signal transmitted through the C / A bus 325, for example, instructions for processing the data information conveyed in the data signal may be included in the previous C / A signal.

[0122] In some cases, the configuration of the C / A bus 325 may be dynamically configured—e.g., based on the past, current, or predicted operation of the system 300, or a combination thereof. For example, the controller 305 may disable a particular controller pin 335 based on determining that the rate at which ACT commands are transmitted is below a threshold. In another example, the controller 305 may enable additional controller pins 335 based on identifying that the number of commands in the command queue has exceeded a threshold. In another example, the controller 305 may enable additional controller pins 335 based on predicting that the rate at which ACT commands are transmitted will increase. By dynamically adapting the configuration of the C / A bus 325, the controller 305 may save power without sacrificing timely execution of commands. In some examples, the controller 305 indicates the configuration of the C / A bus 325 to the memory device 310. For example, the controller 305 may transmit a bus width configuration message to the memory device 310, the bus width configuration message indicating which transmission lines 315 of the C / A bus 325 are being used to convey information.

[0123] The memory device 310 may receive control information through the dynamically adapted C / A bus 325. In some cases, the memory device 310 determines the configuration of the C / A bus 325 based on signals transmitted through the C / A bus 325 based on implicit or explicit messages. For example, based on identifying that the voltage on certain transmit lines 315 is set to a high voltage or a low voltage. In other cases, as discussed herein, the memory device may determine the configuration of the C / A bus 325 based on messages received from the controller 305. For example, the memory device 310 may receive a configuration message and disable the device pins 345 based on the indicated configuration of the C / A bus 325, for example, the memory device 310 may determine based on the bus width configuration message that the transmit line 3a to M is disabled, and may disable the device pin 3a to M. By disabling the device pins 345, the memory device 310 may save power.

[0124] In some cases, the number of cycles used to transmit C / A information is also configured based on the configuration of the C / A bus 325. That is, as the number of pins used to transmit C / A information is adapted, the number of cycles used to transmit C / A information through the pins may increase or decrease. For example, if the controller 305 reduces the number of pins used to transmit C / A information, the number of cycles used to transmit C / A information may increase, for example, so that a complete command can be transmitted, as described in more detail herein and with respect to Figures 6A to 6C When the configuration of the C / A bus 325 is adapted, the number of cycles adapted to receive C / A information at the memory device 310 may similarly be adapted at the memory device 310.

[0125] In some cases, instead of disabling the pins dedicated to the C / A bus 325, unused controller and device pins dedicated to the C / A bus 325 may be rescheduled for communicating data information and included in the data bus 330. By reassigning the pins dedicated to the C / A bus 325 for use with the data bus 330, the data transfer rate between the memory device 310 and the controller 305 may be increased.

[0126] Figure 4A Various aspects of an exemplary host device that supports configuring a C / A channel are described according to various aspects of the present disclosure.

[0127] The host device 400-a may be configured to dynamically configure various aspects of the C / A channel to communicate control and address information with other devices. The host device 400-a may also be configured to dynamically configure various aspects of the data channel used to communicate data with other devices. In some cases, the host device 400-a may be an example of an external memory controller 105 or controller 305, as described with reference to FIG. Figure 1 and 3 The host device 400-a may include a command encoder 405-a, a bus width configuration component 410-a, a driver component 415-a, a first pin 420-a, and an Mth pin 425-a. The host device 400-a may communicate with a memory device (e.g., as shown in FIG. 1 ) via a C / A channel 430-a. Figure 5A The device controller 500-a) is coupled to and communicates with the C / A channel 430-a, which may be an example of the channel 115, as shown in reference Figure 1 described.

[0128] In some cases, the transmitter (e.g., as shown in reference Figure 3 The controller transceiver 320 or the memory device transceiver 340 described may include any one of a command encoder 405-a, a bus width configuration component 410-a, a driver component 415-a, and a first pin 420-a to an Mth pin 425-a or any combination thereof.

[0129] The command encoder 405-a may be configured to generate a set of encoded information bits for the received command and memory address according to a configured modulation and coding scheme. For example, if the command encoder 405-a receives a signal representing a row activate command and a row address, the command encoder 405-a may generate one (1) command bit, four (4) memory bank address bits, and sixteen (16) row address bits—a total of 21 bits. In another example, if the command encoder 405-a receives a signal representing a read command and a column address, the command encoder 405-a may generate three (3) command bits, four (4) memory bank address bits, and six (6) column address bits—a total of 13 bits. The command encoder 405-a may signal the set of encoded information bits to the driver component 415-a.

[0130] In some cases, the command encoder 405-a may be further configured to generate the set of encoded bits based on the configured bus width. That is, the command encoder 405-a may be configured to encode the command and memory address based on the number of enabled drivers / pins located at the host device 400-a. For example, if the command encoder 405-a receives a signal representing a row activation command and a row address, eleven (11) pins are enabled, and using a binary modulation scheme and double data rate signaling, the command encoder 405-a may generate and signal eleven (11) of the 21 information bits before the rising edge of the first signaling cycle, and generate and signal the remaining ten (10) of the 21 information bits before the falling edge of the first signaling cycle. In another example, if the command encoder 405-a receives a signal representing a row activation command and a row address, then six (6) pins are enabled, and using a binary modulation scheme and double data rate signaling, the command encoder 405-a can generate concurrent signaling to notify the first six (6) of the 21 information bits before the rising edge of the first signaling cycle, generate concurrent signaling to notify the next six (6) of the 21 information bits before the falling edge of the first signaling cycle, generate concurrent signaling to notify the next six (6) of the 21 information bits before the rising edge of the second signaling cycle, and generate concurrent signaling to notify the last three (3) of the 21 information bits before the falling edge of the second signaling cycle.

[0131] The bus width configuration component 410-a can be configured to dynamically determine the number of pins and / or cycles used to transmit the C / A signal through the C / A channel 430-a. For example, the bus width configuration component 410-a can determine the number of pins and / or cycles used to transmit the command based on the number of commands in the queue waiting to be transmitted from the host device 400-a, for example, the bus width configuration component 410-a can determine that the command should be transmitted using an increased number of pins (e.g., all available pins) and a reduced number of cycles (e.g., one (1) cycle) if the number of commands in the queue exceeds a threshold. In another example, the bus width configuration component 410-a can determine the number of pins and / or cycles used to transmit the command based on the type of commands in the queue waiting to be transmitted from the host device 400-a, for example, the bus width configuration component 410-a can determine that the command should be transmitted using a reduced number of cycles (e.g., one (1) cycle) if the number of row commands included in the queue exceeds a threshold. In another example, the bus width configuration component 410-a may determine a number of pins and / or cycles to use to transmit a command based on an expected or predicted hit rate for the memory bank, for example, the bus width configuration component 410-a may determine to reduce the number of pins (e.g., six (6) pins) and increase the number of cycles (e.g., two (2) cycles) when the predicted hit rate is greater than or equal to two.

[0132] The bus width configuration component 410-a may be further configured to store a value corresponding to the determined number of pins / cycles for transmitting the C / A signal. In some cases, the bus width configuration component 410-a stores the value in a bus width configuration register included within or external to the bus width configuration component 410-a. For example, the bus width configuration component 410-a may store a first value (e.g., "00") corresponding to a first number of enabled pins (e.g., eleven (11) pins) and a first number of cycles (e.g., one (1) cycle), a second value (e.g., "01") corresponding to a second number of enabled pins (e.g., six (6) pins) and / or a second number of cycles (e.g., two (2) cycles), etc. In some cases, various aspects of the bus width configuration component 410-a are implemented in different areas of the host device 400-a. For example, components of the bus width configuration component 410-a for determining the number of pins and / or cycles may be located in a processing portion of the host device 400-a, and bus width configuration registers may be located elsewhere (e.g., within a transceiver). In some cases, the bus width configuration component 410-a may be implemented using at least a portion of one or more memory controllers (e.g., external memory controller 105, device memory controller 155, local memory controller 165 or 260, or a combination thereof) and / or registers. In addition, the bus width configuration registers may be in direct electronic communication with the command encoder 405-a and the driver component 415-a, while components of the bus width configuration component 410-a for determining the number of pins and / or cycles may be in indirect electronic communication with the command encoder 405-a and the driver component 415-a.

[0133] The bus width configuration component 410-a may be further configured to program the encoding scheme of the command encoder 405-a by causing the bus width configuration register to indicate the stored value to the command encoder 405-a. For example, the bus width configuration component 410-a may indicate to the command encoder 405-a the value stored in the bus width configuration register corresponding to the pin configuration, and the command encoder 405-a may use the encoding scheme corresponding to the indicated value / pin configuration. In some cases, the command encoder 405-a may generate a bus width configuration command based on receiving the indication of the bus width from the bus width configuration component 410-a, and transmit the bus width configuration command via the C / A channel 430-a.

[0134] The bus width configuration component 410-a may be further configured to activate / deactivate one or more drivers of the driver component 415-a by indicating to the driver component 415-a a value stored in a bus width configuration register. For example, the bus width configuration component 410-a may indicate to the driver component 415-a a value corresponding to a pin configuration stored in a bus width configuration register, and the driver component 415-a may enable / disable one or more drivers corresponding to the indicated value and / or pin configuration.

[0135] The driver component 415-a may be configured to generate a signal based on a set of received information bits. In some cases, the driver component 415-a generates a signal based on a set of encoded information bits received from the command encoder 405-a. In some examples, the driver component 415-a may be configured to generate a signal according to a configuration modulation scheme (e.g., NRZ, PAM2, or PAM4) and / or a signaling scheme (e.g., SDR or DDR signaling). The driver component 415-a may be in electronic communication with the first pin 420-a to the Mth pin 425-a.

[0136] The first through Mth pins 420-a, 425-a may be configured to provide a signaling interface between the host device 400-a and the C / A channel 430-a. In some cases, the number of pins (M) included in the host device 400-a is selected to accommodate the transmission of the maximum C / A combination within a single cycle. For example, if 21 bits are used to convey the maximum C / A combination, and a binary modulation scheme and double data rate signaling are used, then M may be equal to eleven (11) pins.

[0137] Figure 4B Various aspects of an exemplary host device that supports configuring a C / A channel are described according to various aspects of the present disclosure.

[0138] Host device 400-b may be an example of host device 400-a, as described in reference Figure 4A The host device 400-b may include a bus width configuration component 410-b and a driver component 415-b, which may be examples of the bus width configuration component 410-a and the driver component 415-a, as described in reference to Figure 4A The host device 400-b may also include a row command encoder 435-b, a column command encoder 440-b, a first pin 445-b, a Kth pin 450-b, a second pin 455-b, and an Nth pin 460-b. The host device 400-b may be coupled to and communicate through a row C / A channel 465-b and a column C / A channel 470-b, which may be an example of channel 115, as described with reference to FIG. Figure 1 describe.

[0139] In some cases, for example, Figure 3 The transmitter of the described controller transceiver 320 may include any one of a bus width configuration component 410-b, a driver component 415-b, a row command encoder 435-b, a column command encoder 440-b, a first pin 445-b to a Kth pin 450-b and a second pin 455-b to an Nth pin 460-b, or any combination thereof.

[0140] The row command encoder 435-b may be configured to generate a set of encoded information bits for a received row command and row address according to a configured encoding scheme. For example, if the row command encoder 435-b receives a signal representing a row activation command and a row address, the row command encoder 435-b may generate one (1) command bit, four (4) memory bank address bits, and sixteen (16) row address bits—a total of 21 bits. The row command encoder 435-b may signal the set of encoded information bits to the driver component 415-b. In some cases, similar to the example in reference to FIG. Figure 4A The described command encoder 405-a, row command encoder 435-b may be further configured to generate the set of encoded bits based on the configured row bus width. In some cases, the grouping of the row C / A channel 465-b and the first pin 445-b to the Kth pin 450-b may be referred to as a row bus.

[0141] The column command encoder 440-b may be configured to generate a set of encoded information bits for a received column command and column address according to a configured encoding scheme. For example, if the column command encoder 440-b receives a signal representing a read command and a column address, the column command encoder 440-b may generate three (3) command bits, four (4) bank address bits, and six (6) column address bits—a total of 13 bits. The column command encoder 440-b may signal the set of encoded information bits to the driver component 415-b. In some cases, similar to the example of reference 415, the column command encoder 440-b may generate a set of encoded information bits for a received column command and column address. Figure 4A The described command encoder 405-a, column command encoder 440-b may be further configured to generate the set of encoded bits based on the configured column bus width. In some cases, the grouping of the column C / A channel 470-b and the second pin 455-b to the Nth pin 460-b may be referred to as a column bus.

[0142] The bus width configuration component 410-b can be configured to dynamically determine the number of pins and / or cycles used to transmit the row C / A signal through the row C / A channel 465-b. For example, the bus width configuration component 410-b can determine the number of pins and / or cycles used to transmit the row command based on the number of row commands waiting to be issued, the type of row command waiting to be issued, and / or based on a predicted web page hit rate. The bus width configuration component 410-b can similarly be configured to dynamically determine the number of pins and / or cycles used to transmit the column C / A signal through the column C / A channel 470-b.

[0143] The bus width configuration component 410-b may be further configured to store one or more values ​​corresponding to a determined number of pins and / or cycles for transmission through the row C / A channel 465-b and the column C / A channel 470-b in, for example, a bus width configuration register included within or external to the bus width configuration component 410-b.

[0144] The bus width configuration component 410-b may indicate or cause the bus width configuration register to indicate one or more stored values ​​to the row command encoder 435-b and the column command encoder 440-b, and the row command encoder 435-b and the column command encoder 440-b may encode the command based on the received values. The bus width configuration component 410-b may indicate or cause the bus width configuration register to indicate one or more stored values ​​to the driver component 415-b, and the driver component 415-b may activate / deactivate a specific driver based on the received values. In some cases, the row command encoder 435-b and / or the column command encoder 440-b may generate a bus width configuration command based on receiving an indication of the bus width from the bus width configuration component 410-b, and transmit the bus width configuration command via the row C / A channel 465-b or the column C / A channel 470-b, respectively.

[0145] The driver component 415-b may be configured to generate parallel row and column C / A signals based on the pin configuration determined by the bus width configuration component 410-b. The driver component 415-b may use one or more of the first pin 445-b to the K-th pin 450-b to transmit the row C / A / signal, and may use one or more of the second pin 455-b to the N-th pin 460-b to transmit the column C / A signal. In some examples, the driver component 415-b may be configured to use one or more of the first pin 445-b to the K-th pin 450-b and one or more of the second pin 455-b to the N-th pin 460-b to transmit the row C / A signal. And the driver component 415-b may be configured to use one or more of the first pin 445-b to the K-th pin 450-b and one or more of the second pin 455-b to the N-th pin 460-b to transmit the column C / A signal. By receiving the row C / A signal through a driver connected to one or more of the second pin 455 - b or the Nth pin 460 - b , and vice versa, the number of pins used to communicate row and column C / A signaling may be reduced.

[0146] The first pin 445-b through the Kth pin 450-b may be configured to provide a signaling interface between the host device 400-b and the row C / A channel 465-b. In some cases, the number of pins (K) included in the host device 400-b is selected to accommodate the transmission of the maximum row C / A combination in a single cycle. The second pin 455-b through the Nth pin 460-b may be configured to provide a signaling interface between the host device 400-b and the column C / A channel 470-b. In some cases, the number of pins (N) included in the host device 400-b is selected to accommodate the transmission of the maximum column C / A combination in a single cycle.

[0147] Figure 5A

[0013] Aspects of an exemplary device controller that supports configuring a C / A channel are described in accordance with various aspects of the present disclosure.

[0148] The device controller 500-a may be configured to receive control and address information via a dynamically configurable C / A channel. The device controller 500-a may be configured to receive data information via a dynamically configurable data channel. In some cases, the device controller may be an instance of a device memory controller 155, a local memory controller 165, a local memory controller 260, or a memory device 310, as described with reference to FIG. Figures 1 to 3 The device controller 500-a may include a command decoder 505-a, a bus width configuration component 510-a, a driver component 515-a, and a first pin 520-a to an Mth pin 525-a. The device controller 500-a may communicate with an external controller (e.g., a reference signal) via a C / A channel 530-a. Figure 4AA host device 400 - a ) is depicted coupled to and in communication with.

[0149] In some cases, for example, Figure 3 The receiver of the depicted memory device transceiver 340 may include any one of a command decoder 505-a, a bus width configuration component 510-a, a driver component 515-a, and first through Mth pins 520-a, 525-a, or any combination thereof.

[0150] The command decoder 505-a may be configured to decode the received signal according to the configured modulation and coding scheme. The command decoder 505-a may be further configured to obtain commands and memory addresses based on the configuration of the C / A channel 530-a. In some cases, the command decoder 505-a may decode the encoded signal received from the driver component 515-a to obtain the command and memory address represented by the signal transmitted through the C / A channel 530-a. In some cases, the command decoder 505-a decodes the received signal based on the configured bus width. That is, the command decoder 505-a may be configured to decode the command and memory address based on the determined configuration of the C / A channel 530-a. For example, if a subset of signal paths included in the C / A channel 530-a is used to convey the C / A signal, the command decoder may be configured to use a subset of corresponding drivers and decode the received C / A signal through a determined number of cycles.

[0151] The bus width configuration component 510-a can be configured to determine the number of pins and / or cycles for receiving C / A signals through the dynamically configured C / A channel 530-a. For example, the bus width configuration component 510-a can determine the number of pins and / or cycles for receiving C / A signals based on the received signal, for example, the bus width configuration component 510-a can determine that certain pins are disabled based on the voltage pattern of the signal path across the C / A channel 530-a. In another example, the bus width configuration component 510-a can determine the number of pins and / or cycles for receiving C / A signals based on the received bus width configuration command.

[0152] The bus width configuration component 510-a may be further configured to store a value corresponding to the determined number of pins and / or cycles for receiving the C / A signal, for example, in a bus width configuration register included within or external to the bus width configuration component 510-a. The bus width configuration component 510-a may be further configured to program the command decoder 505-a by indicating to the command decoder 505-a or causing the bus width configuration register to indicate the stored value. For example, the bus width configuration component 510-a may indicate to the command decoder 505-a or cause the bus width configuration register to indicate the stored value corresponding to the pin configuration, and the command decoder 505-a may use a decoding scheme corresponding to the indicated value / pin configuration, for example, if binary modulation scheme DDR signaling is used and the bus width configuration component 510-a indicates to the command decoder 505-a that six (6) pins are enabled, then the command decoder 505-a may determine that the received row activation command is spread across two cycles.

[0153] The bus width configuration component 510-a can be similarly configured to program the driver component 515-a by indicating to the driver component 515-a or causing the bus width configuration register to indicate a stored value. For example, the bus width configuration component 510-a can indicate to the driver component 515-a a stored value corresponding to the pin configuration, and the driver component 515-a can activate / disable the driver according to the indicated value / pin configuration, for example, if the pin configuration indicates that pins 1 and 2 should be active, and pins 3, 4, and M should be inactive, then the driver component 515-a can disable the corresponding drivers 3, 4, and M.

[0154] The driver component 515-a may be configured to receive a signal and output one or more voltages representing a binary value. That is, if the voltage of the signal received at the driver of the driver component 515-a is at or near a voltage level representing a binary value, the driver may output the voltage level to the command decoder 505-a. In some cases, the driver component 515-a outputs a voltage using only activated drivers in the driver component 515-a.

[0155] The first pin 520-a through the Mth pin 525-a may be configured to provide a signaling interface between the device controller 500-a and the C / A channel 530-a. In some cases, the number of pins (M) included in the device controller 500-a is selected to accommodate the transmission of the maximum C / A combination within a single cycle. For example, if 21 bits are used to convey the maximum C / A combination, and a binary modulation scheme and double data rate signaling are used, then M may be equal to eleven (11) pins.

[0156] Figure 5B

[0013] Aspects of an exemplary device controller that supports configuring a C / A channel are described in accordance with various aspects of the present disclosure.

[0157] Device controller 500-b may be an example of device controller 500-a, as described in reference Figure 5A Device controller 500-b may include a bus width configuration component 510-b and a driver component 515-b, which may be examples of bus width configuration component 510-a and driver component 515-a, as described in reference to FIG. Figure 5A The device controller 500-b may also include a row command decoder 535-b, a column command decoder 540-b, a first pin 545-b, a Kth pin 550-b, a second pin 555-b, and an Nth pin 560-b. The device controller 500-b may be coupled to and communicate through a row C / A channel 565-b and a column C / A channel 570-b, which may be as described in reference Figure 1 An example of channel 115 is described.

[0158] In some cases, for example, Figure 3 The receiver of the described memory device transceiver 340 may include any one of a bus width configuration component 510-b, a driver component 515-b, a row command decoder 535-b, a column command decoder 540-b, a first pin 545-b to a Kth pin 550-b and a second pin 555-b to an Nth pin 560-b, or any combination thereof.

[0159] The row command decoder 535-b may be configured to decode the received signal to identify the row command and row address conveyed in the signal. The row command decoder 535-b may be further configured to identify the row command and row address based on the configuration of the row C / A channel 565-b. For example, the row command decoder 535-b may decode the row command and row address in a plurality of clock cycles based on the number of pins used to convey the C / A signal. In some cases, the row command decoder 535-b decodes the received signal based on a value corresponding to the pin configuration received from the bus width configuration component 510-b.

[0160] The bus width configuration component 510-b may be configured to determine the number of pins and / or cycles used to receive row C / A signals via the row C / A channel 565-b. For example, the bus width configuration component 510-b may determine the number of pins and / or cycles used to receive row C / A commands based on the number of active signal paths in the row C / A channel 565-b or the received bus width configuration message received via the row C / A channel. The bus width configuration component 510-b may similarly be configured to dynamically determine the number of pins and / or cycles used to receive C / A signals via the column C / A channel 570-b.

[0161] The bus width configuration component 510-b may be further configured to store one or more values ​​corresponding to a determined number of pins and / or cycles for transmission through the row C / A channel 565-b and the column C / A channel 570-b in, for example, a bus width configuration register included within or external to the bus width configuration component 510-b.

[0162] The bus width configuration component 510-a may indicate or cause the bus width configuration register to indicate one or more stored values ​​to the row command decoder 535-b and the column command decoder 540-b, and the row command decoder 535-b and the column command decoder 540-b may decode the command based on the pin configuration and the corresponding timing corresponding to the stored values. For example, if the bus width configuration component 510-b indicates that six of the first pin 545-b to the Kth pin 550-b are active and binary and DDR signaling are used, the row command decoder may decode the received 21-bit row activation command within two clock cycles. The bus width configuration component 510-a may also indicate or cause the bus width configuration register to indicate one or more stored values ​​to the driver component 515-b, and the driver component 515-b may activate / deactivate the driver corresponding to the activated / deactivated pin indicated by the stored value / pin configuration.

[0163] The driver component 515-b may be configured to receive parallel row and column C / A signals based on the pin configuration indicated by the bus width configuration component 510-b. The driver component 515-b may use one or more of the first pin 545-b to the K-th pin 550-b to receive the row C / A signal, and may use one or more of the second pin 555-b to the N-th pin 560-b to receive the column C / A signal. In some examples, the driver component 515-b may be configured to use one or more of the first pin 545-b to the K-th pin 550-b and one or more of the second pin 555-b to the N-th pin 560-b to receive the row C / A signal. And the driver component 515-b may be configured to use one or more of the first pin 545-b to the K-th pin 550-b and one or more of the second pin 555-b to the N-th pin 560-b to receive the column C / A signal. By receiving the row C / A signal through a driver connected to one or more of the second pin 555 - b or the Nth pin 560 - b , and vice versa, the number of pins used to convey row and column C / A signaling may be reduced.

[0164] The first pin 545-b through the Kth pin 550-b may be configured to provide a signaling interface between the device controller 500-b and the row C / A channel 565-b. In some cases, the number of pins (K) included in the device controller 500-b is selected to accommodate the transmission of the maximum row C / A combination in a single cycle. The second pin 555-b through the Nth pin 560-b may be configured to provide a signaling interface between the device controller 500-b and the column C / A channel 570-b. In some cases, the number of pins (N) included in the device controller 500-b is selected to accommodate the transmission of the maximum column C / A combination in a single cycle.

[0165] Fig. 6A An exemplary timing diagram for configuring a C / A channel as disclosed herein is illustrated.

[0166] Figures 6A to 6C One or more operations of a dynamically configurable C / A channel are illustrated. Timing diagram 600-a is depicted in reference Figure 4B The host device 400-b described in reference Figure 5B Exemplary communication between device controllers 500-b is depicted via column channels 610-a and row channels 615-a. Figures 6A to 6C In the example, DDR signaling and a binary modulation scheme can be used to convey information.

[0167] The clock signal 605-a can provide a signal that notifies a receiving device (e.g., device controller 500-b) when to latch (e.g., store) information communicated over a channel. For example, the receiving device can process a signal on the channel after recognizing that the clock signal 605-a has transitioned from a low voltage to a high voltage. As discussed herein, when DDR signaling is used, first information can be signaled at the rising edge of a clock pulse, and second information can be signaled at the falling edge of a clock pulse. Thus, when DDR signaling is used, the receiving device can also process a second signal on the channel after recognizing that the clock signal 605-a has transitioned from a high voltage to a low voltage.

[0168] As in Fig. 6A , a read command may be transmitted over column channel 610-a per cycle 620-a, and alternating ACT and PRE commands may be transmitted over row channel 615-a per cycle 620-a. In some cases, an ACT command may include twenty-one (21) bits—1 command bit, 4 bank address bits, and 16 row address bits—a read may include thirteen (13) bits—3 command bits, 4 bank address bits, and 7 column address bits, and a PRE command may include seven (7) bits—3 command bits and 4 bank address bits. The number of pins (N) used to determine communication over column channel 610-a and row channel 615-a may be determined by the number of pins (N) used to determine communication over column channel 610-a and row channel 615-a. Pins) can be expressed by the following equation: Where N Bits Indicates the number of bits used to convey the command, N cycles represents the number of cycles used to transmit the command, where N cycles is multiplied by two (2) because DDR signaling is used.

[0169] In some cases, based on identifying the number of pins that can transmit row and column commands within a single cycle 620-a, a maximum number of pins dedicated to the C / A channel can be determined for communicating signals. Applying the above equations, the host device 400-b and the device controller 500-b can use eleven (11) row pins to transmit and receive row commands via the row channel 615-a, for example, based on a maximum row command comprising 21 bits. Similarly, seven (7) column pins can be used to transmit and receive column commands via the column channel 610-a, for example, based on a read command comprising 13 bits. Thus, in reference to Fig. 6A In the described example, the maximum number of pins dedicated to the C / A channel may be equal to eighteen (18) pins. In some cases, the C / A channel is configured to use the maximum number of pins as a default configuration to ensure that control information and data can be transmitted at the desired rate.

[0170] Figure 6B An exemplary timing diagram for configuring a C / A channel as disclosed herein is illustrated.

[0171] Timing diagram 600-b is depicted in reference Figure 4B The host device 400-b described is similar to the host device 400-b described in reference Figure 5B The device controllers 500-b are described to communicate with each other via one or more of the column channels 610-b and the row channels 615-b. The clock signal 605-b may be similarly configured as described with reference to Fig. 6A A clock signal 605-a is depicted.

[0172] In one example, relative to Fig. 6A Reducing the number of pins used to communicate C / A signaling. The number of pins used to communicate C / A signaling may be reduced to save power or free up pins for data transmission. The number of pins may be reduced based on determining that the number of commands in the command queue is below a threshold, based on determining that the page hit rate is above a threshold, or a combination thereof. In some examples, the row pin count may be reduced to six (6) row pins and the column pin count may be maintained at four (4) column pins, thereby reducing the total number of pins used by the C / A channel to ten (10) pins.

[0173] like Figure 6B As explained in , as the number of pins decreases, the length of some commands can be relatively Fig. 6AIncrease. For example, applying the equations provided above, if the row pin count is reduced to six (6) row pins, and the column pin count is reduced to four (4) column pins, then the number of cycles 620-b used to communicate the ACT and read commands may be increased to two (2) cycles 620-b. In some cases, the number of cycles 620-b used to communicate the PRE command may remain the same, such as at one (1) cycle 620-b. In some cases, as the length of the read command increases, the burst length may also be increased to ensure full utilization of the data bus—for example, if the length of the read command is doubled, then the burst length may also be doubled.

[0174] In another example, the number of pins used to communicate C / A signaling may be relative to Figure 6C Increase. As discussed herein, the number of pins used to communicate C / A signaling can be increased to avoid latency in command execution. As discussed herein, the number of pins can be increased based on determining that the number of commands in the command queue is above a threshold, based on determining that a predicted page hit rate is below a threshold, etc.

[0175] Figure 6C An exemplary timing diagram for configuring a C / A channel as disclosed herein is illustrated.

[0176] Timing diagram 600-c is depicted in reference Figure 4B The host device 400-b described is similar to the host device 400-b described in reference Figure 5B The device controllers 500-b are described to communicate with each other via one or more exemplary column channels 610-c and row channels 615-c. The clock signal 605-c may be similarly configured to communicate with each other via one or more exemplary column channels 610-c and row channels 615-c. Fig. 6A The clock signal 605-a and Figure 6B The clock signal 605-b is used for timing.

[0177] In one example, the number of pins used to communicate C / A signaling may be similar to Figure 6B The discussion in this paper is relative to Fig. 6A and / or 6B reduction, for example, to increase power savings or make additional pins available for data communications.

[0178] exist Figure 6C , the row pin count may be reduced to four (4) row pins, and the column pin count may remain at four (4) column pins, thereby reducing the total number of pins used by the C / A channel to eight (8) pins. Using the above equations, the number of cycles 620-c used to communicate ACT commands may be increased to three (3) cycles 620-c, and the number of cycles 620-c used to communicate read commands may remain at two (2) cycles. In some cases, the number of cycles 620-b used to communicate PRE commands may remain the same, such as at one (1) cycle 620-b.

[0179] In some cases, the row pin count may be reduced to four (4) pins after determining that the page hit rate is equal to or greater than two (2), or based on determining that the rate of ACT commands is below a threshold.

[0180] Figure 7 A process flow for configuring a C / A channel is described as disclosed herein.

[0181] Process flow 700 may illustrate one or more communications between an external controller 705 and a memory device controller 710 via a dynamically configurable C / A channel or one or more functions performed by the external controller 705 and / or the memory device controller 710. The external controller 705 may be an example of an external memory controller 105, a controller 305, a host device 400-a, or a host device 400-b, as described in detail in reference to FIG. Figure 1 , 3 , 4A and 4B. Memory device controller 710 may be an example of memory device 110, device memory controller 155, local memory controller 165, local memory controller 260, memory device 310, device controller 500-a or device controller 500-b, as described in reference Figures 1 to 3 , 5A and 5B.

[0182] At 715, the external controller 705 may determine a C / A channel configuration. Determining the C / A channel configuration may include determining a number of pins of the C / A channel to configure for communicating C / A signaling with the memory device controller 710. As discussed herein, the number of pins to be configured may be based on previous or future operations of the memory system, sizes of different types of C / A signaling, a state of the system (e.g., a power-on or initialization state), a number of commands in a command queue, and the like. For example, determining the number of pins to be configured may be based on identifying a number of unused command slots in a previous time period, e.g., the external controller 705 may disable pins based on determining that the number of unused command slots exceeds a threshold. In some cases, the number of pins to be configured may be determined based on operating parameters of the memory device controller 710. For example, the external controller 705 may disable pins based on determining that the temperature of the memory device controller 710 is below a threshold, e.g., because the rate of refresh commands may be reduced at lower temperatures. In another example, the external controller 705 may disable pins to support a power consumption level of the memory device controller 710, e.g., because the rate of refresh commands may be reduced at lower temperatures.

[0183] In some cases, determining the C / A channel configuration also includes determining the number of cycles for communicating different types of C / A signaling with the memory device controller 710. As discussed herein, the number of cycles of a certain type of C / A signaling may be adapted as the number of pins is adapted, for example, the number of cycles of a particular type of C / A signaling may increase as the number of pins decreases. In some cases, determining the C / A channel configuration may include determining whether to use a single C / A channel or dual C / A channels (e.g., row C / A and column C / A channels). In some cases, determining the C / A channel configuration may include identifying a default C / A channel configuration (e.g., at power-on). In some cases, a bus width configuration component located at the external controller 705 determines the C / A channel configuration and stores a value corresponding to the current C / A channel configuration.

[0184] In some cases, determining the C / A channel configuration may include determining whether to use a single C / A channel or dual C / A channels (e.g., row C / A and column C / A channels). For example, when dual C / A channels are used, the external controller 705 may configure different C / A channels separately.

[0185] At 720, the external controller 705 may indicate the C / A channel configuration to the memory device controller 710. In some cases, the external controller 705 transmits an explicit indication of the C / A channel configuration to the memory device controller 710. For example, the external controller 705 may transmit a value stored at a bus width configuration component corresponding to a specific C / A channel configuration in a bus width configuration message. The memory device may receive the bus width configuration message and determine the configuration of the C / A channel based on the value in the bus width configuration message. In some instances, the external controller 705 may transmit the value of the bus width configuration component using an access command such as an RD, WR, ACT, or PRE command. In another example, the external controller 705 may implicitly indicate the C / A channel configuration by driving certain pins to a high level or a low level after a reset occurs, for example, the pins driven to a high level may be identified by the memory device controller 710 as disabled. In some cases, the external controller 705 may transmit an indication through a pin different from the pin used to transmit C / A signaling to the memory device controller 710.

[0186] At 725, the memory device controller 710 may determine the C / A channel configuration. In some cases, the memory device controller 710 may determine the C / A channel configuration without receiving an indication from the external controller 705, for example, by identifying a default configuration at power on. In other cases, the memory device controller 710 may determine the C / A channel configuration based on an explicit (e.g., using a bus width configuration message) or implicit (e.g., using a voltage mode) indication received from the external controller 705. In some cases, the memory device controller 710 may determine the C / A channel configuration using the same procedure described with reference to 715 and / or the external controller 705.

[0187] At 730, the external controller 705 may configure the C / A channel. Configuring the C / A channel may include activating and spoofing specific pins at the external controller 705 based on the number of determined pins. For example, if the number of determined pins is less than the number of available pins, the external controller 705 may disable unused pins. This may also be referred to as configuring the C / A bus width. In some examples, the external controller 705 may program the C / A bus width by driving certain pins to a high level or a low level (e.g., after a reset occurs). Configuring the C / A channel may also include configuring one or more components (e.g., encoders, driver components, and / or transmitters) at the external controller 705 coupled to the C / A channel based on the number of determined pins and / or the number of cycles. For example, if the number of pins used to transmit commands is reduced, the external controller 705 may configure the encoder to generate commands spanning multiple cycles. In addition, the external controller 705 may configure the driver component to disable the driver coupled to the disabled pin.

[0188] At 735, the memory device controller 710 may configure the C / A channel. Configuring the C / A channel may include activating and spoofing specific pins at the memory device controller 710 based on the number of determined pins. For example, if the number of determined pins is less than the number of available pins, the memory device controller 710 may disable unused pins. Configuring the C / A channel may also include configuring one or more components (e.g., decoders, and / or receivers) at the memory device controller 710 coupled to the C / A channel based on the number of determined pins and / or the number of cycles. For example, if a certain number of pins are disabled, the memory device controller 710 may configure the decoder to process received signals across multiple cycles. In addition, the memory device controller 710 may configure the receiver to disable a receiving component or driver coupled to the disabled pins.

[0189] As discussed herein, in some cases, the memory device controller 710 may adapt the C / A channel configuration during operation of a system including the external controller 705 and the memory device controller 710 (e.g., the C / A channel configuration may be adapted on the fly). For example, the C / A channel configuration may be adapted based on receiving a bus width configuration message. In some cases, the memory device controller 710 observes a timeout duration between reconfiguring the C / A channel and processing a subsequent command. During the timeout period, the memory device controller 710 and / or the external controller 705 may avoid passing any additional commands. The memory device controller 710 and / or the external controller 705 may use the timeout period to reconfigure components (e.g., encoders, decoders, receivers, transmitters, and / or drivers) to support the current C / A channel configuration. The timeout period may also allow previous commands to be processed according to the previous C / A channel configuration.

[0190] In some cases, both the external controller 705 and the memory device controller 710 include command truth tables for each of the different C / A channel configurations that can be used to recognize and process commands received in C / A signaling.

[0191] At 740, the external controller 705 may transmit C / A signaling to the memory device controller 710 through the C / A channel according to the current C / A channel configuration. That is, the external controller 705 may transmit C / A signaling using an enable pin located at the external controller 705 and according to the corresponding command timing, for example, if six (6) row pins are enabled, the external controller 705 may transmit an ACT command through a row C / A channel using the six (6) enabled row pins and within two cycles. When dual C / A channels are used, the external controller 705 may transmit row C / A signaling (e.g., ACT command) through the row C / A channel, and may transmit column C / A signaling (e.g., read and write commands) through the column C / A channel.

[0192] In addition, the memory device controller 710 may receive C / A signaling from the external controller 705 through the C / A channel according to the current C / A channel configuration. That is, the memory device may receive C / A signaling using an enable pin located at the memory device controller 710 and according to the corresponding command timing, wherein the enable pin at the memory device controller 710 may correspond to the enable pin at the external controller 705. For example, if six (6) row pins are enabled, the memory device controller 710 may receive an ACT command within two cycles by using the row C / A channel of the six (6) enabled row pins. In some cases, the memory device controller 710 identifies that the ACT command is received, or is in the process of being received, based on determining that the first information bit of the received signal is a logic "0" or some other predetermined symbol (e.g., in the case of a modulation scheme including three or more symbols).

[0193] After receiving the C / A signaling, the memory device controller 710 can decode the received C / A signaling to identify the command and address information. The memory device controller 710 can then pass the decoded command and memory address to the memory array, which can access the memory cells located at the identified memory address according to the decoded command.

[0194] The order of performing some operations discussed above may be reconfigured, omitted, and / or performed in parallel. For example, the determination at 725 may be performed after or simultaneously with the configuration at 730.

[0195] Figure 8 800 that supports configuring C / A channels as disclosed herein. Figure 1 and 2 Examples of external memory controller 105, device memory controller 155, local memory controller 165, local memory controller 260, or combinations thereof are described.

[0196] The controller 800 includes a bias component 810, a timing component 815, a bus width configuration component 820, and a command processing component 825. The controller 800 may be an example of an external memory controller 105, a device memory controller 155, a local memory controller 165, a local memory controller 260, or a controller 305, as described in detail in reference to FIG. Figures 1 to 3 described.

[0197] The bias component 810 can be configured to apply a voltage and / or current in a memory system. In some cases, the bias component 810 can be configured to apply a voltage of a larger signal to a channel of a device connected in a memory system.

[0198] The timing component 815 can be configured to provide one or more clock signals throughout the memory system. In some cases, the timing component 815 can be configured to trigger the bias component 810 to apply a voltage or current in the memory system. The timing component 815 can be further configured to trigger other components in the memory system to process signals and perform storage operations.

[0199] In some examples, bus width configuration component 820 can be configured to determine a first number of pins of a channel for receiving one or more commands (e.g., row or column commands and / or addresses) from a host device and / or a first number of cycles for receiving one or more commands from a host device. Bus width configuration component 820 can also be configured to configure components (e.g., receivers and / or decoders) coupled to the channel based on the first number of pins and the first number of cycles. Command processing component 825 can be configured to receive commands over the channel based on the configured components.

[0200] In some cases, the bus width configuration component 820 may also be configured to receive an indication of a first number of pins for receiving one or more commands, or a first number of cycles for one or more commands, or both, from the host device, and may determine the first number of pins and the first number of cycles based on the indication. In some cases, the indication is a second command. In other cases, the indication is an access command including the indication. In some cases, the indication is communicated via a channel pin different from the pin used to communicate the access command. In some cases, the bus width configuration component 820 may also be configured to determine that a duration from receiving the indication satisfies a timing threshold, wherein receiving the command occurs after the timing threshold is met.

[0201] In some cases, the bus width configuration component 820 may also configure a second component (e.g., a second receiver and / or a second decoder) coupled to the second channel based on a second number of pins of the second channel for receiving one or more commands (e.g., row commands and / or addresses) from the host device and a second number of cycles of the second channel for the one or more commands. The command processing component 825 may be configured to receive a second command through the second channel based on configuring the second component.

[0202] In some cases, bus width configuration component 820 can determine the first number of cycles and / or the first number based on identifying an initialization event (e.g., a boot, power-on, or reset event) of the memory. In some cases, bus width configuration component 820 can determine the first number of cycles and / or the first number based on identifying an operating parameter of the memory device. In some cases, the operating parameter includes a power consumption parameter associated with the memory device, a third number of commands in a buffer of the memory device that meets the criteria, or both.

[0203] In some cases, bus width configuration component 820 can determine a first number of pins for receiving the one or more commands based at least in part on determining a first number of cycles of the one or more commands.

[0204] In some examples, the bus width configuration component 820 can be configured to determine a first number of pins of a channel for transmitting one or more commands to a memory device, and a first number of cycles for transmitting one or more commands (e.g., row or column commands and / or addresses) to the memory device. The bus width configuration component 820 can also be configured to configure a component (e.g., a driver or encoder) coupled to the channel based at least in part on the first number of pins of the channel for transmitting one or more commands and the first number of cycles. The command processing component 825 can be configured to transmit commands to the memory device through the channel based at least in part on the configuration component.

[0205] In some cases, the bus width configuration component 820 and / or the command processing component 825 can be configured to transmit an indication of a first number of pins for transmitting one or more commands or a first number of cycles for one or more commands, or both, to the memory device (e.g., a bus width configuration command). In some cases, the command processing component 825 can determine that a duration from transmitting the indication satisfies a timing threshold, based at least in part on determining that the command was transmitted after the timing threshold was satisfied. In some cases, the timing threshold can indicate a lower limit on the duration from receiving the indication. In some cases, the lower limit can be a minimum amount of time.

[0206] In some cases, the bus width configuration component 820 can be further configured to configure a second component (e.g., a second driver and / or a second encoder) coupled to the second channel based at least in part on a second number of pins of the second channel for transmitting one or more commands to the memory device and a second number of cycles of the second channel for the one or more commands. In some cases, the command processing component 825 can be configured to transmit a second command (e.g., a row command and / or an address) through the second channel based at least in part on configuring the second component.

[0207] In some examples, bus width configuration component 820 can determine a first number of pins or a first number of cycles based on identifying an operating parameter of the memory device. In some cases, the operating parameter is a power consumption parameter associated with the memory device, a third number of commands in a buffer of the memory device that meets the criteria, or both. In bus width configuration, component 820 can determine the first number of pins or the first number of cycles based on identifying a start-up event of the memory device.

[0208] Fig. 9A method 900 or a flowchart of a plurality of methods for configuring a C / A channel is described according to various examples disclosed herein. In some cases, the method 900 may be implemented by the controller 800, such as referring to Figure 8 described.

[0209] At block 905, the method may include determining a first number of pins of a channel for receiving one or more commands from a host device and a first number of cycles for receiving one or more commands from the host device, as described with reference to Figures 1 to 7 In some examples, the operations of block 905 may be performed or facilitated by a controller, such as with reference to Figure 1 , 2 , 3 and 8 described.

[0210] At block 910, as shown in reference Figures 1 to 7 As described, the method may include configuring a component coupled to the channel based at least in part on a first number of pins and a first number of cycles, the component comprising a receiver or a decoder or both. In some examples, the operations of block 910 may be performed or facilitated by a controller, as described with reference to Figure 1 , 2 , 3 and 8 described.

[0211] At block 915, as shown in reference Figures 1 to 7 As described, the method may include receiving a command via a channel based at least in part on configuring the component. In some examples, the operations of block 915 may be performed or facilitated by a controller, as described with reference to Figure 1 , 2 , 3 and 8 described.

[0212] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for determining a first number of pins of a channel for receiving one or more commands from a host device and a first number of cycles for receiving the one or more commands from the host device; configuring a component coupled to the channel based at least in part on the first number of pins and the first number of cycles, the component including a receiver or a decoder or both; and at least in part configuring the component to receive the command over the channel.

[0213] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein may further include operations, features, devices, or instructions for performing the following operations: receiving an indication of the first number of pins for receiving the one or more commands, or the first number of cycles for the one or more commands, or both, from a host device, wherein determining the first number of pins and the first number of cycles is based at least in part on the indication. In some examples of the methods, apparatuses, and non-transitory computer-readable media described herein, receiving the indication includes receiving a second command including the indication from the host device via a channel. In some examples of the methods, apparatuses, and non-transitory computer-readable media described herein, receiving the indication includes receiving an access command including the indication from the host device via a channel. In some examples of the methods, apparatuses, and non-transitory computer-readable media described herein, the indication is communicated via one or more pins of the channel, the one or more pins being different from the one or more pins via which the access command is communicated.

[0214] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for determining that a duration from receiving the indication satisfies a timing threshold, wherein receiving the command occurs after the timing threshold is satisfied.

[0215] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, devices, or instructions for performing the following operations: configuring a second component coupled to a second channel based at least in part on a second number of pins of a second channel for receiving one or more commands from a host device and a second number of cycles of the second channel for the one or more commands, the second component comprising a second receiver or a second decoder or both; and receiving a second command through the second channel based at least in part on configuring the second component.

[0216] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for identifying an initialization event for a memory device, wherein determining a first number of pins and determining a first number of cycles are based at least in part on identifying the initialization event.

[0217] Some examples of methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: identifying an operating parameter of the memory device, wherein determining the first number of pins or determining the first number of cycles is based at least in part on identifying the operating parameter of the memory device. In some examples of methods, apparatus, and non-transitory computer-readable media described herein, the operating parameter includes a power consumption parameter associated with the memory device, a third number of commands in a buffer of the memory device that satisfy the criteria, or both.

[0218] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, determining a first number of pins for receiving one or more commands is based at least in part on determining a first number of cycles for the one or more commands.

[0219] Fig.10 A method 1000 or a flowchart of a plurality of methods for configuring a C / A channel is described according to various examples disclosed herein. In some cases, the method 1000 may be implemented by the controller 800, such as referring to Figure 8 described.

[0220] At block 1005, the method may include determining a first number of pins of a channel configured to transmit one or more commands to a memory device and a first number of cycles for transmitting the one or more commands to the memory device, as described with reference to FIG. Figures 1 to 7 In some examples, the operations of block 1005 may be performed or facilitated by a controller, such as with reference to Figure 1 , 2 , 3 and 8 described.

[0221] At block 1010, the method may include configuring a component coupled to the channel based at least in part on the first number of pins of the channel and the first number of cycles for transmitting the one or more commands, the component including a driver or a decoder or both, as described in reference to Figures 1 to 7 In some examples, the operations of block 1010 may be performed or facilitated by a controller, such as with reference to Figure 1 , 2 , 3 and 8 described.

[0222] At block 1015, the method may include transmitting a command to a memory device over a channel based at least in part on configuring the component, as described with reference to Figures 1 to 7 In some examples, the operations of block 1015 may be performed or facilitated by a controller, such as with reference to Figure 1 , 2 , 3 and 8 described.

[0223] In some examples, an apparatus as described herein may perform one or more methods, such as method 1000. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for determining a first number of pins of a channel for transmitting one or more commands to a memory device and a first number of cycles for transmitting the one or more commands to the memory device; configuring a component coupled to the channel based at least in part on the first number of pins of the channel and the first number of cycles for transmitting the one or more commands, the component including a driver or an encoder or both; and transmitting commands to the memory device through the channel based at least in part on configuring the component.

[0224] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, devices, or instructions for transmitting to the memory device an indication of the first number of pins for transmitting the one or more commands, or the first number of cycles for the one or more commands, or both.

[0225] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for determining that a duration from transmitting the indication satisfies a timing threshold, wherein receiving the command occurs after the timing threshold is satisfied based at least in part on the determination.

[0226] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, devices, or instructions for performing the following operations: configuring a second component coupled to the second channel based at least in part on a second number of pins of a second channel for transmitting one or more commands to a memory device and a second number of cycles for the one or more commands of the second channel, the second component comprising a second driver or a second encoder or both; and transmitting a second command through the second channel based at least in part on configuring the second component.

[0227] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for performing the following operations: identifying operating parameters of the memory device, wherein determining the first number of pins or determining the first number of cycles is based at least in part on identifying the operating parameters of the memory device.

[0228] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, the operating parameter is a power consumption parameter associated with the memory device, a third number of commands in a buffer of the memory device that satisfy the criteria, or both.

[0229] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for identifying a startup event for a memory device, wherein determining a first number of pins and determining a first number of cycles are based at least in part on identifying the startup event.

[0230] It should be noted that the above described method describes possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, two or more examples from the method may be combined.

[0231] In some examples, an apparatus or device may use general or special purpose hardware to perform various aspects of the functionality described herein. For example, an apparatus or device may include: a first receiver including a plurality of pins for receiving one or more commands over a first channel; a first decoder coupled to the first receiver and configured to decode the one or more commands received over the first channel; and a register coupled to the first receiver and the first decoder and configured to configure a width of the first channel based at least in part on the one or more commands received over the first channel.

[0232] In some examples of an apparatus or device, the register is configured to determine a first number of pins of the first channel for receiving the one or more commands and is configured to determine a first number of cycles for the one or more commands.

[0233] In some instances, an apparatus or device includes: a second receiver including a plurality of pins for receiving one or more commands via a second channel; and a second decoder coupled to the second receiver and for decoding the one or more commands received via the second channel, wherein the register is for configuring a width of the second channel based at least in part on the one or more commands received via the second channel, the register being coupled to the second receiver and the second decoder. In some instances of an apparatus or device, a first channel is used to communicate row commands, and a second channel is used to communicate column commands. In some instances of an apparatus or device, a first number of pins of the first channel is different from a second number of pins of the second channel, and is configurable independently of the second number of pins of the second channel.

[0234] In some examples, an apparatus or device may use general or special purpose hardware to perform various aspects of the functionality described herein. For example, an apparatus or device may include: a first driver including a plurality of pins for transmitting one or more commands through a first channel; a first encoder coupled to the first driver and for encoding the one or more commands transmitted through the first channel; and a register coupled to the first driver and the first encoder and for configuring a width of the first channel based at least in part on the one or more commands transmitted through the first channel.

[0235] In some examples of an apparatus or device, a register is used to determine a first number of pins of a first channel for transmitting one or more commands and to determine a first number of cycles for the one or more commands.

[0236] In some instances, an apparatus or device includes: a second driver comprising a plurality of pins for transmitting one or more commands via a second channel; and a second encoder coupled to the second driver and for encoding the one or more commands transmitted via the second channel, wherein the register is for configuring a width of the second channel based at least in part on the one or more commands transmitted via the second channel, the register being coupled to the second driver and the second encoder.

[0237] An apparatus is described. The apparatus may include: a first receiver including a set of pins configured to receive one or more commands over a first channel; a first decoder coupled to the first receiver and configured to decode the one or more commands received over the first channel; and a register coupled to the first receiver and the first decoder and programmable to configure a width of the first channel based on the one or more commands received over the first channel.

[0238] In some examples, the register may be configured to determine a first number of pins of a first channel for receiving one or more commands and may be configured to determine a first number of cycles for the one or more commands.

[0239] Some instances of an apparatus may include a second receiver including a set of pins configured to receive one or more commands over a second channel, and a second decoder coupled to the second receiver and configured to decode the one or more commands received over the second channel, wherein the register is programmable to configure a width of the second channel based at least in part on the one or more commands received over the second channel, the register being coupled to the second receiver and the second decoder.

[0240] In some examples, the first channel may be configured to communicate row commands and the second channel may be configured to communicate column commands.

[0241] In some examples, a first number of pins of a first channel can be different from, and can be configured independently of, a second number of pins of the second channel.

[0242] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have various bit widths.

[0243] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at a voltage of approximately zero volts (0V) but is not directly coupled to ground. Therefore, the voltage of the virtual ground may temporarily fluctuate and return to approximately 0V in a steady state. Virtual ground may be implemented using various electronic circuit elements, such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are also possible. "Virtual ground" or "virtually grounded" means connected to approximately 0V.

[0244] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with (or in conductive contact with, or connected or coupled to) each other if there is any conductive path between the components that can readily support the flow of signals between the components. At any given time, the conductive paths between components that are in electronic communication with (or in conductive contact with, or connected or coupled to) each other may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some cases, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0245] The term "coupled" refers to a state of moving from an open circuit relationship between components (where signals are currently unable to communicate between components via conductive paths) to a closed circuit relationship between components (where signals are able to communicate between components via conductive paths). When a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0246] The term "isolation" refers to a relationship between components where a signal is not currently able to flow between the components. If an open circuit exists between the components, then the components are isolated from each other. For example, two components separated by a switch between the components are isolated from each other when the switch is open. When a controller isolates two components, the controller affects a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0247] As used herein, the term "layer" refers to a layer or sheet of a geometric structure. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure in which two dimensions are larger than the third dimension, such as a thin film. A layer may include different elements, components, and / or materials. In some cases, a layer may be composed of two or more sub-layers. In some of the drawings, two dimensions of a three-dimensional layer are depicted for illustrative purposes. However, one skilled in the art will recognize that the layer is three-dimensional in nature.

[0248] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0249] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0250] The description set forth herein describes example configurations in conjunction with the accompanying drawings, and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "used as an example, instance, or illustration," and does not mean "preferred" or "better than other examples." In order to provide an understanding of the described techniques, the detailed description includes specific details. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0251] In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0252] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0253] Thus, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0254] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the accompanying claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be actually located at various locations, including portions that are distributed so that the functions are implemented at different physical locations. In addition, as used herein (included in the claims), as used in a list of items (e.g., a list of items followed by a phrase such as "at least one of" or "one or more of"), "or" indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be considered as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be considered in the same manner as the phrase "based at least in part on."

[0255] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special-purpose computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage, disk storage or other magnetic storage, or can be used to carry or store the desired program code device in the form of an instruction or data structure and any other non-transitory media that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. In addition, any connection can be appropriately referred to as computer-readable media. For example, if a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then the coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are all included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0256] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art without departing from the scope of the present disclosure, and the general principles defined herein may be applied to other variations. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method performed by a memory device, comprising: determining a first number of pins of a channel for receiving the one or more commands from a host device and a first number of cycles for receiving the one or more commands from the host device based at least in part on a type of the one or more commands; configuring a component coupled to the channel based at least in part on the first number of pins and the first number of cycles, the component comprising a receiver or a decoder or both; receiving a command via the channel based at least in part on configuring the component; configuring a second component coupled to the second channel based at least in part on a second number of pins of a second channel for receiving the one or more commands from the host device and a second number of cycles for the one or more commands of the second channel, the second component comprising a second receiver or a second decoder or both; and Based at least in part on configuring the second component, a second command is received over the second channel.

2. The method according to claim 1, further comprising: An indication of the first number of pins for receiving the one or more commands, or the first number of cycles for the one or more commands, or both, is received from the host device, wherein determining the first number of pins and the first number of cycles is based at least in part on the indication. 3 . The method of claim 2 , wherein receiving the indication comprises receiving a third command including the indication from the host device over the channel.

4. The method of claim 3, wherein the indication is communicated via one or more pins of the channel, the one or more pins being different from the one or more pins via which the third command is communicated.

5. The method of claim 2, wherein receiving the indication comprises receiving the indication within a memory array access command from the host device over the channel.

6. The method according to claim 2, further comprising: A determination is made that a duration from receiving the indication satisfies a lower timing threshold, wherein receiving the command occurs after the lower timing threshold is satisfied.

7. The method according to claim 1, further comprising: An initialization event for the memory device is identified, wherein determining the first number of pins and determining the first number of cycles are based at least in part on identifying the initialization event.

8. The method according to claim 1, further comprising: An operating parameter of the memory device is identified, wherein determining the first number of pins or determining the first number of cycles is based at least in part on identifying the operating parameter of the memory device.

9. The method according to claim 8, wherein: The operating parameters include a power consumption parameter associated with the memory device, a third number of commands in a buffer of the memory device that meet a criterion, or both.

10. The method of claim 1, wherein determining the first number of pins for receiving the one or more commands is based at least in part on determining the first number of cycles for the one or more commands.

11. A memory device comprising: a first receiver comprising a first plurality of pins configured to receive one or more commands over a first channel; a first decoder coupled to the first receiver and configured to decode the one or more commands received over the first channel; a register coupled to the first receiver and the first decoder and programmable to configure a width of the first channel based at least in part on a type of the one or more commands received over the first channel; a second receiver comprising a second plurality of pins configured to receive one or more second commands over a second channel; and a second decoder coupled to the second receiver and configured to decode the one or more second commands received over the second channel, wherein the register is programmable to configure a width of the second channel based at least in part on the one or more second commands received over the second channel, the register being coupled to the second receiver and the second decoder.

12. The memory device of claim 11, wherein the register is configured to determine a first number of pins of the first channel for receiving the one or more commands and is configured to determine a first number of cycles for the one or more commands.

13. The memory device of claim 11, wherein the first channel is configured to communicate row commands and the second channel is configured to communicate column commands.

14. The memory device of claim 11, wherein a first number of pins of the first channel is different from and configurable independently of a second number of pins of the second channel.

15. A method performed by a host device, comprising: determining, based at least in part on a type of one or more commands, a first number of pins of a channel configured to transmit the one or more commands to a memory device and a first number of cycles for transmitting the one or more commands to the memory device; configuring a component coupled to the channel based at least in part on the first number of pins of the channel and the first number of cycles for transmitting the one or more commands, the component comprising a driver or an encoder or both; transmitting a command to the memory device via the channel based at least in part on configuring the component; configuring a second component coupled to the second channel based at least in part on a second number of pins of the second channel for transmitting the one or more commands to the memory device and a second number of cycles for the one or more commands of the second channel, the second component comprising a second driver or a second encoder or both; and A second command is transmitted over the second channel based at least in part on configuring the second component.

16. The method according to claim 15, further comprising: An indication of the first number of pins used to transmit the one or more commands, or the first number of cycles used for the one or more commands, or both, is transmitted to the memory device.

17. The method according to claim 16, further comprising: A determination is made that a duration from transmitting the indication satisfies a lower timing threshold, wherein transmitting the command occurs after the lower timing threshold is satisfied based at least in part on determining that the duration satisfies the lower timing threshold.

18. The method of claim 15, further comprising: An operating parameter of the memory device is identified, wherein determining the first number of pins or determining the first number of cycles is based at least in part on identifying the operating parameter of the memory device.

19. The method of claim 18, wherein the operating parameter is a power consumption parameter associated with the memory device, a third number of commands in a buffer of the memory device that satisfy a criterion, or both.

20. The method of claim 15, further comprising: An activation event of the memory device is identified, wherein determining the first number of pins and determining the first number of cycles are based at least in part on identifying the activation event.

21. A host device, comprising: a first driver comprising a plurality of pins configured to transmit one or more commands over a first channel; a first encoder coupled to the first driver and configured to encode the one or more commands transmitted over the first channel; a register coupled to the first driver and the first encoder and programmable to configure a width of the first channel based at least in part on a type of the one or more commands transmitted over the first channel; a second driver comprising a plurality of pins configured to transmit one or more second commands over a second channel; and a second encoder coupled to the second driver and configured to encode the one or more second commands transmitted over the second channel, wherein the register is programmable to configure a width of the second channel based at least in part on the one or more commands transmitted over the second channel, the register being coupled to the second driver and the second encoder.

22. The host device of claim 21, wherein the register is configured to determine a first number of pins of the first channel for transmitting the one or more commands and is configured to determine a first number of cycles for the one or more commands.

Images