Dual transport orientation for stacked vertical transport field effect transistors

Abstract

A semiconductor structure comprising: a substrate; a vertical fin disposed above a top surface of the substrate; a first vertical transport field effect transistor (VTFET) disposed above the top surface of the substrate around a first portion of the vertical fin; an isolation layer disposed above the first VTFET around a second portion of the vertical fin; and a second VTFET disposed above a top surface of the isolation layer around a third portion of the vertical fin. The first portion of the vertical fin comprises a first semiconductor layer having a first crystal orientation, the first crystal orientation providing a first vertical transport channel for the first VTFET, the second portion of the vertical fin comprises an insulator, and the third portion of the vertical fin comprises a second semiconductor layer having a second crystal orientation, the second crystal orientation providing a second vertical transport channel for the second VTFET.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductors, and more specifically to techniques for forming semiconductor structures. BACKGROUND

[0002] Semiconductor and integrated circuit chips have become ubiquitous in many products, particularly because of their continued reduction in cost and size. It is continually desirable to reduce the size of structural features and / or to provide a greater number of structural features for a given chip size. In general, miniaturization allows increasing performance at lower power levels and lower cost. The technology is at or near atomic-scale scaling of certain micro devices such as logic gates, field effect transistors (FETs), and capacitors. SUMMARY

[0003] Embodiments of the present disclosure provide techniques for forming a stacked vertical transport field effect transistor having dual transport orientations.

[0004] In one embodiment, a semiconductor structure includes a substrate, at least one vertical fin disposed above a top surface of the substrate, a first vertical transport field effect transistor disposed above the top surface of the substrate around a first portion of the at least one vertical fin, an isolation layer disposed above the first vertical transport field effect transistor around a second portion of the at least one vertical fin, and a second vertical transport field effect transistor disposed above a top surface of the isolation layer around a third portion of the at least one vertical fin. The first portion of the at least one vertical fin includes a first semiconductor layer having a first crystal orientation that provides a first vertical transport channel for the first vertical transport field effect transistor. The second portion of the at least one vertical fin includes an insulator. The third portion of the at least one vertical fin includes a second semiconductor layer having a second crystal orientation that provides a second vertical transport channel for the second vertical transport field effect transistor.

[0005] In another embodiment, an integrated circuit includes a stacked vertical transfer field effect transistor structure, the stacked vertical transfer field effect transistor structure including a substrate, at least one vertical fin disposed above a top surface of the substrate, a first vertical transfer field effect transistor disposed above the top surface of the substrate around a first portion of the at least one vertical fin, an isolation layer disposed above the first vertical transfer field effect transistor and around a second portion of the at least one vertical fin, and a second vertical transfer field effect transistor disposed above the top surface of the isolation layer and around a third portion of the at least one vertical fin. The first portion of the at least one vertical fin includes a first semiconductor layer having a first crystal orientation, the first crystal orientation providing a first vertical transfer channel for the first vertical transfer field effect transistor, the second portion of the at least one vertical fin includes an insulator, and the third portion of the at least one vertical fin includes a second semiconductor layer having a second crystal orientation, the second crystal orientation providing a second vertical transfer channel for the second vertical transfer field effect transistor.

[0006] In another embodiment, a method of forming a semiconductor structure includes forming at least one vertical fin above a top surface of a substrate, forming a first vertical transfer field effect transistor (VTFET) above the top surface of the substrate surrounding a first portion of the at least one vertical fin, forming an isolation layer above the first VTFET surrounding a second portion of the at least one vertical fin, and forming a second VTFET above the top surface of the isolation layer, the second VTFET surrounding a third portion of the at least one vertical fin. The first portion of the at least one vertical fin includes a first semiconductor layer having a first crystal orientation, the first semiconductor layer providing a first vertical transfer channel for the first VTFET, the second portion of the at least one vertical fin includes an insulator, and the third portion of the at least one vertical fin includes a second semiconductor layer having a second crystal orientation, the second crystal orientation providing a second vertical transfer channel for the second VTFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Depicted is a cross-sectional view of a semiconductor-on-insulator on a semiconductor substrate, in accordance with an embodiment of the present invention.

[0008] Figure 2 Depicts the process of forming a vertical fin and bottom junction after forming the vertical fin and bottom junction according to an embodiment of the present invention. Figure 1 Cross-section of the structure.

[0009] Figure 3 Depicts a first bottom spacer, a first gate stack, and a first top spacer after forming the first bottom spacer, according to an embodiment of the present invention. Figure 2 Cross-sectional view of the structure.

[0010] Figure 4 Depicts the process of forming a first silicate glass layer and isolating spacers after forming a first silicate glass layer and isolating spacers according to an embodiment of the present invention. Figure 3 Cross-sectional view of the structure.

[0011] Figure 5 Depicted is a diagram illustrating, in accordance with an embodiment of the present invention, after forming a second silicate glass layer, a second bottom spacer, a second gate stack, a second top spacer, and a third silicate glass layer. Figure 4 Cross-sectional view of the structure.

[0012] Figure 6 Depicts the process of driving dopants from a silicate glass layer according to an embodiment of the present invention. Figure 5 Cross-sectional view of the structure.

[0013] Figure 7 Depicts an embodiment of the present invention, after depositing an interlayer dielectric. Figure 6 Cross-sectional view of the structure.

[0014] Figure 8 Depicts the second gate stack after etching down to the second silicate glass layer and forming sidewall spacers to protect the second gate stack according to an embodiment of the present invention. Figure 7 Cross-sectional view of the structure.

[0015] Figure 9 Depicts the structure after removing the second silicate glass layer and forming the contact material according to an embodiment of the present invention. Figure 8 Cross-sectional view of the structure.

[0016] Figure 10 Depicts the second gate stack after etching down to the first silicate glass layer and forming sidewall spacers to protect the second gate stack according to an embodiment of the present invention. Figure 7 Cross-sectional view of the structure.

[0017] Figure 11 Depicts, according to an embodiment of the present invention, after removing the first silicate glass layer and forming the contact material, Figure 10 Cross-sectional view of the structure.

[0018] Figure 12 Depicts a circuit diagram of a circuit after forming a first contact to the bottom junction of an upper vertical transfer field effect transistor, a second contact to the top junction of a lower vertical transfer field effect transistor, and a third contact to the top junction of an upper vertical field effect transistor, in accordance with an embodiment of the present invention. Figure 7 Cross-section of the structure.

[0019] Figure 13Described is a method of forming a shared contact to a bottom junction of an upper vertical transfer field effect transistor and a top junction of a lower vertical transfer field effect transistor according to an embodiment of the present invention. Figure 7 Cross-section of the structure.

[0020] Figure 14 Depicts the bottom junction of the lower vertical transfer field effect transistor after etching down to the bottom junction and forming sidewall spacers to protect the first and second gate stacks according to an embodiment of the present invention. Figure 7 Cross-sectional view of the structure.

[0021] Figure 15 Depicts the contact material after forming it according to an embodiment of the present invention. Figure 13 Cross-sectional view of the structure.

[0022] Figure 16 Depicts the following after forming a shared gate contact according to an embodiment of the present invention. Figure 14 Cross-sectional view of the structure. Specific embodiments

[0023] Illustrative embodiments of the present invention may be described herein in the context of illustrative methods for forming stacked vertical transfer field effect transistors having dual transfer orientations, and illustrative apparatuses, systems, and devices formed using such methods. However, it should be understood that the embodiments of the present invention are not limited to the illustrative methods, apparatuses, systems, and devices, but are more broadly applicable to other suitable methods, apparatuses, systems, and devices.

[0024] A field effect transistor (FET) is a transistor having a source, a gate, and a drain, and having a function that depends on the flow of charge carriers (electrons or holes) along a channel extending between the source and the drain. The current through the channel between the source and the drain can be controlled by a lateral electric field below the gate.

[0025] FETs are widely used for switching, amplification, filtering, and other tasks. FETs include metal oxide semiconductor (MOS) FETs (MOSFETs). Complementary MOS (CMOS) devices are widely used, in which both n-type and p-type transistors (nFETs and pFETs) are used to make logic and other circuits. The source and drain regions of a FET are typically formed by adding dopants to target regions of a semiconductor body on either side of a channel, with a gate formed over the channel. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulator material that prevents large leakage currents from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to generate a lateral electric field in the channel.

[0026] The ever-increasing demand for higher density and performance in integrated circuit devices requires the development of new structures and design features, including shrinking gate lengths and other dimensional reductions or scaling of devices. However, continued scaling is reaching the limits of conventional manufacturing technologies.

[0027] Stacking FETs in the vertical direction provides additional dimensions for CMOS area scaling. However, it is difficult to stack planar FETs. Vertical transfer FETs (VTFETs) are seen as viable CMOS architectures that can be scaled to 7 nanometers (nm) and even higher. Compared to other device architectures, VTFETs provide opportunities for further device scaling. VTFETs have potential advantages over other conventional structures, such as fin field-effect transistors (FinFETs). Such advantages can include improvements in density, performance, power consumption, and integration. VTFETs can further provide the advantages of stacked FETs.

[0028] Exemplary embodiments provide techniques for forming stacked VTFETs with favorable channel orientations. In some embodiments, a silicon-on-insulator (SOI) wafer is used to form a stacked VTFET, wherein the substrate and SOI layer have different crystal orientations. Thus, different types of stacked VTFETs (e.g., nFETs or pFETs) can be made from an SOI layer and a substrate beneath a buried oxide (BOX) insulator. The crystal orientations of the SOI and substrate beneath the BOX insulator can be selected to have nFET and pFET devices with optimized transport surfaces and orientations. Using the techniques described herein, a stacked VTFET structure can be formed in which a first type of FET (e.g., one of an nFET and a pFET) is directly on top of a second type of FET (e.g., the other of an nFET and a pFET), wherein a dielectric layer is located between the stacked VTFETs for isolation. The nFET and pFET channels can have different surfaces and transport orientations.

[0029] In some embodiments, a stacked VTFET is formed in which the upper VTFET is made of a single crystal semiconductor having a crystal orientation different from that of the lower VTFET. Such a stacked VTFET can be formed starting from an SOI wafer, wherein the bulk substrate has a first crystal orientation (e.g., (110)) and the SOI layer has a second crystal orientation different from the first crystal orientation (e.g., (100)). The SOI wafer is etched to form one or more fins of a specific thickness comprising the SOI, the BOX, and the underlying bulk silicon. A bottom junction is formed and activated for the source / drain contacts of the lower VTFET (e.g., the nFET), followed by forming a bottom spacer, a gate stack, and a top spacer for the lower VTFET. A silicate glass layer (e.g., phosphosilicate glass (PSG)) is then deposited, followed by forming an isolation layer (e.g., silicon nitride (SiN)). Next, an upper VTFET (e.g., a pFET) is formed by depositing a bottom silicate glass layer (e.g., borosilicate glass (BSG)), followed by forming a bottom spacer, a gate stack, and a top spacer for the upper VTFET. A top silicate glass layer is formed over the top spacer of the upper VTFET. A dopant drive-in anneal is performed to dope the bottom and top junctions or source / drain regions of the upper and lower VTFETs in the stack. An interlayer dielectric (ILD) is then deposited.

[0030] The ILD and lower layer are then patterned and etched to form contacts for the upper VTFET and the lower VTFET. In some embodiments, the ILD layer is patterned and formed into an opening to the bottom silicate glass layer of the upper VTFET. Sidewall spacers are formed to protect the gate stack of the upper VTFET. The bottom silicate glass layer of the upper VTFET is then removed and refilled with contact material, the contact material wrapping around the bottom junction or source / drain of the upper VTFET. The ILD can also be patterned and etched down to the silicate glass layer of the lower VTFET (e.g., the silicate glass layer surrounding the top junction or source / drain region of the lower VTFET). The silicate glass layer of the lower VTFET can then be removed and refilled with contact material, the contact material surrounding the top junction or source / drain of the lower VTFET. In some embodiments, the ILD can be patterned and etched down to form a shared contact between the bottom junction or source / drain of the upper VTFET and the top junction or source / drain of the lower VTFET. The ILD can be further patterned to form openings to the top junction or source / drain of the upper VTFET and complete the remaining contacts to the bottom junction or source / drain of the lower VTFET and to the gate stacks of the upper and lower VTFETs. As a result, stacked VTFET devices are formed with different channel or transfer orientations.

[0031] Now about Figure 1-16An exemplary process for forming a stacked VTFET structure having a bidirectional transmission orientation is described.

[0032] Figure 1 A cross-sectional view 100 is shown of a bulk substrate 102, an insulating layer 104 formed on the bulk substrate 102, and a semiconductor layer 106 formed on the insulating layer 104. The semiconductor layer 106 and the insulator 104 may form a thin BOXSOI.

[0033] The bulk substrate 102 and the semiconductor layer 106 can be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials can be used as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like.

[0034] Figure 1 The horizontal thickness or width (in direction XX") of the structure may vary, such as based on the number of fins to be formed therefrom, as described in further detail below. Figure 1 The vertical thickness or height (in direction YY") of the structures may be in the range of 100 nm to 500 nm, although other heights above or below this range may be used as desired for a particular application.

[0035] The bulk substrate 102 and the semiconductor layer 106 have different crystal orientations, which are suitable for forming different types of VTFET devices (e.g., nFET and pFET). Figure 1 The structure is used to form a stacked VTFET structure in which the lower VTFET is an nFET device and the upper VTFET is a pFET device. It is also assumed that the substrate 102 and the semiconductor layer 106 are both formed of silicon, although as described above, this is not required. The substrate 102 has a first crystal orientation (110) suitable for the formation of nFET devices, and the semiconductor layer 106 has a second crystal orientation (100) suitable for the formation of pFET devices. However, it should be understood that in order to form a stacked VTFET structure in which the lower VTFET is a pFET device and the upper VTFET is an nFET device, the crystal orientations can be reversed (e.g., wherein the substrate 102 has a crystal orientation of (100) and the semiconductor layer 106 has a crystal orientation of (110)).

[0036] For clarity of illustration, the VTFET structure is shown and described with respect to forming a stack having only two VTFETs stacked vertically (e.g., in direction YY”). Figure 1-16However, in other embodiments, the stacked VTFET structure can include three or more vertically stacked VTFETs. Further, while described with respect to stacking one type of VTFET on top of another type of VTFET (e.g., where the upper VTFET is a pFET device and the lower VTFET is an nFET device) Figure 1-16 embodiments are not limited thereto. For example, the upper and lower VTFETs can both be nFET devices or pFET devices. Further, the stacked VTFETs can include any number of nFET devices formed on top of any number of pFET devices as desired for a particular application.

[0037] Figure 2 A cross-sectional view 200 of the structure after forming vertical fins from at least a portion of the semiconductor layer 106, the insulator layer 104, and the substrate 102 is shown. Figure 1 The vertical fins can be formed using sidewall image transfer (SIT) or other suitable techniques (e.g., lithography and etching including reactive ion etching (RIE), etc.). As shown, a hard mask layer (HM) 108 is patterned over a top surface of the semiconductor layer 106.

[0038] The HM 108 can be formed of nitride (e.g., SiN), although other suitable materials can be used. In some embodiments, the HM 108 can be formed as a multi-layer, such as a multi-layer including two layers of nitride and oxide (e.g., SiN and silicon dioxide (Si02), a three-layer multi-layer including one or more layers of nitride and one or more layers of oxide (e.g., SiN / Si02 / SiN, Si02 / SiN / Si02), etc. The HM 108 can have a height or vertical thickness (in direction Y-Y”) in a range of 10 nm to 100 nm, although other heights above or below this range can be used as desired for a particular application.

[0039] The vertical fins can have a width or horizontal thickness (in direction X-X”) in a range of 6 nm to 10 nm, although other widths above or below this range can be used as desired for a particular application. The vertical fins can have a height or vertical thickness (in direction Y-Y”) ranging from 60 nm to 400 nm, although other heights above or below this range can be used as desired for a particular application.

[0040] Although for illustrative clarity, Figure 2 only a single vertical fin formed from Figure 1 the structure is shown, it should be understood that multiple vertical fins can be formed from Figure 1 the structure to form multiple stacked VTFET structures.

[0041] Although Figure 2 Not shown, an interface layer may be formed on the sidewalls of the vertical fins. The interface layer may be formed of SiO2 or another suitable material such as silicon oxynitride (SiOxNy). The interface layer may have a width or horizontal thickness (in direction XX") ranging from 0.5 nm to 1.5 nm, although other widths above or below this range may be used as desired for a specific application.

[0042] Figure 2 The structure also shows the formation of the bottom junction or bottom source / drain region 110. The bottom source / drain region 110 can be formed, for example, by implanting suitable dopants, such as using ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, etc. N-type dopants can be selected from the group of phosphorus (P), arsenic (As) and antimony (Sb), and P-type dopants can be selected from the group of boron (B), boron fluoride (BF2), gallium (Ga), indium (In) and thallium (Tl). The bottom source / drain region 110 can also be formed by an epitaxial growth process. In some embodiments, the epitaxial process includes in situ doping (incorporating dopants into the epitaxial material during epitaxy). The epitaxial material can be grown from a gaseous or liquid precursor. The epitaxial material may be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD), limited reaction process CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and / or carbon-doped silicon (Si:C) silicon may be doped during deposition by adding dopants (in situ doping), such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor. The dopant concentration may be in the range of 1x10 19 cm -3 Up to 3x10 21 cm -3 in the range of, or preferably in the range of 2x10 20 cm -3 Up to 3x10 21 cm -3 between.

[0043] In some embodiments, it is assumed that the bottom junction is formed via ion implantation (e.g., BF2+ or P+ with an energy of 5 keV and a dose of 2e15 for pFET and nFET, respectively). After implantation, an activation anneal (e.g., a spike rapid thermal anneal (RTA) at 1000° C.) may be performed.

[0044] The bottom source / drain region 110 may have a height or vertical thickness (in direction YY″) in the range of 20 nm to 50 nm, although other heights above or below this range may be used as desired for a particular application.

[0045] Figure 3 The bottom spacer 112, gate stack 114 and top spacer 116 are shown after forming Figure 2 Cross-sectional view 300 of the structure.

[0046] The bottom spacer 112 and the top spacer 116 may each be formed using various processes such as non-conformal deposition and etch-back processes (e.g., physical vapor deposition (PVD), high density plasma (HDP) deposition, etc.). The bottom spacer 112 and the top spacer 116 may be formed of SiO2, SiN, silicon carbide oxide (SiCO), silicon carbide boron nitride (SiBCN), etc., although other suitable materials may be used. The bottom spacer 112 and the top spacer 116 may each have a height or vertical thickness in the range of 4 nm to 10 nm (in direction YY"), although other heights above or below this range may be used as desired for a particular application.

[0047] The gate stack 114 includes a gate dielectric disposed near the sidewalls of the vertical fin and a gate conductor formed over the gate dielectric. The gate dielectric may be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide (HfO2), hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl2O3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric may have a uniform thickness in the range of 1 nm to 3 nm, although other thicknesses above or below this range may be used as desired for a particular application.

[0048] The gate conductor may include a metal gate or a work function metal (WFM). In some embodiments, the gate conductor is formed using atomic layer deposition (ALD) or another suitable process. For nFET devices, the WFM used for the gate conductor may be titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), a combination of Ti and Al alloys, a stack including a barrier layer (e.g., TiN or another suitable material) followed by one or more of the aforementioned WFM materials, etc. For pFET devices, the WFM used for the gate conductor may be TiN, TaN, or another suitable material. In some embodiments, the pFET WFM may include a metal stack in which a thicker barrier layer (e.g., made of TiN, TaN, etc.) is formed, followed by a WFM such as Ti, Al, TiAl, TiAlC, or any combination of Ti and Al alloys. It should be understood that various other materials may be used for the gate conductor as desired.

[0049] The gate stack 114 may have a height or vertical thickness in the range of 10 nm to 20 nm (in direction YY″), although other thicknesses above or below this range may be used as desired for a particular application.

[0050] Figure 4 shows the structure after forming the silicate glass layer 118 and the isolation spacer 120. Figure 3 Cross-sectional view 400 of the structure. As described above, it is assumed that the lower or bottom VTFET is an nFET device, and therefore the silicate glass layer 118 can be phosphosilicate glass (PSG) 118, so that during the dopant drive-in, n-type dopants are formed in the vertical fin to form the top junction or top source / drain region of the lower VTFET. It should be understood that if the lower VTFET is a pFET device, the type of silicate glass can be changed (for example, borosilicate glass (BSG) can be used instead of PSG). Further, other types of silicate glass can be used instead of BSG and / or PSG, so that other dopants can be driven into the vertical fin to form the top junction or top source / drain region for the lower VTFET.

[0051] The PSG layer 118 may be deposited using any suitable technique, such as chemical vapor deposition (CVD), although other thicknesses above or below this range may be used as desired for a particular application. The PSG layer 118 may have a height or vertical thickness (in direction YY") in the range of 10 nm to 30 nm.

[0052] An isolation layer 120 is formed on the PSG layer 118. The isolation layer 120 may be deposited using any suitable technique, such as gas cluster ion beam (GCIB) directional deposition. The isolation layer 120 serves to isolate the lower VTFET from the upper VTFET formed around the vertical fin. As described above, in some embodiments, it is assumed that the lower VTFET is an nFET device and the upper VTFET is a pFET device, and therefore the isolation layer 120 provides an np isolation spacer. The isolation layer 120 may be formed of silicon nitride (SiNx) or other suitable material. The isolation layer 120 may have a height or vertical thickness (in direction YY") ranging from 20 nm to 50 nm, although other thicknesses above or below this range may be used as desired for a specific application.

[0053] Figure 5 1 shows the structure after forming silicate glass layer 122, bottom spacer 124, gate stack 126, top spacer 128 and silicate glass layer 130. Figure 4 500 of a cross-sectional view of the structure. As described above, in some embodiments, it is assumed that the upper VTFET is a pFET device, and therefore the silicate glass layers 122 and 124 can be formed of BSG and are also referred to herein as bottom BSG layer 122 and top BSG layer 124. If the upper VTFET is an nFET device, then layers 122 and 124 can be PSG as described above or another suitable material. Bottom BSG layer 122 and top BSG layer 124 can each have a height or vertical thickness (in direction YY") similar to the height or vertical thickness of PSG layer 118.

[0054] The bottom spacer 124 and the top spacer 128 can be formed of similar materials, with similar dimensions, and using similar processes as described above with respect to the bottom spacer 112 and the top spacer 116. The gate stack 126 can be formed of similar materials, with similar dimensions, and using similar processes as described above with respect to the gate stack 114.

[0055] Figure 6 Shown after driving dopants from silicate glass layers 118, 122, and 130 Figure 5 A cross-sectional view 600 of the structure is provided to form a top junction or top source / drain region 132 for the lower VTFET, a bottom junction or bottom source / drain region 134 for the upper VTFET, and a top junction or top source / drain region 136 for the upper VTFET, respectively. The dopant drive-in process may include a rapid thermal anneal (RTA) at a temperature in the range of 900° C. to 1200° C. Figure 6As shown, the dopant drive-in may also cause the doped region 110 at the bottom of the fin to become higher as the dopant in the doped region 110 may diffuse upward during the drive-in anneal.

[0056] The type of silicate glass used in layers 118, 122, and 130 is selected to form the appropriate type of junction. As shown, when the lower VTFET is assumed to be an nFET device, the silicate glass layer 118 is PSG, and n-type dopants P+ are driven into the vertical fin to form top source / drain regions 132 for the lower VTFET. As shown, since the upper VTFET is assumed to be a pFET device, the silicate glass layers 122 and 130 are BSG, and p-type dopants B+ are driven into the vertical fins to form bottom source / drain regions 134 and top source / drain regions 136, respectively.

[0057] Figure 7 shows the top BSG layer 130 after removal and after formation of the ILD 138. Figure 6 Cross-sectional view 700 of the structure. ILD 138 may be formed of any suitable insulating material, such as SiO 2 , SiOC, SiON, etc. ILD 138 may have a height or vertical thickness (in direction YY″) in the range of 40 nm to 200 nm, although other thicknesses above or below this range may be used as long as ILD 138 fully encapsulates HM 108.

[0058] Figure 8-16 shows the method for forming Figure 7 More specifically, Figure 8 and Figure 9 The formation of contacts to the bottom source / drain region 134 of the upper VTFET is shown.

[0059] Figure 8 The bottom BSG layer 122 is shown after etching (e.g., using RIE) down to the bottom BSG layer 122. Figure 7 800 is a cross-sectional view of the structure. This etching can be achieved by appropriately masking and exposing the top surface of ILD 138. After etching, sidewall spacers 140 are formed. Sidewall spacers 140 protect gate stack 126. Sidewall spacers 140 can be formed of SiN, SiBCN, silicon oxycarbonitride (SiOCN), or another suitable material using ALD followed by a directional etch. Sidewall spacers 140 can have a width or horizontal thickness (in direction XX") ranging from 4 nm to 10 nm.

[0060] Figure 9A cross-sectional view 900 of the structure is shown after removal of the bottom BSG layer 122 and after deposition or formation of contact material to form bottom source / drain contacts 142 for the upper VTFET. Figure 8 As shown, the bottom source / drain contacts 142 wrap around portions of the vertical fin that provide the bottom junction or bottom source / drain region 134. The contact material can be formed using any suitable deposition process, such as PVD, CVD, ALD, etc. The contact material can include tungsten (W), Ti, TiN, Ti / TiN, Ti / TiN plus cobalt (Co), etc.

[0061] Figure 10 and Figure 11 processing similar to that of Figure 8 and Figure 9 but to form contacts to the top junction or top source / drain region 132 of the lower VTFET. Figure 10 A cross-sectional view 1000 of the structure is shown after etching (e.g., using RIE) down to the PSG layer 118. After the etching, a sidewall spacer 144 is formed to protect the gate stack 126. The sidewall spacer 144 can be formed of similar materials, in similar dimensions, and using similar processes as described above with respect to the sidewall spacer 140. Figure 7

[0062] A cross-sectional view 1100 of the structure of Figure 11 is shown after removal of the PSG layer 118 and after deposition or formation of contact material to form top source / drain contacts 146 for the lower VTFET. The top source / drain contacts 146 can be formed of similar materials, in similar dimensions, and using similar processes as described above with respect to the contacts 142. Figure 10

[0063] A cross-sectional view 1200 of the structure is shown after formation of the top and bottom source / drain contacts for the upper VTFET and formation of the top source / drain contacts for the lower VTFET. Figure 12 A cross-sectional view 1200 of the structure is shown after formation of the sidewall spacer 140 as shown and described above with respect to Figure 12 and the bottom source / drain contacts 142 for the upper VTFET, the sidewall spacer 144, and the top source / drain contacts 146 for the lower VTFET. Figure 8-11 Figure 7 Figure 12 ​​Formation of top source / drain contacts 148 for the upper VTFET is further shown. Top source / drain contacts 148 for the upper VTFET can be formed by patterning and etching ILD 138, removing HM 108, and depositing a contact material. Top source / drain contacts 148 can be formed of similar materials as described above with respect to contacts 142.

[0064] It should be understood that, Figure 12 The contact arrangements shown in Figure 12 While the arrangement in which separate contacts 142 and 146 are formed to bottom source / drain regions 134 of the upper VTFET and to top source / drain regions 132 of the lower VTFET is shown, this is not necessary. In some embodiments, as Figure 13 shown in FIG. 1 1 1, a shared contact is formed to both bottom source / drain regions 134 of the upper VTFET and to top source / drain regions 132 of the lower VTFET.

[0065] Figure 13 A cross-sectional view 1300 of the structure after etching down to PSG layer 1 18 and forming sidewall spacers 140 is shown. Figure 7 Figure 13 Removal of PSG layer 1 18 and bottom BSG layer 122, and deposition of a contact material to form a shared contact 143 between bottom source / drain regions 134 of the upper VTFET and top source / drain regions 132 of the lower VTFET is also shown.

[0066] Figure 14-16 Formation of contacts to bottom source / drain regions 1 10 of the lower VTFET and formation of a shared gate contact to gate stacks 1 14 and 126 is shown. While the above Figure 1-13 is a cross-sectional view taken "across" the vertical fin, Figure 14-16 a cross-sectional view taken "along" the length of the fin is shown.

[0067] Figure 14 A cross-sectional view 1400 of the structure after etching down to bottom source / drain regions 1 10 of the lower VTFET away from the edge of the vertical fin (e.g., a distance away from the end edge of the vertical fin in direction Z-Z', which is perpendicular to direction X-X' of FIG. 1 1 1 ) is shown. Sidewall spacers 150 are formed to protect gate stacks 1 14 and 126. Sidewall spacers 150 can be formed of similar materials, in similar dimensions, and using similar processes as described above with respect to sidewall spacers 140. Figures 1 to 13 Figure 7

[0068] Figure 15 ​​​Shown after depositing or forming contact material to form bottom source / drain contacts 152 for the lower VTFET Figure 14 Cross-sectional view of the structure 1500. Bottom source / drain contacts 152 may be formed of similar materials as contacts 142 described above.

[0069] Figure 16 shows the shared gate contact 154 after formation. Figure 15 1600 is a cross-sectional view of a structure of FIG. 1600. A shared gate contact 154 is formed by patterning an opening and etching down to the gate stack 114, followed by deposition of contact material. The shared gate contact 154 can be formed of similar materials as the contact 142. Sidewall spacers 156 and 158 are also shown, which prevent the shared gate contact 154 from shorting the top source / drain contacts of the lower VTFET and the bottom source / drain contacts of the upper VTFET. Alternatively, the PSG layer 118 and the BSG layer 122 can be patterned in such a way that they are removed from the gate contact area and become a dielectric instead, thereby ensuring that shorting does not occur. The sidewall spacers 156 and 158 can be formed of similar materials, with similar dimensions, and using similar processes as described above with respect to the sidewall spacer 140. Similar to the bottom source / drain contacts 152 of the lower VTFET, the shared gate contact 154 is formed (in direction ZZ") a distance away from the end of the vertical fin (opposite the end where the bottom source / drain contacts 152 for the lower VTFET are formed).

[0070] In some embodiments, a semiconductor structure includes a substrate, at least one vertical fin disposed above a top surface of the substrate, a first VTFET disposed above the top surface of the substrate and surrounding a first portion of the at least one vertical fin, an isolation layer disposed above the first VTFET and surrounding a second portion of the at least one vertical fin, and a second VTFET disposed above a top surface of the isolation layer and surrounding a third portion of the at least one vertical fin. The first portion of the at least one vertical fin includes a first semiconductor layer having a first crystal orientation, the first semiconductor layer providing a first vertical transfer channel for the first VTFET, the second portion of the at least one vertical fin includes an insulator, and the third portion of the at least one vertical fin includes a second semiconductor layer having a second crystal orientation, the second semiconductor layer providing a second vertical transfer channel for the second VTFET.

[0071] The first crystal orientation may provide a first vertical transfer orientation for one of the nFET and the pFET, and the second crystal orientation may provide a vertical transfer orientation for the other of the nFET and the pFET.

[0072] The first semiconductor layer may include silicon having one of a (110) crystal orientation and a (100) crystal orientation, and the second semiconductor layer may include silicon having the other of the (110) crystal orientation and the (100) crystal orientation.

[0073] The semiconductor structure may further include a first bottom source / drain region for a first VTFET, the first bottom source / drain region including a doped region adjacent to a top surface of the substrate and a doped region of a first portion of the first semiconductor layer adjacent to the top surface of the substrate; a first bottom spacer disposed above the top surface of the substrate and surrounding the first portion of the first semiconductor layer; a first gate stack disposed above a top surface of the first bottom spacer and surrounding a second portion of the first semiconductor layer; a first top spacer disposed above a top surface of the first gate stack and surrounding a third portion of the first semiconductor layer; and a first top source / drain contact for the first VTFET, the first top source / drain contact disposed above a top surface of the first top spacer and surrounding a fourth portion of the first semiconductor layer. The third portion of the first semiconductor layer and the fourth portion of the first semiconductor layer are doped to provide a first top source / drain region for the first VTFET.

[0074] The semiconductor structure may further include a second bottom source / drain contact for a second VTFET, the second bottom source / drain contact being disposed above the top surface of the isolation layer and surrounding a first portion of the second semiconductor layer; a second bottom spacer being disposed above the top surface of the second bottom source / drain contact and surrounding a second portion of the second semiconductor layer; a second gate stack being disposed above the top surface of the second bottom spacer and surrounding a third portion of the second semiconductor layer; and a second top spacer being disposed above the top surface of the second gate stack and surrounding a fourth portion of the second semiconductor layer. The first portion of the second semiconductor layer and the second portion of the semiconductor layer are doped to provide a second bottom source / drain region for the second VTFET. The fourth portion of the second semiconductor layer and a fifth portion of the second semiconductor layer disposed above the fourth portion of the second semiconductor layer are doped to provide a second top source / drain region for the second VTFET.

[0075] The semiconductor structure may further include a second top / source-drain contact for a second VTFET, the second top / source-drain contact surrounding a fifth portion of the second semiconductor layer and disposed above the top surface of the second semiconductor layer; and an interlayer dielectric disposed above the second top spacer and surrounding the second top / source-drain contact.

[0076] The semiconductor structure may further include a first sidewall spacer having a first vertical surface disposed adjacent to a first sidewall of the interlayer dielectric, a second top spacer, a second gate stack, and a second bottom spacer, wherein the second bottom source / drain contact is further disposed adjacent to the second vertical surface of the first sidewall spacer. The semiconductor structure may further include a second sidewall spacer having a first vertical surface disposed adjacent to a second sidewall of the interlayer dielectric, a second top spacer, a second gate stack, a second bottom spacer, and an isolation layer, wherein the first top source / drain contact is further disposed adjacent to the second vertical surface of the second sidewall spacer.

[0077] The semiconductor structure may further include a first sidewall spacer having a first vertical surface disposed adjacent to a first sidewall of the interlayer dielectric, a second top spacer, a second gate stack, and a second bottom spacer, wherein the first top source / drain contact and the second bottom source / drain contact include a shared contact disposed adjacent to the second vertical surface of the first sidewall spacer and adjacent to a first edge of the isolation layer.

[0078] The semiconductor structure may also include: a first sidewall spacer, the first sidewall spacer having a first vertical surface spaced apart from the first end of the at least one vertical fin, and arranged adjacent to the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the isolation layer, the first top spacer, the first gate stack and the first end of the first bottom spacer, and a first bottom source / drain contact for the first VTFET, the first bottom source / drain contact being arranged above the top surface of the substrate and adjacent to the second vertical surface of the first sidewall spacer.

[0079] The semiconductor structure may also include a shared gate contact to the first gate stack and the second gate stack disposed in the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer and the first top spacer, the shared gate contact being spaced apart from the second end of the at least one vertical fin.

[0080] In some embodiments, an integrated circuit includes a stacked VTFET structure comprising a substrate, at least one vertical fin disposed above a top surface of the substrate, a first VTFET disposed above the top surface of the substrate and surrounding a first portion of the at least one vertical fin, an isolation layer disposed above the first VTFET and surrounding a second portion of the at least one vertical fin, and a second VTFET disposed above the top surface of the isolation layer and surrounding a third portion of the at least one vertical fin. The first portion of the at least one vertical fin includes a first semiconductor layer having a first crystal orientation, the first semiconductor layer providing a first vertical transfer channel for the first VTFET, the second portion of the at least one vertical fin includes an insulator, and the third portion of the at least one vertical fin includes a second semiconductor layer having a second crystal orientation, the second semiconductor layer providing a second vertical transfer channel for the second VTFET.

[0081] The first crystal orientation may provide a first vertical transfer orientation for one of the nFET and the pFET, and the second crystal orientation may provide a vertical transfer orientation for the other of the nFET and the pFET.

[0082] The first semiconductor layer may include silicon having one of a (110) crystal orientation and a (100) crystal orientation, and the second semiconductor layer may include silicon having the other of the (110) crystal orientation and the (100) crystal orientation.

[0083] In some embodiments, a method of forming a semiconductor structure includes forming at least one vertical fin above a top surface of a substrate, forming a first VTFET above the top surface of the substrate surrounding a first portion of the at least one vertical fin, forming an isolation layer above the first VTFET surrounding a second portion of the at least one vertical fin, and forming a second VTFET above the top surface of the isolation layer surrounding a third portion of the at least one vertical fin. The first portion of the at least one vertical fin includes a first semiconductor layer having a first crystal orientation, the first semiconductor layer providing a first vertical transfer channel for the first VTFET, the second portion of the at least one vertical fin includes an insulator, and the third portion of the at least one vertical fin includes a second semiconductor layer having a second crystal orientation, the second crystal orientation providing a second vertical transfer channel for the second VTFET.

[0084] The first crystal orientation may provide a first vertical transfer orientation for one of the nFET and the pFET, and the second crystal orientation may provide a vertical transfer orientation for the other of the nFET and the pFET.

[0085] The first semiconductor layer may include silicon having one of a (110) crystal orientation and a (100) crystal orientation, and the second semiconductor layer may include silicon having the other of the (110) crystal orientation and the (100) crystal orientation.

[0086] Forming the at least one vertical fin may include patterning a hard mask over a layered stack including a first semiconductor layer, an insulator, and a second semiconductor layer; and etching exposed portions of the layered stack to form the at least one vertical fin.

[0087] The method may further include: forming a doped region adjacent to a top surface of the substrate and in a first portion of the first semiconductor layer, wherein the doped region provides a first bottom source / drain region for the first VTFET; forming a first bottom spacer over the top surface of the substrate and surrounding the first portion of the first semiconductor layer; forming a first gate stack over a top surface of the first bottom spacer and surrounding a second portion of the first semiconductor layer; forming a first top spacer over a top surface of the first gate stack and surrounding a third portion of the first semiconductor layer; forming a first silicate glass layer over a top surface of the first top spacer and surrounding a fourth portion of the first semiconductor layer; and forming an isolation layer over the first silicate glass layer and surrounding the insulator of the at least one vertical fin. The first silicate glass layer includes one of an n-type dopant material and a p-type dopant material.

[0088] The method may further include: forming a second silicate glass layer on a top surface of the isolation layer and surrounding a first portion of the second semiconductor layer, forming a second bottom spacer on a top surface of the second silicate glass layer and surrounding a second portion of the second semiconductor layer; forming a second gate stack over a top surface of the second bottom spacer and surrounding a third portion of the second semiconductor layer; forming a second top spacer over a top surface of the second gate stack and surrounding a fourth portion of the second semiconductor layer; and forming a third silicate glass layer over a top surface of the second top spacer and surrounding a fifth portion of the second semiconductor layer. The second silicate glass layer and the third silicate glass layer include the other of an n-type dopant material and a p-type dopant material.

[0089] The method may further include performing a dopant drive-in to drive dopants from the first, second, and third silicate glass layers to form: a first top source / drain region for the first VTFET in the third portion of the first semiconductor layer and the fourth portion of the first semiconductor layer, a second bottom source / drain region for the second VTFET in the first portion of the second semiconductor layer and the second portion of the second semiconductor layer, and a second top source / drain region for the second VTFET in the fourth portion of the second semiconductor layer, the fifth portion of the second semiconductor layer, and the sixth portion of the second semiconductor layer above the fifth portion of the second semiconductor layer.

[0090] The method may further include removing the third silicate glass layer and forming an interlayer dielectric over the second top spacer and encapsulating the fifth portion of the second semiconductor layer, the sixth portion of the second semiconductor layer, and the hard mask over the sixth portion of the second semiconductor layer.

[0091] The method may further include: etching the interlayer dielectric, the second top spacer, the second gate stack, and a first portion of the second bottom spacer apart from a first sidewall of the at least one vertical fin; forming a first sidewall spacer adjacent to edges of the etched first portion of the interlayer dielectric, the second top spacer, the second gate stack, and the second bottom spacer; removing the second silicate glass layer; depositing a contact material to form a second bottom source / drain contact for a second VTFET, the second top source / drain contact wrapping around a first portion of the second semiconductor layer exposed by removing the second silicate glass layer; etching the interlayer dielectric, the second top spacer, the second gate stack, and the second bottom spacer; and forming a second sidewall spacer adjacent to edges of the etched first portion of the interlayer dielectric, the second top spacer, the second gate stack, and the second bottom spacer. The invention also provides for forming a first top source / drain contact for a first VTFET, wherein the first top source / drain contact is wrapped around a fourth portion of the first semiconductor layer exposed by removing the first silicate glass layer.

[0092] The method may also include: etching the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second silicate glass layer, and the first portion of the isolation layer to separate them from the first sidewall of at least one vertical fin; forming a first sidewall spacer adjacent to the edge of the etched first portion of the interlayer dielectric, the second top spacer, the second gate stack, and the second bottom spacer; removing the second silicate glass layer and the first silicate glass layer; and depositing a contact material to form a shared contact to the second bottom source / drain region of the second VTFET and the first top source / drain region of the first VTFET, the shared contact wrapping around the first portion of the second semiconductor layer and the fourth portion of the first semiconductor layer exposed by removing the second silicate glass layer and the first silicate glass layer.

[0093] The method may further include: etching the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second silicate glass layer, the isolation layer, the first silicate glass layer, the first top spacer, the first gate stack, and a portion of the first bottom spacer to expose a portion of the top surface of the substrate spaced apart from the first end of the at least one vertical fin; and forming a sidewall spacer having a first vertical surface, the second top spacer, the second gate stack, the second bottom spacer, the second silicate glass layer, the isolation layer, the first silicate glass layer, the first top spacer, the first gate stack, and the first bottom spacer at the etched edge of the interlayer dielectric. spacer; depositing a contact material to form a first bottom source / drain region contact to the first bottom source / drain region of the first VTFET above the exposed top surface of the substrate adjacent the second vertical surface of the sidewall spacer; etching portions of the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second silicate glass layer, the isolation layer, the first silicate glass layer, and the first top spacer to form an exposed portion spaced apart from the second end of the at least one vertical fin; and depositing a contact material in the exposed portion to form a shared gate contact to the first gate stack of the first VTFET and the second gate stack of the second VTFET.

[0094] It should be understood that the different materials, processing methods (eg, etching type, deposition type, etc.), and dimensions provided in the above discussion are presented by way of example only. Various other suitable materials, processing methods, and dimensions may be used as desired.

[0095] Semiconductor devices and methods for forming the same according to the above-mentioned techniques can be used in different applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, sensors, sensing devices, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smart phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware comprising semiconductor devices are embodiments contemplated by the present invention. Given the teachings provided herein, one of ordinary skill in the art will be able to conceive of other implementations and applications of embodiments of the present invention.

[0096] The various structures described above can be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer having many unpackaged chips), as bare dies, or in a packaged form. In the latter case, the chips are mounted in single chip packages (such as plastic carriers, with leads for interconnection to a motherboard or other higher level carrier) or multiple chip packages (such as ceramic carriers that have one or more wafers) with the leads connected to a motherboard or other higher level carrier. In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of the product design. The product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

[0097] The description of the different embodiments of the application has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: substrate; at least one vertical fin disposed above a top surface of the substrate; a first vertical transfer field effect transistor disposed above the top surface of the substrate surrounding a first portion of the at least one vertical fin; an isolation layer disposed above the first vertical transfer field effect transistor and surrounding a second portion of the at least one vertical fin; as well as a second vertical transfer field effect transistor disposed above the top surface of the isolation layer surrounding a third portion of the at least one vertical fin; wherein the first portion of the at least one vertical fin comprises a first semiconductor layer having a first crystal orientation, the first crystal orientation providing a first vertical transfer channel for the first vertical transfer field effect transistor; wherein the second portion of the at least one vertical fin comprises an insulator; and wherein the third portion of the at least one vertical fin comprises a second semiconductor layer having a second crystal orientation, the second crystal orientation providing a second vertical transfer channel for the second vertical transfer field effect transistor; a first bottom source / drain region for the first vertical transfer field effect transistor, the first bottom source / drain region comprising a doped region adjacent the top surface of the substrate and a doped region of a first portion of the first semiconductor layer adjacent the top surface of the substrate; a first bottom spacer disposed over the top surface of the substrate and surrounding the first portion of the first semiconductor layer; a first gate stack disposed over a top surface of the first bottom spacer and surrounding a second portion of the first semiconductor layer; a first top spacer disposed over a top surface of the first gate stack and surrounding a third portion of the first semiconductor layer; as well as a first top source / drain contact for the first vertical transfer field effect transistor, the first top source / drain contact disposed above a top surface of the first top spacer and surrounding a fourth portion of the first semiconductor layer; The third portion of the first semiconductor layer and the fourth portion of the first semiconductor layer are doped to provide a first top source / drain region for the first vertical transfer field effect transistor.

2. The semiconductor structure of claim 1 , wherein the first crystal orientation provides a first vertical transfer orientation for one of an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET), and wherein the second crystal orientation provides a vertical transfer orientation for the other of the nFET and the pFET.

3. The semiconductor structure of claim 1 , wherein the first semiconductor layer comprises silicon having one of a (110) crystal orientation and a (100) crystal orientation, and wherein the second semiconductor layer comprises silicon having the other of the (110) crystal orientation and the (100) crystal orientation.

4. The semiconductor structure of claim 1 , further comprising: a second bottom source / drain contact for the second vertical transfer field effect transistor, the second bottom source / drain contact being disposed above the top surface of the isolation layer and surrounding a first portion of the second semiconductor layer; a second bottom spacer disposed over a top surface of the second bottom source / drain contact and surrounding a second portion of the second semiconductor layer; a second gate stack disposed over a top surface of the second bottom spacer and surrounding a third portion of the second semiconductor layer; as well as a second top spacer disposed over a top surface of the second gate stack and surrounding a fourth portion of the second semiconductor layer; wherein the first portion of the second semiconductor layer and the second portion of the second semiconductor layer are doped to provide a second bottom source / drain region for the second vertical transfer field effect transistor; and The fourth portion of the second semiconductor layer and a fifth portion of the second semiconductor layer disposed above the fourth portion of the second semiconductor layer are doped to provide a second top source / drain region for the second vertical transfer field effect transistor.

5. The semiconductor structure of claim 4, further comprising: a second top / source-drain contact for the second vertical transfer field effect transistor, the second top / source-drain contact surrounding the fifth portion of the second semiconductor layer and disposed above a top surface of the second semiconductor layer; as well as An interlayer dielectric is disposed over the second top spacer and surrounding the second top / source / drain contact.

6. The semiconductor structure of claim 5 , further comprising a first sidewall spacer having a first vertical surface disposed adjacent to the first sidewall of the interlayer dielectric, a second top spacer, a second gate stack, and a second bottom spacer, wherein the second bottom source / drain contact is further disposed adjacent to the second vertical surface of the first sidewall spacer.

7. The semiconductor structure of claim 6 , further comprising a second sidewall spacer having a first vertical surface disposed adjacent to a second sidewall of the interlayer dielectric, a second top spacer, a second gate stack, a second bottom spacer, and the isolation layer, wherein the first top source / drain contact is further disposed adjacent to a second vertical surface of the second sidewall spacer.

8. The semiconductor structure of claim 5 , further comprising a first sidewall spacer having a first vertical surface disposed adjacent to a first sidewall of the interlayer dielectric, a second top spacer, a second gate stack, and a second bottom spacer, wherein the first top source / drain contact and the second bottom source / drain contact comprise a shared contact disposed adjacent to a second vertical surface of the first sidewall spacer and adjacent to a first edge of the isolation layer.

9. The semiconductor structure of claim 5, further comprising: a first sidewall spacer having a first vertical surface spaced apart from the first end of the at least one vertical fin and disposed adjacent to the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the isolation layer, the first top spacer, the first gate stack, and the first end of the first bottom spacer; as well as A first bottom source / drain contact for the first vertical transfer field effect transistor is disposed above the top surface of the substrate and adjacent to the second vertical surface of the first sidewall spacer.

10. The semiconductor structure of claim 9 further comprises a shared gate contact to the first gate stack and the second gate stack disposed in the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, and the first top spacer, the shared gate contact being spaced apart from the second end of the at least one vertical fin.

11. An integrated circuit comprising the semiconductor structure according to any one of claims 1 to 10.

12. A method of forming a semiconductor structure, comprising: forming at least one vertical fin above a top surface of the substrate; forming a first vertical transfer field effect transistor over the top surface of the substrate around a first portion of the at least one vertical fin; forming an isolation layer over the first vertical transfer field effect transistor and surrounding a second portion of the at least one vertical fin; as well as forming a second vertical transfer field effect transistor over a top surface of the isolation layer surrounding a third portion of the at least one vertical fin; wherein the first portion of the at least one vertical fin comprises a first semiconductor layer having a first crystal orientation, the first crystal orientation providing a first vertical transfer channel for the first vertical transfer field effect transistor; wherein the second portion of the at least one vertical fin comprises an insulator; and wherein the third portion of the at least one vertical fin comprises a second semiconductor layer having a second crystal orientation, the second crystal orientation providing a second vertical transfer channel for the second vertical transfer field effect transistor; forming a first bottom source / drain region for the first vertical transfer field effect transistor, the first bottom source / drain region comprising a doped region adjacent to the top surface of the substrate and a doped region of a first portion of the first semiconductor layer adjacent to the top surface of the substrate; forming a first bottom spacer disposed over the top surface of the substrate and surrounding the first portion of the first semiconductor layer; forming a first gate stack disposed over a top surface of the first bottom spacer and surrounding a second portion of the first semiconductor layer; forming a first top spacer disposed above a top surface of the first gate stack and surrounding a third portion of the first semiconductor layer; as well as forming a first top source / drain contact for the first vertical transfer field effect transistor, the first top source / drain contact being disposed above a top surface of the first top spacer and surrounding a fourth portion of the first semiconductor layer; The third portion of the first semiconductor layer and the fourth portion of the first semiconductor layer are doped to provide a first top source / drain region for the first vertical transfer field effect transistor.

13. The method of claim 12, wherein the first crystal orientation provides a first vertical transfer orientation for one of an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET), and wherein the second crystal orientation provides a vertical transfer orientation for the other of the nFET and the pFET.

14. The method of claim 12, wherein the first semiconductor layer comprises silicon having one of a (110) crystal orientation and a (100) crystal orientation, and wherein the second semiconductor layer comprises silicon having the other of the (110) crystal orientation and the (100) crystal orientation.

15. The method of claim 12, wherein forming the at least one vertical fin comprises: patterning a hard mask over a layered stack comprising the first semiconductor layer, the insulator, and the second semiconductor layer; as well as The exposed portion of the layered stack is etched to form the at least one vertical fin.

16. A method of forming a semiconductor structure, comprising: forming at least one vertical fin above a top surface of the substrate; forming a first vertical transfer field effect transistor over the top surface of the substrate around a first portion of the at least one vertical fin; forming an isolation layer over the first vertical transfer field effect transistor and surrounding a second portion of the at least one vertical fin; as well as forming a second vertical transfer field effect transistor over a top surface of the isolation layer surrounding a third portion of the at least one vertical fin; wherein the first portion of the at least one vertical fin comprises a first semiconductor layer having a first crystal orientation, the first crystal orientation providing a first vertical transfer channel for the first vertical transfer field effect transistor; wherein the second portion of the at least one vertical fin comprises an insulator; and wherein the third portion of the at least one vertical fin comprises a second semiconductor layer having a second crystal orientation, the second crystal orientation providing a second vertical transfer channel for the second vertical transfer field effect transistor; ： forming a doped region adjacent to the top surface of the substrate and in a first portion of the first semiconductor layer, wherein the doped region provides a first bottom source / drain region for the first vertical transfer field effect transistor; forming a first bottom spacer over the top surface of the substrate and surrounding the first portion of the first semiconductor layer; forming a first gate stack over a top surface of the first bottom spacer and surrounding a second portion of the first semiconductor layer; forming a first top spacer over a top surface of the first gate stack and surrounding a third portion of the first semiconductor layer; forming a first silicate glass layer over the top surface of the first top spacer and surrounding a fourth portion of the first semiconductor layer; and forming the isolation layer over the first silicate glass layer and surrounding the insulator of the at least one vertical fin; The first silicate glass layer includes one of an n-type dopant material and a p-type dopant material.

17. The method of claim 16, further comprising: forming a second silicate glass layer over the top surface of the isolation layer and surrounding a first portion of the second semiconductor layer; forming a second bottom spacer over the top surface of the second silicate glass layer and surrounding a second portion of the second semiconductor layer; forming a second gate stack over the top surface of the second bottom spacer and surrounding a third portion of the second semiconductor layer; forming a second top spacer over a top surface of the second gate stack and surrounding a fourth portion of the second semiconductor layer; and forming a third silicate glass layer over the top surface of the second top spacer and surrounding a fifth portion of the second semiconductor layer; The second silicate glass layer and the third silicate glass layer contain the other of the n-type dopant material and the p-type dopant material.

18. The method of claim 17, further comprising performing a dopant drive-in to drive dopants from the first silicate glass layer, the second silicate glass layer, and the third silicate glass layer to form: a first top source / drain region of a first vertical transfer field effect transistor in the third portion of the first semiconductor layer and in the fourth portion of the first semiconductor layer; a second bottom source / drain region of the second vertical transfer field effect transistor in the first portion of the second semiconductor layer and in the second portion of the second semiconductor layer; as well as A second top source / drain region for the second vertical transfer field effect transistor in the fourth portion of the second semiconductor layer, the fifth portion of the second semiconductor layer, and a sixth portion of the second semiconductor layer above the fifth portion of the second semiconductor layer.

19. The method of claim 18, further comprising: removing the third silicate glass layer; as well as An interlayer dielectric is formed over the second top spacer and encapsulates the fifth portion of the second semiconductor layer, the sixth portion of the second semiconductor layer, and a hard mask over the sixth portion of the second semiconductor layer.

20. The method of claim 19, further comprising: etching the interlayer dielectric, the second top spacer, the second gate stack, and a first portion of the second bottom spacer apart from a first sidewall of the at least one vertical fin; forming first sidewall spacers adjacent to edges of the etched first portion of the interlayer dielectric, the second top spacer, the second gate stack, and the second bottom spacer; removing the second silicate glass layer; depositing a contact material to form a second bottom source / drain contact for the second vertical transfer field effect transistor, the second top source / drain contact wrapping around a first portion of the second semiconductor layer exposed by removing the second silicate glass layer; etching the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second top source / drain contact, and a second portion of the isolation layer away from a second sidewall of the at least one vertical fin; forming second sidewall spacers adjacent to the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second top source / drain contact, and edges of the etched second portion of the isolation layer; removing the first silicate glass layer; as well as A contact material is deposited to form a first top source / drain contact for the first vertical transfer field effect transistor, the first top source / drain contact wrapping around the fourth portion of the first semiconductor layer exposed by removing the first silicate glass layer.

21. The method of claim 20, further comprising: etching the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second silicate glass layer, and a first portion of the isolation layer away from a first sidewall of the at least one vertical fin; forming first sidewall spacers adjacent to edges of the etched first portion of the interlayer dielectric, the second top spacer, the second gate stack, and the second bottom spacer; removing the second silicate glass layer and the first silicate glass layer; as well as A contact material is deposited to form a shared contact with the second bottom source / drain region of the second vertical transfer field effect transistor and the first top source / drain region of the first vertical transfer field effect transistor, the shared contact wrapping around the first portion of the second semiconductor layer and the fourth portion of the first semiconductor layer exposed by removing the second silicate glass layer and the first silicate glass layer.

22. The method of claim 20, further comprising: etching portions of the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second silicate glass layer, the isolation layer, the first silicate glass layer, the first top spacer, the first gate stack, and the first bottom spacer to expose a portion of the top surface of the substrate spaced apart from the first end of the at least one vertical fin; forming sidewall spacers having a first vertical surface at etched edges of the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second silicate glass layer, the isolation layer, the first silicate glass layer, the first top spacer, the first gate stack, and the first bottom spacer; depositing a contact material to form a first bottom source / drain contact to the first bottom source / drain region of the first vertical transfer field effect transistor over the exposed top surface of the substrate adjacent the second vertical surface of the sidewall spacer; etching portions of the interlayer dielectric, the second top spacer, the second gate stack, the second bottom spacer, the second silicate glass layer, the isolation layer, the first silicate glass layer, and the first top spacer to form an exposed portion spaced apart from a second end of the at least one vertical fin; as well as A contact material is deposited in the exposed portion to form a shared gate contact with the first gate stack of the first vertical transfer field effect transistor and the second gate stack of the second vertical transfer field effect transistor.

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