Through-hole wiring substrate, manufacturing method thereof, and semiconductor device mounting components

Abstract

A through-hole wiring forming substrate for mounting at least one semiconductor chip includes: a support substrate; a peelable adhesive layer disposed on the support substrate; a first insulating layer disposed on the peelable adhesive layer; and a second insulating layer stacked on the first insulating layer. Through-hole wiring forming vias are formed in the first insulating layer and the second insulating layer by directly penetrating both layers without misalignment. Each through-hole wiring forms a plurality of connection terminals of the semiconductor chip and is capable of forming through-hole wiring that connects to the connection terminals.

Description

Technical Field

[0001] This invention relates to a substrate for forming through-hole wiring, a method for manufacturing the substrate for forming through-hole wiring, and a semiconductor device mounting component. Background Technology

[0002] Previously, in the fields of portable terminals and information appliances, multi-layer substrate structures with built-in semiconductor chips were required to meet the demands for miniaturization, lightweighting, high functionality, and consequently high speed and high frequency. As a technology for such multi-layer substrate structures with built-in semiconductor chips, fan-out wafer-level packages (FO-WLP) have attracted attention in order to cope with high-density wiring by forming a redistribution layer outside the semiconductor chip area.

[0003] As such a FO-WLP, the following method is proposed: First, a wafer (hereinafter referred to as "temporary wafer") is obtained by integrating semiconductor chips cut from a wafer in a state of open gaps. A redistribution layer is formed on the temporary wafer. After the redistribution layer is formed, the temporary wafer is cut to obtain individual packages (Chip-first) (see Patent Document 1).

[0004] Furthermore, as a type of mass-produced FO-WLP, there exists a method called InFO (Integrated Fan-Out) (see Patent Document 2). In this method, columnar electrical connectors 108 (FIG.1B) are provided on an internal wiring layer 104 provided on a support substrate 102. A first semiconductor chip 110 with an electrical connector 112 is provided on the internal wiring layer 104 between the electrical connectors 108 with the active surface facing upward (FIG.1C). The electrical connectors 108 and the semiconductor chip 110 are molded using a molding material 114. After curing (FIG.1D), the molding material 114 is ground to expose the upper end face 108A of the electrical connector 108 and the upper end face 112A of the electrical connector 112 of the semiconductor chip 110. The electrical connectors 108 and 112 are used as through-holes through the molded surface (FIG.1E). Next, an internal wiring layer (rewiring layer) 116 is provided and connected to the electrical connectors 108 and 112 that pass through the molded through-hole. An electrical connector 118 (FIG.1F) is formed on the internal wiring layer 116, and a second semiconductor chip 120 (FIG.1G) is mounted on the electrical connector 118.

[0005] In this method, the cylindrical electrical connector 108 and the electrical connector 112 on the semiconductor chip 110 need to be molded together, and then the upper surface is exposed by grinding. The higher the wiring density, the greater the difficulty, and the connection with the rewiring layer also becomes more difficult. In addition, the height limit of the cylindrical electrical connector 108 is about 150 to 200 μm. When the height of the semiconductor chip 110 is large, it may become difficult to manufacture. Furthermore, when multiple semiconductor chips are initially mounted, if the heights of the semiconductor chips are different, the electrical connector of one semiconductor chip needs to be formed into a cylindrical shape, which also presents a difficult problem to handle.

[0006] Prior art literature

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2013-58520

[0009] Patent Document 2: U.S. Patent Application Publication No. 2018 / 0138089 Summary of the Invention

[0010] The problem that the invention aims to solve

[0011] The purpose of this invention is to solve the above-mentioned problems and to provide a substrate for forming through-hole wiring, a method for manufacturing the same, and a semiconductor device mounting component manufactured using the same method. The substrate for forming through-hole wiring can simultaneously mount semiconductor chips of different heights without the need to pre-manufacture columnar electrical connectors.

[0012] Technical solutions for solving the problem

[0013] A first aspect of the present invention that achieves the above-mentioned objective is a through-hole wiring forming substrate for mounting at least one semiconductor chip, comprising: a support substrate; a peelable adhesive layer disposed on the support substrate; a first insulating layer disposed on the peelable adhesive layer; and a second insulating layer stacked on the first insulating layer, wherein through-hole wiring forming vias are formed by passing through the first insulating layer and the second insulating layer without misalignment, and the through-hole wiring forming vias correspond to a plurality of connection terminals of the semiconductor chip and are capable of forming through-hole wiring connected to the connection terminals.

[0014] The second aspect of the present invention is based on the through-hole wiring substrate described in the first aspect, wherein the second insulating layer is composed of a low-flow adhesive material.

[0015] The third aspect of the present invention is based on the through-hole wiring substrate described in the first or second aspect, wherein the first insulating layer is composed of an epoxy-based sealing material.

[0016] The fourth aspect of the present invention is a method for manufacturing a substrate for forming through-hole wiring, comprising the following steps: a step of preparing a laminated substrate, wherein the laminated substrate is obtained by laminating a first support substrate, a first peelable adhesive layer formed on the first support substrate, a first metal layer formed on the first peelable adhesive layer, and a second metal layer formed on the first metal layer and having etching characteristics different from the first metal layer; a step of providing a resist layer on the second metal layer and forming a plurality of first through-hole forming holes in the resist layer in a given pattern; a step of forming a second through-hole forming hole communicating with the first through-hole forming hole in the second metal layer through the first through-hole forming hole of the resist layer, using the first metal layer as an etch stop layer; a step of embedding a third metal with etching characteristics different from the second metal layer in the first through-hole forming hole and the second through-hole forming hole to form a third metal pillar; a step of peeling off the resist layer; the second The process includes: forming a first insulating layer on a metal layer into which the third metal pillar is embedded; grinding the surface of the first insulating layer to expose the first end face of the third metal pillar; bonding a second support substrate to the first insulating layer and the third metal pillar using a second peelable adhesive layer; peeling off the first peelable adhesive layer and the first support substrate; removing the first metal layer to expose the second metal layer and the second end face of the third metal pillar on the side opposite to the first end face; etching away the second metal layer using the third metal pillar and the first insulating layer as an etch stop layer; setting a second insulating layer on the first insulating layer and embedding the third metal pillar; grinding the surface of the second insulating layer to expose the second end face of the third metal pillar; and etching away the third metal pillar using the first insulating layer and the second insulating layer as an etch stop layer to form a through-hole for wiring.

[0017] The fifth aspect of the present invention is based on the manufacturing method of the substrate for forming through-hole wiring described in the fourth aspect, wherein the second insulating layer is composed of a low-flow adhesive material.

[0018] The sixth aspect of the present invention is based on the manufacturing method of a substrate for forming through-hole wiring described in the fourth or fifth aspect, wherein the first insulating layer is composed of an epoxy-based sealing material.

[0019] The seventh aspect of the present invention is based on the manufacturing method of a substrate for forming through-hole wiring described in any of the fourth to sixth aspects, wherein the first metal layer is composed of nickel or a nickel alloy, and the second metal layer is composed of copper or a copper alloy.

[0020] The eighth aspect of the present invention is based on the manufacturing method of a substrate for forming through-hole wiring described in any of the fourth to seventh aspects, wherein the third metal pillar is made of nickel or a nickel alloy.

[0021] The ninth aspect of the present invention is a method for manufacturing a semiconductor device mounting component, comprising the following steps: preparing a through-hole wiring forming substrate as described in any of the first to third aspects, or a through-hole wiring forming substrate manufactured using a manufacturing method for a through-hole wiring forming substrate as described in any of the fourth to eighth aspects; preparing a semiconductor chip with connection terminals as copper terminals, and bonding the semiconductor chip to a second insulating layer of the through-hole wiring forming substrate, or to a second insulating layer of the through-hole wiring forming substrate made of a low-flow adhesive, with the copper terminals facing each other; forming a third insulating layer embedded in the semiconductor chip; peeling off the peelable adhesive layer and the support substrate, or the second peelable adhesive layer and the second support substrate; and embedding copper into the through-hole wiring forming via from the side opposite to the side where the semiconductor chip is disposed, thereby forming through-hole wiring connected to the copper terminals.

[0022] A tenth aspect of the present invention is a semiconductor device mounting component comprising: a component support stack having a first layer composed of a first insulating layer and a second layer stacked on the first layer, wherein through-hole wiring forming vias are formed in the first layer and the second layer, the through-hole wiring forming vias being formed by passing through the first layer and the second layer without misalignment; at least one component bonded to the first layer or the second layer of the component support stack, having a connection terminal opposite to the through-hole wiring forming via; a third layer composed of molding resin embedded in the component; and through-hole wiring having one end connected to the connection terminal of the component and the other end led out through the through-hole wiring forming via to the opposite side of the component support stack, wherein the total thickness of the first layer and the second layer of the component support stack is selected from the range of 15 μm to 70 μm.

[0023] The eleventh aspect of the present invention is based on the semiconductor device mounting component described in the tenth aspect, wherein the first insulating layer of the first layer is composed of an epoxy-based sealing material.

[0024] The twelfth aspect of the present invention is based on the semiconductor device mounting component described in the tenth or eleventh aspect, wherein the component includes: at least one semiconductor chip having connection terminals; and at least one semiconductor chip or passive component with different heights, wherein the height is a dimension in the thickness direction of the stack on which the semiconductor chip and the component bear.

[0025] The thirteenth aspect of the present invention is based on the semiconductor device mounting component of any of the tenth to twelfth aspects, wherein the second layer is composed of a second insulating layer, and the component is bonded to the second layer.

[0026] The fourteenth aspect of the present invention is based on the semiconductor device mounting component described in the thirteenth aspect, wherein the through-hole wiring is led out from the connection terminal of the component to the opposite side of the component receiving laminate via a through hole provided in the redistribution insulating layer, and the redistribution insulating layer is provided in the through hole for forming the through-hole wiring.

[0027] The fifteenth aspect of the present invention is based on the semiconductor device mounting component described in the thirteenth or fourteenth aspect, wherein the second layer is composed of a low-flow adhesive material.

[0028] The sixteenth aspect of the present invention is based on a semiconductor device mounting component of any of the tenth to twelfth aspects, wherein the second layer is composed of a metal layer, the component is bonded to the first layer, the via wiring is led out from the connection terminal of the component through a through hole provided in a rewiring insulating layer, the rewiring insulating layer is provided in the via forming via, and a second through hole is provided in the rewiring insulating layer and the first layer to expose the metal layer, and a second wiring connected to the metal layer is provided in the second through hole.

[0029] The seventeenth aspect of the present invention is based on the semiconductor device mounting component of the sixteenth aspect, wherein the metal layer is a copper foil.

[0030] The eighteenth aspect of the present invention is based on a semiconductor device mounting component of any of the tenth to seventeenth aspects, wherein one of the connection terminals of the component is configured correspondingly to one of the through holes for forming through-hole wiring, the semiconductor device mounting component is provided with a photosensitive resin layer, the photosensitive resin layer covers a first through-hole wiring provided through the through hole for forming through-hole wiring, a through hole is provided on the photosensitive resin layer at a position opposite to the first through-hole wiring, and a wiring layer is provided on the photosensitive resin layer, the wiring layer including a second through-hole wiring formed in the through hole and connected to the first through-hole wiring.

[0031] The nineteenth aspect of the present invention is based on a semiconductor device mounting component described in any of the tenth to seventeenth aspects, wherein a plurality of connection terminals of the component are configured to correspond to one of the through holes for forming through-hole wiring, a plurality of through holes opposite to the plurality of connection terminals are formed in the photosensitive resin layer of the through hole for forming through-hole wiring, and the through-hole wiring is provided in each through hole.

[0032] The twentieth aspect of the present invention is based on the semiconductor device mounting component described in the nineteenth aspect. The component is a region pad type semiconductor chip in which a plurality of connection terminals are arranged in a given area in the center. The vias for forming wiring are formed in a shape corresponding to the given area. The photosensitive resin layer is formed to fill the vias for forming wiring and forms a plurality of through holes opposite to the plurality of connection terminals. The via wiring is provided in each through hole.

[0033] The twenty-first aspect of the present invention is based on the semiconductor device mounting component described in the nineteenth aspect. The component is a semiconductor chip with a plurality of connection terminals arranged on a given peripheral portion surrounding a central portion. The vias for forming wiring are formed in a shape corresponding to the given peripheral portion surrounding the central portion. The photosensitive resin layer is formed to fill the vias for forming wiring and forms a plurality of through holes opposite to the plurality of connection terminals. The via wiring is provided in each through hole.

[0034] The twenty-second aspect of the present invention is based on the semiconductor device mounting component described in any of the tenth to seventeenth aspects, wherein a rewiring layer is provided on the surface through which the via wiring is led out, with a photosensitive resin layer in between, and the rewiring layer is formed with rewiring.

[0035] The twenty-third aspect of the present invention is based on the semiconductor device mounting component described in the twenty-second aspect, wherein the redistribution layer is provided with three or four or more layers.

[0036] The twenty-fourth aspect of the present invention is based on the semiconductor device mounting component described in the twenty-second aspect, wherein the redistribution layer has two or three layers, and the component support stack is further provided on the redistribution layer, and the redistribution layer is further provided on the component support stack.

[0037] The twenty-fifth aspect of the present invention is based on the semiconductor device mounting component described in the twenty-second aspect, wherein the component further comprises a component support stack on the outermost layer of the redistribution layer.

[0038] The twenty-sixth aspect of the present invention is based on a semiconductor device mounting component described in any of the nineteenth to twenty-second aspects, wherein the component is obtained by placing two or three layers of the redistribution layer onto a semiconductor chip via an eWLP.

[0039] Furthermore, the thirty-first aspect of the present invention is a through-hole wiring forming substrate for mounting at least one semiconductor chip. The through-hole wiring forming substrate includes: a support substrate; a peelable adhesive layer disposed on the support substrate; and an insulating layer disposed on the peelable adhesive layer. In the insulating layer, through-holes for forming through-hole wiring are formed by passing through the insulating layer without misalignment. The through-holes for forming through-hole wiring correspond to a plurality of connection terminals of the semiconductor chip and are capable of forming through-hole wiring connected to the connection terminals. The through-holes for forming through-hole wiring are straight holes with a diameter of 15 μm to 70 μm, and the positional accuracy of the through-holes for forming through-hole wiring is photolithographic accuracy.

[0040] The thirty-second aspect of the present invention is based on the through-hole wiring forming substrate described in the thirty-first aspect, wherein the through-hole wiring forming through-hole is not formed by drilling or laser processing, but by removing the metal pillars or photosensitive resin pillars embedded in the insulating layer.

[0041] The thirty-third aspect of the present invention is based on the through-hole wiring substrate described in the thirty-first or thirty-second aspects, wherein the insulating layer is composed of an epoxy-based sealing material.

[0042] The thirty-fourth aspect of the present invention is based on a through-hole wiring forming substrate described in any of the thirty-first to thirty-third aspects, wherein a metal layer is provided between the insulating layer and the peelable adhesive layer, and the through-hole for forming the through-hole wiring is formed through the metal layer.

[0043] The thirty-fifth aspect of the present invention is based on the through-hole wiring substrate described in the thirty-fourth aspect, wherein the metal layer between the insulating layer and the peelable adhesive layer is composed of a first metal layer and a second metal layer from the peelable adhesive layer side.

[0044] The thirty-sixth aspect of the present invention is based on the through-hole wiring substrate described in the thirty-fourth aspect, wherein the metal layer and the metal pillar are made of nickel or a nickel alloy.

[0045] The thirty-seventh aspect of the present invention is based on the through-hole wiring substrate described in the thirty-fifth aspect, wherein the first metal layer and the metal pillar are made of nickel or a nickel alloy, and the second metal layer is made of copper or a copper alloy.

[0046] The thirty-eighth aspect of the present invention is a method for manufacturing a substrate for forming through-hole wiring, comprising the following steps: a step of preparing a laminated substrate, wherein the laminated substrate is obtained by sequentially stacking a first support substrate, a first peelable adhesive layer formed on the first support substrate, and a metal layer on the first peelable adhesive layer; a step of providing a resist layer on the metal layer and forming a plurality of through-hole forming holes in the resist layer in a given pattern; a step of embedding metal in the metal layer in the through-hole forming holes to form metal pillars; a step of peeling off the resist layer; a step of forming an insulating layer on the metal layer in which the metal pillars are embedded; a step of grinding the surface of the insulating layer to expose a first end face of the metal pillars; and a step of using the insulating layer and the peelable adhesive layer as an etch stop layer to etch away the metal pillars to form through-hole wiring.

[0047] The thirty-ninth aspect of the present invention is based on the manufacturing method of the through-hole wiring substrate described in the thirty-eighth aspect, and includes the following steps: after a step of exposing the first end face of the metal pillar, a step of bonding a second support substrate to the insulating layer and the metal pillar via a second peelable adhesive layer; a step of peeling off the peelable adhesive layer and the support substrate; and a step of removing the metal layer to expose the second end face opposite to the first end face of the metal pillar, and then etching away the metal pillar to form a through-hole for through-hole wiring.

[0048] The fortieth aspect of the present invention is a method for manufacturing a substrate for through-hole wiring formation, comprising the following steps: a step of preparing a laminated substrate, wherein the laminated substrate is obtained by sequentially laminating a support substrate, a peelable adhesive layer formed on the support substrate, and a first metal layer and a second metal layer on the peelable adhesive layer; a step of providing a resist layer on the second metal layer and forming a plurality of through-hole forming holes on the resist layer in a given pattern; a step of etching only the second metal layer using the resist layer in the given pattern as a mask; a step of forming metal pillars with embedded metal on the first metal layer in the through-hole forming holes; a step of peeling off the resist layer; a step of forming an insulating layer with the embedded metal pillars on the first metal layer; a step of grinding the surface of the insulating layer to expose a first end face of the metal pillars; and a step of etching away the metal pillars and the first metal layer by using the insulating layer and the peelable adhesive layer as an etching stop layer to form through-holes for through-hole wiring formation.

[0049] The forty-first aspect of the present invention is a method for mounting a semiconductor chip, comprising the following steps: preparing a through-hole wiring forming substrate as described in any of the thirty-first to thirty-seventh aspects, or a through-hole wiring forming substrate manufactured using a manufacturing method for a through-hole wiring forming substrate as described in any of the thirty-eighth to fortieth aspects; preparing a semiconductor chip with connection terminals as copper terminals on the insulating layer of the through-hole wiring forming substrate, and bonding the semiconductor chip to the insulating layer via an adhesive with the copper terminals facing the through-hole wiring forming via of the through-hole wiring forming substrate; forming an embedded insulating layer in which the semiconductor chip is embedded; peeling off the peelable adhesive layer and the support substrate, or the second peelable adhesive layer and the second support substrate; and embedding copper into the through-hole wiring forming via from the side opposite to the side where the semiconductor chip is disposed, thereby forming through-hole wiring connected to the copper terminals.

[0050] The forty-second aspect of the present invention is a method for mounting a semiconductor chip, comprising the following steps: preparing a through-hole wiring forming substrate as described in the thirty-fourth or thirty-sixth aspect, or a through-hole wiring forming substrate manufactured using the manufacturing method of the through-hole wiring forming substrate described in the thirty-eighth aspect; preparing a semiconductor chip with connection terminals as copper terminals on the insulating layer of the through-hole wiring forming substrate, and bonding the semiconductor chip to the insulating layer via an adhesive with the copper terminals facing the through-hole wiring forming via of the through-hole wiring forming substrate; forming an embedded insulating layer for embedding the semiconductor chip; peeling off the peelable adhesive layer and the support substrate; removing the metal layer; and embedding copper into the through-hole wiring forming via from the side opposite to the side where the semiconductor chip is disposed, thereby forming through-hole wiring connected to the copper terminals.

[0051] The forty-third aspect of the present invention is a method for mounting a semiconductor chip, comprising the following steps: preparing a through-hole wiring forming substrate as described in the thirty-fifth or thirty-seventh aspect, or a through-hole wiring forming substrate manufactured using the manufacturing method of the through-hole wiring forming substrate described in the fortyth aspect; preparing a semiconductor chip with connection terminals as copper terminals on the insulating layer of the through-hole wiring forming substrate, and bonding the semiconductor chip to the insulating layer with an adhesive while the copper terminals are facing the through-hole wiring forming via of the through-hole wiring forming substrate; forming an embedded insulating layer for embedding the semiconductor chip; peeling off the peelable adhesive layer and the support substrate; removing the first metal layer; embedding copper into the through-hole wiring forming via from the side opposite to the side where the semiconductor chip is disposed, thereby forming through-hole wiring connected to the copper terminals; and forming a wiring pattern using the second metal layer.

[0052] Invention Effects

[0053] As described above, according to the present invention, it is possible to provide a semiconductor device mounting component manufactured using a through-hole wiring forming substrate, which does not require the pre-manufacturing of columnar electrical connectors and can simultaneously mount semiconductor chips of different heights. Attached Figure Description

[0054] Figure 1 This is a cross-sectional view of the through-hole wiring substrate according to substrate embodiment 1.

[0055] Figure 2 This is a cross-sectional view showing the manufacturing process of the through-hole wiring substrate according to Embodiment 1 of the substrate.

[0056] Figure 3 This is a cross-sectional view showing the manufacturing process of the through-hole wiring substrate according to Embodiment 1 of the substrate.

[0057] Figure 4 This is a cross-sectional view of the substrate for forming through-hole wiring according to substrate embodiment 2.

[0058] Figure 5 This is a cross-sectional view of the substrate for forming through-hole wiring according to substrate embodiment 3.

[0059] Figure 6 This is a cross-sectional view showing the manufacturing process of the through-hole wiring substrate according to embodiment 3.

[0060] Figure 7 This is a cross-sectional view showing the manufacturing process of a semiconductor chip with copper pads (PADs) and an adhesive layer.

[0061] Figure 8 This is a cross-sectional view showing the manufacturing process of the through-hole wiring substrate according to Embodiment 1.

[0062] Figure 9 This is a cross-sectional view showing the effect of the installation process involved in Embodiment 1.

[0063] Figure 10 This is a cross-sectional view showing the manufacturing process of a semiconductor chip with copper pads and an adhesive layer.

[0064] Figure 11 This is a cross-sectional view illustrating the installation process involved in Embodiment 2.

[0065] Figure 12 This is a cross-sectional view showing a comparison between the semiconductor chip mounting component of the present invention and a conventional eWLP structure.

[0066] Figure 13 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0067] Figure 14 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0068] Figure 15 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0069] Figure 16 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0070] Figure 17 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0071] Figure 18 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0072] Figure 19 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0073] Figure 20 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0074] Figure 21 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0075] Figure 22 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0076] Figure 23 This is a cross-sectional view of the substrate for forming through-hole wiring according to substrate embodiment 4.

[0077] Figure 24 This is a cross-sectional view showing the manufacturing process of the through-hole wiring substrate according to embodiment 4.

[0078] Figure 25 This is a cross-sectional view of the substrate for forming through-hole wiring according to substrate embodiment 5.

[0079] Figure 26 This is a cross-sectional view showing the manufacturing process of the through-hole wiring substrate according to embodiment 5.

[0080] Figure 27 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0081] Figure 28 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0082] Figure 29 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0083] Figure 30 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0084] Figure 31 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention.

[0085] Figure 32 This is a cross-sectional view showing a modified example of the semiconductor chip mounting component of the present invention. Detailed Implementation

[0086] The present invention will now be described in further detail.

[0087] First, a substrate for forming through-hole wiring used in manufacturing the semiconductor device mounting component of the present invention will be described.

[0088] (Substrate Embodiment 1)

[0089] Figure 1 This is a cross-sectional view of the substrate for forming through-hole wiring according to this embodiment. Figures 2-3 This is a cross-sectional view showing the manufacturing process of a substrate for forming through-hole wiring.

[0090] As shown in the accompanying drawings, the through-hole wiring substrate 1 includes: a support substrate 11, a peelable adhesive layer 12 disposed on one side of the support substrate 11, a first insulating layer 13 disposed on the peelable adhesive layer 12, and a second insulating layer 14 disposed on the first insulating layer 13, and has a plurality of through-hole wiring forming vias 15 that penetrate only the first insulating layer 13 and the second insulating layer 14.

[0091] The through-hole 15 for forming through-hole wiring is a hole used to form through-hole wiring, for example, a hole formed to match the location of the connection terminal to be mounted on the semiconductor chip to be manufactured in the FO-WLP, and the location of the through-hole wiring provided around the mounted semiconductor chip.

[0092] The through-hole 15 for forming wiring does not affect the support substrate 11 and the peelable adhesive layer 12 disposed on one side of the support substrate 11. It only penetrates the first insulating layer 13 and the second insulating layer 14, and is disposed such that the first insulating layer 13 and the second insulating layer 14 are connected without misalignment. Here, "connected without misalignment" means that the through-hole 15a that penetrates the first insulating layer 13 and the through-hole 15b that penetrates the second insulating layer 14 are integrally and continuously formed without misalignment.

[0093] The first insulating layer 13 and the second insulating layer 14 cannot stand alone and need to be supported by the support substrate 11. Furthermore, since the first insulating layer 13 and the second insulating layer 14 are made of different materials and have different mechanical and processing characteristics, they cannot be formed by drilling or laser processing. Such a through-hole wiring forming via 15 that only penetrates the first insulating layer 13 and the second insulating layer 14 supported by the support substrate 11 can be formed by a new photolithography process as follows.

[0094] Here, the through-hole 15 for forming wiring has the same precision as the through-hole formed by photolithography on the first insulating layer 13 and the second insulating layer 14 while supported on the support substrate 11. Therefore, it has good positional accuracy and can be formed with finer hole diameters and spacings than drilling. The through-hole 15 is a straight hole with a diameter of 15μm to 70μm, and the positional accuracy is the photolithography precision. Specifically, for example, it is ±5μm or less.

[0095] The first insulating layer 13 and the second insulating layer 14 cannot stand alone; they need to be supported by the support substrate 11. Furthermore, the through-hole wiring 15 cannot be formed solely by drilling or laser processing of the first insulating layer 13 and the second insulating layer 14. Even if formed by drilling, the diameter is approximately 75 μm, and the processing accuracy is ±5 μm, making it impossible to form through-holes smaller than 70 μm. Additionally, the positional accuracy is approximately ±10 μm. Furthermore, if laser processing is used, a tapered hole can be formed, but a straight hole cannot be formed. This could also damage the support substrate 11, hindering its repeated use.

[0096] Here, the total thickness of the first insulating layer 13 and the second insulating layer 14 is selected from a range of 15 μm to 70 μm. Furthermore, the thickness of the first insulating layer 13 is selected from a range of 5 μm to 50 μm, and the thickness of the second insulating layer 14 is selected from a range of 3 μm to 35 μm. Since a laminate of this thickness cannot stand on its own and cannot be processed during the mounting process, it needs to be used together with a support substrate in the mounting process. Additionally, the thicknesses of the first insulating layer 13 and the second insulating layer 14 can each be selected from the aforementioned ranges.

[0097] Furthermore, since the vias 15 for forming via wiring are formed using a photoresist formed by photolithography and by etching / plating metal, unlike machining, they have the advantage that even with a large number of vias, the cost does not increase significantly. Moreover, unlike drilling and laser machining, they are not affected by the machinability of the first insulating layer 13 and the second insulating layer 14, and can be formed with high precision using photolithography. Conversely, the materials for the first insulating layer 13 and the second insulating layer 14 offer greater freedom of choice.

[0098] Assuming that the diameter and minimum spacing of the through-hole 15 for forming through-hole wiring are small areas that are difficult to machine by drilling, but can be set to areas that can be machined by drilling. The diameter of the through-hole 15 for forming through-hole wiring is, for example, 15μm to 70μm, preferably 20μm to 50μm, and the minimum spacing is 50μm to 200μm.

[0099] The support substrate 11 is a substrate temporarily used to improve operability in the manufacturing process and can be reused. It can be made of any material that has mechanical strength, a low coefficient of thermal expansion, high dimensional stability, and resistance to the etching solution used in the photolithography process. Furthermore, when the peelable adhesive layer 12 is peeled off by light irradiation, it needs to be transparent relative to the wavelength used, but when peeled off by heat, it does not need to be transparent. For example, glass, metal, or resin plates can be used as the support substrate 11, with glass being preferred.

[0100] The peelable adhesive layer 12 is not peeled off during the manufacturing process, but can be peeled off when needed by light irradiation, heating, etc. There are no particular limitations as long as it has this function; for example, as an adhesive that can be peeled off by ultraviolet (UV) irradiation, JV peeling tape SELFA-SE (manufactured by Sekisui Chemicals Co., Ltd.) can be used. Furthermore, as an adhesive layer that can be peeled off by heating, examples include adhesives containing a foaming agent that expands upon heating at a given temperature.

[0101] The first insulating layer 13 can be formed from a thermosetting resin with a low coefficient of thermal expansion, such as epoxy resin, filled with inorganic fillers like silica. In particular, an epoxy-based sealing resin can be used. Instead of a photosensitive resist resin that allows partial photoexposed areas to be removed via a mask, it is made of a durable insulating material that can be used as a wiring substrate structure. Therefore, through-holes cannot be formed directly on the first insulating layer 13 by photolithography and etching.

[0102] Since the second insulating layer 14 exists on the first insulating layer 13, it will not directly contact the active surface of the semiconductor chip even when the semiconductor chip is mounted. Therefore, it is not necessary to use a low-impurity, halogen-free material. However, since the through-hole wiring forming via 15 is formed with a fine pitch, it is preferable to use a thermosetting resin material filled with micro-fillers. As for the maximum particle size of the filler, it is preferable to use about 5μm to 30μm.

[0103] The second insulating layer 14 is made of a thermosetting or thermoplastic resin material that contains no filler or has less filler than the first insulating layer 13 and has a lower elastic modulus than the first insulating layer 13. This is to ensure that the second insulating layer 14, which is disposed on top of the first insulating layer 13 and directly bonds to the semiconductor chip, has lower elasticity than the first insulating layer 13. Furthermore, since the second insulating layer 14 is in direct contact with the active surface of the mounted semiconductor chip, a low-impurity, halogen-free material is used.

[0104] As a resin material with this characteristic, an adhesive resin with lower flowability than general adhesives can be used. For example, it can be configured as an adhesive resin layer using adhesive resins such as epoxy resin, phenolic resin, or polyimide resin.

[0105] By providing this second insulating layer 14, as described later, after bonding the semiconductor chip to the second insulating layer 14, during the molding of the semiconductor chip, compared to the case of directly bonding to the first insulating layer 13, the bonding to the second insulating layer 14, which has low elasticity, has the advantage of being less prone to cracking. Conversely, if the semiconductor chip is directly bonded to the first insulating layer 13 and then molded, cracks may occur because the first insulating layer 13 is too rigid. The structure of the present invention solves this problem.

[0106] The adhesive resin layer can be formed by printing adhesive resin or attaching sheet material.

[0107] As described later, the second insulating layer 14 is the surface that bonds to the active surface of the semiconductor chip, and needs to have appropriate flowability to follow the unevenness of the active surface. However, if the flowability is too high, it will enter the via 15 for forming via wiring. Therefore, it is preferable to use a resin with appropriate elasticity and flowability. In this embodiment, the second insulating layer 14 is set as a non-flowing adhesive layer (NFA) with lower flowability than general adhesives. In this case, for example, a commercially available low-elasticity chip bonding film, such as the HS series (manufactured by Hitachi Chemical Co., Ltd.), can be used.

[0108] As described in the manufacturing process below, the via 15 for forming via wiring can be formed with the same aperture and spacing as vias formed by photolithography. However, the uniformity of the depth (aspect ratio) and aperture in the depth direction is better than that of vias formed directly on the first insulating layer 13 and the second insulating layer 14 by photolithography. In addition, since the support substrate 11 is present, it is not possible to form vias by laser processing or drilling. However, even if processing can be performed without the support substrate, vias with finer apertures and spacing than those produced by such processing can be formed, resulting in vias with uniform apertures in both depth (aspect ratio) and depth direction.

[0109] The through-hole 15 for forming through-hole wiring is formed to match the terminal configuration and size of the semiconductor chip to be mounted and the configuration and size of the columnar through-hole wiring to be disposed around it. Since multiple through-holes with different apertures are patterned and arranged, the aperture and spacing are not limited in general, but the aperture is 15μm to 70μm, preferably 20μm to 50μm, and the minimum spacing is 50μm to 200μm, preferably 50μm to 120μm, and more preferably 50μm to 100μm.

[0110] The following is for reference Figure 2 , Figure 3 Here is an example illustrating the manufacturing process of substrate 1 for forming through-hole wiring.

[0111] First, for example, a first support substrate 21 made of glass is prepared. Figure 2 (a)) having a first peelable adhesive layer 22 on one side thereof. Figure 2 (b)). The first peelable adhesive layer 22 can also be applied by coating a sheet adhesive layer, but here a UV release tape SELFA HW (manufactured by Sekisui Chemicals Co., Ltd.) is applied.

[0112] Next, a first metal layer 23 and a second metal layer 24 are disposed on the first peelable adhesive layer 22. Figure 2 (c) The first metal layer 23 and the second metal layer 24 are made of materials with different etching properties, so that in subsequent processes, the first metal layer 23 can be used as an etching stop layer and only the second metal layer 24 can be etched. Furthermore, considering the relationship with the resist layer that serves as a mask, it is preferable to use an acidic etchant for etching.

[0113] The metals used to form the first metal layer 23 and the second metal layer 24 can be selected from titanium (Ti), silver (Ag), aluminum (Al), tin (Sn), nickel (Ni), copper (Cu), etc. For example, the etching solution for Ti is NH4FHF-H2O2, for Ag it is CH3COOH-H2O2, for Al it is HCl, for Sn it is NH4FHF-H2O2, and for Ni it is HCl. For example, if any of these metals is used, FeCl3, Cu(NH3)2, H2SO4-H2O2, etc., can be listed as etching solutions capable of etching Cu for these metals and the etching stop layer.

[0114] Combinations of metals that form the first metal layer 23 and the second metal layer 24 can include, but are not limited to, Ti-Cu, Ag-Cu, Al-Cu, Sn-Cu, Ni-Cu, Ni-Ti, Ni-Sn, Al-Ti, Al-Sn, Ti-Ag, Al-Ag, An-Ag, Ni-Ag, etc.

[0115] Furthermore, there are no particular limitations on the formation methods of the first metal layer 23 and the second metal layer 24. There are no particular limitations on various vapor phase film formation methods, plating methods, or methods of attaching foils or sheets. However, from the perspective of work efficiency, it is preferable to attach commercially available double-layer metal sheets.

[0116] In this example, a double-layer metal foil with nickel as the first metal layer 23 and copper as the second metal layer 24 is attached. Furthermore, in this example, the thickness of the nickel in the first metal layer 23 is 0.5 μm, and the thickness of the copper in the second metal layer 24 is 12 μm. Here, the thickness of the first metal layer 23 is not particularly limited; approximately 0.5 μm to 5 μm is sufficient, and anything thicker would be wasteful. On the other hand, the thickness of the second metal layer 24 is essentially equivalent to the thickness of the second insulating layer 14 of the through-hole wiring forming substrate 1, and therefore needs to be selected based on the required thickness of the second insulating layer 14. Depending on the application of the through-hole wiring forming substrate 1, it is approximately 5 μm to 40 μm, preferably approximately 5 μm to 35 μm.

[0117] In addition, in this specification, for example, when referred to simply as nickel or copper, it also includes substances containing desired additive elements or unavoidable trace elements. Furthermore, substances containing desired additive elements or trace elements are sometimes referred to as nickel alloys or copper alloys.

[0118] Next, a resist layer 25 is formed on the second metal layer 24. Using conventional methods, an opening 26 is formed through the resist layer 25 by photoresist patterning. Figure 2 (d) The thickness of the resist layer 25, while not directly affecting the thickness of the first insulating layer 13 of the substrate 1 for forming via wiring, also influences its patterning characteristics, namely, the shape (aperture and perpendicularity) of the opening 26, which is transferred to the shape of the via 15 for forming via wiring. Therefore, the resist resin used to form the resist layer 25 can be either positive or negative, but it is preferable to select a resist resin that satisfies the aforementioned required characteristics. Examples of preferred resist resins include the Photec PKG substrate circuit forming RY series (manufactured by Hitachi Chemical Co., Ltd.). Here, the thickness of the resist layer 25 is set to 35 μm, and the diameter of the opening 26 is set to 30 μm.

[0119] Regarding exposure, it refers to irradiation with 100–300 mJ / cm². 2 The process involves UV spraying with a 1% Na2CO3 solution for 30 seconds for development and patterning.

[0120] Next, using the patterned resist layer 25 as a mask, only the second metal layer 24 made of Cu within the opening 26 is etched. Figure 2 (e)). In this example, by using FeCl3, Cu(NH3)2 or H2SO4-H2O2 as the etching solution, the first metal layer 23 composed of Ti can be used as an etching stop layer while only the second metal layer 24 is etched.

[0121] Next, using the first metal layer 23 made of Ni exposed inside the opening 26 as an electrode, a metal pillar 27 made of nickel is formed inside the opening 26. Figure 2 (f)). In this example, the thickness of metal column 27 is set to 20 μm.

[0122] In addition, in this example, the metal pillar 27 is set to nickel, but there is no particular limitation as long as it is a metal that is etch-resistant when the second metal layer 24 is etched away in the process described later. It can be the same metal as the first metal layer 23 or a different metal.

[0123] In addition, the metal pillar 27 is made by electroplating, but it is not particularly limited to electroplating as long as the method can completely fill the opening 26.

[0124] Next, peel off the resist layer 25 ( Figure 2 (g)), the first molding resin 28 (g) will be applied to form the first insulating layer 13. Figure 2 (h)), then, the first molding resin 28 is ground to expose the upper surface of the metal pillar 27 covered by the first molding resin 28. Figure 2 (i)

[0125] The first molding resin 28 can be the resin material described above that forms the first insulating layer 13, with a thickness sufficient to cover the metal pillar 27. The application method of the first molding resin 28 is not particularly limited and can be performed by vacuum printing, film lamination, compression molding using a mold, etc. In this example, R4212 molding resin manufactured by Nagase Chemtec was used, compressed at 120°C for 10 minutes, and then cured at 150°C for 1 hour to produce the first molding resin 28.

[0126] Furthermore, the grinding used to expose the upper surface of the metal pillar 27 can be performed using a general grinding machine such as a diamond tool.

[0127] Next, a second support substrate 30 is disposed on the first molding resin 28 exposed on the upper surface of the metal pillar 27 via a second peelable adhesive layer 29. Figure 3 (a)). The second support substrate 30 and the second peelable adhesive layer 29 become the support substrate 11 and peelable adhesive layer 12 of the through-hole wiring forming substrate 1, respectively. The second peelable adhesive layer 29 can also be a sheet adhesive layer applied by coating, but here a UV release tape (manufactured by Sekisui Chemicals Co., Ltd.) is applied, and the second support substrate 30 is a glass plate.

[0128] Next, flip the whole thing over, peel off the first peelable adhesive layer 22, and remove the first support substrate 21. Figure 3(b)), then, the first metal layer 23 on the uppermost surface is removed. Figure 3 (c)). The removal of the first metal layer 23 can be achieved by etching, grinding, or grinding after etching. In the case of etching, hydrochloric acid solution, sulfuric acid, or sulfuric acid hydrogen peroxide (H2SO4-H2O2) can be used as the etching solution.

[0129] Next, the second metal layer 24 is removed, exposing the upper end of the metal pillar 27. Figure 3 (d)). The removal of the second metal layer 24 is performed by etching. As the etching solution in this case, FeCl3, Cu(NH3)2, H2SO4-H2O2, etc. can be used.

[0130] Next, a second resin layer 31, which will become the second insulating layer 14, is set to cover the upper end of the metal pillar 27. Figure 3 (e)), then, the second resin layer 31 is ground to expose the upper end face of the metal pillar 27. Figure 3 (f) Here, the material of the second insulating layer 14 can be used for the second resin layer 31. In addition, the grinding to expose the upper surface of the metal pillar 27 can be performed using a general grinding machine such as a diamond tool.

[0131] Next, the metal pillar 27 is removed by etching, forming a through-hole 32 that will become a through-hole wiring 15 in the substrate 1 for through-hole wiring formation. Figure 3 (g) Thus, a through-hole wiring forming substrate 1 is formed having a first insulating layer 13 and a second insulating layer 14 on a support substrate 11 and a peelable adhesive layer 12, and having a through-hole wiring forming through-hole 15 that penetrates only the first insulating layer 13 and the second insulating layer 14.

[0132] (Substrate Embodiment 2)

[0133] Figure 4 The image shows a cross-sectional view of the substrate for forming through-hole wiring according to this embodiment.

[0134] like Figure 4 As shown, the through-hole wiring forming substrate 1A includes: a support substrate 11; a peelable adhesive layer 12 disposed on one side of the support substrate 11, a first insulating layer 13 disposed on the peelable adhesive layer 12, and a second insulating layer 14A disposed on the first insulating layer 13, and a plurality of through-hole wiring forming through-holes 15 formed therethrough through the first insulating layer 13 and the second insulating layer 14A.

[0135] For the through-hole wiring substrate 1A, the second insulating layer 14A is not a non-flowing adhesive layer (NFA). Except for using a thermosetting or thermoplastic resin material that does not contain filler or has less filler than the first insulating layer 13 and has a lower elastic modulus than the first insulating layer 13, the manufacturing process is the same as in Embodiment 1, so repeated descriptions are omitted. Specifically, as the second insulating layer 14A, HS-270 (DAF) manufactured by Hitachi Chemical Co., Ltd. is used, and lamination is performed at 80°C to 200°C, followed by bonding at 120°C to 160°C and a pressure of 0.02 MPa to 0.2 MPa for 30 seconds.

[0136] Alternatively, as the resin material used for the second insulating layer 14, a photosensitive resin such as a photosensitive polyimide resin used for the redistribution layer, or a thermosetting resin, may also be used.

[0137] (Substrate Embodiment 3)

[0138] Figure 5 The image shows a cross-sectional view of the substrate for forming through-hole wiring according to this embodiment.

[0139] like Figure 5 As shown, the through-hole wiring forming substrate 1B includes: a support substrate 11, a peelable adhesive layer 12 disposed on one side of the support substrate 11, and a metal layer 16 and an insulating layer 17 disposed on the peelable adhesive layer 12, and has a plurality of through-hole wiring forming through-holes 18 that penetrate only the metal layer 16 and the insulating layer 17.

[0140] In any case, the through-hole 18 for forming through-hole wiring is a hole for forming through-hole wiring, for example, a hole formed to match the location of the connection terminal to be mounted on the semiconductor chip to be manufactured in the FO-WLP, and the location of the through-hole wiring provided around the mounted semiconductor chip.

[0141] Here, the insulating layer 17 can be formed from a thermosetting resin material with a low thermal expansion integer, such as epoxy resin, filled with inorganic fillers like silica. In particular, an epoxy-based sealing resin can be used. Instead of a photosensitive resist resin that allows partial photoexposed areas to be removed via a mask, it is made of a durable insulating material that can be used as a wiring substrate structure. Therefore, through-holes cannot be formed directly on the insulating layer 17 by photolithography or etching.

[0142] Furthermore, since the insulating layer 17 may be in direct contact with the active surface of the semiconductor chip, a low-impurity, halogen-free material is preferred. Since the vias 18 are formed with fine-pitch wiring, a resin material filled with micro-fillers is preferred. As for the maximum particle size of the filler, a filler with a particle size of approximately 5 μm to 30 μm is preferred.

[0143] The through-hole 18 for forming the wiring is configured to not affect the support substrate 11 and the peelable adhesive layer 12, but only penetrate the metal layer 16 and the insulating layer 17.

[0144] Here, the through-hole 18 for forming the through-hole wiring is a straight hole with a diameter of 15μm to 70μm, and the positional accuracy is the photolithographic accuracy. Specifically, for example, it is ±5μm or less.

[0145] The metal layer 16 and insulating layer 17 cannot stand alone; they need to be supported by the support substrate 11. Furthermore, the through-hole wiring 18 cannot be formed solely by drilling or laser processing of the metal layer 16 and insulating layer 17. Even if formed by drilling, the diameter is approximately 75 μm, and the processing accuracy is ±5 μm, making it impossible to form through-holes smaller than 70 μm. Additionally, the positional accuracy is approximately ±10 μm. Furthermore, if laser processing is used, a tapered hole can be formed, but a straight hole cannot. This through-hole wiring 18, which only penetrates the metal layer 16 and insulating layer 17 supported by the support substrate 11, can be formed using a new process as described below.

[0146] Here, the total thickness of the metal layer 16 and the insulating layer 17 is selected from a range of 15 μm to 70 μm. Furthermore, the thickness of the metal layer 16 is selected from a range of 1 μm to 20 μm, and the thickness of the insulating layer 17 is selected from a range of 5 μm to 50 μm. Since a laminate of this thickness cannot stand on its own and cannot be processed during the mounting process, it needs to be used together with a support substrate in the mounting process. Additionally, the thicknesses of the first insulating layer 13 and the second insulating layer 14 can each be selected from the aforementioned ranges.

[0147] In addition, the metal layer 16 can be used as a grounding wiring, a shielding layer for semiconductor chips, and a heat dissipation layer for semiconductor chips. Therefore, the thickness can be set according to the required conductivity and thermal conductivity for each function.

[0148] The support substrate 11 is a substrate temporarily used to improve operability in the manufacturing process and can be reused. It can be made of a material that has mechanical strength, a low coefficient of thermal expansion, high dimensional stability, and resistance to the etching solutions used in the following processes. Furthermore, when the peelable adhesive layer 12 is peeled off by light irradiation, it needs to be transparent relative to the wavelength used, but when peeled off by heat, it does not need to be transparent. For example, glass, metal, or resin plates can be used as the support substrate 11, with glass being preferred.

[0149] The peelable adhesive layer 12 is not peeled off during the manufacturing process, but can be peeled off when needed by light irradiation, heating, etc. There are no particular limitations as long as it has this function; for example, as an adhesive that can be peeled off by ultraviolet (UV) irradiation, a UV peeling tape such as SELFA-SE (manufactured by Sekisui Chemicals Co., Ltd.) can be used. Furthermore, as an adhesive layer that can be peeled off by heating, examples include adhesives containing a foaming agent that expands upon heating at a given temperature.

[0150] As described above, the insulating layer 17 can be formed from a molding resin or the like, in which fillers are filled into a thermosetting resin such as epoxy resin, and in particular, an epoxy-based sealing resin can be used.

[0151] As described in the manufacturing process below, the via 18 for forming via wiring can be formed with the same aperture and spacing as vias formed by photolithography. However, the uniformity of the depth (aspect ratio) and aperture in the depth direction is better than that of vias formed directly on the insulating layer 17 by photolithography. That is, even if the insulating layer 17 is photosensitive and vias can be formed directly by exposure / development, the addition of filler results in different light refraction and light transmittance, leading to large deviations in coating thickness. Therefore, the aperture is easily affected by these factors. However, according to the process of the present invention, vias formed on a high-resolution resist can be transferred via metal pillars, thus forming apertures and spacing with the same precision as those formed by photolithography. In addition, since the support substrate 11 is present, vias cannot be formed by laser processing or drilling. However, even if processing can be performed without the support substrate, vias with finer apertures and spacing than those produced by such processing can be formed, resulting in vias with uniform aperture in both depth (aspect ratio) and depth direction.

[0152] The through-hole 18 for forming through-hole wiring is formed to match the terminal configuration and size of the semiconductor chip to be mounted and the configuration and size of the columnar through-hole wiring to be disposed around it. Since multiple through-holes with different apertures are patterned and arranged, the aperture and spacing are not limited in general, but the aperture is 15μm to 70μm, preferably 20μm to 50μm, and the minimum spacing is 50μm to 200μm, preferably 50μm to 120μm, and more preferably 50μm to 100μm.

[0153] The following is for reference Figure 6 Here is an example illustrating the manufacturing process of the substrate 1B for forming through-hole wiring.

[0154] First, for example, prepare a glass support substrate 121 ( Figure 6 (a)) has a peelable adhesive layer 122 on one side thereon. Figure 6 (b)). The peelable adhesive layer 122 can also be applied by coating to attach a sheet adhesive layer, but here a UV release tape SELFA-HW (manufactured by Sekisui Chemicals) is attached.

[0155] Next, a metal layer 123 is disposed on the peelable adhesive layer 122. Figure 6 (c)). Based on its relationship with the resist layer that serves as a mask, the metal layer 123 is preferably etched using an acidic etchant.

[0156] The metal used to form the metal layer 123 can be selected from titanium (Ti), silver (Ag), aluminum (Al), tin (Sn), nickel (Ni), copper (Cu), etc., with copper being preferred.

[0157] For example, the etching solution for Ti is NH4FHF-H2O2, for Ag it is CH3COOH-H2O2, for Al it is HCl, for Sn it is NH4FHF-H2O2, and for Ni it is HCl. For instance, if any of these metals is used, etching solutions capable of etching Cu, such as FeCl3, Cu(NH3)2, and H2SO4-H2O2, can be listed for these metals and the etching stop layer.

[0158] In addition, in this specification, for example, when referred to simply as nickel or copper, it also includes substances containing desired additive elements or unavoidable trace elements. Furthermore, substances containing desired additive elements or trace elements are sometimes referred to as nickel alloys or copper alloys.

[0159] Furthermore, there are no particular limitations on the method of forming the metal layer 123. There are no particular limitations on various methods of film formation under vapor phase, film formation by plating, or methods of attaching foil or sheet. However, from the perspective of work efficiency, it is preferable to attach commercially available metal foil.

[0160] In this example, a metal foil made of Cu is attached as metal layer 123. Furthermore, in this example, the Cu thickness of metal layer 123 is 0.5 μm.

[0161] Next, a resist layer 125 is formed on the metal layer 123. Using conventional methods, an opening 126 is formed through the resist layer 125 by photoresist patterning to create a given pattern. Figure 6 (d) The thickness of the resist layer 125, while not directly affecting the thickness of the insulating layer 17 of the substrate 1 for forming via wiring, also influences its patterning characteristics, i.e., the shape (aperture and perpendicularity) of the opening 126 is transferred to the shape of the via 18 for forming via wiring. Therefore, the resist resin used to form the resist layer 125 can be either positive or negative, but it is preferable to select a resist resin that satisfies the aforementioned required characteristics. Examples of preferred resist resins include the Photec PKG substrate circuit forming RY series (manufactured by Hitachi Chemical Co., Ltd.).

[0162] Next, using the patterned resist layer 125 as a mask, the Ni-based metal layer 123 exposed within the opening 126 is used as an electrode, and a copper-based metal pillar 127 is formed within the opening 126. Figure 6 (e)). In this example, the thickness of the metal pillar 127 is set to 25 μm. The thickness of the metal pillar 127 is directly related to the depth of the via 18 for forming the via wiring, and therefore the thickness of the metal pillar 127 is determined according to the required depth.

[0163] In addition, in this example, the metal pillar 127 is made of the same copper as the metal layer 123, but it can also be the same metal as the metal layer 123 or a different metal.

[0164] Furthermore, the metal pillar 127 is formed by electroplating, but it is not particularly limited to any method that can completely fill the opening 26. However, forming it by electroplating is the most efficient and cost-effective method.

[0165] Next, peel off the resist layer 125 ( Figure 6 (f)), the molding resin 128 that will become the insulating layer 17 is applied. Figure 6 (g)), then, the molding resin 128 is ground to expose the first end face, i.e., the upper surface, of the metal pillar 127 covered by the molding resin 128. Figure 6 (h)

[0166] As the molding resin 128, any resin material that forms the insulating layer 17 can be used, with a thickness sufficient to cover the metal pillar 127. The method of applying the molding resin 128 is not particularly limited; it can be done through vacuum printing, film lamination, compression molding using a mold, etc. In this example, molding resin R4212 manufactured by Nagase Chemtec was used, compressed at 120°C for 10 minutes, and then cured at 150°C for 1 hour to produce molding resin 128.

[0167] The grinding used to expose the upper surface of the metal pillar 27 can be performed using a general grinding machine such as a diamond tool.

[0168] Next, by etching away the metal pillar 127 and the metal layer 123, a through-hole 129 for forming a through-hole wiring 18, which will become the through-hole wiring forming substrate 1, is formed. Figure 6 (i)). Thus, a through-hole wiring forming substrate 1B is formed having a metal layer 16 and an insulating layer 17 on a support substrate 11 and a peelable adhesive layer 12, and having a through-hole wiring forming through-hole 18 that penetrates only the metal layer 16 and the insulating layer 17 (see reference). Figure 5 ).

[0169] As described above, since the opening 126 formed on the resist layer 125 by photolithography is transferred to the insulating layer 17 (molding resin 128) via the metal pillar 127, the size and position accuracy of the through hole 18 for forming the through-hole wiring has the accuracy that can be formed by photolithography, which is referred to as photolithography accuracy in this application.

[0170] In the above example, the insulating layer 17 is formed of a molding resin commonly used in molding, such as epoxy resin containing fillers like silica. However, it is generally impossible to form through-holes 18 with the aforementioned precision on such an insulating layer 17. Furthermore, in the above embodiment, the through-holes 18 penetrate the metal layer 16 together with the insulating layer 17, and since the through-holes in the insulating layer 17 and the metal layer 16 are formed by the above process, there is no misalignment and the inner walls are formed straight. In addition, multiple through-holes 18 are formed with photolithographic precision, which is a novel structure not previously seen.

[0171] Furthermore, as the material for the insulating layer 17, thermosetting resins such as epoxy resin or photocurable / thermosetting resins, which contain minimal or no fillers, can be used, as long as the desired strength, durability, and coefficient of thermal expansion are obtained. Since such materials have a higher surface smoothness than general molding resins, they offer advantages such as the ability to form fine wiring on the surface during the installation process described later; therefore, they can be used depending on the application. Additionally, photocurable + thermosetting resins are insulating layers that can be used by photocuring followed by thermocuring; however, although they are photocurable, it is not possible to directly form fine patterns such as through-holes for wiring.

[0172] (Installation Component Implementation Method 1)

[0173] Hereinafter, an example of a process for mounting a semiconductor chip on a through-hole wiring substrate 1 will be described with reference to the accompanying drawings.

[0174] First, refer to Figure 7 An example of a method for manufacturing a semiconductor chip with copper pads is illustrated.

[0175] like Figure 7 As shown in (a), a semiconductor chip 50 with aluminum pads 51 is prepared, and a seed metal layer 55 is disposed thereon. Figure 7 (b)). Next, a photosensitive resin layer 56 is set. Figure 7 (c) is exposed, developed, and patterned to form an opening 56a above the aluminum pad 51. Figure 7 (d)) A copper pad 52 is formed on the seed metal layer 55 within the opening 56a by electroplating. Figure 7 (e)), removing the photosensitive resin layer 56 ( Figure 7 (f) is used to remove the seed metal layer 55 by soft etching, thereby forming a semiconductor chip 50 with copper pads 52. Figure 7 (g)

[0176] Furthermore, the method for setting the copper pad 52 is not limited to the methods described above. For example, the copper pad 52 is not limited to copper electroplating; it can also be formed by sputtering seed metal onto the aluminum pad 51, then applying copper paste and metallizing it, or by directly applying copper paste onto the aluminum pad 51 and metallizing it. In any case, compared to the columnar electrical connectors of InFO described in the prior art, the process can be significantly reduced.

[0177] Next, the process of mounting a semiconductor chip 50 with such copper pads 52 onto the via wiring forming substrate 1 of the present invention will be described. Furthermore, the via wiring forming substrate 1 of the present invention has a first insulating layer 13 and a second insulating layer 14 on a support substrate 11 and a peelable adhesive layer 12, and has via wiring forming vias 15 that penetrate only the first insulating layer 13 and the second insulating layer 14. However, the first insulating layer 13 is an epoxy molding resin, and the second insulating layer 14 is a non-flowing adhesive layer (NFA).

[0178] Furthermore, the through-hole wiring forming via 15, which penetrates only the first insulating layer 13 and the second insulating layer 14, is formed in a manner that matches the position of the connection terminal of the semiconductor chip 50.

[0179] With the copper pad 52 aligned with the through-hole wiring forming through-hole 15, the semiconductor chip 50 is bonded to the second insulating layer 14, which serves as the NFA. Figure 8 (a) Specifically, following conventional methods, temporary bonding is performed while heating / pressurizing each semiconductor chip 50, and formal bonding is performed while positioning the entire assembly and applying pressure and heat.

[0180] Next, a molding resin layer 41 is formed so that the embedded semiconductor chip 50 ( Figure 8 (b)). As the molding resin layer 41, it can be formed from a molding resin or the like, in which a thermosetting resin such as epoxy resin is filled with filler, and in particular, an epoxy-based sealing resin can be used. The molding resin layer 41 is in direct contact with the active surface of the semiconductor chip 50, so a low-impurity, halogen-free material is required. In addition, since it is not a process with a fine pitch, it can contain filler larger than the resin material used in the first insulating layer 13. For example, a thermosetting resin containing filler with a maximum particle size of 5 μm to 50 μm can be used.

[0181] Alternatively, a support substrate can be provided via a peelable adhesive layer after the molding resin layer 41 has been applied. This support substrate is used to improve the operability after peeling off the support substrate 11 in the next process, and is peeled off in the final process to form a product, but it is omitted from the illustration in any case.

[0182] Next, the support substrate 11 is peeled off via the peelable adhesive layer 12. Figure 8 (c) When using UV release tape SELFA-HW (manufactured by Sekisui Chemicals Co., Ltd.) as the peelable adhesive layer 12, the support substrate 11 can be peeled off by UV irradiation.

[0183] Next, through-hole wiring 59 is formed in the through-hole 15 by electroplating. Figure 8(d) Specifically, after providing chemical copper seeds or sputtering seeds in the through-hole 15 for forming through-hole wiring, the through-hole wiring 59 is formed by electroplating. In addition, the wiring layer formed on the surface of the insulating layer 13 is patterned to a given size to form the through-hole wiring 59.

[0184] Here, the formation of the through-hole wiring 59 is not limited to electroplating. For example, a conductive paste including copper can be filled into the through-hole 15 for forming the through-hole wiring to form the through-hole wiring 59.

[0185] Furthermore, the via wiring 59 can also be formed by pattern plating. In pattern plating, after setting a copper seed layer, after patterning the plating resist layer, the via wiring 59 can be formed in the via 15 for via wiring formation by pattern electroplating through the plating resist layer. The plating resist is then stripped off, and the seed layer other than the lower layer of the via wiring 59 is removed by soft etching to form the via wiring 59.

[0186] In addition, when the through-hole wiring 59 is formed by the pattern plating method, it is not necessary to set the aluminum pad 51 of the semiconductor chip 50 as the copper pad 52. The semiconductor 50 can be mounted with the aluminum pad 51 as is.

[0187] Next, as Figure 8 As shown in (e), multiple redistribution layers 70 (three layers in the illustration) are formed on the insulating layer 13 where the through-hole wiring 59 is formed, using conventional methods, to form a semiconductor chip mounting component 3. The semiconductor chip mounting component 3 is the semiconductor component mounting component of this embodiment.

[0188] If the via wiring forming substrate 1 of the present invention is used, vias 15 for via wiring forming can be formed with high precision according to semiconductor chips and functional components having high-density connection terminals, so various semiconductor chips and functional components can be easily mounted. In addition, since multiple semiconductor chips 50 and functional components are molded after the bonding terminal side is bonded to the via wiring forming substrate 1, it has the advantage that even if the heights of multiple semiconductor chips 50 and functional components are different, they can be easily mounted.

[0189] Figure 9 An example of this installation is shown in the figure. Figure 9 (a) shows a case where semiconductor chips 501 and 502 of different heights are mounted on the through-hole wiring forming substrate 1 of the present invention. Figure 9(b) shows the case where semiconductor chip 501 and passive component 510 are mounted. In any of these cases, since the terminal sides of semiconductor chips 501, 502 and passive component 510 are bonded to the through-hole wiring forming substrate 1 of the present invention, semiconductor chips 501, 502 and passive component 510 are not a problem.

[0190] On the other hand, in the InFO described in the prior art, the cylindrical electrical connector 108 and the electrical connector 112 on the semiconductor chip 110 need to be molded together, and then the upper surface needs to be exposed by grinding. The higher the wiring density, the greater the difficulty, and the connection with the rewiring layer also becomes more difficult. In addition, the height limit of the cylindrical electrical connector 108 is about 150μm to 200μm. When the height of the semiconductor chip 110 is large, it may become difficult to manufacture. Furthermore, when multiple semiconductor chips are initially mounted, if the heights of the semiconductor chips are different, the cylindrical electrical connector of one semiconductor chip needs to be lengthened, which presents a difficult problem to solve.

[0191] Furthermore, when using the through-hole wiring forming substrate 1 of the present invention, since there is a relatively rigid first insulating layer 13 between the redistribution layer 70 and the semiconductor chip 50, it is difficult for the redistribution layer 70 to crack even if multiple redistribution layers 70 are provided on the first insulating layer 13. Furthermore, since there is a second insulating layer 14 with lower elasticity than the first insulating layer 13 between the relatively rigid first insulating layer 13 and the semiconductor chip 50, it is difficult for the redistribution layer 70 to further crack even if multiple redistribution layers 70 are provided on the first insulating layer 13.

[0192] (Installation Component Implementation Method 2)

[0193] Next, an example of a process for mounting a semiconductor chip on a through-hole wiring substrate 1A will be described with reference to the accompanying drawings.

[0194] For the substrate 1A for forming through-hole wiring, since the second insulating layer 14A on the surface is not a non-flowing adhesive layer (NFA), it is necessary to set the NFA on the semiconductor chip.

[0195] Reference Figure 10 To illustrate this process.

[0196] like Figure 10 As shown, preparations are made to have... Figure 9 The semiconductor chip 50 with copper pads 52 manufactured using the process shown is then followed by the application of an adhesive layer 61 to cover the copper pads 52 using a non-flowing adhesive with relatively low flowability. Figure 10(a) After that, the copper pads 52 are ejected through a grinding process, thereby forming a semiconductor chip 50A with an adhesive layer 61. Figure 10 (b)

[0197] Next, the process of mounting the semiconductor chip 50A onto the through-hole wiring forming substrate 1A will be described. With the copper pad 52 aligned with the through-hole 15 for through-hole wiring forming, the semiconductor chip 50A is bonded to the second insulating layer 14A using the adhesive layer 61. Figure 11 (a)

[0198] Next, a molding resin layer 41 is formed so that the semiconductor chip 50A is embedded. Figure 11 (b)). As the molding resin layer 41, with Figure 8 The same process is used in the same way.

[0199] Alternatively, a support substrate can be provided via a peelable adhesive layer after the molding resin layer 41 has been applied. This support substrate is used to improve the operability after peeling off the support substrate 11 in the next process, and is peeled off in the final process to form a product, but it is omitted from the illustration in any case.

[0200] Next, the support substrate 11 is peeled off via the peelable adhesive layer 12. Figure 11 (c) That is, when using UV release tape SELFA-HW (manufactured by Sekisui Chemicals Co., Ltd.) as the peelable adhesive layer 12, the support substrate 11 can be peeled off by UV irradiation.

[0201] Next, through-hole wiring is formed in the through-hole 15 by electroplating. Specifically, a seed layer 57 composed of chemical copper seeds or sputtered seeds is provided in the through-hole 15. Figure 11 (d)), then, a wiring layer 58 including through-hole wiring is formed by electroplating. Figure 11 (e)). Additionally, the wiring layer 58 formed on the surface of the insulating layer 13 is patterned to a given size to create through-hole wiring 59. Figure 11 (f)

[0202] Next, as Figure 11As shown in (g), a plurality of redistribution layers 70 (three layers in the illustration) are formed on the second insulating layer 14A on which the through-hole wiring 59 is formed, using conventional methods, to form a semiconductor chip mounting component 3A having through-hole wiring 91 on its surface. The semiconductor chip mounting component 3A is a semiconductor device mounting component of this embodiment. Furthermore, the redistribution layer 70 is composed of a redistribution insulating layer, through-hole wiring penetrating the redistribution insulating layer, and wiring patterns provided on the redistribution insulating layer. In addition, as the redistribution insulating layer, a photosensitive resin such as photosensitive polyimide resin or a thermosetting resin can be used. When using a non-photosensitive resin, patterning such as through-hole formation is performed by laser processing or the like.

[0203] (Modification 1 of the implementation of the mounting component)

[0204] exist Figure 12 The diagram shows a comparison between the semiconductor chip mounting component 3 of the present invention manufactured in mounting component embodiment 1 and mounting component embodiment 2 and the conventional eWLP (Embedded Wafer Level Package) structure.

[0205] exist Figure 12 In the conventional eWLP structure of (b), the redistribution layer 700 is directly disposed on the molding resin layer 410 of the molded semiconductor chip 50. On the other hand, in Figure 12 In the semiconductor chip mounting component 3 of the present invention shown in (a), a relatively low elasticity second insulating layer 14 and a relatively high elasticity and rigid first insulating layer 13 are disposed between the molding resin layer 41 and the redistribution layer 70 from the side of the molding resin layer 41, thereby making it difficult for the redistribution layer 70 to crack.

[0206] In addition to the standard usage methods of embodiments 3 and 4, the through-hole wiring forming substrates 1 and 1A of embodiments 1 and 2 can also be used for various other applications.

[0207] For example, such as Figure 13 As shown in (a), a second insulating layer 14 and a first insulating layer 13 can also be provided between multiple redistribution layers 70 of the semiconductor chip mounting component 3 in embodiments 3 and 4 using a via wiring forming substrate 1. A via wiring 92 is provided on the uppermost surface. In this case, crack prevention of the redistribution layers 70 can be achieved, and more redistribution layers 70 can be stacked than in the past. For example, if 3 to 4 or more redistribution layers 70 are stacked, cracks may occur, but by providing a component consisting of the second insulating layer 14 and the first insulating layer 13 in the middle to support the stack, especially due to the presence of the rigid first insulating layer 13, it is advantageous to prevent crack formation.

[0208] Furthermore, if the redistribution layer 70 is configured as multiple layers, it has the advantage of being able to increase the spacing of via routing. Figure 13 In case (a), for example, the spacing P1 of the semiconductor chip 50 is set to about 40 μm to 100 μm, and the spacing P2 of the uppermost surface can be increased to about 300 μm to 500 μm.

[0209] In addition, such as Figure 13 As shown in (b), there is also a method of using a through-hole wiring forming substrate 1 to provide a second insulating layer 14 and a first insulating layer 13 on the surface of the semiconductor chip mounting component 3 in embodiments 3 and 4. This method can replace the solder resist that is usually provided on the surface of the mounting component. This method is possible because the component support stack can be made very thin, and the positional accuracy of the through holes is good, so it can handle fine wiring structures in the same way as photosensitive solder resist. In addition, it cannot be achieved by mechanical processing such as drilling or laser processing. Furthermore, the presence of a rigid first insulating layer 13 on the surface has the effect of preventing cracks in the redistribution layer 70. In addition, the through-hole wiring forming through-hole 15 is used to connect to the through-hole wiring 91.

[0210] Furthermore, in addition to the conventional mounting structure, the through-hole wiring forming substrates 1 and 1A of embodiments 1 and 2 can also be used.

[0211] For example, such as Figure 14 As shown in (a), it can also be set in the previous eWLP500 (see reference). Figure 14 In (b)), a second insulating layer 14 and a first insulating layer 13 are provided in the middle of the multiple redistribution layers 700 using a through-hole wiring substrate 1, and through-hole wiring 93 is provided through the redistribution layer 70 on the first insulating layer 13.

[0212] In addition, such as Figure 14 As shown in (b), a second insulating layer 14 and a first insulating layer 13 can also be formed on the surface of the eWLP500 using a through-hole wiring substrate 1 to form through-hole wiring 94, and then, as Figure 14 As shown in (c), it is also possible to set the second insulating layer 14 and the first insulating layer 13 on the surface of the eWLP500 using a through-hole wiring forming substrate 1, and use the through-hole wiring forming through-hole 15 as a connection to the terminal of the eWLP500.

[0213] Furthermore, for the through-hole wiring forming substrates 1 and 1A of embodiments 1 and 2, for example, an eWLP500 (see reference) can also be mounted. Figure 14 (b) is used to replace the installation of semiconductor chips.

[0214] exist Figure 15An example of this manufacturing process is shown below. For example... Figure 15 As shown in (a), prepare the eWLP500, as follows: Figure 15 As shown in (b), the eWLP500 is mounted and bonded on the through-hole wiring forming substrate 1.

[0215] Next, similarly to the above embodiment, eWLP500 is molded using molding resin layer 41. Figure 15 (c)).

[0216] Alternatively, a support substrate can be provided via a peelable adhesive layer after the molding resin layer 41 has been applied. This support substrate is used to improve the operability after peeling off the support substrate 11 in the next process, and is peeled off in the final process to form a product, but it is omitted from the illustration in any case.

[0217] Next, the support substrate 11 is peeled off via the peelable adhesive layer 12. Figure 15 (d) Next, within the through-hole 15 for forming through-hole wiring, through-hole wiring 95 is formed by electroplating or the like. Figure 15 (e)). Next, as Figure 15 As shown in (f), multiple redistribution layers 70 (3 layers in the figure) are formed on the insulating layer 13 on which through-hole wiring 95 is formed by conventional methods, thereby forming a semiconductor chip mounting component with through-hole wiring 97 on the uppermost surface.

[0218] The above describes the semiconductor component mounting process and various semiconductor component mounting components. However, in any case, the via 15 for forming via wiring and the copper pad 52 correspond one-to-one, and the via wiring 59 fills the entire via wiring via 15, but is not limited to this.

[0219] Summarizing the characteristics of the construction in the above examples, Figure 16 As shown in the image. Figure 16 As shown in (a), a through-hole wiring 15 is formed corresponding to a copper pad 52 of the semiconductor chip 50 molded by the molding resin layer 41, and the through-hole wiring 59 is configured to fill the through-hole wiring 15. Furthermore, in this case, as... Figure 16 As shown in (b), generally, a rewiring insulating layer 81 made of photosensitive resin, thermosetting resin, or the like is formed on the first insulating layer 13, which includes the through-hole wiring 59. Through-hole wiring 83, connected to the through-hole wiring 59, is formed in a through-hole 82 formed in the rewiring insulating layer 81 at a position opposite to the through-hole wiring 59. Alternatively, in practice, wiring (not shown) connected to the through-hole wiring 83 is formed on the rewiring insulating layer 81, constituting a rewiring layer 80.

[0220] Figure 17This is another example illustrating a one-to-one correspondence between through-hole routing and copper pad 52. For example... Figure 17 As shown in (a), a rewiring insulation layer 81A is formed on the periphery of the through-hole 15 for forming through-hole wiring and on the first insulating layer 13, and a through-hole 82A is provided on the portion of the rewiring insulation layer 81A opposite to the copper pad 52. Furthermore, as... Figure 17 As shown in (b), a through-hole wiring 83A connected to a copper pad 52 is provided in a through-hole 82A provided in a rerouting insulating layer 81A within a through-hole wiring forming through-hole 15. Additionally, a wiring (not shown) connected to the through-hole wiring 83A is actually formed on the rerouting insulating layer 81A, constituting a rerouting layer 80A.

[0221] Figure 16 as well as Figure 17 This refers to the case where through-hole wiring is formed by a one-to-one correspondence between through-hole 15 and copper pad 52. Figure 18 as well as Figure 19 The image shows an example of a one-to-many correspondence.

[0222] exist Figure 18 as well as Figure 19 In the process, the semiconductor chip molded by the molding resin layer 41 is a region pad type semiconductor chip 51A, and the through hole wiring forming through hole 15A is formed to have a shape corresponding to a rectangular region 53 on which a plurality of copper pads 52 of the region pad type are provided. Figure 18 It is a state in which an insulating layer for rewiring is formed. Figure 19 It is a state with wiring formed. (a) is a top view, and (b) is the bb′ section corresponding to (a).

[0223] As shown in the accompanying drawings, a rewiring insulating layer 81B is provided on a first insulating layer 15 including a through-hole 15A corresponding to the rectangular region 53, and a through-hole 82B is provided at each of the rewiring insulating layers 81B opposite to each of the plurality of copper pads 52. Furthermore, a through-hole wiring 83B connected to the copper pads 52 is provided within the through-hole 82B, and a wiring 84B for rewiring the through-hole wiring 83B is provided, thereby forming a rewiring layer 80B. This is an example of a semiconductor device mounting component of the present invention.

[0224] Figure 20 as well as Figure 21 Other examples illustrating the case where through-hole wiring is formed with through-hole 15 and copper pad 52 in a one-to-many correspondence.

[0225] exist Figure 20 as well as Figure 21In the process, the semiconductor chip molded by the molding resin layer 41 is a peripheral pad type semiconductor chip 51B, and the through-hole wiring forming through-hole 15B is formed in a shape corresponding to the rectangular annular peripheral region 54 on which a plurality of peripheral pads 52 are provided. Figure 20 It is a state in which an insulating layer for rewiring is formed. Figure 21 It is a state with wiring formed. (a) is a top view, and (b) and (c) correspond to the bb′ section and cc′ section of (a).

[0226] As shown in the accompanying drawings, a rewiring insulating layer 81C is provided on a first insulating layer 15 including a through-hole 15B corresponding to a rectangular annular peripheral region 54. Through-holes 82C are provided in the rewiring insulating layer 81C at positions opposite to each of the plurality of copper pads 52. Furthermore, through-hole wiring 83C connected to the copper pads 52 is provided within the through-holes 82C, and wiring 84C rewiring the through-hole wiring 83C is provided, thereby forming a rewiring layer 80C. This is an example of a semiconductor device mounting component of the present invention.

[0227] Figure 22 This illustration shows a mounting process for an example of a semiconductor component mounting component according to the present invention. This example shows a through-hole wiring forming substrate 1B (see Figure 3) using substrate embodiment 3. Figure 5 Semiconductor component mounting components.

[0228] Figure 22 (a) shows that will have Figure 10 The state is shown where the semiconductor chip 50A is bonded to the through-hole wiring forming substrate 1B with adhesive layer 61, the semiconductor chip 50A is molded by molding resin layer 41, and then the support substrate 1 is peeled off. The state is also shown where the semiconductor chip 50A is mounted in the component mounting laminate. Next, as... Figure 22 As shown in (b), a redistribution insulating layer 81D is provided on the metal layer 17, including the through-hole 18 for forming the through-hole, as... Figure 22 As shown in (c), a through-hole 82D exposing the copper pad 52 and a grounding through-hole 85D exposing the metal layer 17 are formed at a position opposite to the copper pad 52. Furthermore, as... Figure 22 As shown in (d), a through-hole wiring 83D connected to the copper pad 52 and a wiring 84D for rewiring the through-hole wiring 83D are formed in the through-hole 82D. Furthermore, a ground wiring 86D connected to the metal layer 17 is provided in the grounding through-hole 85D. Thus, a rewiring layer 80D having a second wiring 86D connected to the metal layer 17 is formed.

[0229] In this semiconductor component mounting component, the metal layer 17 can be used as a grounding wiring, a shielding layer for semiconductor chips, and a heat dissipation layer for dissipating heat from semiconductor chips.

[0230] (Substrate Embodiment 4)

[0231] Reference Figure 23 The present invention describes a through-hole wiring forming substrate 1B having a metal layer 16 and an insulating layer 17 on a peelable adhesive layer 12 provided on one side of a support substrate 11, and having a plurality of through-hole wiring forming through-holes 18 that penetrate only the metal layer 16 and the insulating layer 17. As a variation thereof, an embodiment in which the metal layer 16 is omitted is described.

[0232] Figure 23 This is a cross-sectional view of the substrate for forming through-hole wiring according to Embodiment 4. Figure 24 This is a cross-sectional view showing the manufacturing process of a substrate for forming through-hole wiring.

[0233] Figure 23 The through-hole wiring forming substrate 1C shown includes: a support substrate 11, a peelable adhesive layer 12 disposed on one side of the support substrate 11, and an insulating layer 17 disposed on the peelable adhesive layer 12, and a plurality of through-hole wiring forming through-holes 18 formed therethrough only through the insulating layer 17.

[0234] exist Figure 24 The manufacturing process of substrate 1A for forming through-hole wiring is shown in the figure.

[0235] like Figure 24 As shown in (a), firstly, in Figure 6 After step (i), the support substrate 11 is bonded to the opposite side of the support substrate 121 via a peelable adhesive layer 12. The support substrate 11 and the peelable adhesive layer 12 can be made of the same material as the support substrate 121 and the peelable adhesive layer 122.

[0236] Next, peel off the support substrate 11 and the peelable adhesive layer 12. Figure 24 (b)). Furthermore, by etching away the metal layer 123 and the metal pillars 127, a through-hole wiring substrate 1C is formed. Figure 24 (c)).

[0237] (Substrate Embodiment 5)

[0238] Figure 25 This is a cross-sectional view of the substrate for forming through-hole wiring according to substrate embodiment 5. Figure 26 This is a cross-sectional view showing the manufacturing process of a substrate for forming through-hole wiring.

[0239] The through-hole wiring forming substrate 1D of this embodiment includes: a peelable adhesive layer 12 disposed on one side of a support substrate 11, two metal layers 19 and 20 disposed on the peelable adhesive layer 12, and an insulating layer 17, and has a plurality of through-hole wiring forming vias 18 that penetrate only the metal layers 19, 20 and 17.

[0240] Here, metal layer 20 can be used for wiring that can connect to the formed via wiring after the semiconductor chip is mounted, thus simplifying the post-mounting process. Furthermore, metal layers 19 and 20 preferably have different etching characteristics, and it is preferable that metal layer 20 is retained and only metal layer 19 is removed after the semiconductor chip is mounted. Moreover, considering its relationship with the resist layer that serves as a mask, etching with an acidic etchant is preferred. Therefore, when using nickel as metal layer 19, if metal layer 20 is considered as a wiring layer, it is preferable to use copper.

[0241] The following is for reference Figure 26 Here is an example illustrating the manufacturing process of a substrate 1D for forming through-hole wiring.

[0242] First, for example, prepare a glass support substrate 221 ( Figure 26 (a)) has a peelable adhesive layer 222 on one side thereon. Figure 26 (b)). The peelable adhesive layer 222 can also be applied by coating a sheet adhesive layer, but here a JV release tape SELFA-SE (manufactured by Sekisui Chemicals) is applied.

[0243] Next, metal layers 223 and 224 are disposed on the peelable adhesive layer 222. Figure 26 (c) The method of forming metal layer 223 and metal layer 224 is not particularly limited. There are no particular limitations on the film formation under various vapor phase methods, film formation by plating methods, or methods of attaching foils or sheets. However, from the perspective of work efficiency, it is preferable to attach commercially available double-layer metal sheets.

[0244] In this example, a double-layer metal foil is attached, with Ni as metal layer 223 and Cu as metal layer 224. Furthermore, in this example, the Ni thickness of metal layer 223 is 0.5 μm, and the Cu thickness of metal layer 224 is 3 μm. The thickness of metal layer 223 is not particularly limited; approximately 0.5 μm to 5 μm is sufficient, and anything thicker would be wasteful. On the other hand, the thickness of metal layer 224 can be set to the thickness required for the wiring layer, for example, 3.5 μm to 10 μm.

[0245] Next, a resist layer 225 is formed on the metal layer 224. Using conventional methods, an opening 226 is formed through the resist layer 225 by photoresist patterning to create a given pattern. Figure 26 (d) The thickness of the resist layer 225, while not directly affecting the thickness of the insulating layer 17 of the through-hole wiring substrate 1, also influences its patterning characteristics, namely, the shape (aperture and perpendicularity) of the opening 226 is transferred to the shape of the through-hole 18 for through-hole wiring formation. Therefore, the resist resin used to form the resist layer 225 can be either positive or negative, but it is preferable to select a resist resin that satisfies the aforementioned required characteristics. Examples of preferred resist resins include the Photec PKG substrate circuit formation RY series (manufactured by Hitachi Chemical Co., Ltd.).

[0246] Here, the thickness of the resist layer 225 is set to 35 μm, and the diameter of the opening 226 is set to 30 μm.

[0247] Regarding exposure, it refers to irradiation with 100–300 mJ / cm². 2 The process involves UV spraying with a 1% Na2CO3 solution for 30 seconds for development and patterning.

[0248] Next, using the patterned resist layer 225 as a mask, only the Cu-based metal layer 224 exposed within the opening 226 is etched to form an opening 224a continuous with the opening 226. Figure 26 (e)).

[0249] Next, using the patterned resist layer 225 as a mask, and the exposed Ni metal layer 223 in the openings 226 and 224a as electrodes, a nickel metal pillar 227 is formed in the openings 226 and 224a by electroplating. Figure 26 (f)). At this time, since a metal layer 224 made of copper with excellent conductivity is formed on the metal layer 223 up to the vicinity of the opening 226, no voltage drop of metal electroplating will occur, which has the advantage of being able to effectively form the metal pillar 227.

[0250] In this example, the thickness of the metal pillar 227 is set to 25 μm. Since the thickness of the metal pillar 227 is directly related to the depth of the via 18 for forming the via wiring, the thickness of the metal pillar 227 is determined according to the required depth.

[0251] Next, peel off the resist layer 225 ( Figure 26 (g)), the molding resin 228 that will become the insulating layer 17 is coated. Figure 26 (h)), then, the molding resin 228 is ground so that the first end face, i.e. the upper surface, of the metal pillar 227 covered by the molding resin 228 is exposed. Figure 26(i)

[0252] As the molding resin 228, any resin material that forms the insulating layer 17 can be used, with a thickness set to cover the metal pillar 227. The application method of the molding resin 228 is not particularly limited and can be performed by vacuum printing, film lamination, compression molding using a mold, etc. In this example, R4212 molding resin manufactured by Nagase Chemtec was used, compressed at 120°C for 10 minutes, and then cured at 150°C for 1 hour to produce the first molding resin 228.

[0253] Furthermore, the grinding used to expose the upper surface of the metal pillar 227 can be performed using a general grinding machine such as a diamond tool.

[0254] Next, by etching away the metal pillars 227 and the metal layer 223, a through-hole 229 is formed, which becomes the through-hole wiring 18 of the through-hole wiring forming substrate 1. Figure 26 (j)). Thus, a through-hole wiring forming substrate 1D (refer to) is formed having a metal layer 19, a metal layer 20, and an insulating layer 17 on a support substrate 11 and a peelable adhesive layer 12, and having a through-hole wiring forming through-hole 18 that penetrates only the metal layer 19, the metal layer 20, and the insulating layer 17. Figure 25 ).

[0255] (Modification 2 of the implementation of the mounting component)

[0256] Hereinafter, an example of a process for mounting a semiconductor chip on a through-hole wiring substrate 1B to 1D will be described with reference to the accompanying drawings.

[0257] In this embodiment, an installation having Figure 10 The semiconductor chip 50A with the adhesive layer shown.

[0258] First, the process of mounting a semiconductor chip 50A having such copper pads 52 and adhesive layer 61 onto the via wiring forming substrate 1B of the present invention will be described. Furthermore, the via wiring forming substrate 1B of the present invention has a metal layer 16 and an insulating layer 17 on a support substrate 11 and a peelable adhesive layer 12, and has a via wiring forming via 18 that penetrates only the metal layer 16 and the insulating layer 17.

[0259] Next, with the copper pad 52 aligned with the via 18 forming the via wiring, the semiconductor chip 50A is bonded to the insulating layer 17 using the adhesive layer 61. Figure 27(a) Specifically, according to conventional methods, each semiconductor chip 50 is positioned while being heated / pressurized for temporary bonding, and the entire assembly is positioned while being pressurized and heated for formal bonding.

[0260] Next, a molding resin layer 71 is formed to embed the semiconductor chip 50. Figure 27 (b)). As the molding resin layer 71, it can be formed from a molding resin or the like, in which a thermosetting resin such as epoxy resin is filled with filler, and in particular, an epoxy-based sealing resin can be used. The molding resin layer 71 is in direct contact with the active surface of the semiconductor chip 50A, so a low-impurity, halogen-free material is required. In addition, since it is not a process with a fine pitch, it can contain fillers larger than the resin material used in the insulating layer 17. For example, a thermosetting resin containing fillers with a maximum particle size of 30 μm to 50 μm can be used.

[0261] Alternatively, a support substrate can be provided via a peelable adhesive layer after the molding resin layer 71 has been provided. This support substrate is used to improve the operability after peeling off the first support substrate 11 in the next process, and is peeled off in the final process to form a product, but it is omitted from the illustration in any case.

[0262] Next, the support substrate 11 is peeled off via the peelable adhesive layer 12. Figure 27 (c) That is, when using JV release tape SELFA-SE (manufactured by Sekisui Chemicals Co., Ltd.) as the peelable adhesive layer 12, the support substrate 11 can be peeled off by UV irradiation.

[0263] Next, for example, the metal layer 16 made of Ni is removed by etching. Figure 27 (d) Here, the metal layer 16 is made of Ni, so it does not affect the copper pad 52 and can be etched using an acidic etching solution, such as hydrochloric acid solution, sulfuric acid or sulfuric acid hydrogen peroxide (H2SO4-H2O2).

[0264] Next, through-hole wiring is formed in the through-hole 18 by electroplating. Specifically, a seed layer 57 composed of chemical copper seeds or sputtered seeds is provided in the through-hole 18. Figure 27 (e)), then, a wiring layer 58 including through-hole wiring is formed by electroplating. Figure 27 (f)). Additionally, the wiring layer 58 formed on the surface of the insulating layer 17 is patterned to a given size to create through-hole wiring 59. Figure 27 (g)

[0265] Next, as Figure 27As shown in (h), multiple redistribution layers 80 (three layers in the illustration) are formed on the insulating layer 17 where the through-hole wiring 59 is formed, using conventional methods, to create a semiconductor chip mounting component 3C. Furthermore, each redistribution layer 80 consists of an insulating layer, through-hole wiring penetrating the insulating layer, and wiring patterns 91 disposed on the insulating layer. Additionally, a photosensitive resin such as photosensitive polyimide resin or a thermosetting resin is used as the insulating layer.

[0266] In addition, Figure 27 (a)~ Figure 27 In (g), only the connection terminal 51 of a semiconductor chip 50A is shown, but... Figure 27 In (h), multiple connection terminals 51 are shown. Furthermore, multiple semiconductor chips 50A can be configured on a through-hole wiring substrate 1, and other functional components can be mounted together with the semiconductor chips 50.

[0267] In any case, by using the via wiring forming substrate 1 of the present invention, via wiring forming vias 18 can be formed with high precision according to semiconductor chips and functional components having high-density connection terminals, thus allowing easy mounting of various semiconductor chips and functional components. Furthermore, since multiple semiconductor chips 50 and functional components are molded after the bonding terminal side is bonded to the via wiring forming substrate 1, it has the advantage that even if the heights of the multiple semiconductor chips 50A and functional components are different, they can be easily mounted.

[0268] exist Figure 28 An example of this installation is shown in the figure. Figure 28 (a) is the case where semiconductor chips 501A and 502A of different heights are mounted on the through-hole wiring forming substrate 1 of the present invention. Figure 28 (b) shows the case where semiconductor chip 501A and passive component 510A are mounted. In any of these cases, since the terminal sides of semiconductor chips 501A, 502A and passive component 510A are bonded to the through-hole wiring forming substrate 1 of the present invention, semiconductor chips 501A, 502A and passive component 510A are not a problem.

[0269] On the other hand, in the InFO described in the prior art, the cylindrical electrical connector 108 and the electrical connector 112 on the semiconductor chip 110 need to be molded together, and then the upper surface needs to be exposed by grinding. The higher the wiring density, the greater the difficulty, and the connection with the rewiring layer also becomes more difficult. In addition, the height limit of the cylindrical electrical connector 108 is about 150 to 200 μm. When the height of the semiconductor chip 110 is large, it may become difficult to manufacture. Furthermore, when multiple semiconductor chips are initially installed, if the heights of the semiconductor chips are different, the electrical connector of one semiconductor chip needs to be cylindrical, etc., which presents a difficult problem to solve.

[0270] In addition, the method for mounting a semiconductor chip using a through-hole wiring substrate 1A is the same as the example above, except that there is no removal process for the metal layer 13, so detailed descriptions are omitted.

[0271] (Modification 3 of the implementation of the mounting component)

[0272] The following is for reference Figure 29 Other examples of processes for mounting semiconductor chips on a through-hole wiring substrate 1D are described.

[0273] A through-hole wiring forming substrate 1D of the present invention is prepared. The through-hole wiring forming substrate 1D has a metal layer 19, a metal layer 20, and an insulating layer 17 on a support substrate 11 and a peelable adhesive layer 12, and has a through-hole 18 for through-hole wiring forming that penetrates only the metal layer 19, the metal layer 20, and the insulating layer 17.

[0274] Next, with the copper pad 52 aligned with the via 18 forming the via wiring, the semiconductor chip 50A is bonded to the insulating layer 17 using the adhesive layer 61. Figure 29 (a)

[0275] Next, the molding resin layer 71 is set so that the semiconductor chip 50A is embedded. Figure 29 (b)). As the molding resin layer 71, it can be formed from a molding resin or the like that in which a filler is filled in a thermosetting resin filler such as epoxy resin, and in particular, an epoxy-based sealing resin can be used.

[0276] Next, the support substrate 11 is peeled off via the peelable adhesive layer 12. Figure 29 (c) That is, when using JV release tape SELFA-SE (manufactured by Sekisui Chemicals Co., Ltd.) as the peelable adhesive layer 12, the support substrate 11 can be peeled off by UV irradiation.

[0277] Next, for example, the metal layer 19 composed of Ni is removed by etching. Figure 29(d) Here, the metal layer 19 is made of Ni, so it does not affect the copper pad 52 and can be etched using an acidic etching solution, such as hydrochloric acid solution, sulfuric acid or sulfuric acid hydrogen peroxide (H2SO4-H2O2).

[0278] Next, through-hole wiring is formed in the through-hole 18 by electroplating. Specifically, in this embodiment, a conductive paste including copper is filled into the through-hole 18 to form through-hole wiring 66. Figure 29 (e)). Of course, as mentioned above, it is also possible to form the via by electroplating after placing a chemical copper sheet or sputtering seed in the via 18 for forming the via wiring.

[0279] Next, the raised portion 66a of the through-hole wiring 66 is ground. Figure 29 (f) The metal layer 14 on the insulating layer 17 is patterned in a given manner to form a through-hole wiring 67 and to form the desired wiring pattern 68. In addition, the protrusions 66a of the through-hole wiring 66 can be directly retained, which has the advantage that the conduction between the through-hole wiring and the surface wiring layer becomes more reliable.

[0280] In addition, in the next step, the same as in the above embodiment, multiple rewiring layers are formed on the insulating layer 17 on which the through-hole wiring 67 and wiring pattern 68 are formed by conventional methods, thereby enabling the semiconductor chip mounting component to be manufactured.

[0281] In this case, in this embodiment, since wiring can be directly formed on the insulating layer 17, it has the advantage of further omitting the rewiring layer. Other effects are the same as in the examples described above.

[0282] If a through-hole wiring forming substrate 1D is used, having a copper metal layer 20 beneath an insulating layer 17 made of filler-added molding resin, then after installation, if the support substrate 11 is removed, the copper metal layer 20 remains on the insulating layer 17, offering significant advantages in terms of its suitability for wiring. That is, while the surface smoothness of the filler-added insulating layer 17 is not excellent, resulting in poor adhesion to the wiring layer and difficulty in forming the wiring layer and performing micro-processing, in this case, since it is present from the formation of the insulating layer 17, the adhesion is good, and micro-processing is also possible. Therefore, various applications can be considered, and the following are some examples.

[0283] (Modification 4 of the implementation of the mounting component)

[0284] Reference Figure 30 Other examples of a process for mounting a semiconductor chip onto a through-hole wiring substrate 1D will be described. This process is different from variation 3 of the mounting component embodiment. Figure 29 (a)~ Figure 29 The process of (d) is the same, so the subsequent process is shown.

[0285] First, such as Figure 30 As shown in (a), a seed layer 57 is set, and then electroplating is performed to embed through-hole wiring forming vias 18, forming a wiring layer 58. Figure 30 (b)

[0286] Next, a resist layer is applied and a patterned resist layer 75 is formed. Figure 30 (c) Patterning is performed on wiring layer 58 and metal layer 14 to form via wiring 59 and wiring 60. Figure 30 (d)

[0287] The process for forming this wiring 60 is not limited to this; for example, it can also be as follows: Figure 31 As shown.

[0288] Figure 31 Implementation method 5 is also shown. Figure 29 (a)~ Figure 29 The process following process (d), such as Figure 31 As shown in (a), after setting the seed layer 57, a resist layer is first set, and a patterned resist layer 75 is formed. Then, electroplating is performed to embed through-hole wiring 18, thereby forming through-hole wiring 59 and wiring 60. Figure 31 (b) Finally, remove the resist layer 75, the seed layer 57 below the resist layer 75, and the metal layer 14. Figure 31 (c)).

[0289] (Modification 5 of the implementation of the mounting component)

[0290] Reference Figure 32 Other examples of a process for mounting a semiconductor chip onto a through-hole wiring substrate 1D will be described. This process is different from variation 3 of the mounting component embodiment. Figure 29 (a)~ Figure 29 The process of (d) is the same, so the subsequent process is shown.

[0291] First, such as Figure 32 As shown in (a), after mounting the semiconductor chip 50 and peeling off the support substrate 11, for example, through-hole wiring forming vias 18 and metal layer 14 are buried using insulating material such as a redistribution layer, and an insulating layer 82 is provided. Figure 32 (b)). Furthermore, through-holes 83 are formed to expose the copper pads 52 of the semiconductor chip 50A and through-holes 84 to expose the metal layer 14 at the desired location. Figure 32(c)). For the formation of these through-holes 83 and 84, when using photosensitive resins such as photosensitive polyimide as the insulating material, only photolithography exposure and development processes are required. Furthermore, when using thermosetting resins, laser processing is sufficient. Moreover, for example, according to... Figure 30 The method shown involves setting up and patterning copper wiring to embed through-holes 83 and 84 and covering them with an insulating layer 82, thereby forming through-hole wiring 59A and wiring 60A. Figure 32 (d)). Furthermore, the method for forming the through-hole wiring 59A and wiring 60A is not limited to this, and can be based on... Figure 31 The method shown can be used, or copper paste can be used to form it.

[0292] Furthermore, the effects of this implementation are the same as those in the examples described above.

[0293] (Other implementation methods)

[0294] The substrate for forming through-hole wiring according to the present invention is not limited to the above-described manufacturing process, and other manufacturing processes can also be used.

[0295] For example, such as Figure 6 As shown in (i), in order to form a through-hole wiring forming through-hole 18, in Figure 6 (d) Figure 6 In the process shown in (f), the metal pillar 127 is formed with the same precision as photolithography. However, if a resin pillar replacing the metal pillar 127 is formed with high precision using a photosensitive resin made of a material that can be selectively removed from the state of the embedded insulating layer 17, the resin pillar can be formed directly by photolithography, and then the following steps can be performed. Figure 6 (g) Figure 6 The process of (i) is used to manufacture a substrate for forming through-hole wiring. In addition, photosensitive resins such as photosensitive silicone resins and photosensitive acrylic resins can be used as photosensitive resins for implementing this process.

[0296] (Explanation of reference numerals in the attached diagram)

[0297] 1.1A Through-hole wiring substrate

[0298] 11 Supporting substrate

[0299] 12 Peelable adhesive layer

[0300] 13, 28 First Insulation Layer

[0301] 14, 31 Second Insulation Layer

[0302] 15, 15A, 15B Through-hole wiring forming through-holes

[0303] 27 Metal Columns

[0304] 28 Molding Resin

[0305] 50 Semiconductor chips

[0306] 51 Aluminum solder pads

[0307] 52 Copper pads

[0308] 61 Adhesive layer

[0309] 41 Molding resin layer

[0310] 70, 70A, 70B, 80, 80A-80D Rewiring Layers

[0311] Insulation layer for rewiring 81, 81A~81D

Claims

1. A substrate for forming through-hole wiring, used for mounting at least one semiconductor chip, characterized in that, The substrate for forming through-hole wiring includes: Support substrate; A peelable adhesive layer is disposed on the support substrate; A first insulating layer is disposed on the peelable adhesive layer; and A second insulating layer is stacked on top of the first insulating layer. Through-hole wiring is formed by connecting the first insulating layer and the second insulating layer without misalignment. The through-hole wiring corresponds to a plurality of connection terminals of the semiconductor chip and can form through-hole wiring that connects to the connection terminals. At the junction of the first insulating layer and the second insulating layer, the opening of the through-hole wiring in the first insulating layer is consistent with the opening of the second insulating layer.

2. The via wiring formation substrate according to claim 1, wherein The second insulating layer is made of a low-flow adhesive material.

3. The via wiring formation substrate according to claim 1, wherein The first insulating layer is made of epoxy-based sealing material.

4. A manufacturing method of a substrate for via wiring formation, characterized by, The process includes the following steps: The process of preparing a laminated substrate is to laminate a first support substrate, a first peelable adhesive layer formed on the first support substrate, a first metal layer formed on the first peelable adhesive layer, and a second metal layer formed on the first metal layer with different etching characteristics than the first metal layer. The process of providing a resist layer in the second metal layer and forming a plurality of first through-holes in the resist layer in a given pattern; The process of forming a second through-hole in the second metal layer, which communicates with the first through-hole, through the first through-hole formed by the first through-hole in the resist layer, using the first metal layer as an etching stop layer; The process of embedding a third metal with different etching characteristics than the second metal layer in the first through-hole forming hole and the second through-hole forming hole to form a third metal pillar; The process of peeling off the resist layer; The process of forming a first insulating layer on the second metal layer into which the third metal pillar is embedded; The process of grinding the surface of the first insulating layer to expose the first end face of the third metal pillar; The process of bonding the second support substrate to the first insulating layer and the third metal pillar by a second peelable adhesive layer; The process of peeling off the first peelable adhesive layer and the first support substrate; The process of removing the first metal layer to expose the second metal layer and the second end face of the third metal pillar on the side opposite to the first end face; The process of etching away the second metal layer by using the third metal pillar and the first insulating layer as etching stop layers; The process of setting a second insulating layer on the first insulating layer and embedding the third metal pillar; The process of grinding the surface of the second insulating layer to expose the second end face of the third metal pillar; and The process of etching away the third metal pillar by using the first and second insulating layers as etching stop layers to form a through-hole for wiring is described. The through-hole for forming wiring is located at the junction of the first insulating layer and the second insulating layer, and the opening of the first insulating layer of the through-hole for forming wiring coincides with the opening of the second insulating layer.

5. The method for manufacturing a substrate for forming through-hole wiring according to claim 4, characterized in that, The second insulating layer is made of a low-flow adhesive material.

6. The method for manufacturing a substrate for forming through-hole wiring according to claim 4, characterized in that, The first insulating layer is made of epoxy-based sealing material.

7. The method for manufacturing a substrate for forming through-hole wiring according to claim 4, characterized in that, The first metal layer is made of nickel or a nickel alloy, and the second metal layer is made of copper or a copper alloy.

8. The method for manufacturing a substrate for forming through-hole wiring according to claim 4, characterized in that, The third metal column is made of nickel or a nickel alloy.

9. A method of manufacturing a semiconductor device mounting member, characterized by comprising: The process includes the following steps: The process of preparing a substrate for forming through-hole wiring as described in any one of claims 1 to 3; A process of preparing a semiconductor chip with connection terminals as copper terminals, and bonding the semiconductor chip to the second insulating layer of the through-hole wiring forming substrate with an adhesive while the copper terminals are facing the through-hole of the through-hole wiring forming substrate, or bonding the semiconductor chip to the second insulating layer of the through-hole wiring forming substrate made of a low-flow adhesive. The process of forming a third insulating layer embedded in the semiconductor chip; The process of peeling off the peelable adhesive layer and the supporting substrate; and The process of embedding copper in the through-hole wiring forming through-hole from the side opposite to the side where the semiconductor chip is disposed, thereby forming a through-hole wiring connected to the copper terminal.

10. A method of manufacturing a semiconductor device mounting member, characterized by comprising: The process includes the following steps: A process for preparing a through-hole wiring forming substrate to be manufactured using the manufacturing method of any one of claims 4 to 8; A process of preparing a semiconductor chip with connection terminals as copper terminals, and bonding the semiconductor chip to the second insulating layer of the through-hole wiring forming substrate with an adhesive while the copper terminals are facing the through-hole of the through-hole wiring forming substrate, or bonding the semiconductor chip to the second insulating layer of the through-hole wiring forming substrate made of a low-flow adhesive. The process of forming a third insulating layer embedded in the semiconductor chip; The process of peeling off the second peelable adhesive layer and the second support substrate; as well as The process of embedding copper in the through-hole wiring forming through-hole from the side opposite to the side where the semiconductor chip is disposed, thereby forming a through-hole wiring connected to the copper terminal.

11. A substrate for forming through-hole wiring, used for mounting at least one semiconductor chip, characterized in that, The substrate for forming through-hole wiring includes: Support substrate; A peelable adhesive layer is disposed on the support substrate; A metal layer disposed on the peelable adhesive layer; and An insulating layer, which is stacked on the metal layer, In the metal layer and the insulating layer, the through-hole for forming wiring is a straight hole that passes through the metal layer and the insulating layer without misalignment. The through-hole for forming wiring corresponds to each of the multiple connection terminals of the semiconductor chip and can form through-hole wiring that connects to the connection terminals. At the junction of the metal layer and the insulating layer, the opening of the through-hole for forming wiring in the metal layer is consistent with the opening of the insulating layer.

12. A manufacturing method of a substrate for via wiring formation, characterized by comprising: The process includes the following steps: The process of preparing a laminated substrate, wherein the laminated substrate is obtained by sequentially stacking a support substrate, a peelable adhesive layer formed on the support substrate, and a first metal layer and a second metal layer on the peelable adhesive layer. The process of providing a resist layer in the second metal layer and forming a plurality of through-holes in the resist layer in a given pattern; The process of using the resist layer of the given pattern as a mask to etch only the second metal layer; The process of embedding metal in the first metal layer in the through hole to form a metal pillar; The process of peeling off the resist layer; The process of forming an insulating layer embedded in the metal pillar on the first metal layer; The process of grinding the surface of the insulating layer to expose the first end face of the metal pillar; and The process of etching away the metal pillars and the first metal layer, using the insulating layer and the peelable adhesive layer as etching stop layers, to form a through-hole for wiring. The through-hole for wiring formation is located at the junction of the first metal layer and the insulating layer, and the opening of the first metal layer of the through-hole for wiring formation coincides with the opening of the insulating layer.

Images