Method and system for performance optimization of object grouping patterns in storage devices

By optimizing the object grouping pattern through an adaptive regression model, the performance bottleneck of KV-SSD when handling a mixture of large and small object I/O is resolved, and I/O performance is improved, especially the latency of small object I/O and the throughput of large object I/O.

CN113254439BActive Publication Date: 2026-02-03SAMSUNG ELECTRONICS CO LTD
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Patent Information

Application Number
CN202110176982.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-03-12
Filing Date
2021-02-09
Publication Date
2026-02-03
Estimated Expiration
2041-02-09

AI Technical Summary

Technical Problem

Existing key-value solid-state drives (KV-SSDs) struggle to simultaneously improve IO performance when handling a mix of large and small object IO, resulting in either high latency for small object IO or low throughput for large object IO.

Method used

An adaptive regression model is used to optimize the object grouping pattern. By receiving object I/O, tracking performance parameters associated with input parameters, storing data entries, training and cross-validating the model, and updating the inference model to adjust the input parameters, the object grouping pattern is optimized.

Benefits of technology

It improves the average latency and throughput of object I/O, enhancing the overall I/O performance of KV-SSD.

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Abstract

Methods and systems are provided for performance optimization of object grouping patterns in storage devices. The methods include receiving object IOs for a target device; grouping the object IOs using a first plurality of input parameters; associating tracking parameters with the first plurality of input parameters and performance parameters corresponding to the first plurality of input parameters; storing first data entries comprising the tracking parameters, the first plurality of input parameters, and the performance parameters in a database; extracting a plurality of data entries from the database, the plurality of data entries including the first data entries; training a training model using one or more of the plurality of data entries; cross-validating the training model to determine a degree of error reduction of the training model; performing a model check to compare the training model to an inference model; and updating the inference model based on the model check.
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Description

[0001] This application claims priority and benefit to U.S. Provisional Application No. 62 / 976,281, filed February 13, 2020, entitled "Performance Optimization of Object Grouping Scheme in a Network Key-Value Store Device Using Adaptive Regression," the entire contents of which are incorporated herein by reference. This application also includes the subject matter disclosed in Co-Pending U.S. Application No. 16 / 815,974, filed March 11, 2020, entitled "GROUPING KEY VALUE OBJECT IOs TO IMPROVE IO PERFORMANCE FOR KEY-VALUESTORAGE DEVICES," the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more aspects of embodiments of this disclosure generally relate to optimizing the input / output (“IO”) performance of a key-value storage device. Background Technology

[0003] In recent years, key-value solid-state drives (KV-SSDs) have been used in an increasing number of diverse applications. Therefore, enhancing the IO performance of KV-SSDs to increase throughput and reduce latency can be beneficial.

[0004] However, because KV-SSDs handle both large and small object I / O in the same way, it may be difficult to improve I / O performance when KV-SSDs encounter a mix of large and small object I / O.

[0005] Therefore, KV-SSD processing may benefit large object I / O, resulting in higher latency for small object I / O. Alternatively, KV-SSD processing may benefit small object I / O, resulting in lower throughput for large object I / O. Summary of the Invention

[0006] An aspect of the embodiments of this disclosure relates to a system and method for using an adaptive regression model to improve or optimize the performance of object grouping patterns.

[0007] An aspect of embodiments of this disclosure relates to a system and method for updating an inference model with appropriate input parameters for inferring object grouping patterns, wherein the inference model is incrementally trained using an adaptive regression model.

[0008] According to one embodiment of this disclosure, a method for optimizing or improving parameters for grouping object I / O is provided, the method comprising: receiving object I / O for a target device; grouping the object I / O using a first plurality of input parameters; associating tracking parameters with the first plurality of input parameters and associating the tracking parameters with performance parameters corresponding to the first plurality of input parameters; storing a first data entry including the tracking parameters, the first plurality of input parameters, and the performance parameters in a database; retrieving a plurality of data entries from the database, the plurality of data entries including the first data entry; training a training model using one or more of the plurality of data entries; performing cross-validation on the training model to determine the extent to which the error of the training model is reduced; performing a model check to compare the training model with an inference model; and updating the inference model based on the model check.

[0009] The method may further include: determining performance parameters corresponding to the first plurality of input parameters.

[0010] The plurality of data entries may also include a plurality of historical data entries, and the method further includes: using the plurality of historical data entries to train or cross-validate the inference model.

[0011] The method may further include: in response to performance parameters being outside the expected range, using an inference model to infer a second plurality of input parameters for grouping object I / O.

[0012] The method may further include: preprocessing the plurality of data entries to remove data entries that reduce the predictive ability of the trained model.

[0013] Performance parameters may include input / output operations per second, and the first plurality of input parameters may include object group size and flash time.

[0014] Databases can include time-series databases.

[0015] Cross-validation of the trained model can be performed using the k-fold cross-validation method.

[0016] According to another embodiment of this disclosure, a non-transitory computer-readable medium implemented on a system for optimizing or improving parameters for grouping object I / O is provided. The non-transitory computer-readable medium has computer code configured, when executed on a processor, to implement a method for optimizing or improving the parameters for grouping object I / O. The method includes: receiving object I / O for a target device; grouping the object I / O using a first plurality of input parameters; associating tracking parameters with the first plurality of input parameters and associating the tracking parameters with performance parameters corresponding to the first plurality of input parameters; storing a first data entry including the tracking parameters, the first plurality of input parameters, and the performance parameters in a database; retrieving a plurality of data entries from the database, the plurality of data entries including the first data entry; training a training model using one or more of the plurality of data entries; performing cross-validation on the training model to determine the extent to which the error of the training model is reduced; performing a model check to compare the training model with an inference model; and updating the inference model based on the model check.

[0017] When the computer code is executed by the processor, it can also optimize or improve the method for grouping parameters for object I / O by determining performance parameters corresponding to the first plurality of input parameters.

[0018] The plurality of data entries may also include a plurality of historical data entries, and the computer code, when executed by the processor, may also optimize or improve the method for grouping parameters for object I / O by using the plurality of historical data entries to train or cross-validate the inference model.

[0019] When the computer code is executed by the processor, it can also optimize or improve the method for grouping object I / O by using an inference model to infer a second plurality of input parameters for grouping object I / O in response to performance parameters being outside the expected range.

[0020] When the computer code is executed by the processor, it can also optimize or improve the method for grouping parameters for object I / O by preprocessing the plurality of data entries to remove data entries that reduce the predictive power of the trained model.

[0021] Performance parameters may include input / output operations per second, and the first plurality of input parameters may include object group size and flash time.

[0022] Databases can include time-series databases.

[0023] Cross-validation of the trained model can be performed using the k-fold cross-validation method.

[0024] According to another embodiment of this disclosure, a system for optimizing or improving parameters for grouping object I / O is provided. The system includes a target and training circuitry. The target includes a memory cache. The target is configured to: receive object I / O for a target device; group the object I / O using a first plurality of input parameters; associate tracking parameters with the first plurality of input parameters and with performance parameters corresponding to the first plurality of input parameters; and send a first data entry including the tracking parameters, the first plurality of input parameters, and the performance parameters to a database. The training circuitry is configured to: extract a plurality of data entries from the database, the plurality of data entries including the first data entry; train a training model using one or more of the plurality of data entries; perform cross-validation on the training model to determine the extent of error reduction in the training model; perform model checking to compare the training model with an inference model; and update the inference model based on the model checking.

[0025] The objective can also be configured to determine performance parameters corresponding to a first plurality of input parameters.

[0026] The plurality of data entries may also include a plurality of historical data entries, and the training circuit is further configured to use the plurality of historical data entries to train or cross-validate the inference model.

[0027] The system may further include: an inference circuit configured to: infer a second plurality of input parameters for grouping object I / O in response to the target determining performance parameters being outside the expected range.

[0028] The training circuit can also be configured to preprocess the plurality of data entries to remove data entries that reduce the predictive power of the trained model.

[0029] Performance parameters may include input / output operations per second, and the first plurality of input parameters include object group size and flash time.

[0030] The database includes time-series databases.

[0031] Therefore, the system according to embodiments of this disclosure uses an adaptive regression model to infer and / or apply appropriate input parameters to improve or optimize the performance of object grouping patterns. Attached Figure Description

[0032] The following drawings describe a non-limiting and non-exhaustive embodiment of this invention, wherein, unless otherwise stated, the same reference numerals refer to the same parts throughout the various views.

[0033] Figure 1 This is a block diagram depicting a network and object grouping pattern according to one or more embodiments of the present disclosure.

[0034] Figures 2A to 2D This is a flowchart illustrating a method for updating parameters of an object grouping pattern according to one or more embodiments of the present disclosure.

[0035] Throughout the various views in the accompanying drawings, corresponding reference numerals indicate the corresponding components. Those skilled in the art will understand that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements, layers, and regions in the drawings may be exaggerated relative to other elements, layers, and regions to help improve clarity and understanding of the various embodiments. Furthermore, common but easily understood elements and portions unrelated to the description of the embodiments may not be shown in order to lessen the obstruction of views of these various embodiments and to make the description clearer. Detailed Implementation

[0036] The features of this disclosure and methods for implementing the features of this disclosure can be more readily understood by referring to the detailed embodiments and accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not essential for a full understanding of the aspects and features of this disclosure by those skilled in the art are not described.

[0037] Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description will not be repeated. Furthermore, for clarity, parts unrelated to the description of the embodiments may be omitted. In the drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity.

[0038] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be clear that various embodiments can be practiced without these specific details or using one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0039] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising,” “including,” “having,” “possessing,” as used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0041] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to take into account the inherent biases of measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the stated value and indicates an acceptable deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system).

[0042] When a particular embodiment can be implemented differently, a particular order of processing can be performed differently than the order in which it is described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0043] The electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices may be implemented on a flexible printed circuit film, a tape-and-carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0044] Furthermore, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices, which execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense.

[0046] Figure 1 This is a block diagram depicting a network according to one or more embodiments of the present disclosure.

[0047] Reference Figure 1 Network 100 according to one or more embodiments of this disclosure follows the NVMeoF (Non-Volatile Memory Fast Standard over Networks) architecture. In one or more embodiments, network 100 includes one or more hosts 102, network switches 104 (e.g., NVMeoF switches), one or more targets 106 (e.g., NVMe targets), and one or more target storage devices 108 (e.g., NVMe-based key-value SSDs or KV-SSDs).

[0048] Reference Figure 1One or more hosts 102 may generate one or more I / O requests based on data processing applications or software. I / O requests may include I / O operations (such as "place", "get", "delete", etc.) for object-based storage (e.g., for key-value storage). I / O requests may include different I / O sizes (e.g., small object I / O and / or large object I / O). One or more hosts 102 may forward or send one or more I / O requests to a network switch 104 (e.g., a multi-port bridge connecting devices on a computer network). The network switch 104 may use hardware addresses to process and forward data. Therefore, the network switch 104 may send one or more I / O requests to the appropriate target 106 among one or more targets 106.

[0049] One or more targets 106 may include a dispatcher 110, a memory cache (e.g., a dynamic random access memory (DRAM) cache), and a logging device 117 (e.g., a low-latency logging device). The dispatcher 110 may be a KV IO scheduler for receiving one or more IOs from the network switch 104 and scheduling them to multiple portions of the memory cache. The memory cache may include one or more zones 116 (e.g., zone 0, zone 1, zone 2, zone 3) for receiving and processing small object IOs from the dispatcher 110; the one or more zones 116 may be formed by partitions within the memory cache.

[0050] One or more zones 116 may include a flush buffer 114 that flushes object I / O (e.g., (key 8, value), (key 6, value), (key 4, value), (key 1, value), (key 7, value), (key 9, value), etc.) to a target storage device 108 (e.g., to a KV-SSD) to complete the I / O. Zones 116 may also include a log buffer 112 that receives one or more small object I / Os scheduled from scheduler 110. For example, at least two zones may each include a log buffer that receives one or more corresponding small object I / Os scheduled from scheduler 110. Scheduler 110 may schedule one or more I / Os (referred to as a “set of I / Os”) to corresponding log buffers in multiple zones.

[0051] Log buffer 112 can record or store object I / O received from scheduler 110 in log device 117. As an example, for crash recovery purposes, log device 117 can be a non-volatile dual in-line memory module (NVDIMM) or a low-latency SSD.

[0052] The logging device 117 can maintain a log in persistent storage, allowing the log to be examined after a system crash to determine whether the corresponding I / O was completed. If one or more I / Os are incomplete, the system can determine, based on the log, which additional steps (if any) are appropriate to complete any incomplete I / Os. The logging device 117 can appropriately use less storage capacity than the target storage device 108 (e.g., to save costs).

[0053] Based on the size of the object I / O received from network switch 104, target 106 can determine the path of the object I / O. For example, target 106 may include a first path (e.g., a normal path) 118 through which one or more large object I / Os received by target 106 can be directly passed to target storage device 108 without being received by log buffer 112. Large object I / Os can be object I / Os at or above a threshold size, wherein, in one or more embodiments, the threshold size may be adjustable.

[0054] Target 106 may also include a second path (e.g., a grouping path) 120 through which scheduler 110 schedules one or more small object IOs. Small object IOs may be object IOs below a threshold size. On the second path 120, scheduler 110 may schedule or send one or more small object IOs to a corresponding zone 116 (e.g., log buffer 112 of zone 116). According to one or more embodiments of this disclosure, depending on the grouping pattern, one or more small object IOs on the second path 120 may be concatenated in log buffer 112 to form an object group 124 or a clip. In one example, object group 124 may include: (key 0, value), (key 2, value), (key 3, value), empty slots, etc. In one example, target 106 may include a hash table (or lookup table) for lookups in each zone and a linked list of dirty object IOs (e.g., object IOs that have not yet been completed). In one example, the contents of the lookup table may include: H(k1), H(k3), H(k6), H(k7), H(k0), H(k9), empty, H(k8), H(k4), and H(k2). Scheduler 110 may determine which of the one or more zones 116 sends the key-value pair for small object I / O based on a hash key determined from a hash table included in each of the one or more zones 116.

[0055] Therefore, as described above, object IO can be screened by an adjustable threshold size, and large object IO can follow a first path 118, while small object IO follows a second path 120, the details of which are described in co-pending U.S. Application No. 16 / 815,974, filed March 11, 2020, entitled “GROUPING KEY VALUE OBJECT IOs TO IMPROVE IO PERFORMANCE FOR KEY-VALUESTORAGE DEVICES”, which is cross-referenced.

[0056] For example, in one or more embodiments, the log buffer 112 on the second path 120 may receive small object I / Os until a condition is met or a trigger is triggered (e.g., until the object group size exceeds a threshold size or maximum size, until a maximum number of small object I / Os have been formed into the object group, and / or until the timeout window has expired, wherein, in one or more embodiments, the threshold, maximum number, and / or timeout window are adjustable). The timeout window refers to the period of time during which small object I / Os are received by or within the log buffer 112. For example, this period of time may be set based on the object group and / or zone, according to the latency and throughput suitability of the small object I / Os.

[0057] After a condition or trigger is met by log buffer 112, log buffer 112 can log one or more small object IOs that have been concatenated into object group 124 to log device 117. After logging the small object IOs to log device 117, log buffer 112 can change its role to act as a flush buffer. In this way, flush buffer 114 can store object group 122 or fragments that include small object IOs. Flushing buffers can include multiple object groups 122. In this case, multiple log buffers can change their roles to act as flush buffers (e.g., thereby forming a single flush buffer of a larger size). In other words, according to one or more embodiments, there exists a buffer that can be partitioned into multiple buffers or buffer segments. Typically, one of the partitioned buffers operates as a log buffer, and one or more flush buffers can exist. Small object IOs are stored in the log buffer until the log buffer is full, after which the log buffer can change its function to that of a flush buffer.

[0058] When certain conditions are met (such as a threshold flush buffer size and / or a threshold idle period (e.g., based on the elapsed time of object I / O in the flush buffer)), the flush buffer can flush its contents (e.g., flush object group 122) to the target storage device 108. Then, when the flush buffer is emptied and the object I / O is complete, the contents of the flush buffer can be marked for deletion to clear the contents of the flush buffer, thereby freeing up space in the memory cache.

[0059] After the flush buffer is emptied, it may be available to change its role and be used as log buffer 112, thereby enabling a single log flush cycle. In one or more embodiments, multiple log flush cycles for different portions of the memory cache may occur simultaneously (e.g., concurrently or substantially simultaneously). Furthermore, the threshold flush buffer size and / or threshold idle period may be adjustable (e.g., via an algorithm, application programming interface, configuration file, or any other suitable method) as known to those skilled in the art.

[0060] Although the term "object group" is used throughout the specification, a connection may not occur if the log buffer 112 receives a single small object IO during the receive period and no other small object IOs are received, and "object group" can include a single small object IO.

[0061] Therefore, a group or fragment of objects comprising one or more small object IOs is formed in the log buffer 112. For the purpose of writing small object IOs to storage devices (such as log device 117) and target storage devices 108 (such as KV-SSD), the connected object group 124 can be treated as a single large object IO (due to the connection). In this way, because small object IOs are treated as a single large object IO, the average latency and throughput of small object IOs can be enhanced.

[0062] Although the target storage device 108 is Figure 1 While depicted as separate from target 106, the classification of target storage device 108 is not limited to this, and in other embodiments, target storage device 108 may be considered part of target 106. Furthermore, although Figure 1The diagram shows three hosts 102, two targets 106, and two target storage devices 108, but any number of hosts, targets, and target storage devices can be used with appropriate modifications to the inputs and outputs of each host 102, target 106, and target storage device 108. Therefore, network switch 104 can send IO requests to multiple targets 106 associated with one or more target storage devices 108. Thus, the NVMeoF architecture can connect multiple KV-SSDs (e.g., thousands or more KV-SSDs housed in a dedicated storage server) to hosts.

[0063] Figures 2A to 2D This is a flowchart 200 illustrating a method for updating parameters of an object grouping pattern according to one or more embodiments of the present disclosure.

[0064] Reference Figures 2A to 2D The systems and methods disclosed herein include an object storage application 202, one or more hosts 204, a target 106, a database 206, a training circuit 208, and an inference circuit 210.

[0065] In one or more embodiments, object storage application 202 interacts with one or more hosts 204 to generate and send I / O. In one or more embodiments, one or more hosts 204 run host-side software that interacts with an external second software program based on an operational mode. For example, in pass-through mode, the external software program determines which path data should take to reach a specific target (e.g., which of one or more targets), and in non-pass-through mode, the host-side software program determines which path data should take to reach a specific target (e.g., target 106).

[0066] In one or more embodiments, target 106 tracking and about Figure 1 The parameter data 212 is associated with the described object grouping pattern. In one or more embodiments, the parameter data 212 includes tracking parameters 214, input parameters 216, and performance parameters 218.

[0067] In one or more embodiments, the tracking parameter 214 may include data indicating when the input parameter 216 and performance parameter 218 are collected (e.g., a timestamp for determining when data collection occurred or any other suitable parameter). In one example, target 106 may associate the tracking parameter 214 with the input parameter 216 and the performance parameter corresponding to the input parameter 216. The tracking parameter 214 may also include the number of available operating CPU cores and / or threads, determined by the user or specified at startup in a first software module (e.g., the target's key-value store application) 220 for object grouping patterns. Multiple zones may follow the object grouping pattern, and each zone may have a single thread running in that zone. Each thread runs on a specific CPU core; therefore, increasing the number of cores or threads allocated to run on a zone (assuming the zone is available) can improve the performance of the object grouping pattern for high-frequency small object I / O. Therefore, the core or thread count is related to the evaluation of performance parameters such as the input / output operations per second (“IOPS”, also known as the number of inputs / outputs per second) used to determine the inference model (e.g., the Golden model or reference model used to infer input parameters) as described in more detail below.

[0068] In one or more embodiments, input parameter 216 may include parameters of an object grouping pattern that can be adjusted (e.g., via a remote procedure call (“RPC call”)) when the first software module 220 is online. For example, input parameter 216 may include the object group size and flashout time (e.g., the maximum allowed latency for the I / O). The flashout time can be measured as the time period from when a small object I / O is received by the log buffer until when the small object I / O is flushed to the target storage device. Input parameter 216 may also include the object size filtered for the first path and the second path. Input parameter 216 may also include the number of regions allocated via the log buffer for processing small object I / O. For example, when small object I / O is frequent, a higher number of regions may be desired for processing, and when small object I / O is infrequent, a lower number of regions may be desired for processing. Although several input parameters 216 have been discussed, in one or more embodiments, all or fewer of the discussed input parameters 216 may be recorded, stored, and / or adjusted. For example, in one embodiment, the flash time and object group size may be adjusted, and in another embodiment, in addition to the flash time and object group size, the number of regions may also be adjusted.

[0069] In one or more embodiments, performance parameter 218 may include parameters indicative of the performance of the object grouping mode (such as IOPS (i.e., IOs completed per second) and / or latency). Latency refers to the time taken for an object to return. In other words, it is the time period that begins when the object IO is received by the device and ends when the response is sent back to the requesting device.

[0070] Typically, it is desirable to use object grouping patterns to improve or optimize performance parameter 218 (e.g., to maximize IOPS and / or reduce average latency). However, IOPS and / or latency can vary with the amount of IO transmitted to target 106 throughout the day. For example, if input parameter 216 is fixed, changes in IO frequency, mix, and / or size may result in suboptimal input parameters for the object grouping pattern. Therefore, changes in inbound IO may lead to a decrease in IOPS because the object group size and flashout time are not updated. For example, during peak periods, the system may experience a large number of IO operations. Therefore, if the input parameters 216 (such as object group size and flashout time) are not set to appropriate values ​​in a timely manner, the performance of the object grouping pattern may be degraded. Therefore, aspects of embodiments of this disclosure relate to methods for optimizing or improving performance parameter 218 by adjusting input parameter 216.

[0071] In one or more embodiments, parameter data 212 is collected for analysis according to a data capture process. The data capture process may include storing the parameter data 212 in a database (e.g., a time-series database) 206. Data can be transferred via a first software module 220 (e.g., a key-value store application) and a second software module 222 (e.g., a proxy) running on a target node of target 106. The first software module 220 stores and reads the parameter data 212, while the second software module 222 queries the first software module 220 for health statistics of the storage application to be stored in database 206.

[0072] Data capture processing can occur when object group I / O is performed as needed. For example, data capture processing can occur when each object group is flushed to the target storage device, when each other object group is flushed to the target storage device, or when any other suitable sample (e.g., any number) of object groups is flushed to the target storage device. Sampling the data over time enables database 206 to capture additional parameter data 212 throughout the day.

[0073] In one or more embodiments, training circuit 208 receives or retrieves parameter data 212 from database 206. Training circuit 208 may retrieve all or substantially all data relating to target 106 from database 206. Training circuit 208 may receive or retrieve data from database 206 as needed at set intervals (e.g., time-based intervals (e.g., once a day, twice a day, three times a day, etc.)). In one or more embodiments, training circuit 208 receives or retrieves data during off-peak hours or off-peak periods when the system to which training circuit 208 is a part has more resources to perform preprocessing (224), model training and validation (226), model checking (228), and / or inferring model updates (230). In one or more embodiments, as Figures 2A to 2C As shown, the training circuit 208 is separate from the target 106; however, as Figure 2D As shown, in one or more embodiments, the training circuit 208 is integrated with the target 106. Therefore, Figures 2A to 2C In some embodiments, the training circuit 208 can be separated from the target 106 to avoid burdening the target 106 with preprocessing (224), model training and validation (226), model checking (228), and / or inference model updates (230). Figure 2D In some embodiments, target 106 may include, but is not limited to, means optimized or configured for training to serve as training circuit 208. In one or more embodiments, training circuit 208 may be implemented with any suitable number and type of chips known to those skilled in the art. As an example, training circuit 208 may include any suitable software and hardware; for example, training circuit 208 may include FPGA, GPU, and / or any other suitable chip or chip component, and / or one or more discrete analog or digital components, wherein one or more of these components and / or functions may be integrated into a single integrated circuit (IC) chip.

[0074] like Figures 2A to 2DAs shown, parameter data 212 received or extracted from database 206 can be preprocessed (224) by training circuitry 208. Preprocessing the extracted data (224) can include removing bad data (e.g., data entries that reduce or negatively affect the predictive ability of the trained model). For example, data entries that reduce or negatively affect the predictive ability of the trained model can include missing or unexpected values ​​(or values ​​outside the expected range). In a non-limiting example, in one or more embodiments, a single data entry can include a timestamp, object group size, flash time, thread count, and IOPS. If any of these parameters are not present in the extracted data, preprocessing (224) can remove the entire data entry. As another example, if any of these parameters has an unexpected value, the entire data entry can be removed. For example, if the parameter is outside the expected range or the parameter is negative, preprocessing 224 can remove the entire data entry. In one or more embodiments, preprocessed data entries removed before training are also removed from database 206.

[0075] After preprocessing the data (224), training circuit 208 trains the training model (226). In one or more embodiments, the training model is based on all or substantially all data extracted from database 206, including any new data and historical data stored in database 206. The inclusion of historical data in addition to new data across multiple training cycles leads to an incremental learning approach. Thus, in one or more embodiments, historical data may at least capture the data upon which the current inference model is based. In one or more embodiment examples, training circuit 208 uses data including historical data to train or cross-validate the training model.

[0076] In one or more embodiments, training circuit 208 performs cross-validation (226) on the trained model. For example, cross-validation is performed on data samples (e.g., from database 206), wherein the data samples include a training set for training the trained model and a validation set for evaluating the predictive power of the trained model. In one or more embodiments, cross-validation (226) is performed using k-fold cross-validation. For example, the k-fold cross-validation method according to one or more embodiments divides the data samples into k sets, wherein one set is used for validation and (k-1) sets are used for training the model. This process may be repeated k times, wherein the k results are averaged. Although the k-fold cross-validation method has been described with reference to cross-validation, any other suitable cross-validation method may be used.

[0077] In one or more embodiments, training circuitry 208 performs a model check (228) on the trained model to determine whether the accuracy or error reduction (e.g., the degree of error reduction) of the trained model is superior to that of the inference model. For example, the trained model may be evaluated based on error reduction, which refers to the concentration of data points. In one or more embodiments, error reduction is measured using an error handling function (such as mean squared error (MSE), root mean square error (RMSE), R^2, etc.). For example, in one or more embodiments, the RMSE value for each k-fold validation (e.g., training / test split) is collected and averaged to compare with the inference model. Although a specific error handling function for performing the model check has been described, other suitable error handling functions may be used in one or more embodiments.

[0078] If the accuracy or error reduction of the trained model is greater than or better than the accuracy or error reduction of the inference model, the training circuit 208 updates the inference model based on the trained model (230). In one or more embodiments, the training circuit 208 replaces the inference model with the trained model to create a new inference model. Conversely, if the accuracy or error reduction of the trained model is less than or worse than the accuracy or error reduction of the inference model, the trained model is rejected and the inference model remains unchanged. Therefore, the inference model can be updated over time (230) based on historical data stored in the database 206 to become more robust.

[0079] In one or more embodiments, target 106 may perform IOPS and / or latency checks (236) and determine whether performance parameter 218 is outside the expected range. In one or more embodiments, for example, target 106 may continuously monitor the target's IOPS to check whether the IOPS falls outside the range of approximately 5% to approximately 10% of the expected IOPS value. When one or more performance parameters 218 (e.g., IOPS and / or latency) are outside the expected range, inference circuitry 210 may use an inference model to infer (232) appropriate input parameters (e.g., object group size, flash time, etc.). Inference circuitry 210 may perform parameter checks (234) by comparing the inferred input parameters with the input parameters 216 of target 106. If the inferred input parameters are the same as the input parameters 216 of target 106, no action is taken. If the inferred input parameters are different from the input parameters 216 of target 106, inference circuitry 210 may update the input parameters 216 of target 106 (e.g., via an RPC call).

[0080] In one or more embodiments, the inference circuit 210 is separated from the target 106 to avoid, for example Figure 2A and Figure 2B The embodiments shown in the example of inferring the burden of target 106, and in one or more embodiments, as Figure 2C and Figure 2D As shown in the embodiments, the inference circuit 210 is part of the target 106. Although the inference circuit 210 is depicted as separate from the training circuit 208 in the illustrated embodiments, in one or more embodiments, as... Figure 2B As shown in the embodiments, the inference circuit 210 and the training circuit 208 may be part of the same device. In one or more embodiments, the inference circuit 210 may be implemented in any suitable number and type of chips known to those skilled in the art. As an example, the inference circuit 210 may include any suitable software and / or hardware (including, for example, FPGA- and / or GPU-based accelerators for fast inference, and / or any other suitable chip or chip component), and / or one or more discrete analog or digital components, wherein one or more of these components and / or functions may be integrated in a single chip.

[0081] Therefore, as disclosed herein, embodiments of this disclosure improve performance by adjusting input parameters (such as object group size, flash time, number of regions, etc.) to improve IOPS and / or latency of object grouping patterns.

[0082] While this disclosure has been specifically shown and described with reference to some embodiments thereof, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as set forth in the claims and their equivalents.

Claims

1. A method for performance optimization of object grouping patterns in a key-value storage device, the method comprising: Receives object input / output I / O for the target device; Grouping of object I / O using the first multiple input parameters; The tracking parameters are associated with a first plurality of input parameters and with performance parameters corresponding to the first plurality of input parameters, wherein the performance parameters include parameters indicating the performance of the object grouping pattern, and wherein the tracking parameters include data indicating when the first plurality of input parameters and the performance parameters are collected; Store the first data entry, which includes tracking parameters, first multiple input parameters, and performance parameters, in the database; Extract multiple data entries from the database, including the first data entry; The training model is trained using one or more of the plurality of data entries; Cross-validation is performed on the trained model to determine the extent to which the error of the trained model has been reduced; Perform model checks to compare the trained model with the inferred model; and The inference model is updated based on model checking, and The method further includes: in response to performance parameters being outside the expected range, using an inference model to infer a second plurality of input parameters for grouping object I / O.

2. The method according to claim 1, wherein, The multiple data entries also include multiple historical data entries, and The method further includes using the plurality of historical data entries to train or cross-validate the training model.

3. The method according to claim 1, further comprising preprocessing the plurality of data entries to remove data entries that reduce the predictive ability of the trained model.

4. The method according to claim 1, wherein, Performance parameters include input / output operations per second, and The first set of input parameters includes the object group size and the flash time.

5. The method according to claim 1, wherein, The database includes time-series databases.

6. The method according to any one of claims 1 to 5, wherein, Cross-validation of the trained model is performed using the k-fold cross-validation method.

7. A non-transitory computer-readable medium storing instructions, said instructions, when executed on a processor, configuring the processor to implement a method for performance optimization of object grouping patterns in a key-value storage device, said method comprising: Receives object input / output I / O for the target device; Grouping of object I / O using the first multiple input parameters; The tracking parameters are associated with a first plurality of input parameters and with performance parameters corresponding to the first plurality of input parameters, wherein the performance parameters include parameters indicating the performance of the object grouping pattern, and wherein the tracking parameters include data indicating when the first plurality of input parameters and the performance parameters are collected; Store the first data entry, which includes tracking parameters, first multiple input parameters, and performance parameters, in the database; Multiple data entries are extracted from the database, the multiple data entries including a first data entry; The training model is trained using one or more of the plurality of data entries; Cross-validation is performed on the trained model to determine the extent to which the error of the trained model has been reduced; Perform model checks to compare the trained model with the inferred model; and The inference model is updated based on model checking, and The method further includes: in response to performance parameters being outside the expected range, using an inference model to infer a second plurality of input parameters for grouping object I / O.

8. The non-transitory computer-readable medium according to claim 7, wherein, The multiple data entries also include multiple historical data entries, and The method further includes: using the plurality of historical data entries to train or cross-validate the training model.

9. The non-transitory computer-readable medium according to claim 7, wherein, The method further includes: preprocessing the plurality of data entries to remove data entries that reduce the predictive power of the trained model.

10. The non-transitory computer-readable medium according to claim 7, wherein, Performance parameters include input / output operations per second, and The first set of input parameters includes the object group size and the flash time.

11. The non-transitory computer-readable medium according to claim 7, wherein, The database includes time-series databases.

12. The non-transitory computer-readable medium according to any one of claims 7 to 11, wherein, Cross-validation of the trained model is performed using the k-fold cross-validation method.

13. A system for performance optimization of object grouping patterns in a key-value storage device, the system comprising: The target, including the memory cache, is configured as follows: Receives object input / output I / O for the target device. Grouping of object I / O using the first multiple input parameters The tracking parameters are associated with a first plurality of input parameters and with performance parameters corresponding to the first plurality of input parameters, wherein the performance parameters include parameters indicating the performance of the object grouping pattern, and wherein the tracking parameters include data indicating when the first plurality of input parameters and the performance parameters are collected, and Send the first data entry, which includes tracking parameters, first multiple input parameters, and performance parameters, to the database; The training circuit is configured as follows: Multiple data entries are extracted from the database, the multiple data entries including a first data entry. The training model is trained using one or more of the plurality of data entries. Cross-validation is performed on the trained model to determine the extent to which the error of the trained model has been reduced. Perform model checks to compare the trained model with the inferred model, and The inference model is updated based on model checking, and The system further includes an inference circuit configured to infer a second plurality of input parameters for grouping object I / O in response to the target determination performance parameters being outside the expected range.

14. The system according to claim 13, wherein, The multiple data entries also include multiple historical data entries, and The training circuit is also configured to use the plurality of historical data entries to train or cross-validate the training model.

15. The system according to claim 13, wherein, The training circuit is also configured to preprocess the plurality of data entries to remove data entries that reduce the predictive power of the trained model.

16. The system according to claim 13, wherein, Performance parameters include input / output operations per second, and The first set of input parameters includes the object group size and the flash time.

17. The system according to any one of claims 13 to 16, wherein, The database includes time-series databases.

Citation Information

Patent Citations

  • Grouping key value object IOs to improve IO performance for key-value storage devices

    US11243694B2

  • Prediction method and device for cell failure warning

    CN109150564A

  • Generation of synthetic images for training a neural network model

    CN110176054A