Single clock display driver

Abstract

The present application relates to a single-clock display driver. Various aspects of the specification provide a circuit (100). In at least some examples, the circuit includes a driver (104A). The driver includes a phase-locked loop (108A) and a digital interface (105A). The phase-locked loop is configured to receive a clock signal and provide a second clock signal based on a first clock signal. The digital interface is configured to: receive the first clock signal, receive and sample data from a data frame at successive rising and falling transitions of the first clock signal, extract a portion of the data frame addressed to the driver from the data frame, and provide a portion of the data frame remaining after extracting the portion of the data frame addressed to the driver.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 965,492, filed on January 24, 2020, which is hereby incorporated by reference in its entirety. Background Art

[0003] Some visual displays include multiple light-emitting diodes (LEDs) arranged in groups (such as red, green, and blue LED groups), which then form a panel or array of many LEDs. The LED panel is typically controlled by a controller that sends signals to a driver, which drives the LEDs and causes them to illuminate or not illuminate in a certain sequence. This control causes the LED panel to emit a visual display, such as a color, pattern, image, etc. As the display performance standards for LED panels increase, challenges in controlling or driving the LED panels may arise. Summary of the Invention

[0004] In at least some examples, the circuit includes a driver. The driver includes a phase-locked loop (PLL) and a digital interface. The PLL is configured to receive a first clock signal and provide a second clock signal based on the first clock signal. The digital interface is configured to receive the first clock signal, receive and sample data from a data frame at consecutive rising and falling transitions of the first clock signal, extract a portion of the data frame addressed to the driver from the data frame, and provide a portion of the data frame remaining after extracting the portion of the data frame addressed to the driver.

[0005] In at least some examples, the circuit includes a driver. The driver includes a phase-locked loop (PLL) and a digital interface. The PLL is configured to receive a first clock signal and provide a second clock signal based on the first clock signal. The digital interface is configured to receive the first clock signal, receive a data frame, write data into the data frame at consecutive rising and falling transitions of the first clock signal, and provide the data frame after writing the data frame.

[0006] In at least some examples, a system includes a display, a display controller, and a first driver. The display includes portions arranged into multiple rows and columns. The display controller is configured to control the rows of the display, provide a data frame to a first driver in a driver daisy chain, and provide a first clock signal to each driver in the driver daisy chain. The first driver is configured to provide a second clock signal based on the first clock signal, receive a data frame from the display controller, remove a portion of the data frame addressed to the first driver from the data frame, provide the remaining data frame to the next driver in the driver daisy chain, and control a first portion of the display based on the portion of the data frame addressed to the first driver and the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of an example display system.

[0008] Figure 2 is a graphic representation of an example signal waveform.

[0009] Figure 3 It is a table of clock signal frequency relationships.

[0010] Figure 4 is a graphic representation of a sample data frame.

[0011] Figure 5 is a diagram illustrating the order in which sample data is written.

[0012] Figure 6 is a diagram of the order in which sample data is read.

[0013] Figure 7 is a flow chart of an example method.

[0014] Figure 8 is a flow chart of an example method. DETAILED DESCRIPTION

[0015] Modern visual displays generally tend to improve display performance standards, such as frame rate and contrast ratio, among other standards. For example, a frame rate of 60 hertz (Hz) in the past could be considered as acceptable display performance, while a frame rate that improves today, such as about 120Hz, could be considered as acceptable display performance by some people. Even higher frame rates could become what is considered as acceptable display performance in the future. Similarly, a contrast ratio of about 25,000 to 1 (25,000:1) could be considered as acceptable display performance by some people today. Even higher contrast ratios could become what is considered as acceptable display performance in the future. As used herein, contrast ratio is the difference between the brightest image that a visual display can produce and the darkest image that a visual display can produce. Described in another way, contrast ratio can be considered as the ratio formed by dividing the highest brightness that a visual display can display by the lowest brightness that a visual display can display. Acceptable display performance is at least sometimes driven by consumer preferences, so that certain values ​​of display performance standards can be considered as customer or consumer product selection criteria or "careabouts." For example, a customer or consumer attempting to select or purchase a visual display may decline to select or purchase a visual display having a frame rate of less than 120 Hz and will instead select or purchase a different visual display having a frame rate of 120 Hz. Similar selection or purchase criteria may apply to contrast and various other display performance criteria.

[0016] Challenges can arise in controllers or drivers used to control visual displays with these increased display performance standards. For example, at least some drivers receive and operate based on both a data shift clock (SCLK) and a grayscale clock (GCLK). In some examples, SCLK is utilized by drivers associated with data transfer (receiving / transmitting), while GCLK is utilized by drivers associated with grayscale display. For example, a driver provides pulse width modulation (PWM) based on received control data and GCLK to control the brightness of a visual display (e.g., one or more LEDs) under the control of the driver. As the frame rate of a visual display increases, the speed at which data is provided to the visual display to facilitate this increased frame rate also increases. To accommodate the increased data transmission speed, the frequency of the SCLK is increased in at least some conventional driver implementations. Similarly, as contrast increases, the resolution of the data received by the driver for controlling the visual display (e.g., the number of data bits) also increases. As the resolution of the data increases, the frequency of the GCLK is also increased in at least some conventional driver implementations. Additional challenges arise from the increased SCLK and / or GCLK frequencies. For example, many drivers and / or visual displays are subject to emission standards, such as radiated emissions testing. Radiated emissions testing measures the electromagnetic field strength of electromagnetic emissions from a device that are unintentionally provided by the device (e.g., provided as a result of the operation of the device and not as a planned or intended feature or function of the device). As the SCLK and GCLK frequencies increase, the noise in the device and the corresponding electromagnetic emissions of the device may also increase. In devices in which the SCLK and GCLK are increased to a frequency sufficient to support a frame rate of 120 Hz or greater and a contrast ratio of 25,000:1 or greater, in at least some examples, the electromagnetic emissions of the device exceed the permitted standards or specifications. Accordingly, the following challenge may arise: supporting a frame rate of 120 Hz or greater and / or a contrast ratio of 25,000:1 or greater without increasing the SCLK and GCLK frequencies to a level that causes the electromagnetic emissions of the device to exceed the permitted standards or specifications.

[0017] In some examples, a driver according to the present specification can support a frame rate of 120 Hz and a contrast ratio of 25,000:1. In at least some embodiments, the driver receives SCLK and provides GCLK internally via a clock divider or scaler based on SCLK. In at least some examples, the clock divider is implemented as a phase-locked loop (PLL) circuit, such as a PLL frequency analyzer that provides GCLK as multiple SCLKs. In at least some embodiments, the driver of the present specification also samples received input data at both the rising and falling edges of SCLK. In at least some examples, sampling input data at both the rising and falling edges of SCLK enables the driver to support a 120 Hz frame rate with an SCLK frequency that is numerically equal to or less than the SCLK frequency for a 60 Hz frame rate. In at least some examples, enabling support for a 120 Hz frame rate at an SCLK frequency suitable for supporting a 60 Hz frame rate prevents or eliminates the generation of additive signal noise and / or electromagnetic emissions that could cause the driver's electromagnetic emissions to exceed applicable standards or specifications. Additionally, in at least some examples, a driver that internally generates a GCLK based on the SCLK via a PLL circuit reduces electromagnetic (EM) emissions in a system that includes the driver because the high-frequency GCLK signal does not flow through wires, traces, or other interconnects between components of the system.

[0018] Because SCLK is the source for generating GCLK, SCLK is continuous, so the driver continuously receives SCLK regardless of whether it is receiving data. This can lead to challenges in identifying the IDLE, START, DATA, and / or END states of input data and supporting multi-device cascading between or among multiple drivers. Accordingly, at least some aspects of the present disclosure also provide a communication protocol for supporting multi-device cascading between or among multiple drivers in a system with a continuous SCLK.

[0019] Figure 1 is a block diagram of an example display system 100. In at least some examples, display system 100 represents any display system, regardless of form factor (e.g., large or small), that includes LEDs driven by drivers under the control of a controller. For example, display system 100 can represent a consumer device such as a smartphone, smartwatch, tablet, laptop, computer monitor, television, automotive display, or any other type of display, or any other consumer or enterprise product or device having a display screen utilizing LEDs. Display system 100 can further represent a monitor in transportation equipment, a modular LED display, or a large-format screen (e.g., such as a stadium or stage display), among others.

[0020] In at least one embodiment, a display system 100 includes a controller 102, drivers 104A, 104B, 104m, and LED arrays 106A, 106B, 106m, where m is any suitable integer value. Each LED array 106A, 106B, 106m includes a plurality of LEDs arranged into k scan rows (e.g., horizontal rows) and n channels (e.g., vertical columns). Each driver 104A, 104B, 104m includes n outputs, each of which is uniquely coupled to a channel of a corresponding LED array. In some examples, the controller 102, drivers 104A, 104B, 104m, and LED arrays 106A, 106B, 106m are arranged to form a time-division multiplexed circuit or system. For example, the controller 102 is coupled to each of the LED arrays 106A, 106B, 106m to control the k scan rows of the LED arrays 106A, 106B, 106m. Controller 102 is further coupled to each of drivers 104A, 104B, and 104m to provide a data frame (D_FRAME) as a data input (SIN) to driver 104A, provide SCLK to drivers 104A, 104B, and 104m, and receive a data output (SOUT) from driver 104m. Driver 104A is coupled to driver 104B to provide the data output of driver 104A as a data input to driver 104B. Driver 104B is coupled to driver 104m to provide the data output of driver 104B as a data input to driver 104m. Each of drivers 104A, 104B, and 104m also includes a PLL 108A, 108B, and 108m, respectively. In various examples, controller 102 can take any suitable form. For example, in some embodiments, controller 102 is a field programmable gate array (FPGA). In other examples, the controller 102 is a processor, a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or any suitable structure capable of exerting control over the drivers 104A, 104B, 104m. In various examples, the PLLs 108A, 108B, 108m each take any form or architecture suitable for performing at least the actions described herein. Similarly, while the drivers 104A, 104B, 104m are shown and described as including the PLLs 108A, 108B, 108m, respectively, in various examples, the drivers 104A, 104B, 104m include any suitable circuitry or components (such as digital interfaces 105A, 105B, 105m), or processing components, signal generators such as PWM signal generators, and the like. Accordingly, the actions described herein for the respective drivers 104A, 104B, 104m can be implemented or performed by the respective digital interfaces 105A, 105B, 105m configured to perform such actions.

[0021] In an example of the operation of the display system 100, the controller 102 controls each of the scan rows of the LED arrays 106A, 106B, 106m to control the power delivery to each scan row of the LED arrays 106A, 106B, 106m. The controller 102 also provides SCLK to each of the drivers 104A, 104B, 104m. To write data to one or more of the drivers 104A, 104B, 104m, the controller 102 provides a D_FRAME containing one or more commands and one or more data bytes to the driver 104A, which receives the D_FRAME as SIN1. In at least some examples, the D_FRAME (as provided by the controller 102) includes data for one or more of the drivers 104A, 104B, 104m. After driver 104A receives D_FRAME, driver 104A removes the portion of D_FRAME designated for driver 104A and forwards the remaining D_FRAME as SOUT1 to driver 104B as SIN2. After driver 104B receives SIN2, driver 104B removes the portion of D_FRAME designated for driver 104B and forwards the remaining D_FRAME as SOUT2 to driver 104m as SINm. After driver 104m receives SINm, driver 104m removes the portion of D_FRAME designated for 104m.

[0022] To read data from one or more of drivers 104A, 104B, and 104m, controller 102 provides D_FRAME containing one or more commands to driver 104A, which driver 104A receives as SIN1. In at least some examples, the commands instruct one or more of drivers 104A, 104B, and 104m to write data to D_FRAME. After driver 104A receives D_FRAME, driver 104A adds a data byte containing driver 104A's output data to D_FRAME and forwards D_FRAME as SOUT1 to driver 104B as SIN2. After driver 104B receives SIN2, driver 104B adds a data byte containing driver 104B's output data to D_FRAME and forwards D_FRAME as SOUT2 to driver 104m as SINm. After the driver 104 m receives SINm, the driver 104 m adds a data byte containing the output data of the driver 104 m to D_FRAME and forwards D_FRAME to the controller 102 as return data.

[0023] In at least some examples, the drivers 104A, 104B, 104m read from and / or write to D_FRAME at each of the rising edge of SCLK and the falling edge of SCLK. By reading from and / or writing to DFRAME at both the rising edge and the falling edge of SCLK (e.g., dual-edge reading and / or writing), the drivers 104A, 104B, 104m effectively operate at approximately twice the frequency of SCLK. The drivers 104A, 104B, 104m do this without generating the substantial electromagnetic emissions conventionally associated with single-edge systems that operate based on a received clock signal having a frequency approximately twice the frequency of SCLK as received by the drivers 104A, 104B, 104m.

[0024] In at least some examples, SCLK in a dual-edge system has a frequency greater than or equal to the result of the following formula 1, where k, m, and n are as described above, d is the number of data bits (e.g., data width) used to control the LED arrays 106A, 106B, 106m, r is the ratio of the valid data transmission time of one data frame in the display system 100, and R is the frame rate of the display system 100.

[0025]

[0026] Similarly, the frequency of GCLK provided internally by PLLs 108A, 108B, and 108m in drivers 104A, 104B, and 104m, respectively, has a frequency greater than or equal to the result of the following formula 2, where k and q are ratios of the effective display time of one data frame in display system 100, R is as described above, and y is the resolution of each output channel of drivers 104A, 104B, and 104m.

[0027]

[0028] Figure 2 is an example waveform diagram 200. Diagram 200 shows a display system such as Figure 1 Graph 200 illustrates the timing of communications in a display system 100. Graph 200 shows SCLK and SIN of one of the drivers 104A, 104B, and 104m, and SOUT of one of the drivers 104A, 104B, and 104m. Graph 200 represents time horizontally, and each signal in graph 200 shows a logically asserted value and a logically deasserted value vertically.

[0029] like Figure 2As shown, SIN and SOUT completely switch between asserted and de-asserted states or values ​​during the on-time or off-time of SCLK. In this way, the SIN and SOUT values ​​are stable at both the rising and falling edges of SCLK. Because SIN is stable at both the rising and falling edges of SCLK, SIN is suitable for reading (e.g., sampling) at both the rising and falling edges of SCLK. Similarly, because SOUT is stable at both the rising and falling edges of SCLK, SOUT is suitable for shifting or providing to the next device (e.g., the next cascade driver or controller 102 of driver 104A, 104B, 104m) at both the rising and falling edges of SCLK. Sampling or providing data output at both the rising and falling edges of SCLK as described above enables operating drivers 104A, 104B, 104m at a frequency greater than the frequency of SCLK. This prevents the drivers 104A, 104B, 104m from generating electromagnetic emissions that are typically associated with the operating frequency of the drivers 104A, 104B, 104m if the drivers 104A, 104B, 104m sample and provide data as output at only a single edge of SCLK.

[0030] Figure 3 is a table 300 that relates example SCLK to GCLK values. As described above, a driver (such as Figure 1 Drivers 104A, 104B, and 104m of display system 100 each include a clock divider, such as PLLs 108A, 108B, and 108m, respectively. In table 300, columns correspond to GCLK frequencies, rows correspond to SCLK frequencies, and intersections between rows and columns correspond to SCLK obtaining corresponding calibrated values ​​for GCLK. PLLs 108A, 108B, and 108m apply the calibrated values ​​to SCLK to provide GCLK within each driver 104A, 104B, and 104m, respectively. While certain frequencies for SCLK and GCLK are shown in table 300, these are merely examples, and the relationships and principles shown and described with respect to table 300 apply to any other suitable frequencies for SCLK and GCLK.

[0031] Figure 4FIG4 is a diagram 400 of an example data frame. FIG400 shows SCLK and D_FRAME, each of which is described above. FIG400 is further divided into four data communication states: IDLE, START, DATA, and END. During the IDLE state, an asserted value (e.g., a logic high or "1" value) is maintained. During the IDLE state, meaningful data is not communicated as D_FRAME. After the IDLE state, D_FRAME begins in the START state, in which the value of D_FRAME is inverted to a de-asserted value (e.g., a logic low or "0" value). After the START state, the DATA state begins.

[0032] During the DATA state, in at least some examples, D_FRAME includes at least one header byte (Head_byte) and one or more data bytes (Data_byte). For example, in at least one embodiment, during the DATA state, D_FRAME includes a header byte, followed by data byte 1, data byte 2, ..., data byte N, where N is any suitable integer value. In at least some examples, the header byte includes 16 bits of data, followed by a check bit, where the 16 bits of data indicate one or more commands. The command(s) may be instructions to one or more of the drivers 104A, 104B, 104m for performing an action, such as outputting data or modifying a control signal for controlling one of the LED arrays 106A, 106B, 106m, respectively. In at least some examples, each data byte also includes 16 bits of data, followed by a check bit. In at least some examples, the check bits for both the header byte and the data byte are the logical inverse of the previous bit (e.g., the logical inverse of the 16th bit of data applied to the corresponding header byte or data byte or a NOT function),

[0033] In some examples, D_FRAME includes more data bytes than the number of drivers 104A, 104B, 104m. In other examples, D_FRAME includes fewer data bytes than the number of drivers 104A, 104B, 104m. In still other examples, D_FRAME includes the same number of data bytes as the number of drivers 104A, 104B, 104m. Additionally, as described above with respect to Figure 1 As described above and further later in this specification, the number of data bytes in the D_FRAME may increase or decrease as the D_FRAME is communicated between or among the drivers 104A, 104B, 104m and the controller 102.

[0034] After the DATA state, the END state begins. The END state includes the asserted value for 18 consecutive clock cycles (e.g., 9 rising edges of SCLK and 9 falling edges of SCLK). In at least one example, this means that the END state includes 18 consecutive logic high or "1" value data bits.

[0035] Although it has been about Figure 4 A certain number of bits is described, but in various examples, other numbers of bits are also acceptable and within the scope of this specification. For example, a header byte may include more or fewer than 16 bits, and a data byte may include more or fewer than 16 bits. Additionally, a START state may be indicated by any other suitable pattern of any selected number of bits. An END state may include any other suitable pattern of any selected number of bits.

[0036] Figure 5 is a diagram 500 of an example data write sequence. In at least some examples, the data write sequence represents the data written from a controller such as Figure 1 controller 102) to a driver (such as Figure 1 driver 104A) and then in a driver such as Figure 1 Communication between drivers 104A, 104B, 104m).

[0037] As mentioned above about Figure 4 As described above, D_FRAME includes one or more data bytes. For the purpose of explanation, D_FRAME is Figure 5 1 is shown as being provided by the controller 102, having m bytes of data, each data byte uniquely corresponding to one of the drivers 104A, 104B, 104m.

[0038] In at least one example, to write data to one or more of the drivers 104A, 104B, and 104m, the controller 102 provides a D_FRAME to the driver 104A. The driver 104A receives the D_FRAME, reads any commands or instructions in the header byte of the D_FRAME, and removes a specified amount of data from the D_FRAME that complies with the instructions in the header byte. In some examples, the predefined amount of data is predetermined, such as the first X bits after the last bit of the header byte, the last X bits in the D_FRAME before the start of the END indicator, or starting at some other specified location in the D_FRAME. In other examples, the data to be removed by each of the drivers 104A, 104B, and 104m is specified according to any suitable process or indicator. After one of the drivers 104A, 104B, 104m removes the data from the D_FRAME, the remainder of the D_FRAME is forwarded to the next downstream cascaded device, and the above process of receiving the D_FRAME and removing data from the D_FRAME repeats until no additional data bytes remain in the D_FRAME.

[0039] Although Figure 5 The above description is based on the premise that controller 102 sends D_FRAME to driver 104A. However, in other embodiments, controller 102 sends D_FRAME to driver 104m instead. In such examples, the actions attributed to driver 104A are instead performed by driver 104m, and the actions attributed to driver 104m are instead performed by driver 104A.

[0040] Figure 6 is a diagram 600 of an example data read sequence. In at least some examples, the data read sequence represents a drive (such as Figure 1 drivers 104A, 104B, 104m) to a controller such as Figure 1 Communication between and among controllers 102).

[0041] As mentioned above about Figure 4 As described above, D_FRAME includes one or more data bytes. For the purpose of explanation, D_FRAME is Figure 6 1 is shown received by the controller 102, having m data bytes, each data byte uniquely corresponding to one of the drivers 104A, 104B, 104m.

[0042] In at least one example, to read data from one or more of the drivers 104A, 104B, and 104m, the controller 102 provides a D_FRAME to the driver 104A, the D_FRAME having header bytes that instruct at least some of the drivers 104A, 104B, and 104m to write data bytes to the D_FRAME. The driver 104A receives the D_FRAME, reads any commands or instructions in the header bytes of the D_FRAME, and writes a specified amount of data subject to the instructions in the header bytes to the D_FRAME as data bytes. In some examples, the predefined amount of data is predetermined, such as the first X bits after the last bit of the header byte, the last X bits before the start of the END indicator, or the X bits starting at some other specified position of the D_FRAME. In other examples, the data to be written by each of the drivers 104A, 104B, and 104m is specified according to any suitable procedure or indicator. After one of the drivers 104A, 104B, 104m writes data to the D_FRAME, the D_FRAME is forwarded to the next downstream cascaded device, and the above process of receiving and writing data to the D_FRAME repeats until the D_FRAME is provided to the controller 102 by the driver 104m.

[0043] Although Figure 6 The above description is based on the premise that controller 102 sends D_FRAME to driver 104A. However, in other embodiments, controller 102 sends D_FRAME to driver 104m instead. In such examples, the actions attributed to driver 104A are instead performed by driver 104m, and the actions attributed to driver 104m are instead performed by driver 104A.

[0044] Figure 7 is a flow chart of an example method 700. The method 700 is an example of a display control method for writing data from a display controller to multiple drivers. In at least some examples, the method 700 is implemented in a system such as Figure 1 Accordingly, when describing the method 700, reference may be made to the components and / or signals described above with respect to any of the figures described herein.

[0045] At operation 702, the display controller provides a data frame to a driver in a driver daisy chain and provides a clock signal to each driver in the driver daisy chain. In some examples, the data frame is a D_FRAME and the clock is SCLK. As described above, in some embodiments, the D_FRAME includes an indicator of a START state, a header byte, a check bit, an END indicator, and one or more data bytes. In at least some examples, the data frame includes data bytes for multiple drivers. The display controller transmits the data frame to the first of the multiple drivers in the driver daisy chain.

[0046] At operation 704, a first one of the plurality of drivers provides a second clock signal based on the clock signal and samples the received data frame based on the clock signal. In at least some examples, the second clock signal is GCLK, as described elsewhere herein, and the first one of the plurality of drivers provides the second clock signal by processing the clock signal with a PLL. In at least some embodiments, the first one of the plurality of drivers samples the data frame at both the rising and falling edges of the clock signal. The first one of the plurality of drivers removes a portion of the data bytes of the data frame that are addressed to or otherwise designated for the first one of the plurality of drivers, and then provides the remaining portion of the data frame to the next driver (e.g., the second driver) of the plurality of drivers in the driver daisy chain.

[0047] At operation 706, a second driver in the plurality of drivers provides a second clock signal based on the clock signal and samples the received data frame based on the clock signal. In at least some examples, the second clock signal is GCLK, as described elsewhere herein, and the second driver in the plurality of drivers provides the second clock signal by processing the clock signal with a PLL. In at least some embodiments, the second driver in the plurality of drivers samples the data frame at both the rising and falling edges of the clock signal. The second driver in the plurality of drivers removes a portion of the data bytes of the data frame that are addressed to or otherwise designated for the second driver in the plurality of drivers. If the second driver in the plurality of drivers is the last driver in the driver daisy chain, the second driver in the plurality of drivers provides the remaining portion of the data frame to the display controller. If the second driver in the plurality of drivers is not the last driver in the driver daisy chain, the second driver in the plurality of drivers provides the remaining portion of the data frame to the next driver in the plurality of drivers in the driver daisy chain (e.g., the third driver). Operation 706 is repeated for each driver in the driver daisy chain following the first driver in the plurality of drivers until the next hop in the daisy chain is back to the display controller.

[0048] Figure 8800 is a flow chart of an example method. The method 800 is an example of a display control method in which a display controller reads data from multiple drivers. In at least some examples, the method 800 is used in a system such as Figure 1 Accordingly, when describing the method 800, reference may be made to the components and / or signals described above with respect to any of the figures described herein.

[0049] At operation 802, the display controller provides a data frame to the drivers in the driver daisy chain and provides a clock signal to each driver in the driver daisy chain. In some examples, the data frame is D_FRAME and the clock is SCLK. As described above, in some embodiments, D_FRAME includes an indicator of the START state, a header byte, a check bit, and an END indicator. The display controller transmits the data frame to the first of the plurality of drivers in the driver daisy chain.

[0050] At operation 804, a first one of the plurality of drivers provides a second clock signal based on the clock signal and writes data to the received data frame based on the clock signal. In at least some examples, the second clock signal is GCLK, as described elsewhere herein, and the first one of the plurality of drivers provides the second clock signal by processing the clock signal with a PLL. In at least some examples, the first one of the plurality of drivers writes the data to the data frame at both the rising and falling edges of the clock signal. In some examples, the data to be written to the data frame by the first one of the plurality of drivers is output data of the first one of the plurality of drivers. After writing the data to the data frame, the first one of the plurality of drivers transmits the data frame to the next driver (e.g., the second driver) among the plurality of drivers in the driver daisy chain.

[0051] At operation 806, a second driver among the plurality of drivers provides a second clock signal based on the clock signal and writes data into the received data frame based on the clock signal. In at least some examples, the second clock signal is GCLK, as described elsewhere herein, and the second driver among the plurality of drivers provides the second clock signal by processing the clock signal with a PLL. In at least some embodiments, the second driver among the plurality of drivers writes data into the data frame at both the rising and falling edges of the clock signal. In some examples, the data to be written into the data frame by the second driver among the plurality of drivers is output data of the second driver among the plurality of drivers. If the second driver among the plurality of drivers is the last driver in the driver daisy chain, the second driver among the plurality of drivers transmits the data frame to the display controller after writing the data into the data frame. If the second driver among the plurality of drivers is not the last driver in the driver daisy chain, the second driver among the plurality of drivers transmits the data frame to the next driver among the plurality of drivers in the driver daisy chain (e.g., the third driver). Operation 806 is repeated for each driver in the driver daisy chain following the first driver among the plurality of drivers in the driver daisy chain until the next hop in the daisy chain is back to the display controller.

[0052] In this specification, the term "coupled" can cover any connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: (a) in the first example, device A is directly coupled to device B; or (b) in the second example, device A is indirectly coupled to device B through an intermediate component C, where the intermediate component C does not substantially change the functional relationship between devices A and B, such that device B is controlled by device A via the control signal provided by device A.

[0053] A device that is "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform that function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may occur through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0054] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more power sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or power sources to form the structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0055] Although certain components may be described herein as belonging to a specific process technology, these components may be replaced for components of other process technologies. The circuits described herein may be reconfigured to include replaced components to provide functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide a certain amount of impedance represented by the resistors shown. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0056] The phrase "ground voltage potential" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise specified, the phrase "about," "approximately," or "substantially" preceding a numerical value means ±10% of the stated value. Modifications are possible in the examples described, and other examples are possible within the scope of the claims. Modifications are possible in the examples described, and other examples are possible within the scope of the claims.

Claims

1. A circuit comprising: A driver comprising: a phase-locked loop configured to receive a first clock signal and provide a second clock signal based on the first clock signal; and A digital interface configured to: receiving the first clock signal; receiving and sampling data from a data frame at successive rising edge transitions and falling edge transitions of a first clock signal, wherein the first clock signal is based on a frame rate, a ratio of a transmission time of one data frame, and a number of data bits, and wherein the second clock signal is based on a ratio of the frame rate and a display time of one data frame; extracting from the data frame a portion of the data frame addressed to the driver; and A portion of the data frame remaining after extracting the portion of the data frame addressed to the driver is provided.

2. The circuit of claim 1 , wherein the driver is a first driver and the circuit further comprises a second driver, and the data bits comprise the portion of the data frame addressed to the first driver and data addressed to the second driver.

3. The circuit of claim 2 , wherein the second driver comprises: a second phase-locked loop configured to receive the first clock signal and provide a replica of the second clock signal based on the first clock signal; as well as A second digital interface, wherein the second digital interface is configured to: receiving the first clock signal; receiving and sampling data from the remaining portion of the data frame at successive rising edge transitions and falling edge transitions of the first clock signal; extracting from the data frame a portion of the data frame addressed to the second driver; as well as A second portion of the data frame remaining after extracting the portion of the data frame addressed to the second driver is provided. 4 . The circuit of claim 3 , wherein when the remaining second portion of the data frame includes data addressed to a third driver, the second digital interface is configured to provide the second remaining portion of the data frame to a third driver.

5. The circuit of claim 3 , wherein when the remaining second portion of the data frame does not include data addressed to other drivers, the second digital interface is configured to provide the second remaining portion of the data frame to a display controller, the display controller providing the data frame and the first clock signal.

6. The circuit of claim 5 , wherein the display controller, the first driver, and the second driver are each configured to control a display, the first driver controlling a first portion of the display based at least in part on the portion of the data frame addressed to the first driver and the second clock signal, and the second driver being configured to control a second portion of the display based at least in part on the portion of the data frame addressed to the second driver and the replica of the second clock signal.

7. The circuit of claim 1 , wherein the driver is configured to receive the data frame and the first clock signal from a display controller, the display controller being configured to control rows of a display, and the driver is configured to control columns of the display based at least in part on the portion of the data frame addressed to the driver and the second clock signal.

8. A circuit comprising: A driver comprising: a phase-locked loop configured to receive a first clock signal and provide a second clock signal based on the first clock signal, wherein the first clock signal is based on a frame rate, a ratio of transmission time of one data frame, and a number of data bits, and wherein the second clock signal is based on a ratio of the frame rate and display time of one data frame; and A digital interface configured to: receiving the first clock signal; Receive data frames; writing data into the data frame at successive rising edge transitions and falling edge transitions of the first clock signal; and The data frame is provided after the data frame is written.

9. The circuit of claim 8, wherein the data frame received by the driver includes a start indicator, a header byte, a check bit, and an end indicator.

10. The circuit of claim 9, wherein the data frame provided by the driver includes a start indicator, the header byte, the check bit, data bytes, and the end indicator.

11. The circuit of claim 8, wherein the driver is a first driver, and the circuit further comprises a second driver comprising: a second phase-locked loop configured to receive the first clock signal and provide a replica of the second clock signal based on the first clock signal; as well as A second digital interface, wherein the second digital interface is configured to: receiving the first clock signal; receiving the data frame from the first driver; writing data into the data frame at successive rising edge transitions and falling edge transitions of the first clock signal; The data frame is provided after the data frame is written.

12. The circuit of claim 11, wherein the second digital interface provides the data frame to a third driver when the third driver is in a daisy chain between the second driver and a display controller.

13. The circuit of claim 11, wherein when a third driver is not coupled between the second driver and the display controller, the second digital interface provides the data frame to the display controller, and the display controller provides the data frame and the first clock signal.

14. The circuit according to claim 11, wherein the data written by the first driver to the data frame is output data provided by the first driver based on control of a first portion of the display, and the data written by the second driver to the data frame is output data provided by the second driver based on control of a second portion of the display.

15. A system comprising: a display comprising a portion arranged in a plurality of rows and columns; A display controller configured to: controlling said rows of said display; providing a data frame to a first driver of a driver daisy chain; as well as providing a first clock signal to each driver in the driver daisy chain; and The first driver, wherein the first driver is configured to: providing a second clock signal based on the first clock signal, wherein the first clock signal is based on a frame rate, a ratio of transmission time of one data frame, and a number of data bits, and wherein the second clock signal is based on a ratio of the frame rate and display time of one data frame; receiving the data frame from the display controller; removing from the data frame a portion of the data frame addressed to the first driver; providing the remainder of the data frame to the next driver in the driver daisy chain; and The portion of the display is controlled based on the portion of the data frame addressed to the first driver and the second clock signal.

16. The system of claim 15 , wherein the portion is a first portion, the display includes a second portion arranged in a plurality of rows and columns, and the system further includes the next driver in the driver daisy chain, and the next driver in the driver daisy chain is a second driver, the second driver being configured to: providing a replica of the second clock signal based on the first clock signal; receiving the remaining portion of the data frame from the first driver; removing a portion of the remaining portion of the data frame addressed to the second driver from the remaining portion of the data frame; providing a second remaining portion of the data frame after removing the portion of the remaining portion of the data frame addressed to the second driver to a next device; as well as The second portion of the display is controlled based on the portion of the data frame addressed to the second driver and the copy of the second clock signal.

17. The system of claim 16, wherein when the driver daisy chain includes more than two drivers, the next device is a third driver in the driver daisy chain, and when the driver daisy chain includes two drivers, the next device is the display controller.

18. The system of claim 16, wherein the display controller is configured to provide a second data frame to the first driver in the driver daisy chain, and the first driver is configured to: receiving the second data frame from the display controller; writing the data output of the first driver into the second data frame; as well as providing the second data frame to the second driver; and wherein the second driver is configured to: receiving the second data frame from the first driver; writing the data output of the second driver into the second data frame; and The second data frame is provided to the next device.

19. The system of claim 18, wherein when the driver daisy chain includes more than two drivers, the next device is a third driver in the driver daisy chain, and when the driver daisy chain includes two drivers, the next device is the display controller.

Images