A packaged antenna device using chip-in-film technology

Abstract

Embodiments disclose packaged antenna devices employing chip-in-film technology. A semiconductor device includes a dielectric substrate; an integrated circuit (IC) die disposed inside an opening of the dielectric substrate, wherein the IC die is configured to transmit or receive radio frequency (RF) signals; a dielectric material located in the opening of the dielectric substrate and around the IC die; a redistribution structure along a first side of the dielectric substrate, wherein a first conductive feature of the redistribution structure is electrically coupled to the IC die; a second conductive feature along a second side of the dielectric substrate opposite the first side; a via extending through the dielectric substrate, wherein the via electrically couples the first conductive feature and the second conductive feature; and an antenna located at the second side of the dielectric substrate, wherein the second conductive feature is electrically or electromagnetically coupled to the antenna.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and in certain embodiments to packaged antenna (AiP) devices. Background Technology

[0002] Semiconductor devices with embedded radio frequency integrated circuits (RFICs) are used in electrical equipment such as mobile devices. An example of such a semiconductor device is an antenna-in-package (AiP) device.

[0003] Antenna-in-Package (AiP) represents a new trend in integrated circuit (IC) packaging, enabling smaller and highly integrated semiconductor devices. AiP devices comprise an RF IC (e.g., an IC including both a baseband module and an RF module) and an antenna within the same package. AiP allows complex RF components to be integrated with baseband circuitry into a self-contained module. AiP devices not only reduce the footprint of the integrated functional modules but also streamline the work of system integrators. For example, system integrators no longer need to design complex RF circuitry at the application's printed circuit board (PCB) level. Furthermore, the overall size of the entire application is reduced.

[0004] While the continued reduction in the size of AiP devices due to the shrinking size of electrical equipment (e.g., mobile phones) may be advantageous, challenges exist. For example, at millimeter-wave frequencies, limiting factors for reducing the size of AiP devices may not stem from antenna size, but rather from the allocation and wiring of ball pads (e.g., conductive pads on which external connectors such as solder balls are formed) and the size of the ball pads themselves. New structural and integration methods are needed in the art to further reduce the size of AiP devices. Summary of the Invention

[0005] According to an embodiment of the present invention, a semiconductor device includes: a dielectric core; a radio frequency integrated circuit (RFIC) disposed in an opening of the dielectric core and surrounded by a dielectric material, wherein the dielectric material fills the space between the RFIC and the dielectric core; a redistribution structure located on a first side of the dielectric material, wherein a first conductive feature of the redistribution structure is electrically coupled to the RFIC; an antenna located on a second side of the dielectric material opposite to the first side; and a via laterally spaced from the RFIC and extending through the dielectric core, wherein a first end of the via is electrically coupled to the first conductive feature of the redistribution structure, and a second end of the via is electrically coupled to the antenna or electrically coupled to a second conductive feature extending along the second side of the dielectric material, wherein the second conductive feature is configured to be electromagnetically coupled to the antenna.

[0006] According to an embodiment of the present invention, a semiconductor device includes: a dielectric substrate; an integrated circuit (IC) die disposed within an opening in the dielectric substrate, wherein the IC die is configured to transmit or receive radio frequency (RF) signals; a dielectric material located in the opening of the dielectric substrate and around the IC die; a redistribution structure along a first side of the dielectric substrate, wherein a first conductive feature of the redistribution structure is electrically coupled to the IC die; a second conductive feature along a second side of the dielectric substrate opposite to the first side; a via extending through the dielectric substrate, wherein the via is electrically coupled to the first and second conductive features; and an antenna located on the second side of the dielectric substrate, wherein the second conductive feature is electrically or electromagnetically coupled to the antenna.

[0007] According to an embodiment of the present invention, a method includes placing a radio frequency integrated circuit (RFIC) in an opening of a dielectric core; filling the opening of the dielectric core with a dielectric material; forming a via extending through the dielectric core; forming a redistribution structure on a first side of the dielectric core, wherein a first conductive feature of the redistribution structure is formed to be electrically coupled to the RFIC; forming a second conductive feature on a second side of the dielectric core opposite to the first side, wherein the second conductive feature is electrically coupled to the first conductive feature through the via; and forming an antenna on the second side of the dielectric core, wherein the antenna is formed to be electrically or electromagnetically coupled to the second conductive feature. Attached Figure Description

[0008] To gain a more complete understanding of the invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 These are block diagrams of radio frequency integrated circuits (RFICs) in some embodiments;

[0010] Figures 2 to 6 , Figure 7A and Figure 7B Various diagrams of a semiconductor device at different manufacturing stages are shown in one embodiment;

[0011] Figures 8 to 13 Cross-sectional views of a semiconductor device at different manufacturing stages are shown in one embodiment;

[0012] Figures 14 to 19 Cross-sectional views of a semiconductor device at different manufacturing stages are shown in one embodiment;

[0013] Figures 20 to 24 Cross-sectional views of semiconductor devices of various embodiments are shown;

[0014] Figure 25 This is a flowchart of a method for forming a semiconductor device in some embodiments. Detailed Implementation

[0015] The manufacture and use of the currently disclosed embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of manufacturing and using the invention and do not limit the scope of the invention. Throughout the discussion, unless otherwise stated, the same or similar reference numerals in different embodiments refer to the same or similar components formed from the same or similar materials using the same or similar forming methods.

[0016] This invention will be described with reference to an example embodiment in a specific context (i.e., an antenna-in-package (AiP) device). In one embodiment, the AiP device includes a radio frequency integrated circuit (RFIC) disposed in an opening in a dielectric core and surrounded by a dielectric material, wherein the dielectric material fills the space between the RFIC and the dielectric core. The AiP device also includes a redistribution structure on a first side of the dielectric material, wherein a first conductive feature of the redistribution structure is electrically coupled to the RFIC. The AiP device also includes an antenna located on a second side of the dielectric material opposite to the first side, and a via laterally spaced from the RFIC and extending through the dielectric core, wherein a first end of the via is electrically coupled to the first conductive feature of the redistribution structure, and a second end of the via is electrically coupled to the antenna or electrically coupled to a second conductive feature extending along the second side of the dielectric material, wherein the second conductive feature is configured to be electromagnetically coupled to the antenna.

[0017] Figure 1 This is a block diagram of a radio frequency integrated circuit (RFIC) 103 in one embodiment. RFIC 103 can be used to form various embodiments of the antenna-in-package (AiP) device disclosed herein.

[0018] Figure 1 A functional block diagram of RFIC 103 is shown. RFIC 103 can also be referred to as an RFIC die or RFIC chip. Note that for simplicity, in... Figure 1 Not all function blocks of RFIC 103 are shown in the diagram. Figure 1In the example, RFIC 103 includes a baseband module 311, an RF module 313, a transmit (Tx) module 315, and a receive (Rx) module 317. The baseband module 311 is designed to perform digital baseband processing functions, such as digital filtering, equalization, and digital resampling. The RF module 313 is designed to process RF signals and perform RF-related functions, such as modulating or demodulating RF signals. The RF module 313 may include RF-related components, such as mixers and oscillators. Depending on the design of RFIC 103, analog-to-digital converters (ADCs) and / or digital-to-analog converters (DACs) may be formed in the RF module 313 or the baseband module 311. The Tx module 315 is designed to perform functions related to transmitting RF signals and may include electrical components such as power amplifiers. The Rx module 317 is designed to perform functions related to receiving RF signals and may include electrical components such as analog filters and low-noise amplifiers. RFIC103 is electrically coupled to external circuitry via conductive pad 102 (also known as input / output (I / O) pad). Figure 1 Also shown is an RF terminal 102R (e.g., an I / O pad connected to a Tx module or Rx module), which is electrically coupled to Tx module 315 and / or Rx module 317. In some embodiments, RFIC 103 transmits only RF signals and therefore includes Tx module 315 but not Rx module 317. In other embodiments, RFIC 103 receives only RF signals and therefore includes Rx module 317 but not Tx module 315. These and other variations are fully intended to be included within the scope of this disclosure.

[0019] Figures 2 to 6 , Figure 7A and Figure 7B Various diagrams (e.g., cross-sectional views, planar views) of a semiconductor device 100 (e.g., an AiP device) at different manufacturing stages are shown in one embodiment. Reference Figure 2 A core 107 (also referred to as a dielectric core, dielectric core substrate, or dielectric substrate) having an opening 108 is attached to a carrier 101, and an RFIC 103 is placed inside the opening 108 and attached to the carrier 101. In other words, the opening 108 forms a cavity in the core 107, in which the RFIC 103 is disposed. Therefore, the core 107 laterally surrounds the RFIC 103. For example, the cavity is disposed in the central region of the core 107.

[0020] The carrier 101 may be made of a material such as metal foil, ceramic, glass, epoxy glass, silicon, polymer, polymer composite, beryllium oxide, tape, or other suitable material for structural support. In some embodiments, an adhesive layer such as a die attachment film (DAF) may be used to attach the core 107 and / or RFIC 103 to the carrier 101.

[0021] Core 107 is formed of a dielectric material such as epoxy resin or glass fiber (such as pre-preg). For example, core 107 may include bismaleimide triazine (BT) resin, FR-4 (a composite material made of woven glass fiber cloth with flame-retardant epoxy resin adhesive), ceramic, glass, plastic, tape, membrane, or other support material. Opening 108 is formed in core 107, for example, by a drilling process such as mechanical drilling or laser drilling. Opening 108 is large enough to accommodate RFIC 103.

[0022] exist Figure 2 In the example, the front side of RFIC 103 (e.g., the side with I / O pads 102) is attached to carrier 101. The back side of RFIC 103 has a ground plane 105, which may be a layer of conductive material (e.g., copper) formed on the back side of RFIC 103. The ground plane 105 may be electrically grounded, for example, by electrically coupling the ground plane 105 to a through-substrate via (TSV) 104 of a ground I / O pad 102G (e.g., an I / O pad configured to be electrically grounded). For simplicity, TSV 104 and ground I / O pad 102G may not be shown in subsequent figures, as it is understood that TSV 104 and ground I / O pad 102G may be formed. The ground plane 105 is optional and therefore may be omitted in some embodiments. As will be readily understood by those skilled in the art, the ground plane 105 can reduce electromagnetic interference (EMI) to or from RFIC 103.

[0023] Next, in Figure 3 In this process, a dielectric material 109 (also referred to as a sealant) is formed on the carrier 101 to surround the RFIC 103 and fill the opening 108. The dielectric material 109 may also cover the upper surface of the core 107. The dielectric material 109 may be formed from a suitable encapsulation material (such as resin, epoxy resin, organic polymer, polymer with or without silicon-based or glass fillers, or other materials). For example, it may be... Figure 2 A resin sheet (such as an Ajinomoto polymer film (ABF)) is deposited on the structure shown and cured to form a dielectric material 109. Therefore, in the illustrated embodiment, the dielectric material 109 forms a molding material.

[0024] Next, in Figure 4 In this process, for example, the carrier 101 is removed by a carrier de-bonding process. Furthermore, for example, using the same or similar formation process described above, additional dielectric material 109 is formed on the lower surface of the core 107 and the front side of the RFIC 103. Next, a seed layer 111 is formed on the upper and lower surfaces of the dielectric material 109. The seed layer 111 may include a suitable conductive material (such as copper) and may be formed by stacking thin metal foils (such as copper foil) on the upper and lower surfaces of the dielectric material 109. In some embodiments, the seed layer 111 is formed using a suitable formation method (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.).

[0025] Next, in Figure 5 An opening 113 (e.g., 113A and 113B) is formed in the core 107 or the dielectric material 109. Figure 5 In the example, opening 113A (e.g., a through-hole) extends through core 107 / dielectric material 109 and can be formed by a mechanical drilling process. Opening 113B (e.g., a recess) partially extends through dielectric material 109 to expose conductive pads 102 of RFIC 103. In some embodiments, the bottom surface of conductive pad 102 may be a copper layer or include a copper layer, and opening 113B is formed by a laser drilling process. The copper layer of conductive pad 102 can be used as a stop layer to control the stopping point of the laser drilling process.

[0026] Next, in Figure 6 In the middle, using a suitable forming method (such as electroplating), in the opening 113 (see Figure 5 Conductive material (e.g., copper) is formed on the upper and lower surfaces of the dielectric material 109. The conductive material in opening 113A forms a via 125, and the conductive material in opening 113B forms a microvia 115.

[0027] Additionally, conductive features 117, such as metal lines, are formed along the lower surface of the dielectric material 109. These metal lines reroute signals from the conductive pads 102 of the RFIC 103 to different locations for connection to, for example, vias 125 or external connectors 127 (see [link]). Figure 7AFor example, conductive feature 117 (e.g., a metal line) can be electrically coupled to conductive pad 102 of RFIC 103 via microvia 115, and RFIC 103 can be electrically coupled to conductive feature (e.g., 126) formed on the upper surface of dielectric material 109. Conductive feature 117 can be formed by forming a patterned photoresist layer with a designed pattern on seed layer 111, plating conductive material on exposed portions of seed layer 111 (e.g., exposed by the pattern of the patterned photoresist layer), removing the patterned photoresist layer after plating, and etching away portions of seed layer 111 where no conductive material is formed.

[0028] After the conductive feature 117 is formed, a dielectric layer 119 is formed on the lower surface of the dielectric material 109 to cover the conductive feature 117. In some embodiments, the dielectric layer 119 is formed of a polymer (such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.). In other embodiments, the dielectric layer 119 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), or boron-doped phosphosilicate glass (BPSG), etc. The dielectric layer 119 can be formed by any acceptable deposition process (such as spin coating, chemical vapor deposition (CVD), lamination, etc., or combinations thereof). The conductive feature 117 and the dielectric layer 119 can be collectively referred to as the redistribution structure 118. Although Figure 6 A single conductive feature 117 and a dielectric layer 119 are shown in the redistribution structure 118, but the redistribution structure 118 may include multiple layers of conductive features (e.g., wires and vias) formed in multiple dielectric layers.

[0029] Still referencing Figure 6 Conductive feature 126 (e.g., metal wire) and antenna 121 are formed on the upper surface of dielectric material 109. Conductive feature 126 and antenna 121 can be formed using the same or similar forming method as conductive feature 117, so details will not be repeated. Conductive feature 126 can be a metal wire (e.g., copper wire) electrically coupling via 125 to antenna 121.

[0030] For reference only Figure 7B It shows a top view of conductive feature 126 and antenna 121. Figure 7BIn the example, antenna 121 is a rectangular metal pattern (e.g., a copper pattern) having a first dimension D1 and a second dimension D2, wherein D1 is, for example, between 0.5 mm and 1.5 mm, and D2 is, for example, between 0.5 mm and 1.5 mm. The dimensions D1 and D2 can vary depending on the material parameters. In some embodiments, the dimensions of antenna 121 are determined by the frequency of the radio signal being transmitted or received, and can therefore be modified to accommodate different RF communication frequencies. Antenna 121 is configured to transmit or receive RF signals. Figure 7B In the example, one of the antennas 121 can be a transmitting (Tx) antenna, while the other of the antennas 121 can be a receiving (Rx) antenna. Therefore, the semiconductor device 100 can transmit and receive RF signals. In some embodiments, only one antenna (e.g., a Tx antenna or an Rx antenna) is formed, in which case the semiconductor device only transmits or only receives RF signals. In some embodiments, more than one Tx antenna or more than one Rx antenna is formed in the semiconductor device 100.

[0031] Return to reference Figure 6 A dielectric layer 123 is formed on the upper surface of the dielectric material 109 and covers the antenna 121. In some embodiments, the dielectric layer 123 may be formed of the same material as the dielectric layer 119. In other embodiments, the dielectric layer 123 may be formed of a different dielectric material than the dielectric layer 119. In the illustrated embodiment, the dielectric layer 123 is a solder resist layer and is different from the dielectric layer 119.

[0032] Next, in Figure 7A An external connector 127 is formed. In the illustrated embodiment, the external connector 127 extends into the dielectric layer 119 and is mechanically and electrically coupled to the conductive feature 117. In one embodiment, the external connector 127 is a conductive bump (such as a controlled folded chip connection (C4) bump) and comprises a material such as tin or other suitable materials such as silver or copper. In embodiments where the external connector 127 is a solder bump, the external connector 127 may be formed by initially forming a tin layer by any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the tin layer is structurally formed, a reflow is performed to shape the material into a bump shape.

[0033] However, although external connector 127 has been described above as having C4 bumps, these bumps are intended to be illustrative only and not to limit the embodiments. In contrast, any suitable type of external contact can be optionally utilized, such as ball grid arrays (BGAs), microbumps, copper pillars, copper layers, nickel layers, lead-free (LF) layers, electroless nickel-plated palladium-plated immersion gold (ENEPIG) layers, Cu / LF layers, Sn / Ag layers, Sn / Pb, combinations thereof, etc. Any suitable external connector and any suitable process for forming the external connector can be used for external connector 127, and all such external connectors are fully intended to be included within the scope of the embodiments.

[0034] In some embodiments, the external connector 127 is omitted. In embodiments where the external connector 127 is omitted, an opening may be formed in the dielectric layer 119 to expose portions of the conductive feature 117 for electrical connection to another device. For example, a pad grid array (LGA) connector for a semiconductor device 100 may be formed.

[0035] Figure 7B It shows Figure 7A A plan view of the semiconductor device 100. Note that in Figure 7B Not all features of the semiconductor device 100 are shown in the diagram, and Figure 7B The features shown may not be along the same cross-section. Figure 7B The periphery (e.g., boundary or sidewall) of RFIC 103 and dielectric layer 123 is shown. Figure 7B The via 125, the antenna 121, and the conductive features 126 that electrically couple the via 125 to the corresponding antenna 121 are also shown. Figure 7B External connector 127 is further shown.

[0036] During normal operation, the RF signal generated by RFIC 103 is routed from conductive pad 102 to antenna 121 via, for example, via 125 and conductive features 117 / 126. Antenna 121 then transmits the RF signal in a specific RF frequency band. Similarly, the RF signal received at antenna 121 is routed from antenna 121 to conductive pad 102, and RFIC 103 processes the received RF signal.

[0037] Figures 8 to 13 Cross-sectional views of a semiconductor device 200 at different manufacturing stages are shown in one embodiment. Figure 8 In this configuration, the front side of RFIC 103 is attached to carrier 101. RFIC 103 is positioned in an opening in core 107, which is also attached to carrier 101. Dielectric material 109 is formed around RFIC 103 and fills the opening in core 107. Figure 8 The semiconductor device 200 shown can be used with Figure 2 and Figure 3 The same or similar processing steps are used to form it. Figure 8 The optional ground plane 105 on the back of the RFIC 103 is further shown.

[0038] Next, in Figure 9 In this process, an etching process (such as dry plasma etching or chemical mechanical planarization (CMP)) is performed to remove excess portions of the dielectric material 109 from the upper surface of the core 107. After the etching process, the upper surface of the dielectric material is flush with (e.g., coplanar) the upper surface of the core 107. Next, the carrier 101 is removed, for example, by a carrier debonding process. The lower surface of the dielectric material 109 is flush with (e.g., coplanar) the lower surface of the core 107. The conductive pads 102 of the RFIC 103 are exposed on the lower surface of the dielectric material 109, as shown below. Figure 9 As shown.

[0039] Next, in Figure 10 In this process, seed layers 111 are formed on the upper and lower surfaces of the dielectric material 109. The seed layer 111 can be, for example, a copper layer formed by sputtering, PVD, CVD, or other suitable formation methods. The seed layer 111 can be patterned, for example, by forming a patterned mask layer on the seed layer 111 and etching the exposed portions of the seed layer 111. In other embodiments, the seed layer 111 is blanket-deposited and not patterned. Figure 10 As shown, the seed layer 111 partially overlaps with and physically contacts the conductive pads 102 of the RFIC 103.

[0040] Next, in Figure 11 An opening 113 is formed in the core 107. The opening 113 can be formed by a mechanical drilling process. The opening 113 extends through the core 107 and can also extend through the seed layer 111.

[0041] Next, in Figure 12 In this process, conductive material (e.g., copper) is formed in the opening 113 by electroplating and on the seed layer 111. Thus, a via 125 is formed in the opening 113, and conductive features 117 are formed along the lower surface of the dielectric material 109 and / or along the lower surface of the core 107. Additionally, conductive features 126 and an antenna 121 are formed on the upper surface of the dielectric material 109 and / or the upper surface of the core 107. In embodiments where the seed layer 111 is not patterned, a patterned mask layer is formed on the (unpatterned) seed layer 111 before electroplating, and after the electroplating process is completed, the patterned mask layer is removed, and the unplated conductive material portion on the seed layer 111 is removed, for example, by etching. Note that in Figure 12Once formed, conductive feature 117 is electrically coupled to conductive pad 102. This is related to semiconductor device 100 (e.g., see...). Figure 6 Compared to this, there is no need for a microvia 115 to electrically couple the conductive feature 117 to the conductive pad 102.

[0042] Still referencing Figure 12 A dielectric layer 119 is formed on the lower surface of the dielectric material 109 and covers the conductive feature 117. Openings may be formed in the dielectric layer 119 to expose portions of the conductive feature 117. A dielectric layer 123 (e.g., a solder resist layer) is formed on the upper surface of the dielectric material 109 and covers the antenna 121 and the conductive feature 126.

[0043] Next, in Figure 13 In this embodiment, an external connector 127, such as a BGA, is formed. In other embodiments, the external connector 127 is omitted, and an LGA connector for the semiconductor device 200 can be formed.

[0044] According to an embodiment, Figure 13 The dielectric material 109 in the semiconductor device 200 has the same thickness as the core 107. In other words, the dielectric material 109 has an upper surface and a lower surface that are coplanar with the core 107. In contrast, Figure 7A The dielectric material 109 of the semiconductor device 100 has a greater thickness than the core 107, and therefore the dielectric material 109 extends along the upper and lower surfaces of the core 107 and physically contacts the upper and lower surfaces of the core 107.

[0045] Figures 14 to 19 Cross-sectional views of a semiconductor device 300 at different manufacturing stages are shown in one embodiment. The fabrication process of the semiconductor device 300 is similar to that of the semiconductor device 200, but the vias 125 of the semiconductor device 300 are pre-formed as part of the core 107.

[0046] In some embodiments, to form the pre-formed via 125, a conductive post (e.g., a copper post) is formed on the carrier 101. Next, a material (e.g., epoxy resin or glass fiber) is formed on the carrier 101 and around the copper post to form the core 107. Once encapsulated by the core 107, the conductive post becomes (e.g., serves as) the via 125. An opening 108 is then formed in the core 107 (e.g., by drilling) to provide a space for attaching the RFIC 103 in subsequent processing. Figure 14 A core 107 with a pre-formed via 125 and an opening 108 is shown. Other methods for forming a core 107 with a pre-formed via 125, besides those described above, are also possible and are fully intended to be included within the scope of this disclosure.

[0047] Next, in Figure 15 In this configuration, the front side of the RFIC 103 is attached to the carrier 101, wherein the RFIC 103 is located in an opening in the core 107. Next, a dielectric material 109 is formed around the RFIC 103 and fills the opening. The dielectric material 109 may have excess portions disposed on the upper surface of the core 107.

[0048] Next, in Figure 16 In the process, an etching process (such as dry plasma etching or CMP process) is performed to remove excess portions of the dielectric material 109, and thereafter, the carrier 101 is removed. After the etching process and carrier debonding, the via 125 and conductive pad 102 are exposed, as shown. Figure 16 As shown.

[0049] Next, in Figure 17 In this process, seed crystal layers 111 are formed on the upper and lower surfaces of the dielectric material 109. For example... Figure 17 As shown, the seed layer 111 partially overlaps and physically contacts the via 125 and conductive pad 102 of the RFIC 103.

[0050] Next, in Figure 18 In this process, a conductive material (e.g., copper) is formed on the seed layer 111, for example, by an electroplating process. Next, a dielectric layer 119 is formed on the lower surface of the dielectric material 109, and a dielectric layer 123 (e.g., solder resist) is formed on the upper surface of the dielectric material 109.

[0051] Next, in Figure 19 In this embodiment, an external connector 127 (such as a BGA) is formed to be mechanically and electrically coupled to conductive feature 117. In some embodiments, the external connector 127 is omitted, and an LGA-type connector may be formed for the semiconductor device 300.

[0052] Variations to the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. For example, depending on the number of antennas 121 used and / or the target RF sensitivity of the semiconductor device formed, multiple metal layers and multiple dielectric layers may be formed on the upper surface of the dielectric material 109. Figures 20 to 24 Cross-sectional views of semiconductor devices of various embodiments are shown.

[0053] Figure 20 A cross-sectional view of a semiconductor device 100A in one embodiment is shown. Semiconductor device 100A and... Figure 7A The semiconductor device 100 is similar, but has an additional dielectric layer 133 between the dielectric material 109 and the dielectric layer 123. Figure 20In this configuration, via 125 electrically couples RFIC 103 to a conductive feature 131 extending (e.g., in physical contact) along the upper surface of dielectric material 109. The conductive feature 131 may be, for example, a copper wire, and may have a... Figure 7A and Figure 7B The conductive features 126 in the figure have the same or similar shapes.

[0054] Still referencing Figure 20 The dielectric layer 133 can be a high-performance RF material, such as Rogers 3003. The antenna 121 is formed on the upper surface of the dielectric layer 133 and is covered by the dielectric layer 123 (e.g., a solder mask). Note that in Figure 20 In this configuration, antenna 121 is not electrically coupled to conductive feature 131. In contrast, antenna 121 (also referred to as a patch antenna) is electromagnetically coupled to the corresponding conductive feature 131. The thickness and / or material of dielectric layer 133 can be adjusted to provide different RF sensitivities, for example, in semiconductor device 100A. Figure 20 The antenna structure shown can be called a proximity-coupled patch antenna.

[0055] Figure 21 A cross-sectional view of a semiconductor device 100B in one embodiment is shown. Semiconductor device 100B and... Figure 20 The semiconductor device 100A is similar, but has a conductive feed line 130 (e.g., copper wire or via) that directly connects (e.g., electrically couples) the antenna 121 to the corresponding conductive feature 131. Figure 21 The antenna structure shown can be called a single-layer probe-fed antenna or a U-slot antenna.

[0056] Figure 22 A cross-sectional view of a semiconductor device 100C in one embodiment is shown. Semiconductor device 100C and... Figure 20 Similar to the semiconductor device 100A, but with an additional grounding structure comprising a horizontal metal layer 135 (e.g., a copper layer or copper wire) and a vertical metal structure 137 (e.g., a copper via), wherein the horizontal metal layer 135 and the vertical metal structure 137 are electrically grounded. The vertical metal structure 137 may be formed by a copper via extending from the upper surface of the dielectric layer 133 to the lower surface of the dielectric layer 133. The horizontal metal layer 135 and the vertical metal structure 137 may be referred to as ground metal layers.

[0057] exist Figure 22In this configuration, the horizontal metal layer 135 has an opening 136 between the antenna 121 and the corresponding conductive feature 131, allowing RF signals emitted from the conductive feature 131 to be electromagnetically coupled to the antenna 121 through the opening 136. In some embodiments, a grounding structure forms a Faraday cage (electromagnetic shield) around each pair of antennas 121 and conductive features 131, thereby reducing EMI between different pairs of antennas 121 and conductive features 131. The Faraday cage also helps reduce EMI from the RFIC 103 to other nearby devices, and reduces EMI from other nearby devices to the RFIC 103. Figure 22 The antenna structure shown can be called a dual-aperture coupled antenna.

[0058] Figure 23 A cross-sectional view of a semiconductor device 100D in one embodiment is shown. Semiconductor device 100D and... Figure 22 The semiconductor device 100C is similar, but has a via 132 coupled between conductive feature 131 and another conductive feature 139 (e.g., a copper wire). Conductive feature 139 is formed between conductive feature 131 and horizontal metal layer 135, and therefore closer to opening 136 in horizontal metal layer 135. Additionally, Figure 23 A ground metal layer 134 is shown extending along and physically contacting the upper surface of the dielectric material 109. The ground metal layer 134 is disposed directly above the RFIC 103 and between the conductive features 131. The semiconductor device 100D can achieve improved spurious mode suppression.

[0059] Figure 24 A cross-sectional view of a semiconductor device 400 in one embodiment is shown. Semiconductor device 400 and... Figure 21 The semiconductor device 100B is similar, but the front side of the RFIC 103 faces the dielectric layer 133. Figure 24 In the example, the conductive pad 102 of RFIC 103 is electrically coupled to the conductive feature 131 through a microvia 115.

[0060] Additional changes are possible and are entirely intended to be included within the scope of this disclosure. For example, although Figures 20 to 24 The dielectric material 109 in the middle has a greater thickness than the core 107, but Figures 20 to 24 The embodiments in the embodiment can be modified so that the dielectric material 109 has the same thickness as the core 107, similar to the dielectric material 109 in, for example, the semiconductor device 200.

[0061] The embodiments can achieve advantages. For example, the disclosed embodiments provide improved integration density and reduce the size of the formed AiP device. The smaller device size not only reduces the footprint of the AiP device on the circuit board, but also improves RF sensitivity due to the reduced distance between antenna 121 and conductive feature 131. The ground plane 105 on the back of RFIC 103 reduces EMI to or from RFIC 103. The Faraday cage formed by the grounding structure further reduces EMI between different pairs of antenna 121 and conductive features (e.g., 131 or 139) and can provide improved spurious mode suppression.

[0062] Figure 25 This is a flowchart of a method for forming a semiconductor device in some embodiments. It should be understood that... Figure 25 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 25 The various steps shown.

[0063] refer to Figure 25 In step 1010, a radio frequency integrated circuit (RFIC) (e.g., 103) is placed on a dielectric core (e.g., see...). Figure 2 In the opening of 107). In step 1020, with a dielectric material (e.g., see 107) Figure 3 In step 1030, a via extending through the dielectric core is formed (e.g., see 109). Figure 6 (125 in the text). In step 1040, a redistribution structure is formed on the first side of the dielectric core (e.g., see 125 in the text). Figure 6 In step 118), a first conductive feature of the redistribution structure (e.g., see 117) is formed to be electrically coupled to the RFIC. In step 1050, a second conductive feature (e.g., see 118) is formed on the second side of the dielectric core opposite to the first side. Figure 6 In step 1060, an antenna is formed on the second side of the dielectric core (see, for example, 126), wherein the second conductive feature is electrically coupled to the first conductive feature through a via. Figure 6 In 121), the antenna is formed to be electrically or electromagnetically coupled to the second conductive feature.

[0064] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the overall description and claims submitted herein.

[0065] Example 1: In one embodiment, a semiconductor device includes: a dielectric core; a radio frequency integrated circuit (RFIC) disposed in an opening of the dielectric core and surrounded by a dielectric material, wherein the dielectric material fills the space between the RFIC and the dielectric core; a redistribution structure located on a first side of the dielectric material, wherein a first conductive feature of the redistribution structure is electrically coupled to the RFIC; an antenna located on a second side of the dielectric material opposite to the first side; and a via laterally spaced from the RFIC and extending through the dielectric core, wherein a first end of the via is electrically coupled to the first conductive feature of the redistribution structure, and a second end of the via is electrically coupled to the antenna or electrically coupled to a second conductive feature extending along the second side of the dielectric material, wherein the second conductive feature is configured to be electromagnetically coupled to the antenna.

[0066] Example 2: According to the semiconductor device of Example 1, the redistribution structure includes a dielectric layer and a first conductive feature in the dielectric layer.

[0067] Example 3: The semiconductor device according to Example 1 further includes an external connector electrically coupled to a first conductive feature of the redistribution structure, wherein the redistribution structure is between the external connector and the RFIC.

[0068] Example 4: The semiconductor device according to Example 1 further includes a solder resist layer on a second side of the dielectric material, wherein the solder resist layer covers the antenna.

[0069] Example 5: A semiconductor device according to Example 1, wherein the dielectric material and the dielectric core have a coplanar upper surface and a coplanar lower surface.

[0070] Example 6: A semiconductor device according to Example 1, wherein a dielectric material has a first thickness, the first thickness being greater than a second thickness of a dielectric core, wherein the first thickness and the second thickness are measured along a direction from a first side of the dielectric material to a second side of the dielectric material.

[0071] Example 7: A semiconductor device according to Example 1, wherein an antenna extends along and contacts a second side of a dielectric material, wherein a second end of a via is electrically coupled to the antenna.

[0072] Example 8: The semiconductor device according to Example 1 further includes a dielectric material between the dielectric material and the antenna, wherein the antenna extends along a first side of the dielectric material opposite to the RFIC and contacts the first side of the dielectric material opposite to the RFIC, wherein a second end of the via is electrically coupled to a second conductive feature extending parallel to the second side of the dielectric material.

[0073] Example 9: The semiconductor device according to Example 8 further includes a conductive feed in a dielectric material that electrically couples the second conductive feature to the antenna.

[0074] Example 10: The semiconductor device according to Example 8 further includes a metal layer in a dielectric material disposed between the antenna and the second conductive feature, wherein the metal layer extends parallel to a second side of the dielectric material, the metal layer is electrically grounded and has an opening, wherein the second conductive feature is configured to be electromagnetically coupled to the antenna through the opening of the metal layer.

[0075] Example 11: The semiconductor device according to Example 10 further includes a metal structure in the dielectric material and on the opposite side of the opening in the metal layer, wherein the metal structure is electrically grounded and extends from a first side of the dielectric material to a second side of the dielectric material facing the RFIC.

[0076] Example 12: In one embodiment, a semiconductor device includes: a dielectric substrate; an integrated circuit (IC) die disposed within an opening in the dielectric substrate, wherein the IC die is configured to transmit or receive radio frequency (RF) signals; a dielectric material located in the opening of the dielectric substrate and around the IC die; a redistribution structure along a first side of the dielectric substrate, wherein a first conductive feature of the redistribution structure is electrically coupled to the IC die; a second conductive feature along a second side of the dielectric substrate opposite to the first side; a via extending through the dielectric substrate, wherein the via is electrically coupled to the first and second conductive features; and an antenna located on the second side of the dielectric substrate, wherein the second conductive feature is electrically or electromagnetically coupled to the antenna.

[0077] Example 13: A semiconductor device according to Example 12, wherein the antenna and the second conductive feature are at the same distance from the IC die.

[0078] Example 14: The semiconductor device according to Example 12 further includes a dielectric material between the antenna and the second conductive feature, wherein the antenna extends further from the IC die than the second conductive feature.

[0079] Example 15: The semiconductor device according to Example 14 further includes a ground metal layer in a dielectric material, wherein the ground metal layer has an opening and is located between the antenna and the second conductive feature.

[0080] Example 16: A semiconductor device according to Example 12, wherein the IC die has input / output (I / O) pads on the front side of the IC die and a ground plane on the rear side of the IC die.

[0081] Example 17: A semiconductor device according to Example 16, wherein the front side of the IC die faces the antenna.

[0082] Example 18: In one embodiment, a method includes placing a radio frequency integrated circuit (RFIC) in an opening of a dielectric core; filling the opening of the dielectric core with a dielectric material; forming a via extending through the dielectric core; forming a redistribution structure on a first side of the dielectric core, wherein a first conductive feature of the redistribution structure is formed to be electrically coupled to the RFIC; forming a second conductive feature on a second side of the dielectric core opposite to the first side, wherein the second conductive feature is electrically coupled to the first conductive feature through the via; and forming an antenna on the second side of the dielectric core, wherein the antenna is formed to be electrically or electromagnetically coupled to the second conductive feature.

[0083] Example 19: The method of Example 18 further includes forming a dielectric material between the second conductive feature and the antenna.

[0084] Example 20: The method according to Example 19 further includes forming a ground metal layer with an opening in a dielectric material, wherein the ground metal layer is formed between the second conductive feature and the antenna.

[0085] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the description, illustrative embodiments, and other embodiments of the invention will be apparent to those skilled in the art. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A semiconductor device, comprising: Dielectric core; A radio frequency integrated circuit (RFIC) is disposed in an opening of the dielectric core and surrounded by a dielectric material, wherein the dielectric material fills the space between the RFIC and the dielectric core. A redistribution structure is located on a first side of the dielectric material, wherein a first conductive feature of the redistribution structure is electrically coupled to the RFIC; The antenna is located on the second side of the dielectric material opposite to the first side; as well as A via, laterally spaced from the RFIC and extending through the dielectric core, wherein a first end of the via is electrically coupled to a first conductive feature of the redistribution structure, and a second end of the via is electrically coupled to the antenna or to a second conductive feature extending along a second side of the dielectric material, wherein the second conductive feature is configured to be electromagnetically coupled to the antenna.

2. The semiconductor device of claim 1, wherein the redistribution structure comprises a dielectric layer and the first conductive feature in the dielectric layer.

3. The semiconductor device of claim 1, further comprising an external connector electrically coupled to the first conductive feature of the redistribution structure, wherein the redistribution structure is between the external connector and the RFIC.

4. The semiconductor device of claim 1, further comprising a solder resist layer on the second side of the dielectric material, wherein the solder resist layer covers the antenna.

5. The semiconductor device of claim 1, wherein the dielectric material and the dielectric core have a coplanar upper surface and a coplanar lower surface.

6. The semiconductor device of claim 1, wherein the dielectric material has a first thickness greater than a second thickness of the dielectric core, wherein the first thickness and the second thickness are measured along a direction from the first side of the dielectric material to the second side of the dielectric material.

7. The semiconductor device of claim 1, wherein the antenna extends along and contacts the second side of the dielectric material, wherein the second end of the via is electrically coupled to the antenna.

8. The semiconductor device of claim 1, further comprising a dielectric material between the dielectric material and the antenna, wherein the antenna extends along a first side of the dielectric material opposite to the RFIC and contacts the first side of the dielectric material opposite to the RFIC, wherein the second end of the via is electrically coupled to a second conductive feature extending parallel to the second side of the dielectric material.

9. The semiconductor device of claim 8, further comprising a conductive feed line in the dielectric material, the conductive feed line electrically coupling the second conductive feature to the antenna.

10. The semiconductor device of claim 8, further comprising a metal layer in the dielectric material, the metal layer being disposed between the antenna and the second conductive feature, wherein the metal layer extends parallel to the second side of the dielectric material, the metal layer is electrically grounded, and the metal layer has an opening, wherein the second conductive feature is configured to be electromagnetically coupled to the antenna through the opening of the metal layer.

11. The semiconductor device of claim 10, further comprising a metal structure in the dielectric material and on the opposite side of the opening in the metal layer, wherein the metal structure is electrically grounded and extends from the first side of the dielectric material to a second side of the dielectric material facing the RFIC.

12. A semiconductor device, comprising: Dielectric substrate; An integrated circuit (IC) die is disposed inside an opening in the dielectric substrate, wherein the IC die is configured to transmit or receive radio frequency (RF) signals; A first dielectric material is located in the opening of the dielectric substrate and surrounds the IC die; A redistribution structure that directly contacts and extends along the first side of the first dielectric material, wherein a first conductive feature of the redistribution structure is electrically coupled to the IC die. The second conductive feature directly contacts and extends along the second side of the first dielectric material opposite to the first side and along the second side of the first dielectric material. A dielectric layer having a first surface that directly contacts a second side of the first dielectric material and extends along the second side, and having a second surface away from the first dielectric material, wherein the dielectric layer includes a second dielectric material that extends continuously from the first surface of the dielectric layer to the second surface of the dielectric layer; A via extending through the dielectric substrate, wherein the via electrically couples the first conductive feature and the second conductive feature; The antenna directly contacts and extends along the second surface of the dielectric layer; as well as The ground metal layer in the dielectric layer, wherein the ground metal layer has an electromagnetic coupling opening and is located between the antenna and the second conductive feature. The second conductive feature is electrically coupled or electromagnetically coupled to the antenna via the electromagnetic coupling opening.

13. The semiconductor device of claim 12, wherein the IC die has input / output (I / O) pads on the front side of the IC die and a ground plane on the rear side of the IC die.

14. The semiconductor device of claim 13, wherein the front side of the IC die faces the antenna.

15. A method of forming a semiconductor device, comprising: The radio frequency integrated circuit (RFIC) is placed in the opening of the dielectric core; The opening in the dielectric core is filled with a dielectric material; Forming a via extending through the dielectric core; A redistribution structure is formed on a first side of the dielectric material, wherein a first conductive feature of the redistribution structure is formed to be electrically coupled to the RFIC; A second conductive feature is formed on a second side of the dielectric material opposite to the first side, wherein the second conductive feature is electrically coupled to the first conductive feature through the via; as well as An antenna is formed on the second side of the dielectric material, wherein the antenna is formed to be electrically coupled or electromagnetically coupled to the second conductive feature.

16. The method of claim 15, further comprising forming a dielectric material between the second conductive feature and the antenna.

17. The method of claim 16, further comprising forming a ground metal layer having an opening in the dielectric material, wherein the ground metal layer is formed between the second conductive feature and the antenna.

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