On-chip antennas and on-chip antenna devices

Abstract

This application relates to an on-chip antenna and an on-chip antenna device. The on-chip antenna includes: a first antenna section having a parasitic patch disposed therein; a second antenna section having a radiating patch disposed therein and a feed line connected to the radiating patch, the feed line being used to feed a high-frequency signal to the radiating patch; and a carrier structure disposed between the first antenna section and the second antenna section, such that an air layer is formed between the parasitic patch and the radiating patch, allowing the high-frequency signal to be electromagnetically coupled within the air layer before being transmitted to the parasitic patch. The radiating patch can radiate the received high-frequency signal to the parasitic patch through the air layer to achieve signal transmission. This method of signal transmission via air can reduce signal transmission loss and improve radiation efficiency.

Description

Technical Field

[0001] This application relates to the field of antenna technology, and in particular to an on-chip antenna and an on-chip antenna device. Background Technology

[0002] With the continuous development of the mobile internet and information technology industry, the requirements for data transmission rates are becoming increasingly stringent. Increasing the communication frequency can effectively increase communication bandwidth, thereby improving the data transmission rate. To improve the communication frequency, antenna-in-package (AiP) and antenna-on-chip (AoC) technologies have been proposed.

[0003] In traditional technologies, packaged antennas utilize flip-chip bonding, wire bonding, or embedded packaging techniques to integrate the chip onto a PCB (Printed Circuit Board), and then connect it to the antenna via a re-distribution layer (RDL) on the package. On-chip antennas, based on semiconductor processes and materials, integrate the antenna and radio frequency circuitry onto the same chip.

[0004] However, in traditional packaged antennas, due to limitations in PCB manufacturing processes, the electrical dimensions of the interconnect structures are generally relatively large, making them prone to parasitic effects and resulting in excessive signal transmission loss, leading to low radiation efficiency. Similarly, in traditional on-chip antennas, signal transmission is affected by surface waves and ohmic losses within the silicon substrate, causing excessive signal transmission loss and resulting in low radiation efficiency. Therefore, both packaged and on-chip antennas in traditional technologies suffer from high signal transmission loss and low radiation efficiency. Summary of the Invention

[0005] Therefore, it is necessary to provide an on-chip antenna and on-chip antenna device that can reduce signal transmission loss and improve radiation efficiency in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides an on-chip antenna. The on-chip antenna includes: a first antenna section in which a parasitic patch is disposed; a second antenna section in which a radiating patch is disposed and a feed line connected to the radiating patch, the feed line being used to feed a high-frequency signal to the radiating patch; and a carrier structure disposed between the first antenna section and the second antenna section, such that an air layer is formed between the parasitic patch and the radiating patch, so that the high-frequency signal is transmitted to the parasitic patch after electromagnetic coupling in the air layer.

[0007] In one embodiment, the first antenna section further includes a dielectric substrate, and a plurality of parasitic patches are disposed in the first antenna section. The plurality of parasitic patches are stacked sequentially and disposed at different positions on the dielectric substrate.

[0008] In one embodiment, a target parasitic patch is present among a plurality of parasitic patches, the target parasitic patch comprising an array of electromagnetic metasurfaces.

[0009] In one embodiment, the radiating patch includes multiple signal ports, each of which is connected to a different feeder.

[0010] In one embodiment, the appearance parameters of both the parasitic patch and the radiating patch are determined based on the appearance parameters of the supporting structure.

[0011] In one embodiment, the second antenna section further includes a second welding structure for transmitting low-frequency signals and / or high-frequency signals; the first antenna section further includes a first welding structure and a first redistribution layer, the first welding structure being electrically connected to the second welding structure via a carrier structure, and the first redistribution layer being electrically connected to the first welding structure.

[0012] In one embodiment, the first welding structure includes a first pad connected to a first redistribution layer and electrically connected to a second welding structure via a carrier structure.

[0013] In one embodiment, the first welding structure includes a second pad and a third pad, wherein the third pad is electrically connected to a first redistribution layer; the second pad is electrically connected to the second welding structure through a carrier structure; and the third pad is electrically connected to the second pad through a metallized via.

[0014] In one embodiment, the load-bearing structure includes solder balls or metal spikes.

[0015] Secondly, this application also provides an on-chip antenna device. The on-chip antenna device includes the on-chip antenna and packaging structure described in any one of the first aspects above, with the on-chip antenna packaged within the packaging structure.

[0016] In one embodiment, the packaging structure includes a housing and a substrate; the substrate includes a groove, into which a second antenna portion of the on-chip antenna is embedded and fixedly connected; both the substrate and the on-chip antenna are disposed within the housing.

[0017] In one embodiment, a signal transmission structure is provided within the substrate; the signal transmission structure is connected to a first rewiring layer in the first antenna portion of the on-chip antenna.

[0018] In one embodiment, the signal transmission structure includes a fourth pad and a fifth pad connected via metallized vias; the fourth pad is connected to a first redistribution layer.

[0019] In one embodiment, the fifth pad is connected to an external system carrier and / or an external second redistribution layer.

[0020] The aforementioned on-chip antenna and on-chip antenna device include a first antenna section, a second antenna section, and a supporting structure. The first antenna section contains a parasitic patch, and the second antenna section contains a radiating patch and a feed line connected to the radiating patch. The feed line feeds a high-frequency signal to the radiating patch. The supporting structure is positioned between the first and second antenna sections, creating an air layer between the parasitic patch and the radiating patch. This allows the high-frequency signal to be electromagnetically coupled within the air layer before being transmitted to the parasitic patch. In this way, the radiating patch radiates the received high-frequency signal into the air layer, where the high-frequency signal undergoes electromagnetic coupling. Finally, the parasitic patch receives the electromagnetically coupled high-frequency signal, thus achieving signal transmission. This method of signal transmission through air reduces signal transmission loss and improves radiation efficiency. Attached Figure Description

[0021] Figure 1 This is a structural diagram of an on-chip antenna in one embodiment;

[0022] Figure 2 This is a structural diagram of a first antenna section in one embodiment;

[0023] Figure 3 This is a structural diagram of a target parasitic patch in one embodiment;

[0024] Figure 4 This is a structural diagram of a radiating patch and feeder in one embodiment;

[0025] Figure 5 This is a structural diagram of another type of radiating patch and feeder in one embodiment;

[0026] Figure 6 This is a structural diagram of a second-side antenna section in one embodiment;

[0027] Figure 7 This is a structural diagram of a first antenna section and a second antenna section in one embodiment;

[0028] Figure 8 This is a structural diagram of a first welding structure in one embodiment;

[0029] Figure 9 One embodiment is an on-chip antenna device;

[0030] Figure 10 This is another on-chip antenna device in one embodiment. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0032] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0033] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, for example, two, three, etc., unless otherwise explicitly specified.

[0034] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0035] With the continuous development of the mobile internet and information technology industry, applications such as artificial intelligence, virtual reality, uncompressed high-definition video streaming, and the Internet of Things are gradually becoming more widespread. Future communications need to meet data transmission rates at the gigabits per second (Tbps) level. Increasing the communication frequency can effectively increase communication bandwidth, thereby improving the data transmission rate. To increase the communication frequency, since the wavelengths of electromagnetic waves in the millimeter-wave and terahertz bands are comparable to chip sizes, packaged antennas integrating the chip and antenna, and on-chip antennas, have been proposed.

[0036] Encapsulated antennas integrate chips within a package structure using encapsulation technology. The antenna is designed inside or on top of the package structure, and the chip is connected to the antenna via a redistribution layer on the package structure. Encapsulation technologies include flip-chip bonding, wire bonding, and embedded packaging. Flip-chip bonding and wire bonding technologies can effectively integrate chips onto a PCB board and interconnect them with the antenna. However, when the frequency of the chip's output signal exceeds 100GHz, the electrical dimensions of the chip-antenna interconnect structure are generally relatively large due to limitations in PCB manufacturing processes. This leads to more pronounced parasitic effects, requiring additional circuit compensation structures. Both the large electrical dimensions of the interconnect structure and the designed compensation structures cause signal loss and affect bandwidth during transmission, resulting in lower radiation efficiency for the encapsulated antenna. While embedded packaging technologies can precisely interconnect the chip's signal lines with the antenna, limitations in material loss and manufacturing complexity still restrict the radiation efficiency of encapsulated antennas and increase manufacturing costs.

[0037] On-chip antennas integrate antennas and radio frequency circuits onto a single chip based on semiconductor processes and materials. Compared to packaged antennas, on-chip antennas offer lower interconnect losses and higher integration density. However, the radiation efficiency of on-chip antennas is still affected by surface waves and ohmic losses within the silicon substrate, resulting in a typical gain of less than 1 dBi in the D-band. Currently, there are three methods to improve this issue, each with its own drawbacks, as follows:

[0038] The first method involves mounting a high-dielectric-constant lens on the back of the chip, typically a silicon lens. Thermally conductive adhesive is used to attach the lens to the back of the chip, which is then mounted on the circuit board. The antenna on the chip uses various forms such as monopoles, patches, slots, and loops as the excitation source. Since the silicon layer on the back of the chip also has a high dielectric constant, and the antenna's energy is more easily radiated to the high-dielectric material, passing the lens through it can improve the antenna's radiation efficiency. However, this back-mounted lens method is not conducive to chip heat dissipation, and the lens size is relatively large, making array configuration difficult.

[0039] The second method involves etching the silicon layer on the back of the chip, but this additional process increases the manufacturing cost of the on-chip antenna and also affects the chip's strength.

[0040] The third method involves mounting another resonator on the front side of the chip. Commonly used resonant structures include dielectric resonators, parasitic patches, and artificial metamaterials. However, all of these require the use of insulating adhesive for bonding and require alignment and pressing by a chip mounter. In addition, the loss of the adhesive is often quite large above 100GHz. This poses a significant challenge to the assembly and radiation performance improvement of this type of on-chip antenna, limiting its widespread application.

[0041] Furthermore, chips with output power above 100GHz have relatively low output power. Increased propagation loss in space makes the demand for high-power chips for communication even more urgent. The common solution is power combining, but passive components such as power amplifier power distribution circuits and power combining circuits occupy a large chip area and introduce additional transmission losses, hindering cost control. Moreover, the large circuit structure is unsuitable for future array configurations. On-chip power combining can effectively overcome these problems, becoming the preferred solution for power combining in high-frequency millimeter-wave and terahertz radio frequency chips. Current on-chip antenna power combining utilizes multi-port excited radiators to directly combine the outputs of multiple power amplifiers at the antenna end. Due to its short transmission path (low loss) and high power output potential, it has received widespread attention since its inception. However, the multi-port antennas in on-chip antennas are still mainly slot antennas, with low inherent gain. Often, external silicon lenses and dielectric resonators are needed on the chip to improve gain. While external silicon lenses and dielectric resonators can improve antenna gain, the subsequent chip packaging still requires gold wire bonding, resulting in the antenna and packaging structure not being integrated, making it impossible to package the on-chip antenna.

[0042] Therefore, based on the above problems, it is necessary to propose effective technical means to reduce signal loss, improve radiation efficiency, reduce costs, and achieve perfect packaging while enabling internal antenna power combining.

[0043] In one embodiment, such as Figure 1 As shown, a structural diagram of an on-chip antenna is provided. The on-chip antenna includes: a first antenna section 100, a second antenna section 200, and a support structure 300. A parasitic patch 101 is disposed in the first antenna section 100; a radiating patch 201 and a feed line 202 connected to the radiating patch 201 are disposed in the second antenna section 200, and the feed line 202 is used to feed high-frequency signals to the radiating patch 201; the support structure 300 is disposed between the first antenna section 100 and the second antenna section 200, such that an air layer 301 is formed between the parasitic patch 101 and the radiating patch 201, so that the high-frequency signal is transmitted to the parasitic patch 101 after electromagnetic coupling in the air layer 301.

[0044] Both the parasitic patch 101 and the radiating patch 201 are patch antennas, which can be rectangular patches, microstrip monopoles, substrate integrated waveguide-fed slot structures, etc., possessing the characteristic of radiating signals. The specific model of the patch antenna can be set as needed. The feed line 202 is a signal transmission line, which can be a single-polarized feed line or a dual-polarized feed line. The single-polarized feed line polarizes the signal only in the vertical or horizontal direction, depending on the feed line type, while the dual-polarized feed line can polarize the signal in both the vertical and horizontal directions. The specific feed line type can be set as needed. The supporting structure 300 can be a metal component that provides support and signal transmission. There can be multiple of them, and the gaps near the supporting structure 300 can be filled with sealant to provide physical support for the first antenna section 100 and the second antenna section, making the assembly more secure. The height of the air layer is determined by the height of the supporting structure 300.

[0045] Optionally, the principle of high-frequency signal radiation achieved by the on-chip antenna is as follows: The high-frequency signal line of the chip is connected to the feed line 202 and transmits high-frequency signals to the feed line 202, wherein the chip is an RF chip. After receiving the high-frequency signal, the feed line 202 feeds the high-frequency signal to the radiating patch 201. Then, the radiating patch 201 radiates the received high-frequency signal to the air layer supported by the carrier structure 300. The high-frequency signal radiated to the air layer 301 undergoes electromagnetic coupling in the air layer 301. Finally, the electromagnetically coupled high-frequency signal reaches the parasitic patch 101, and the parasitic patch 101 radiates the received electromagnetically coupled high-frequency signal to the outside of the on-chip antenna.

[0046] In summary, the on-chip antenna includes a first antenna section 100, a second antenna section 200, and a support structure 300. The first antenna section 100 contains a parasitic patch 101, and the second antenna section 200 contains a radiating patch 201 and a feed line 202 connected to the radiating patch 201. The feed line 202 feeds high-frequency signals to the radiating patch 201. The support structure 300 is positioned between the first antenna section 100 and the second antenna section 200, forming an air layer 301 between the parasitic patch 101 and the radiating patch 201. This allows the high-frequency signal to be electromagnetically coupled within the air layer 301 before being transmitted to the parasitic patch 101. Thus, the radiating patch 201 radiates the received high-frequency signal into the air layer 301, where the high-frequency signal undergoes electromagnetic coupling. Finally, the parasitic patch 101 receives the electromagnetically coupled high-frequency signal, thereby achieving signal transmission. This method of signal transmission through air reduces signal transmission loss and improves radiation efficiency.

[0047] In one embodiment, such as Figure 2The above provides a structural diagram of a first antenna section 100, which further includes a dielectric substrate 102. The first antenna section 100 is provided with a plurality of parasitic patches 101, which are stacked sequentially and respectively disposed at different positions on the dielectric substrate 102.

[0048] The dielectric substrate 102 can be a gas-based dielectric substrate or a solid-based dielectric substrate, without limitation. By selecting appropriate materials and thicknesses of the dielectric substrate 102, as well as the shape and size of the parasitic patches, the radiation efficiency among multiple parasitic patches 101 can be improved, thereby improving the radiation efficiency of the on-chip antenna.

[0049] Optionally, multiple parasitic patches 101 are disposed at different thickness positions on the dielectric substrate 102. Specifically, there can be two or more parasitic patches 101. If there are two parasitic patches, namely a first parasitic patch and a second parasitic patch, the first parasitic patch is disposed on the end of the dielectric substrate 102 near the radiating patch 201, and the second parasitic patch is disposed on the end of the dielectric substrate 102 away from the radiating patch 201. If there are two or more parasitic patches 101, including a first parasitic patch, multiple intermediate layer patches, and a second parasitic patch, the first parasitic patch is disposed on the end of the dielectric substrate 102 near the radiating patch 201, the second parasitic patch is disposed on the end of the dielectric substrate 102 away from the radiating patch 201, and multiple intermediate layers are sequentially disposed between the first parasitic patch and the second parasitic patch.

[0050] Optionally, the principle of high-frequency signal transmission using multiple parasitic patches is as follows: The parasitic patch 101 closest to the radiating patch 201 first receives the high-frequency signal through the air, and then radiates the received high-frequency signal. The next parasitic patch 101 receives the high-frequency signal radiated by the previous parasitic patch and radiates it as well. This process involves a complex electromagnetic coupling process. Moreover, multiple parasitic patches can improve radiation performance.

[0051] In one embodiment, such as Figure 3 As shown, a structural diagram of a target parasitic patch is provided, in which a target parasitic patch is present among a plurality of parasitic patches 101, and the target parasitic patch includes an array of electromagnetic metasurfaces.

[0052] The target parasitic patch can be one or multiple. The electromagnetic metasurface can be composed of a periodic arrangement of subwavelength unit structures, which can achieve flexible and effective control over the characteristics of electromagnetic wave polarization, amplitude, phase, polarization mode, and propagation mode. That is, the electromagnetic metasurface has multimode characteristics, which can enable the on-chip antenna to have greater bandwidth and gain during signal transmission.

[0053] In one embodiment, such as Figure 4As shown, a structural diagram of a radiating patch and a feed line is provided. The radiating patch 201 includes multiple signal ports, and each signal port is connected to a different feed line 202.

[0054] In one embodiment, such as Figure 5 As shown, another structural diagram of a radiating patch and feeder is provided. The radiating patch 201 includes a signal port, which is connected to the feeder 202.

[0055] The signal port can be a chip RF output port or a probe on-chip output port, etc.

[0056] Optionally, when the radiating patch 201 has multiple signal ports, multiple feed lines 202 are provided. Each feed line 202 is used to feed high-frequency signals to the radiating patch 201, so that the power combining inside the antenna is completed in the radiating patch 201. This can save the operation of power combining by the power amplifier outside the on-chip antenna and improve the power combining efficiency. The characteristic impedance of the feed line 202 can be set as needed.

[0057] In one embodiment, the appearance parameters of the parasitic patch 101 and the radiating patch 201 are determined based on the appearance parameters of the support structure 300.

[0058] The appearance parameters include shape and size, such as a rectangle in shape and length × width in size.

[0059] Optionally, the appearance parameters of the support structure 300 determine the height of the air layer 301. To ensure that the high-frequency signals radiated from the radiating patch into the air layer 301 can be received by the parasitic patch 101 after air coupling, the appearance parameters of both the parasitic patch 101 and the radiating patch 201 need to be determined based on the appearance parameters of the support structure 300. Specifically, the dimensions of both the parasitic patch 101 and the radiating patch 201 are determined based on the height of the support structure.

[0060] In one embodiment, such as Figure 6 As shown, a structural diagram of a second antenna section is provided. The second antenna section 200 also includes a metal ground 203, a second dielectric substrate 204, and a third dielectric substrate 205. The second dielectric substrate 204 is disposed between the radiating patch 201 and the metal ground 203. The third dielectric substrate 205 is disposed on the side of the metal ground 203 away from the second dielectric substrate 204.

[0061] The second dielectric substrate 204 can be a silicon dioxide dielectric, the third dielectric substrate 205 can be a silicon dielectric, and the radiating patch 201 can be disposed in the second dielectric substrate 204.

[0062] In one embodiment, such as Figure 7As shown, a structural diagram of a first antenna section and a second antenna section is provided. The second antenna section 200 further includes a second welding structure 206, which is used to transmit low-frequency signals and / or high-frequency signals. The first antenna section 100 further includes a first welding structure 103 and a first redistribution layer 104. The first welding structure 103 is electrically connected to the second welding structure 206 through a carrier structure 300, and the first redistribution layer 104 is electrically connected to the first welding structure 103.

[0063] Both the second welding structure 206 and the first welding structure 103 can be solder pads, which are made of metal. The second welding structure 206 and the first welding structure 103 can serve to fix the supporting structure 300, and there can be multiple second welding structures 206 and first welding structures 103. Signal lines are typically low-frequency signal lines of the chip, but can also be high-frequency signal lines. The first redistribution layer 104 is a metal layer composed of metal traces, and there can be multiple first redistribution layers 104.

[0064] Optionally, the on-chip antenna achieves low-frequency signal fan-out as follows: The chip's low-frequency signal line is connected to the second bonding structure 206 and transmits the low-frequency signal to the second bonding structure 206. After receiving the low-frequency signal, the second bonding structure 206 transmits the low-frequency signal to the carrier structure 300. Then, the carrier structure 300 transmits the received low-frequency signal to the first bonding structure 103. Finally, the first bonding structure 103 transmits the received low-frequency signal to the first redistribution layer 104, which then transmits the low-frequency signal to the outside of the on-chip antenna, thus achieving the purpose of low-frequency signal fan-out.

[0065] In one embodiment, such as Figure 8 As shown, a structural diagram of a first welding structure is provided. The first welding structure 103 includes a first pad 1031, which is connected to a first redistribution layer 104 and electrically connected to a second welding structure 206 through a support structure 300.

[0066] In one embodiment, the first soldering structure 103 includes a second solder pad 1032 and a third solder pad 1033, wherein the third solder pad 1033 is electrically connected to the first redistribution layer 104; the second solder pad 1032 is electrically connected to the second soldering structure 206 through the carrier structure 300; and the third solder pad 1033 is electrically connected to the second solder pad 1032 through a metallized via 105.

[0067] In one embodiment, the load-bearing structure 300 includes solder balls or metal studs.

[0068] Among them, the metallized via 105 is a hole with a metal wall, and its shape can be a blind hole, which is set in the dielectric substrate 102. The load-bearing structure 300, whether it is a solder ball or a metal protrusion, is made of metal.

[0069] Optionally, the two structures described above for the first welding structure 103 can be configured simultaneously, or one of them can be selected. When the first welding structure 103 is the first pad 1031, the principle of low-frequency signal fan-out of the on-chip antenna is as described above, and will not be repeated here. When the first welding structure 103 is the second pad 1032 and the third pad 1033, the principle of low-frequency signal fan-out of the on-chip antenna is as follows: The low-frequency signal line of the chip is connected to the second welding structure 206 and transmits the low-frequency signal to the second welding structure 206. After receiving the low-frequency signal, the second welding structure 206 transmits the low-frequency signal to the carrier structure 300. Then, the carrier structure 300 transmits the received low-frequency signal to the second pad 1032. The second pad 1032 transmits the received low-frequency signal to the first redistribution layer 104 through the metallized via 105. The first redistribution layer 104 transmits the low-frequency signal to the outside of the on-chip antenna, thus achieving the purpose of low-frequency signal fan-out.

[0070] In one embodiment, such as Figure 9 As shown, an on-chip antenna device is provided, which includes the on-chip antenna and packaging structure involved in any of the above embodiments, wherein the on-chip antenna is packaged in the packaging structure.

[0071] In one embodiment, the packaging structure includes a housing 801 and a substrate 802; the substrate 802 includes a groove, and the second antenna portion 200 of the on-chip antenna is embedded in the groove and fixedly connected to the substrate 802; the substrate 802 and the on-chip antenna are both disposed within the housing 801.

[0072] The outer casing can be made of insulating material. The substrate can be a PCB (Printed Circuit Board) or an LTCC (Low Temperature Co-fired Ceramic) board.

[0073] Optionally, the second antenna portion 200 of the on-chip antenna is embedded in the substrate 802 and fixed by a filler adhesive 803. The first antenna portion 100 of the on-chip antenna can also be embedded in another substrate, which is disposed within the housing 801. In addition, the substrate 802 and the other substrate are filled with adhesive 804, the thickness of which is the height of the support structure 300 in the on-chip antenna, to ensure the assembly reliability of the substrate 802 and the other substrate.

[0074] In one embodiment, such as Figure 10As shown, another on-chip antenna device is provided, wherein a signal transmission structure is provided in the substrate 802; the signal transmission structure is connected to the first redistribution layer 104 in the first antenna section 100 of the on-chip antenna.

[0075] In one embodiment, the signal transmission structure includes a fourth pad 902 and a fifth pad 903 connected via a metallized via 901; the fourth pad 902 is connected to a first redistribution layer 104.

[0076] In one embodiment, the fifth pad 903 is connected to an external system carrier 904 and / or an external second redistribution layer 905.

[0077] Among them, the metallized via 901 is a hole with a metal wall, and its shape can be a blind via, which is set in the substrate 802. The fourth pad 902 and the fifth pad 903 are both made of metal. The system carrier can be any carrier for receiving low-frequency signals from the chip, such as a PCB board or an LTCC board. The second redistribution layer is a metal layer composed of metal traces.

[0078] Optionally, the fourth pad 902 is connected to the first redistribution layer 104 via the carrier structure 300 and the first soldering structure 103, and the fifth pad 903 is connected to the external system carrier board 904 and / or the external second redistribution layer 905 via the second carrier structure 906 and the sixth pad 907, thereby achieving the purpose of fanning out low-frequency signals. Additionally, adhesive 805 is used to fill the gaps between the system carrier board 904 and the housing 801, and between the second redistribution layer 905 and the housing 801, to ensure the stability of the connection between the package structure and the system carrier board 904 and / or the second redistribution layer.

[0079] Optionally, when the first soldering structure 103 includes a first pad 1031, there can be multiple first pads 1031. Taking two as an example, one is connected to the side of the first redistribution layer 104 near the second soldering structure 206, and the other is connected to the side of the first redistribution layer 104 away from the second soldering structure 206. The principle of low-frequency signal fan-out of the on-chip antenna is as follows: The low-frequency signal line of the chip is connected to the second soldering structure 206 and transmits the low-frequency signal to the second soldering structure 206. After receiving the low-frequency signal, the second soldering structure 206 transmits the low-frequency signal to the carrier structure 300. Then, the carrier structure 300 transmits the received low-frequency signal to the first pad 1031 near the second soldering structure 206. The first pad 1031 transmits the received low-frequency signal to the first redistribution layer 104. The first redistribution layer 104 transmits the received low-frequency signal to the first pad 1031 away from the second soldering structure 206. The first pad 1031 transmits the received low-frequency signal to the first pad 1031 away from the second soldering structure 206. The received low-frequency signal is transmitted to the carrier structure 300, which transmits it to the fourth pad 902. The fourth pad 902 transmits the received low-frequency signal to the fifth pad 903 through the metallized via 901. The fifth pad 903 transmits the received low-frequency signal to the second carrier structure 906, which transmits it to the sixth pad 907. The sixth pad 907 transmits the received low-frequency signal to the system carrier board 904 and / or the second redistribution layer 905.

[0080] Optionally, when the first soldering structure 103 consists of a second pad 1032 and a third pad 1033, there can be multiple second pads 1032, third pads 1033, and metallized vias 105. Taking two as an example, one third pad 1033 is connected to the side of the first redistribution layer 104 closest to the second soldering structure 206, and the other third pad 1033 is connected to the side of the first redistribution layer 104 away from the second soldering structure 206. Correspondingly, the two second pads 1032 and the two metallized vias are respectively connected to the two third pads 1033. The principle of low-frequency signal fan-out on-chip antenna is as follows: The low-frequency signal line of the chip is connected to the second bonding structure 206 and transmits the low-frequency signal to the second bonding structure 206. After receiving the low-frequency signal, the second bonding structure 206 transmits the low-frequency signal to the carrier structure 300. Then, the carrier structure 300 transmits the received low-frequency signal to the second pad 1032 near the second bonding structure 206. The second pad 1032 near the second bonding structure 206 transmits the received low-frequency signal through the metallized via 105 near the second bonding structure 206 to the third pad 1033 near the second bonding structure 206. The third pad 1033 near the second bonding structure 206 transmits the received low-frequency signal to the first redistribution layer 104. The first redistribution layer 104 transmits the received low-frequency signal to the layer farther away from the second bonding structure 206. The third pad 1033, located away from the second welding structure 206, transmits the received low-frequency signal through a metallized via 105 away from the second welding structure 206 to the second pad 1032, which in turn transmits the received low-frequency signal to the carrier structure 300. The carrier structure 300 then transmits the received low-frequency signal to the fourth pad 902. The fourth pad 902 transmits the received low-frequency signal through a metallized via 901 to the fifth pad 903. The fifth pad 903 transmits the received low-frequency signal to the second carrier structure 906. The second carrier structure 906 then transmits the received low-frequency signal to the sixth pad 907. The sixth pad 907 transmits the received low-frequency signal to the system carrier board 904 and / or the second redistribution layer 905.

[0081] Additionally, it should be noted that a chip is also packaged within the package structure. The chip's high-frequency signal lines are connected to feed line 202, and its low-frequency signal lines are connected to the second bonding structure 206. The bottom of the chip can be located anywhere within the package structure.

[0082] In summary, by assembling the internal components of the on-chip antenna and packaging the on-chip antenna, the chip packaging is completed simultaneously, simplifying the on-chip antenna assembly process, improving assembly efficiency, and reducing costs.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. An antenna on a chip, characterized by, The on-chip antenna comprises: a first antenna part, a parasitic patch being arranged in the first antenna part; a second antenna part, a radiation patch and a feed line connected with the radiation patch being arranged in the second antenna part, the feed line being used for feeding a high-frequency signal to the radiation patch; a bearing structure arranged between the first antenna part and the second antenna part, so that an air layer is formed between the parasitic patch and the radiation patch, and the high-frequency signal is transmitted to the parasitic patch after electromagnetic coupling in the air layer; the second antenna part further comprises a second soldering structure used for transmitting a low-frequency signal; the first antenna part further comprises a first soldering structure and a first rewiring layer, the first soldering structure being electrically connected with the second soldering structure through the bearing structure, and the first rewiring layer being electrically connected with the first soldering structure, so that the low-frequency signal is fanned out through the first rewiring layer.

2. The antenna on chip according to claim 1, characterized in that, The first antenna part further comprises a dielectric plate, and a plurality of parasitic patches are arranged in the first antenna part, the plurality of parasitic patches being stacked in sequence and arranged at different positions of the dielectric plate.

3. The antenna on chip of claim 2, wherein, There is a target parasitic patch in the plurality of parasitic patches, and the target parasitic patch comprises an array-arranged electromagnetic super surface.

4. The antenna on chip according to any one of claims 1 to 3, characterized in that, The radiation patch comprises a plurality of signal ports, and each signal port is connected with a different feed line.

5. The antenna on chip according to any one of claims 1 to 3, characterized in that, The appearance parameters of the parasitic patch and the radiation patch are determined according to the appearance parameters of the bearing structure.

6. The antenna on chip of claim 1, wherein, The first soldering structure comprises a first pad, the first pad being connected with the first rewiring layer and being electrically connected with the second soldering structure through the bearing structure.

7. The antenna on chip of claim 1, wherein, The first soldering structure comprises a second pad and a third pad, wherein the third pad is electrically connected with the first rewiring layer; the second pad is electrically connected with the second soldering structure through the bearing structure; the third pad is electrically connected with the second pad through a metallized via.

8. The antenna on chip according to any one of claims 1 to 3, characterized in that, The bearing structure comprises a solder ball or a metal stud.

9. An on-chip antenna device, characterized by The on-chip antenna device comprises the on-chip antenna of any one of claims 1-8 and a packaging structure, and the on-chip antenna is packaged in the packaging structure.

10. The on-chip antenna device according to claim 9, characterized in that, The packaging structure comprises a shell and a substrate; the substrate comprises a groove, and the second antenna part of the on-chip antenna is embedded into the groove and fixedly connected with the substrate; the substrate and the on-chip antenna are arranged in the shell.

11. The on-chip antenna device according to claim 10, characterized in that, The substrate is provided with a signal transmission structure; the signal transmission structure is connected with the first rewiring layer in the first antenna part of the on-chip antenna.

12. The on-chip antenna device according to claim 11, characterized in that, The signal transmission structure comprises a fourth pad and a fifth pad connected through a metallized via; the fourth pad is connected with the first rewiring layer.

13. The on-chip antenna device according to claim 12, characterized in that, The fifth pad is connected with an external system carrier plate and / or a second rewiring layer outside.

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