Substrate structure and substrate processing

Abstract

Embodiments of the present application provide a substrate structure, comprising: a first circuit layer having a first conductive layer; a second circuit layer having a second conductive layer; and a first dielectric layer covered by the first conductive layer and the second conductive layer. Embodiments of the present application provide a substrate structure and a substrate process, and improve the yield of the substrate structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to substrate structure and substrate manufacturing process. Background Technology

[0002] With the development and increasing demand for smart mobile devices, functions are becoming more and more diverse. Consequently, integrated circuit (IC) integration is becoming more and more important. In order to reduce the size of the package, embedding active and passive components into the substrate is a major practice. Embedding the substrate can effectively reduce the electrical transmission path and further reduce power consumption, so as to facilitate the integration of ICs with various functions into a small package.

[0003] Currently, after embedding active and passive components into the substrate, laser-drilled vias are required to connect them to the pads on the chip. In addition to the issues of laser via positioning accuracy and energy, the warpage of the circuit layers is significantly greater than that of the chip due to the mismatch in the coefficient of thermal expansion (CTE), which further increases the difficulty of bonding. On the other hand, relying solely on metal-to-metal bonding forces can lead to peeling problems, reducing the overall product yield. Summary of the Invention

[0004] In view of the problems existing in the related technologies, the purpose of this invention is to provide a substrate structure and substrate manufacturing process to improve the yield of the substrate structure.

[0005] To achieve the above objectives, embodiments of the present invention provide a substrate structure, including: a first circuit layer having a first conductive layer; a second circuit layer having a second conductive layer; and a first dielectric layer covered by the first conductive layer and the second conductive layer.

[0006] In some embodiments, the first dielectric layer comprises a first oxide.

[0007] In some embodiments, the first conductive layer and the second conductive layer are through holes with grooves.

[0008] In some embodiments, the system further includes: a first passivation layer surrounding the first conductive layer; and a second passivation layer surrounding the second conductive layer, wherein the first passivation layer and the second passivation layer are bonded together.

[0009] In some embodiments, the first passivation layer and the second passivation layer comprise a second oxide and a third oxide, respectively.

[0010] In some embodiments, the interface between the first conductive layer and the second conductive layer and the interface between the first passivation layer and the second passivation layer are coplanar.

[0011] In some embodiments, the first dielectric layer is located in a first groove structure of the first conductive layer, and the first dielectric layer and the first passivation layer comprise the same material.

[0012] In some embodiments, the system further includes a second dielectric layer, which is covered by the first conductive layer and the second conductive layer.

[0013] In some embodiments, the second dielectric layer comprises a fourth oxide.

[0014] In some embodiments, the first dielectric layer is bonded to the second dielectric layer.

[0015] In some embodiments, the first dielectric layer is located in a first groove structure of the first conductive layer, the second dielectric layer is located in a second groove structure of the second conductive layer, and the interface between the first conductive layer and the second conductive layer and the interface between the first dielectric layer and the second dielectric layer are coplanar.

[0016] In some embodiments, the device further includes a die located at the same level as the first conductive layer, the die being electrically connected to the second conductive layer through the first conductive layer.

[0017] Embodiments of this application also provide a substrate manufacturing process, characterized in that it includes: disposing a first conductive layer and a first dielectric layer on a first circuit layer; disposing a second conductive layer and a second dielectric layer on a second circuit layer; contacting the first conductive layer and the second conductive layer, while simultaneously contacting the first dielectric layer and the second dielectric layer; and reflowing the first conductive layer, the second conductive layer, the first dielectric layer, and the second dielectric layer to form a hybrid bonding.

[0018] In some embodiments, before contacting the first conductive layer with the second conductive layer and before contacting the first dielectric layer with the second dielectric layer, a planarization process is performed on the first conductive layer and the first dielectric layer, and a planarization process is performed on the second conductive layer and the second dielectric layer.

[0019] In some embodiments, the planarization process includes grinding.

[0020] In some embodiments, before the first conductive layer and the first dielectric layer are disposed on the first circuit layer, the die is disposed on the first circuit layer.

[0021] In some embodiments, when setting the first dielectric layer and the second dielectric layer, the method further includes filling the first dielectric layer and the second dielectric layer into the first groove structure and the second groove structure of the first conductive layer and the second conductive layer, respectively.

[0022] In some embodiments, when the first dielectric layer and the second dielectric layer are provided, the first gap and the second gap are respectively formed in the first conductive layer and the second conductive layer located within the first groove structure and the second groove structure.

[0023] In some embodiments, after hybrid bonding, the first gap and the second gap combine to form an air gap surrounded by the first dielectric layer and the second dielectric layer.

[0024] In some embodiments, both the first conductive layer and the second conductive layer have horizontally extending portions, and during hybrid bonding, the horizontally extending portions of the first conductive layer and the second conductive layer are aligned. Attached Figure Description

[0025] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0026] Figures 1 to 12 The process of forming a circuit layer according to an embodiment of this application is illustrated.

[0027] Figures 13 to 27 The formation process of another circuit layer according to an embodiment of this application is shown.

[0028] Figures 28 to 33 The formation process of a substrate structure according to an embodiment of this application is illustrated.

[0029] Figures 34 to 37 The subsequent processes of the substrate structure according to an embodiment of this application are shown.

[0030] Figures 38 to 42 The substrate structures of different embodiments of this application are shown. Detailed Implementation

[0031] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0032] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0033] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0034] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0035] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0036] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0037] Currently, front-end photolithography (Fab) or microbump processes offer advantages in structural thinning and circuit miniaturization. Thinning facilitates the fabrication of tiny lines (e.g., linewidth / spacing, L / S > 2μm / 2μm) and reduces product thickness, while circuit miniaturization reduces the number of circuit layers, lowers manufacturing costs, and improves yield. However, as the lines become finer, traditional soldering methods become unusable due to limitations in applicable pitch. This necessitates increasing the number of circuit layers for high-end packaged products (e.g., 2.5D / 3D), resulting in high costs. This is primarily because the package structure must use a full substrate, typically accounting for over 50% of the total cost. The high price is due to the inability to fabricate finer lines (e.g., L / S > 10μm / 10μm), necessitating multi-layer redistribution structures. In fact, more layers in the structure can provide more inputs / outputs (I / O), but the cost and yield loss are also relatively higher. Front-end photolithography processes are expensive due to circuit miniaturization and have longer development cycles. If substrate technology can be combined with fan-out structures and hybrid bonding technology, the advantages of circuit miniaturization will inevitably become apparent.

[0038] The embedded substrate of this application will be explained in detail below with reference to the accompanying drawings.

[0039] Reference Figure 1 A first seed layer 12 is formed on the first carrier 10. In an embodiment, the first seed layer 12 can be formed by a physical vapor deposition (PVD) process. A first mask layer 14 is formed on the first seed layer 12, the first mask layer 14 may include a photoresist (PR) material, and a first exposure process 11 is performed to cure the first mask layer 14. The thickness of the seed layer in the embodiments of this application is in the range of 0.1 μm to 0.3 μm.

[0040] Reference Figure 2 The first mask layer 14 is patterned, and a first metal layer 20 is formed in the patterned first mask layer 14. The thickness of the metal layer in the embodiments of this application is in the range of 0.5 μm to 2 μm.

[0041] Reference Figure 3 Remove the patterned first mask layer 14, and use the first metal layer 20 as a mask to etch the first seed layer 12 so that the first seed layer 12 has the same pattern as the first metal layer 20.

[0042] Reference Figure 4A third dielectric layer 40 is formed, covering the first metal layer 20 and the first seed layer 12. In an embodiment, the third dielectric layer 40 may include a polyamide (PA) material, and a second exposure process 41 is performed on the third dielectric layer 40 to cure it. Optional embodiments of the dielectric layer in the embodiments of this application include prepreg (PP), Ajinomoto build-up film (ABF), or polyimide (PI), with a thickness ranging from 5 μm to 20 μm.

[0043] Then, as Figure 5 As shown, a second seed layer 50 is formed in and on the third dielectric layer 40 to contact the first metal layer 20, and a second metal layer 52 is formed on the second seed layer 50. A fourth dielectric layer 54 is formed covering the second seed layer 50 and the second metal layer 52. In an embodiment, the fourth dielectric layer 54 may include a polyamide (PA) material, and a third exposure process 51 is performed on the fourth dielectric layer 54 to cure it.

[0044] See Figure 6 An opening is formed in the fourth dielectric layer 54 to expose the second metal layer 52, and a third seed layer 60 is formed in the opening and on the fourth dielectric layer 54.

[0045] See Figure 7 A second mask layer 70 is formed on the third seed layer 60. The second mask layer 70 may include a photoresist (PR) material, and a fourth exposure process 71 is performed to cure the second mask layer 70.

[0046] See Figure 8 The second mask layer 70 is patterned to expose the third seed layer 60. A third metal layer 80 is then formed on the exposed third seed layer 60.

[0047] See Figure 9 The patterned second mask layer 70 is removed, and the third seed layer 60 is etched using a gas etching process 91 with the third metal layer 80 as a mask so that the third seed layer 60 has the same pattern as the third metal layer 80. The third seed layer 60 and the third metal layer 80 constitute the second conductive layer 90, which is a through-hole with a second groove structure 92.

[0048] See Figure 10A second dielectric layer 100 is formed on the fourth dielectric layer 54, the third seed layer 60, and the third metal layer 80, and the second dielectric layer 100 fills the second trench structure 92. The second dielectric layer 100 comprises oxide and is formed by physical vapor deposition (PVD) process 101. In other embodiments, the second trench structure 92 is filled with a metallic material, or it may be left unfilled. In one embodiment, the unfilled portion of the second dielectric layer 100 within the second trench structure 92 surrounds the second conductive layer 90 and is also referred to as the second passivation layer. In another embodiment, the second passivation layer may also be made of a different material than the second dielectric layer 100.

[0049] See Figure 11 The upper surface of the second dielectric layer 100 is planarized using a planarization process 111. The planarization process 111 includes a polishing process.

[0050] See Figure 12 The planarization process 111 forms the upper surface of the second dielectric layer 100 flush with the upper surface of the second conductive layer 90. An activation process 121 is then performed on the upper surface of the second dielectric layer 100 using an active gas. This forms the second circuit layer 120 of this application. The second gap 122 remains within the second dielectric layer 100.

[0051] Reference Figure 13 A fourth seed layer 132 is formed on the second carrier 130. In an embodiment, the fourth seed layer 132 can be formed by a physical vapor deposition (PVD) process. A third mask layer 134 is formed on the fourth seed layer 132. The third mask layer 134 may include a photoresist (PR) material, and a fifth exposure process 131 is performed to cure the third mask layer 134.

[0052] Reference Figure 14 The third mask layer 134 is patterned, and a fourth metal layer 140 is formed in the patterned third mask layer 134.

[0053] Reference Figure 15 Remove the patterned third mask layer 134, and use the fourth metal layer 140 as a mask to etch the fourth seed layer 132 so that the fourth seed layer 132 has the same pattern as the fourth metal layer 140.

[0054] Reference Figure 16 A fifth dielectric layer 160 is formed, covering the fourth seed layer 132 and the fourth metal layer 140. In an embodiment, the fifth dielectric layer 160 may include a polyamide (PA) material, and a sixth exposure process 161 is performed on the fifth dielectric layer 160 to cure it.

[0055] Then, as Figure 17As shown, a fifth seed layer 170 is formed in and on the fifth dielectric layer 160 to contact the fourth metal layer 140, and a fifth metal layer 172 is formed on the fifth seed layer 170.

[0056] See Figure 18 A sixth dielectric layer 180 is formed, covering the fifth seed layer 170 and the fifth metal layer 172. In an embodiment, the sixth dielectric layer 180 may comprise a polyamide (PA) material.

[0057] See Figure 19 The chip 190 is attached to the sixth dielectric layer 180 via an adhesive layer 192. The chip 190 includes conductive pillars 194.

[0058] See Figure 20 A seventh dielectric layer 200 is formed, covering the sixth dielectric layer 180 and the chip 190, and the seventh dielectric layer 200 exposes the conductive pillars 194 of the chip 190. In an embodiment, the seventh dielectric layer 200 may include a polyamide (PA) material, and a seventh exposure process 201 is performed on the seventh dielectric layer 200 to cure it.

[0059] See Figure 21 An opening is formed through the sixth dielectric layer 180 and the seventh dielectric layer 200 to expose the fifth metal layer 172, and a sixth seed layer 210 is formed in the opening and on the seventh dielectric layer 200.

[0060] See Figure 22 A fourth mask layer 220 is formed on the sixth seed layer 210. The fourth mask layer 220 may include a photoresist (PR) material, and the fourth mask layer 220 is cured by an eighth exposure process 221.

[0061] Reference Figure 23 The fourth mask layer 220 is patterned and a sixth metal layer 230 is formed in the patterned fourth mask layer 220.

[0062] See Figure 24 The patterned fourth mask layer 220 is removed, and the sixth seed layer 210 is etched using a second gas etching process 241 with the sixth metal layer 230 as a mask, so that the sixth seed layer 210 has the same pattern as the sixth metal layer 230. The sixth seed layer 210 and the sixth metal layer 230 constitute the first conductive layer 240, which is a through-hole with a first groove structure 242.

[0063] See Figure 25A first dielectric layer 250 is formed on the seventh dielectric layer 200, the sixth seed layer 210, and the sixth metal layer 230, and the first dielectric layer 250 fills the first trench structure 242. The first dielectric layer 250 comprises oxide and is formed by a second physical vapor deposition (PVD) process 251. In other embodiments, the first trench structure 242 is filled with a metallic material, or it may be left unfilled. In one embodiment, the unfilled portion of the first dielectric layer 250 within the first trench structure 242 surrounds the first conductive layer 240 and is also referred to as the first passivation layer. In another embodiment, the first passivation layer may also be made of a different material than the first dielectric layer 250.

[0064] See Figure 26 The upper surface of the first dielectric layer 250 is planarized using a second planarization process 261. The second planarization process 261 includes a polishing process. A first gap 262 is retained within the first dielectric layer 250.

[0065] See Figure 27 The second planarization process 261 forms the upper surface of the first dielectric layer 250 flush with the upper surface of the first conductive layer 240. A second activation process 271 is then performed on the upper surface of the first dielectric layer 250 using an active gas. This forms the first circuit layer 270 of this application.

[0066] See Figure 28 The first circuit layer 270 and the second circuit layer 120 are assembled together, wherein the first dielectric layer 250 faces the second dielectric layer 100, and the first circuit layer 270 and the second circuit layer 120 are bonded together by a lamination process 280.

[0067] See Figure 29A The first carrier 10 is removed. The first circuit layer 270 is bonded to the second circuit layer 120 via hybrid bonding. In this embodiment, hybrid bonding is achieved through a reflow process. The first dielectric layer 250 is bonded to the second dielectric layer 100 and aligned with each other, and the first conductive layer 240 is bonded to the second conductive layer 90 and aligned with each other. The second conductive layer 90 is also bonded to and aligned with the conductive post 194. The second conductive layer 90 bonded to the first conductive layer 240 is a through-hole with a diameter ranging from 80 μm to 250 μm, and the second conductive layer 90 bonded to the conductive post 194 is also a through-hole with a diameter ranging from 20 μm to 100 μm. The first gap 122 and the second gap 262 combine to form an air gap 296.

[0068] See Figure 29BAn enlarged view is shown showing the second conductive layer 90 and the conductive post 194 bonded together, wherein an exemplary embodiment of the conductive post 194 includes copper; an exemplary embodiment of the pad 195 on the conductive post 194 includes aluminum; an exemplary embodiment of the seventh dielectric layer 200 includes prepreg (PP), Ajinomoto build-up film (ABF), or polyimide (PI); an exemplary embodiment of the first dielectric layer 250 includes oxide; a third metal layer 80 of the second conductive layer 90 is bonded to the conductive post 194 to form a second pad 291, an exemplary embodiment of which includes copper; an exemplary embodiment of the third seed layer 60 of the second conductive layer 90 includes titanium, the third seed layer 60 serving to facilitate bonding between the two layers in contact; an exemplary embodiment of the fourth dielectric layer 54 includes prepreg (PP), Ajinomoto build-up film (ABF), or polyimide (PI). The second dielectric layer 100 includes an oxide, such as silicon dioxide, and the second metal layer 52 is formed as a trace, the exemplary embodiment of which includes copper or titanium.

[0069] See Figure 29C An enlarged view of the second conductive layer 90 and the first conductive layer 240 being bonded together is shown. An exemplary embodiment of the first dielectric layer 250 includes an oxide, such as silicon dioxide; an exemplary embodiment of the sixth metal layer 230 includes copper; an exemplary embodiment of the sixth seed layer 210 includes titanium, which serves to facilitate bonding between the two layers; an exemplary embodiment of the seventh dielectric layer 200 includes a prepreg (PP), an Ajinomoto build-up film (ABF), or polyimide (PI); an exemplary embodiment of the third metal layer 80 of the second conductive layer 90 is bonded to the sixth metal layer 230 of the first conductive layer 240 to form a third pad 292, an exemplary embodiment of which includes copper; an exemplary embodiment of the second dielectric layer 100 includes an oxide, such as silicon dioxide; an exemplary embodiment of the fourth dielectric layer 54 includes a prepreg (PP), an Ajinomoto build-up film (ABF), or a PP. The second conductive layer 90 is made of film (ABF) or polyimide (PI); an exemplary embodiment of the third seed layer 60 of the second conductive layer 90 includes titanium, the third seed layer 60 serving to facilitate bonding between the two layers in contact; an exemplary embodiment of the third metal layer 80 of the second conductive layer 90 includes copper.

[0070] See Figure 30A second solder mask (S / M) 300 is formed on the second circuit layer 120, exposing the first seed layer 12 of the second circuit layer 120. The exposed first seed layer 12 is removed by a first etching process 301.

[0071] See Figure 31 The structure is flipped over, and the second carrier 130 is removed.

[0072] See Figure 32 A first solder mask (S / M) 320 is formed on the first circuit layer 270, exposing the fourth seed layer 132 of the first circuit layer 270. The exposed fourth seed layer 132 is removed by a second etching process 321 to form a layer as shown in the image. Figure 33 The substrate structure 330 of this application is shown. The dielectric layer of this application may use organic materials such as polyamide (PA), polyimide (PI), epoxy resin, polybenzoxazole (PBO), flame retardant grade 4 material (FR4), prepreg (PP), Ajinomoto build-up film (ABF), etc., or / and inorganic materials such as silicon, glass, ceramics, oxides (e.g., SiOx, TaOx), etc. The dielectric layer can also be a material with adhesive properties, such as liquid or / and film-like organic materials, such as non-conductive film (NCF), non-conductive paste (NCP), adaptively coupled plasma (ACP), anisotropic conductive film (ACF), polyimide (PI), epoxy resin, resin, prepreg resin (PP), Ajinomoto build-up film (ABF), adhesive layer, etc. In embodiments, the dielectric layer is fabricated using processes such as printing, lamination, potting, and coating. In embodiments, the metal layer herein includes, for example, Cu, Ag, Au, Ni, Pd, etc., and the seed layer includes, for example, Ti, W, Ni, etc. In embodiments, the seed layer and metal layer are formed using sputtering, electroplating, electroless plating and / or printing, lamination and / or potting processes.

[0073] See Figure 34 The second chip 340 is bonded on the second welding mask (S / M) 300 of the substrate structure 330.

[0074] See Figure 35 Furthermore, a third chip 350 is bonded on the second welding mask (S / M) 300 of the substrate structure 330.

[0075] See Figure 36 The second chip 340 and the third chip 350 are encapsulated using encapsulation compound 360.

[0076] See Figure 37 Solder balls 370 electrically connected to the fourth metal layer 140 are formed on the first solder mask (S / M) 320 of the substrate structure 330.

[0077] See Figure 38 ,and Figure 33 In contrast, the first conductive layer 240 is bonded to the second conductive layer 90 and is offset from it. The second conductive layer 90 is also bonded to the conductive post 194 and is offset from it.

[0078] See Figure 39 ,and Figure 33 In contrast, the seventh dielectric layer 200 is also filled with organic matter 390.

[0079] See Figure 40 ,and Figure 33 In contrast, the first dielectric layer 250 and the second dielectric layer 100 only partially fill the area around the first conductive layer 240 and the second conductive layer 90. The first dielectric layer 250 and the second dielectric layer 100 are not filled at the locations corresponding to the chip 190.

[0080] See Figure 41 ,and Figure 33 In contrast, it forms a pair of upper and lower first line layers 270.

[0081] See Figure 42 ,and Figure 33 In contrast, an active / passive device 420 is also formed adjacent to the chip 190.

[0082] This invention utilizes a hybrid bonding technique to effectively improve the stability of the bonding between two circuit layers, and also enhances the CTE matching degree. This invention strengthens the bonding force between the two circuit layers by bonding oxides within the conductive layer, avoiding peeling caused by CTE mismatch. Furthermore, since the oxide structure is harder than the circuit layer, it effectively resists circuit layer warpage, facilitating control in subsequent processes. Most vias on the circuit layer have groove structures; by filling these grooves with oxides, in addition to increasing the bonding area and capability of the oxides, it can also eliminate or reduce air gaps in the groove structure, avoiding the popcorn effect caused by excessively high-temperature processes.

[0083] The embodiments of this application do not require an additional adhesive layer between the two circuit layers, and the electrical connection between the two circuit layers is achieved through a conductive layer, avoiding the traditional process of laser drilling through the two circuit layers, and reducing the overall space required for the device.

[0084] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A substrate structure, characterized in that, include: The first circuit layer has a first conductive layer; The second circuit layer has a second conductive layer; The first dielectric layer is covered by the first conductive layer and the second conductive layer; as well as A second dielectric layer is covered by the first conductive layer and the second conductive layer. The first dielectric layer and the second dielectric layer are bonded together. The first dielectric layer is located in a first groove structure of the first conductive layer, and the second dielectric layer is located in a second groove structure of the second conductive layer. The interface between the first conductive layer and the second conductive layer and the interface between the first dielectric layer and the second dielectric layer are coplanar. The first conductive layer and the second conductive layer are through holes with grooves and in the shape of a U.

2. The substrate structure according to claim 1, characterized in that, Also includes: A first passivation layer surrounds the first conductive layer; A second passivation layer surrounds the second conductive layer, and the first passivation layer is bonded to the second passivation layer.

3. The substrate structure according to claim 2, characterized in that, The interface between the first conductive layer and the second conductive layer, and the interface between the first passivation layer and the second passivation layer are coplanar.

4. The substrate structure according to claim 2, characterized in that, The first dielectric layer and the first passivation layer comprise the same material.

5. The substrate structure according to claim 1, characterized in that, Also includes: The die is located at the same level as the first conductive layer, and the die is electrically connected to the second conductive layer through the first conductive layer.

6. A substrate manufacturing process, characterized in that, include: A first conductive layer and a first dielectric layer are disposed on the first circuit layer; A second conductive layer and a second dielectric layer are disposed on the second circuit layer; The first conductive layer is in contact with the second conductive layer, and the first dielectric layer is in contact with the second dielectric layer. The first conductive layer, the second conductive layer, the first dielectric layer, and the second dielectric layer are reflowed to form a hybrid bond. In this configuration, the second dielectric layer is covered by both the first and second conductive layers. The first and second dielectric layers are bonded together. The first dielectric layer is located within a first groove structure of the first conductive layer, and the second dielectric layer is located within a second groove structure of the second conductive layer. The interface between the first and second conductive layers and the interface between the first and second dielectric layers are coplanar. The first conductive layer and the second conductive layer are through holes with grooves and in the shape of a U.

7. The substrate manufacturing process according to claim 6, characterized in that, Before contacting the first conductive layer with the second conductive layer and before contacting the first dielectric layer with the second dielectric layer, a planarization process is performed on the first conductive layer and the first dielectric layer, and a planarization process is performed on the second conductive layer and the second dielectric layer.

8. The substrate manufacturing process according to claim 6, characterized in that, Before setting the first conductive layer and the first dielectric layer on the first circuit layer, the method further includes setting the die on the first circuit layer.

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