Semiconductor device and method of forming the same

Abstract

An embodiment of the present invention provides a semiconductor device. The semiconductor device includes a first portion and a vertical conductive structure. The first portion includes: a first dielectric layer; and a first guard ring located in the first dielectric layer. The first guard ring includes a first metal layer connected to a first via in the first dielectric layer. The vertical conductive structure passes through the first dielectric layer and is close to the first guard ring. An embodiment of the present invention also relates to a method for forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic devices, such as mobile phones, laptop computers, desktop computers, tablet computers, watches, game systems, and various other industrial, commercial, and consumer electronic products. Semiconductor devices generally include a semiconductor portion and a wiring portion formed inside the semiconductor portion. Summary of the invention

[0003] According to one aspect of the present invention, a semiconductor device is provided, comprising: a first part, including: a first passivation layer; a first dielectric layer, located above the first passivation layer; a first substrate, located above the first dielectric layer; a first conductive layer, located above the first substrate; and a first guard ring, located in the first dielectric layer; a second part, located below the first part, the second part comprising: a second passivation layer; a second conductive layer, located in the second passivation layer; a second dielectric layer, located below the second passivation layer; and a second substrate, located below the second dielectric layer; and a vertical conductive structure, passing through the first substrate, the first dielectric layer, and the first passivation layer, wherein the vertical conductive structure contacts the first conductive layer and the second conductive layer and is surrounded by the first guard ring.

[0004] According to another aspect of the present invention, a semiconductor device is provided, comprising: a first part, comprising: a first dielectric layer; and a first guard ring, located in the first dielectric layer, wherein the first guard ring comprises a first metal layer connected to a first via in the first dielectric layer; and a vertical conductive structure, passing through the first dielectric layer and close to the first guard ring.

[0005] According to another aspect of the present invention, a method for forming a semiconductor device is provided, comprising: forming a first guard ring in a first dielectric layer; and forming a vertical conductive structure having a tapered sidewall, the vertical conductive structure passing through the first dielectric layer and surrounded by the first guard ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1-Figure 5 illustrates cross-sectional views of semiconductor devices at various stages of fabrication according to some embodiments;

[0008] Figure 6 illustrates a top view of a semiconductor device during fabrication according to some embodiments;

[0009] Figure 7-Figure 9 illustrates cross-sectional views of semiconductor devices at various stages of fabrication according to some embodiments;

[0010] Fig.10 illustrates a top view of a semiconductor device during fabrication according to some embodiments;

[0011] Fig.11 illustrates a cross-sectional view of a semiconductor device during fabrication according to some embodiments;

[0012] Fig.12 A top view of a semiconductor device during fabrication is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] Some embodiments relate to a semiconductor device. According to some embodiments, the semiconductor device includes a first portion, the first portion including a first passivation layer, a first dielectric layer located above the first passivation layer, a first substrate located above the first dielectric layer, a first conductive layer located above the first substrate, and a guard ring located in the first dielectric layer. The semiconductor device includes a second portion located below the first portion. The second portion includes a second passivation layer and a second conductive layer located in the second passivation layer. The semiconductor device includes a vertical conductive structure passing through the first substrate, the first dielectric layer, and the first passivation layer. In some embodiments, the vertical conductive structure contacts the first conductive layer and the second conductive layer and is surrounded by a guard ring.

[0016] According to some embodiments, the first dielectric layer is an ultra low k (ELK) dielectric having a dielectric constant of about 2.6 or less. According to some embodiments, the guard ring protects, shields, electrically isolates, etc., at least one of the vertical conductive structure or the first dielectric layer. In some embodiments, the guard ring provides support, reinforcement, structural integrity, etc., to at least one of the vertical conductive structure or the first dielectric layer.

[0017] Figure 1-Figure 12 Semiconductor device 100 is shown at various stages of fabrication in accordance with some embodiments.

[0018] refer to Figure 1 According to some embodiments, the semiconductor device 100 includes a first portion 110 and a second portion 140. In some embodiments, the first portion 110 and the second portion 140 are manufactured separately and then placed together. In some embodiments, the first portion 110 is manufactured and turned over to Figure 1 The orientation shown is then placed on top of the second portion 140 .

[0019] In some embodiments, the first portion 110 includes a first passivation layer 112, a first dielectric layer 114 located above the first passivation layer 112, a second dielectric layer 120 located above the first dielectric layer 114, a third dielectric layer 122 located above the second passivation layer 120, a fourth dielectric layer 124 located above the third dielectric layer 122, a first interlayer dielectric (ILD) layer 126 located above the fourth dielectric layer 124, and a first substrate 116 located above the first ILD layer 126. According to some embodiments, a first guard ring 118 is located in the first dielectric layer 114, the second dielectric layer 120, the third dielectric layer 122, and the fourth dielectric layer 124. In some embodiments, the first portion 110 includes more than four dielectric layers. In some embodiments, the first portion 110 includes less than four dielectric layers. In some embodiments, the first guard ring 118 is located in all dielectric layers. In some embodiments, the first guard ring 118 is located in less than all dielectric layers.

[0020] In some embodiments, the first passivation layer 112 includes at least one of AlN, Al2O3, SiO2, or Si3N4, or other suitable materials. In some embodiments, the first passivation layer 112 includes a chemically inert, corrosion-resistant dielectric material. In some embodiments, the first passivation layer 112 includes an organic compound having at least one of an N-, P-, or S-group molecular structure. In some embodiments, the first passivation layer 112 has a dielectric constant of about 4.2.

[0021] In some embodiments, the first passivation layer 112 is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, oxidation, passivation process, or other suitable techniques. In some embodiments, a chemically stable material is used to manufacture the first passivation layer 112. In some embodiments, the passivation process is a process in which the first portion 110 is flipped to Figure 1 Before being deposited in the direction shown, the film covers the underlying material, such as the first dielectric layer 114. In some embodiments, the film inhibits the dissolution of the underlying material. In some embodiments, the film reduces the chemical reactivity relative to the underlying material. In some embodiments, the film reduces the electrical reactivity relative to the underlying material. In some embodiments, the passivation process includes at least one of oxidation of the surface of the underlying material or complexation of the surface with an organic compound. In some embodiments, the first passivation layer 112 inhibits at least one of charges, atoms, or ions from diffusing into the underlying material. In some embodiments, the first passivation layer 112 reduces oxidation of the underlying material. In some embodiments, the first passivation layer 112 protects the underlying material from environmental conditions. In some embodiments, the first passivation layer 112 acts as a diffusion barrier relative to the underlying material.

[0022] In some embodiments, at least one of the dielectric layers 114, 120, 122, or 124 includes at least one of a polymer, an oxide, polybenzobisoxazole (PBO), polyimide (PI), a metal nitride, silicon, germanium, carbide, gallium, arsenide, germanium, arsenic, indium, silicon oxide, sapphire, or other suitable materials. In some embodiments, at least one of the dielectric layers 114, 120, 122, or 124 electrically insulates the interconnection lines in the first portion 110. In some embodiments, at least one of the dielectric layers 114, 120, 122, or 124 is formed by physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, oxidation, or at least one of other suitable techniques. In some embodiments, at least some of the dielectric layers are formed in the same manner. In some embodiments, at least some of the dielectric layers are formed in different manners.

[0023] According to some embodiments, at least one of dielectric layers 114 , 120 , 122 , or 124 is an ELK dielectric having a dielectric constant of about 2.6 or less. In some embodiments, at least one of dielectric layers 114 , 120 , 122 , or 124 has a dielectric constant less than that of first passivation layer 112 .

[0024] In some embodiments, the first ILD layer 126 includes at least one of tetraethylorthosilicate (TEOS), borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), polymer thermosetting materials, or other suitable materials. In some embodiments, the first ILD layer 126 reduces the capacitive coupling between adjacent conductive lines. In some embodiments, the first ILD layer 126 has a dielectric constant of about 4.2. In some embodiments, the first ILD layer 126 is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

[0025] In some embodiments, the first substrate 116 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the first substrate 116 includes silicon or other suitable materials.

[0026] According to some embodiments, the first guard ring 118 includes at least one of a metal layer 128 or a vertical interconnect access (VIA) 130. According to some embodiments, at least one of the metal layer 128 or the VIA 130 includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, at least one of the metal layer 128 or the VIA 130 does not include a metal. In some embodiments, at least one of the metal layer 128 or the VIA 130 is located in at least one of the dielectric layers 114, 120, 122, or 124. According to some embodiments, the first guard ring 118 includes alternating layers of metal layers 128 and VIA 130. According to some embodiments, at least some of the metal layers 128 have the same width. In some embodiments, at least some of the metal layers 128 have different widths. In some embodiments, at least some of the metal layers 128 have the same height. In some embodiments, at least some of the metal layers 128 have different heights. In some embodiments, at least some of the metal layers 128 have different compositions than other metal layers 128. In some embodiments, at least some of the VIAs 130 have the same width. In some embodiments, at least some of the VIAs 130 have different widths. In some embodiments, at least some of the VIAs 130 have the same height. In some embodiments, at least some of the VIAs 130 have different heights. In some embodiments, at least some of the VIAs 130 have different compositions than other VIAs 130.

[0027] According to some embodiments, the width of at least some of the metal layers 128 is different from the width of at least some of the VIAs 130. In some embodiments, the width of at least some of the metal layers 128 is the same as the width of at least some of the VIAs 130. In some embodiments, the height of at least some of the metal layers 128 is different from the height of at least some of the VIAs 130. In some embodiments, the height of at least some of the metal layers 128 is the same as the height of at least some of the VIAs 130. In some embodiments, the first guard ring 118 has a width 132 of about 3 microns to about 6 microns. In some embodiments, the first guard ring 118 has a height 134 of about 0.5 microns to about 4 microns.

[0028] In some embodiments, at least one of the metal layer 128 or the VIA 130 is formed by at least one of photolithography, etching, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques. In photolithography, a photosensitive material such as a photoresist is formed above the layer to be patterned. The properties of the photoresist, such as solubility, are affected by light. The photoresist can be a negative photoresist or a positive photoresist. For a negative photoresist, when illuminated by a light source, an area of ​​the negative photoresist becomes insoluble, so that during a subsequent development stage, applying a solvent to the negative photoresist can remove the un-irradiated area of ​​the negative photoresist. Therefore, the pattern formed in the negative photoresist is a negative pattern defined by the opaque area of ​​the template between the light source and the negative photoresist. In positive photoresist, the irradiated area of ​​positive photoresist becomes soluble and can be removed by applying solvent during development. Therefore, the pattern formed in positive photoresist is a positive image of the opaque area of ​​the template between the light source and the positive photoresist. According to some embodiments, the etchant has selectivity, so that the rate at which the etchant removes or etches the photoresist is greater than the rate at which the etchant removes or etches the layer below the photoresist. Therefore, the opening in the photoresist allows the etchant to form a corresponding opening in the layer below the photoresist, thereby transferring the pattern in the photoresist to the layer below the photoresist. The pattern in the layer below the photoresist is filled with one or more materials to form one or more elements, features, etc., and at least one of before or after the pattern in the layer below the photoresist is filled with one or more materials, the patterned photoresist is stripped or washed away. In some embodiments, a dual damascene process is adopted to form at least one of metal layer 128 or VIA 130.

[0029] In some embodiments, a metal layer 128 and a VIA 130 are formed in the first dielectric layer 114, and then a second dielectric layer 120 is formed, and a metal layer 128 and a VIA 130 are formed in the second dielectric layer 120, and then a third dielectric layer 122 is formed, and a metal layer 128 and a VIA 130 are formed in the third dielectric layer 122, and then a fourth dielectric layer 124 is formed, and a metal layer 128 and a VIA 130 are formed in the fourth dielectric layer 124. In some embodiments, such a process is repeated any number of times to form the first guard ring 118. In some embodiments, one or more dielectric layers do not include at least one of the metal layer 128 or the VIA 130. In some embodiments, the first guard ring 118 is discontinuous because one or more intermediate dielectric layers do not include at least one of the metal layer 128 or the VIA 130. In some embodiments, at least one of the one or more metal layers 128, or the one or more VIAs 130 is formed before at least some surrounding dielectric layers, such as before at least one of at least some first dielectric layers 114, at least some second dielectric layers 120, at least some third dielectric layers 122, or at least some fourth dielectric layers 124. In some embodiments, at least some layers are formed and patterned to form at least one metal layer 128, and then at least some first dielectric layers 114 are formed around the at least one metal layer 128, such that the at least one metal layer 128 is located in the first dielectric layer 114. In some embodiments, at least some layers are formed and patterned to form at least one VIA 130, and then at least some first dielectric layers 114 are formed around the at least one VIA 130, such that the at least one VIA 130 is located in the first dielectric layer 114. In some embodiments, at least some layers are formed and patterned to form at least one metal layer 128, and then at least some second dielectric layers 120 are formed around the at least one metal layer 128, such that the at least one metal layer 128 is located in the second dielectric layer 120. In some embodiments, at least some layers are formed and patterned to form at least one VIA 130, and then at least some second dielectric layers 120 are formed around the at least one VIA 130, such that the at least one VIA 130 is located in the second dielectric layer 120. In some embodiments, at least some layers are formed and patterned to form at least one metal layer 128, and then at least some third dielectric layers 122 are formed around the at least one metal layer 128, such that the at least one metal layer 128 is located in the third dielectric layer 122. In some embodiments, at least some layers are formed and patterned to form at least one VIA 130, and then at least some third dielectric layers 122 are formed around the at least one VIA 130, such that the at least one VIA 130 is located in the third dielectric layer 122.In some embodiments, at least some layers are formed and patterned to form at least one metal layer 128 , and then at least some fourth dielectric layer 124 is formed around at least one metal layer 128 such that at least one metal layer 128 is located in fourth dielectric layer 124 .

[0030] In some embodiments, the first portion 110 includes at least one of one or more conductive elements 200 or one or more contacts 121. In some embodiments, at least some of the conductive elements 200 include at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, at least some of the conductive elements 200 have the same composition as at least some of the metal layers 128 or at least some of the VIAs 130. In some embodiments, at least some of the conductive elements 200 have different compositions than at least some of the metal layers 128 or at least some of the VIAs 130. In some embodiments, at least some of the conductive elements 200 have different compositions than other conductive elements 200. In some embodiments, at least some of the contacts 121 include at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, at least some of the contacts 121 have the same composition as at least some of the metal layers 128, at least some of the VIAs 130, or at least some of the conductive elements 200. In some embodiments, at least some of the contacts 121 have a different composition than at least some of the metal layers 128, at least some of the VIAs 130, or at least some of the conductive elements 200. In some embodiments, at least some of the contacts 121 have a different composition than other contacts 121. In some embodiments, at least one of the conductive elements 200 or the contacts 121 does not include metal. In some embodiments, at least some of the contacts 201 are in contact with at least some of the conductive elements 200. In some embodiments, the conductive elements 200 are used as wiring in the semiconductor device 100, and the contacts 201 in contact with the conductive elements provide a conductive path to the wiring.

[0031] According to some embodiments, any conductive element 200 has any desired shape or size. According to some embodiments, any contact 201 has any desired shape or size. In some embodiments, at least one of the conductive element 200 or the contact 201 is formed by photolithography, etching, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or at least one of other suitable techniques. In some embodiments, the conductive element 200 is formed in the first dielectric layer 114, then the second dielectric layer 120 is formed, and the conductive element 200 is formed in the second dielectric layer 120, then the third dielectric layer 122 is formed, and the conductive element 200 is formed in the third dielectric layer 122, then the fourth dielectric layer 124 is formed, and the conductive element 200 is formed in the fourth dielectric layer 124. In some embodiments, this process is repeated any number of times. In some embodiments, at least one of the dielectric layers does not include a conductive element 200. In some embodiments, a first ILD layer 126 is formed, and a contact 201 is formed in the first ILD layer 126, for example, by etching and deposition. In some embodiments, one or more conductive elements 200, or at least one of the one or more contacts 201, are formed before at least some surrounding layers, such as at least some first dielectric layers 114, at least some second dielectric layers 120, at least some third dielectric layers 122, at least some fourth dielectric layers 124, or at least some first ILD layers 126. In some embodiments, at least some layers are formed and patterned to form at least one conductive element 200, and then at least some first dielectric layers 114 are formed around the at least one conductive element 200, so that the at least one conductive element 200 is located in the first dielectric layer 114. In some embodiments, at least some layers are formed and patterned to form at least one conductive element 200, and then at least some second dielectric layers 120 are formed around the at least one conductive element 200, such that the at least one conductive element 200 is located in the second dielectric layers 120. In some embodiments, at least some layers are formed and patterned to form at least one conductive element 200, and then at least some third dielectric layers 122 are formed around the at least one conductive element 200, such that the at least one conductive element 200 is located in the third dielectric layers 122. In some embodiments, at least some layers are formed and patterned to form at least one conductive element 200, and then at least some fourth dielectric layers 124 are formed around the at least one conductive element 200, such that the at least one conductive element 200 is located in the fourth dielectric layers 124.In some embodiments, at least some layers are formed and patterned to form at least one contact 201 , and then at least some first ILD layer 126 is formed around the at least one contact 201 such that the at least one contact 201 is located in the first ILD layer 126 .

[0032] In some embodiments, the first portion 110 includes one or more etch stop layers 136, for example, located between adjacent dielectric layers. In some embodiments, the etch stop layer selectively has a different etch relative to an overlying or adjacent layer, so that when the etchant etches through the overlying layer, the etching process slows down or stops when the etchant encounters the underlying etch stop layer. According to some embodiments, the etch stop layer includes silicon, carbon, or other suitable materials. In some embodiments, at least some of the different etch stop layers have different compositions, for example, due to different etchants being used to etch different materials. In some embodiments, the etch stop layer 136 between the first ILD layer 126 and the fourth dielectric layer 124 has a different composition than at least one other etch stop layer 136, for example, due to the etchant used to etch the first ILD layer 126 being different from the etchant used to etch at least one of the fourth dielectric layer 124, the third dielectric layer 122, the second dielectric layer 120, or the first dielectric layer 114.

[0033] In some embodiments, the second portion 140 includes a second passivation layer 142, a conductive layer 144 in the second passivation layer 142, a transition metal dielectric (TMD) layer 146 below the second passivation layer 142, a first intermetal dielectric (IMD) layer 152 below the TMD layer 146, a second IMD layer 154 below the first IMD layer 152, a third IMD layer 156 below the second IMD layer 154, a fourth IMD layer 158 below the third IMD layer 156, a second ILD layer 160 below the fourth IMD layer 158, and a second substrate 162 below the second ILD layer 160. In some embodiments, the second portion 140 includes more than four IMD layers. In some embodiments, the second portion 140 includes less than four IMD layers.

[0034] In some embodiments, the second passivation layer 142 includes at least one of AlN, Al2O3, SiO2, or Si3N4, or other suitable materials. In some embodiments, the second passivation layer 142 includes a chemically inert, corrosion-resistant dielectric material. In some embodiments, the second passivation layer 142 includes an organic compound having at least one of an N-, P-, or S-group molecular structure. In some embodiments, the second passivation layer 142 includes heteroatoms. In some embodiments, the second passivation layer 142 has a dielectric constant of about 4.2. In some embodiments, the second passivation layer 142 has the same composition as the first passivation layer 112. In some embodiments, the second passivation layer 142 has a different composition than the first passivation layer 112. In some embodiments, the second passivation layer 142 is formed by at least one of a passivation process, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, oxidation, or other suitable techniques. In some embodiments, the second passivation layer 142 is formed in the same manner as the first passivation layer 112. In some embodiments, the second passivation layer 142 is formed in a different manner than the first passivation layer 112.

[0035] In some embodiments, the conductive layer 144 includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, the conductive layer 144 includes a binary alloy of aluminum and copper. In some embodiments, the conductive layer 144 is embedded in the second passivation layer 142, so that it is covered on all sides by the second passivation layer 142. In some embodiments, the conductive layer 144 is formed by at least one of photolithography, etching, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

[0036] In some embodiments, the TMD layer 146 includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, the TMD layer 146 includes an atomic thin layer of a transition metal and a chalcogen. In some embodiments, the transition metal includes at least one of Mo, W, or other suitable materials. In some embodiments, the chalcogen includes at least one of S, Si, Te, or other suitable materials. According to some embodiments, the atoms of the transition metal are sandwiched between two layers of chalcogen atoms. In some embodiments, the TMD layer 146 is formed by physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or at least one of other suitable techniques.

[0037] According to some embodiments, at least one of the IMD layers 152, 154, 156, or 158 includes at least one of a polymer, an oxide, polybenzobisoxazole (PBO), polyimide (PI), a metal nitride, silicon, germanium, carbide, gallium, arsenide, germanium, arsenic, indium, silicon oxide, sapphire, or other suitable materials. In some embodiments, at least one of the IMD layers 152, 154, 156, or 158 is electrically insulated from the interconnection lines in the second portion 140. In some embodiments, at least one of the IMD layers 152, 154, 156, or 158 is formed by physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, oxidation, or at least one of other suitable techniques. In some embodiments, at least some of the IMD layers are formed in the same manner. In some embodiments, at least some of the IMD layers are formed in different manners.

[0038] According to some embodiments, at least one of the IMD layers 152 , 154 , 156 , or 158 has a dielectric constant of about 3 or less. In some embodiments, at least one of the IMD layers 152 , 154 , 156 , or 158 has a dielectric constant less than that of the second passivation layer 142 .

[0039] In some embodiments, the second ILD layer 160 includes at least one of tetraethyl orthosilicate (TEOS), borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), polymer thermosetting materials, or other suitable materials. In some embodiments, the second ILD layer 160 reduces the capacitive coupling between adjacent wires. In some embodiments, the second ILD layer 160 has a dielectric constant of about 4.2. In some embodiments, the second ILD layer 160 is formed by physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or at least one of other suitable techniques. In some embodiments, the second ILD layer 160 is formed in the same manner as the first ILD layer 126. In some embodiments, the second ILD layer 160 is formed in a different manner from the first ILD layer 126.

[0040] In some embodiments, the second substrate 162 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the second substrate 162 includes silicon or other suitable materials. In some embodiments, the second substrate 162 has the same composition as the first substrate 116. In some embodiments, the second substrate 162 has a different composition than the first substrate 116. In some embodiments, the second portion 140 includes at least one of one or more conductive elements 200, one or more contacts 201, or one or more etch stop layers 136. In some embodiments, at least one of at least some of the conductive elements 200 in the second portion 140 has the same composition, is formed in the same manner, performs the same function, etc. as at least some of the conductive elements 200 in the first portion 110. In some embodiments, at least one of at least some of the contacts 201 in the second portion 140 has the same composition, is formed in the same manner, performs the same function, etc. as at least some of the contacts 201 in the first portion 110. In some embodiments, at least one of at least some of the etch stop layers 136 in the second portion 140 has the same composition, is formed in the same manner, performs the same function, etc. as at least some of the etch stop layers 136 in the first portion 110 .

[0041] Figure 2The first portion 110 is shown to be located on the second portion 140 according to some embodiments. According to some embodiments, the first passivation layer 112 contacts the second passivation layer 142. According to some embodiments, the first passivation layer 112 adheres to the second passivation layer 142. According to some embodiments, despite at least one of the first passivation layer 112 contacting the second passivation layer 142 or the first passivation layer 112 adhering to the second passivation layer 142, there is still a demarcation between the first passivation layer 112 and the second passivation layer 142.

[0042] refer to Figure 3 , an opening 180 is formed in the first portion 110 and the second portion 140. In some embodiments, the opening 180 is formed such that the opening 180 is surrounded by the first guard ring 118. In some embodiments, the opening 180 is formed from a top surface of the first substrate 116 and extends through the first substrate 116, the first ILD layer 126, the fourth dielectric layer 124, the third dielectric layer 122, the second dielectric layer 120, the first dielectric layer 114, the first passivation layer 112, and the second passivation layer 142. In some embodiments, the opening 180 exposes the conductive layer 144.

[0043] In some embodiments, the opening 180 is formed by at least one of photolithography, etching, or other suitable techniques. According to some embodiments, the etchant has selectivity, so that the etchant removes or etches the first substrate 116, the first ILD layer 126, the fourth dielectric layer 124, the third dielectric layer 122, the second dielectric layer 120, the first dielectric layer 114, the first passivation layer 112, and the second passivation layer 142 at a rate greater than the etchant removes or etches the patterned photoresist thereon. According to some embodiments, the opening 180 is defined by the sidewalls of the first substrate 116, the first ILD layer 126, the fourth dielectric layer 124, the third dielectric layer 122, the second dielectric layer 120, the first dielectric layer 114, the first passivation layer 112, and the second passivation layer 142. In some embodiments, the etchant removes or etches away an amount of at least one of the first substrate 116, the first ILD layer 126, the fourth dielectric layer 124, the third dielectric layer 122, the second dielectric layer 120, the first dielectric layer 114, the first passivation layer 112, or the second passivation layer 142 to expose at least some of at least one of the metal layer 128 or the VIA 130, so that at least some of the openings 180 are defined by at least some of the metal layer 128 or the VIA 130.

[0044] In some embodiments, opening 180 has a width 182 and a height 184. In some embodiments, width 182 is about 0.5 microns to about 4 microns. In some embodiments, height 184 is about 3 microns to about 8 microns. According to some embodiments, opening 180 is defined by tapered sidewalls such that width 182 of opening 180 varies along height 184. In some embodiments, width 182 decreases as it moves in a direction from first substrate 116 to conductive layer 144. According to some embodiments, the opening may have any cross-sectional profile such as stepped, hourglass, non-tapered, etc., for example, by using one or more etchants, or using at least one of one or more etching processes such as directional etching, isotropic etching, anisotropic etching, etc.

[0045] refer to Figure 4 , a conductive material 150 is formed over the first substrate 116 and in the opening 180. In some embodiments, the conductive material 150 includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, the conductive material is formed by at least one of focused ion beam (FIB), physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

[0046] refer to Figure 5, removing excess conductive material to establish a vertical conductive structure 186 in the opening 180. In some embodiments, the removal of excess conductive material exposes the top surface of the first substrate 116. In some embodiments, the vertical conductive structure 186 has a width 188 and a height 190. According to some embodiments, the width 188 of the vertical conductive structure 186 corresponds to the width 182 of the opening 180. According to some embodiments, the height 190 of the vertical conductive structure 186 corresponds to the height 184 of the opening 180. According to some embodiments, the vertical conductive structure 186 has an arbitrary cross-sectional profile. According to some embodiments, the vertical conductive structure 186 has a cross-sectional profile that corresponds to the cross-sectional profile of the opening. According to some embodiments, the width 188 of the vertical conductive structure 186 varies along the height 190. In some embodiments, the width 188 decreases as it moves along the direction from the first substrate 116 to the conductive layer 144. According to some embodiments, one or more sidewalls of the vertical conductive structure 186 are at least one of tapered, stepped, non-linear, non-tapered, etc. In some embodiments, the excess conductive material is removed by at least one of chemical mechanical polishing (CMP) or other suitable techniques. In some embodiments, abrasive slurry is used to remove excess material. In some embodiments, vertical conductive structure 186 includes through silicon VIA (TSV). In some embodiments, TSV is a high performance interconnect used as an alternative to wire bonding and flip chip. In some embodiments, TSV is used to create 3D packaging. In some embodiments, TSV is used to create 3D integrated circuits (IC). In some embodiments, TSV is used to shorten the connection length. In some embodiments, vertical conductive structure 186 includes organic through VIA (TOV).

[0047] According to some embodiments, a barrier layer (not shown) is formed over the sidewalls, surfaces, etc. of the defined opening 180 before defining the conductive material 150. According to some embodiments, the barrier layer is relatively thin and does not fill the opening 180, so that the conductive material 150 can be formed over the barrier layer. According to some embodiments, the barrier layer includes at least one of titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, or other suitable materials. In some embodiments, the barrier layer is formed by at least one of a focused ion beam (FIB), physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

[0048] Figure 6 FIG. 1 shows a schematic diagram of a process for removing the first substrate 116, the first ILD layer 126, and the etch stop layer 136 according to some embodiments. Figure 5According to some embodiments, Figure 5 Corresponding to along Figure 6 5. In some embodiments, a plurality of conductive elements 200 are present around the first guard ring 118. In some embodiments, the conductive elements 200 are used as wiring inside the semiconductor device 100. According to some embodiments, the first guard ring 118 completely surrounds, wraps around, etc. all sides or sidewalls of the vertical conductive structure 186. According to some embodiments, the first guard ring 118 is discontinuous or has breaks to surround, wrap around, etc. some but not all of the vertical conductive structures 186.

[0049] Although shown as being generally quadrilateral, according to some embodiments, the top profile of at least one of the vertical conductive structure 186 or the first guard ring 118 may be any desired shape other than a quadrilateral, such as at least one of an ellipse, a polygon, a star, etc.

[0050] refer to Figure 7 , a conductive layer 192 is formed over the first substrate 116 and the vertical conductive structures 186. In some embodiments, the conductive layer 192 includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, the conductive layer 192 has the same composition as at least one of the conductive layer 144 or the vertical conductive structure 186. In some embodiments, the conductive layer 192 has a different composition than at least one of the conductive layer 144 or the vertical conductive structure 186. In some embodiments, the conductive layer 144 is formed by physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or at least one of other suitable techniques.

[0051] refer to Figure 8 , the conductive layer 192 is patterned such that a portion of the conductive layer 192 is removed from the top surface of the first substrate 116. In some embodiments, these portions of the conductive layer are removed such that the conductive layer 192 covers at least some of the vertical conductive structures 186. In some embodiments, the conductive layer 192 is patterned by at least one of photolithography, etching, or other suitable techniques. According to some embodiments, the vertical conductive structures 186 connect the conductive layer 192 in or on the first portion 110 of the semiconductor device 100 to the conductive layer 144 in the second portion 140 of the semiconductor device 100 while being at least partially surrounded, encircled, etc. by the first guard ring 118.

[0052] Fig. 9 1 shows a semiconductor device 100 according to some embodiments. In some embodiments, second guard ring 194 is formed adjacent to first guard ring 118, around first guard ring 118, concentric with first guard ring 118, etc. In some embodiments, at least some second guard ring 194 contacts at least some first guard ring 118. In some embodiments, second guard ring 194 does not contact first guard ring 118.

[0053] According to some embodiments, second guard ring 194 includes at least one of metal layer 196 or vertical interconnect via (VIA) 198. According to some embodiments, at least one of metal layer 196 or VIA 198 includes at least one of Al, Cu, Sn, Ni, Au, Ag, W, or other suitable materials. In some embodiments, at least one of metal layer 196 or VIA 198 does not include metal. In some embodiments, second guard ring 194 has the same composition as first guard ring 118. In some embodiments, second guard ring 194 has a different composition than first guard ring 118.

[0054] In some embodiments, at least one of the metal layers 196 or the VIAs 198 is located in at least one of the dielectric layers 114, 120, 122, or 124. According to some embodiments, the second guard ring 194 includes alternating layers of metal layers 196 and VIAs 198. According to some embodiments, at least some of the metal layers 196 have the same width. In some embodiments, at least some of the metal layers 196 have different widths. In some embodiments, at least some of the metal layers 196 have the same height. In some embodiments, at least some of the metal layers 196 have different heights. In some embodiments, at least some of the VIAs 198 have the same width. In some embodiments, at least some of the VIAs 198 have different widths. In some embodiments, at least some of the VIAs 198 have the same height. In some embodiments, at least some of the VIAs 198 have different heights.

[0055] According to some embodiments, at least some metal layers 196 have the same width as at least some metal layers 128, at least some VIAs 130, or at least some VIAs 198. In some embodiments, at least some metal layers 196 have different widths than at least some metal layers 128, at least some VIAs 130, or at least some VIAs 198. In some embodiments, at least some metal layers 196 have the same height as at least some metal layers 128, at least some VIAs 130, or at least some VIAs 198. In some embodiments, at least some metal layers 196 have different heights than at least some metal layers 128, at least some VIAs 130, or at least some VIAs 198. In some embodiments, second guard ring 194 has a width 137 of about 3 microns to about 7 microns. In some embodiments, second guard ring 194 has a height 138 of about 0.5 microns to about 4 microns. In some embodiments, width 137 of second guard ring 194 is the same as width 132 of first guard ring 118. In some embodiments, width 137 of second guard ring 194 is different from width 132 of first guard ring 118. In some embodiments, height 138 of second guard ring 194 is the same as height 134 of first guard ring 118. In some embodiments, height 138 of second guard ring 194 is different from height 134 of first guard ring 118.

[0056] In some embodiments, at least one of the metal layer 196 or the VIA 198 is formed by photolithography, etching, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or at least one of other suitable techniques. In some embodiments, at least some of the second guard rings 194 are formed in the same manner as at least some of the first guard rings 118. In some embodiments, at least some of the second guard rings 194 are formed in a different manner than at least some of the first guard rings 118.

[0057] In some embodiments, a metal layer 196 and a VIA 198 are formed in the first dielectric layer 114, and then a second dielectric layer 120 is formed, and a metal layer 196 and a VIA 198 are formed in the second dielectric layer 120, and then a third dielectric layer 122 is formed, and a metal layer 196 and a VIA 198 are formed in the third dielectric layer 122, and then a fourth dielectric layer 124 is formed, and a metal layer 196 and a VIA 198 are formed in the fourth dielectric layer 124. In some embodiments, such a process is repeated any number of times to form a second guard ring 194. In some embodiments, one or more dielectric layers do not include at least one of the metal layer 196 or the VIA 198. In some embodiments, the second guard ring 194 is discontinuous because one or more intermediate dielectric layers do not include at least one of the metal layer 196 or the VIA 198. In some embodiments, the dielectric layer includes some second guard rings 194, but does not include the first guard ring 118. In some embodiments, the dielectric layer does not include the second guard ring 194 , but includes some of the first guard ring 118 .

[0058] Fig.10 FIG. 1 shows a schematic diagram of a process for removing the conductive layer 192, the first substrate 116, the first ILD layer 126, and the etch stop layer 136 according to some embodiments. Fig. 9 According to some embodiments, Fig. 9 Corresponding to along Fig.10 9. In some embodiments, a plurality of conductive elements 200 are present around the first guard ring 118 and the second guard ring 194. In some embodiments, at least some of the plurality of conductive elements 200 have the same composition as at least some of the metal layers 196 or at least some of the VIAs 198. In some embodiments, at least some of the plurality of conductive elements 200 have a different composition than at least some of the metal layers 196 or at least some of the VIAs 198.

[0059] In some embodiments, the conductive element 200 is used as a wiring inside the semiconductor device 100. According to some embodiments, the first guard ring 118 completely surrounds, surrounds, etc. all sides or sidewalls of the vertical conductive structure 186. According to some embodiments, the first guard ring 118 is discontinuous or has breaks to surround, surround, etc. some but not all of the vertical conductive structure 186. According to some embodiments, the second guard ring 194 completely surrounds, surrounds, etc. all sides or sidewalls of the vertical conductive structure 186 or at least one of all sides or sidewalls of the first guard ring 118. According to some embodiments, the second guard ring 194 is discontinuous or has breaks to surround, surround, etc. some but not all of at least one of the vertical conductive structure 186 or the first guard ring 118.

[0060] Although shown as being generally quadrilateral, in accordance with some embodiments, the top profile of at least one of vertical conductive structure 186 , first guard ring 118 , or second guard ring 194 may be any desired shape other than a quadrilateral, such as at least one of an ellipse, a polygon, a star, etc.

[0061] Fig.11 The semiconductor device 100 is shown in accordance with some embodiments, wherein the metal layer 128, the VIA 130, the metal layer 196, and the VIA 198 have substantially uniform dimensions, such as width and height. In some embodiments, the first guard ring 118 is discontinuous because one or more intermediate dielectric layers do not include at least one of the metal layer 128 or the VIA 130. In some embodiments, the second guard ring 194 is discontinuous because one or more intermediate dielectric layers do not include at least one of the metal layer 196 or the VIA 198.

[0062] Fig.12 FIG. 1 shows a schematic diagram of a process for removing the conductive layer 192, the first substrate 116, the first ILD layer 126, and the etch stop layer 136 according to some embodiments. Fig.11 According to some embodiments, Fig.11 Corresponding to along Fig.12 The cross-sectional view is taken along the line 11-11 in FIG. Assuming that Fig.10 and Fig.12 Only the uppermost metal layer 128 of the first guard ring 118 and the uppermost metal layer 196 of the second guard ring 194 can be seen. Fig.12 and Fig.10Similarly. According to some embodiments, the first guard ring 118 completely surrounds, encircles, etc. all sides or sidewalls of the vertical conductive structure 186. According to some embodiments, the first guard ring 118 is discontinuous or has breaks to surround, encircle, etc. some but not all of the vertical conductive structure 186. According to some embodiments, the second guard ring 194 completely surrounds, encircles, etc. all sides or sidewalls of the vertical conductive structure 186, or at least one of all sides or sidewalls of the first guard ring 118. According to some embodiments, the second guard ring 194 is discontinuous or has breaks to surround, encircle, etc. some but not all of at least one of the vertical conductive structure 186 or the first guard ring 118.

[0063] Although shown as being generally quadrilateral, in accordance with some embodiments, the top profile of at least one of vertical conductive structure 186 , first guard ring 118 , or second guard ring 194 may be any desired shape other than a quadrilateral, such as at least one of an ellipse, a polygon, a star, etc.

[0064] According to some embodiments, the first portion 110 of the semiconductor device 100 is associated with a backside illumination (BSI) contact image sensor (CIS). In some embodiments, the image sensor is inverted and color filters and microlenses are applied to the back side of the pixels for light collection. In some embodiments, this arrangement of elements increases the amount of light captured and thus improves performance in low light situations. In some embodiments, the second portion 140 of the semiconductor device 100 is associated with an application specific integrated circuit (ASIC).

[0065] According to some embodiments, a semiconductor device includes a first portion and a second portion located below the first portion. The first portion includes: a first passivation layer; a first dielectric layer located above the first passivation layer; a first substrate located above the first dielectric layer; a first conductive layer located above the first substrate; and a first guard ring located in the first dielectric layer. The second portion includes: a second passivation layer; a second conductive layer located in the second passivation layer; a second dielectric layer located below the second passivation layer; and a second substrate located below the second dielectric layer. The semiconductor device includes a vertical conductive structure that passes through the first substrate, the first dielectric layer, and the first passivation layer, wherein the vertical conductive structure contacts the first conductive layer and the second conductive layer and is surrounded by a first guard ring.

[0066] In some embodiments, the first passivation layer contacts the second passivation layer.

[0067] In some embodiments, the vertical conductive structures have tapered sidewalls.

[0068] In some embodiments, the first dielectric layer is an ultra low-k dielectric.

[0069] In some embodiments, the first conductive layer covers a portion of the first substrate.

[0070] In some embodiments, the first portion includes a second dielectric layer, wherein the vertical conductive structure passes through the second dielectric layer, and the first guard ring is located in the second dielectric layer.

[0071] In some embodiments, the first portion includes a second guard ring in the first dielectric layer and surrounding the first guard ring.

[0072] In some embodiments, the first guard ring and the second guard ring are not connected to each other.

[0073] According to some embodiments, a semiconductor device includes a first portion and a vertical conductive structure. The first portion includes: a first dielectric layer; and a first guard ring located in the first dielectric layer, wherein the first guard ring includes a first metal layer connected to a first via in the first dielectric layer. The vertical conductive structure passes through the first dielectric layer and is close to the first guard ring.

[0074] In some embodiments, the first portion includes a second dielectric layer, wherein the vertical conductive structure passes through the second dielectric layer, and the first guard ring is located in the second dielectric layer.

[0075] In some embodiments, the first guard ring includes a second metal layer connected to a second via in the second dielectric layer.

[0076] In some embodiments, the first portion includes a third dielectric layer between the first dielectric layer and the second dielectric layer; the vertical conductive structure passes through the third dielectric layer, and the first guard ring is not in the third dielectric layer.

[0077] In some embodiments, the first metal layer has a first width, and the first via has a second width that is smaller than the first width.

[0078] In some embodiments, the first portion includes a second guard ring in the first dielectric layer and surrounding the first guard ring.

[0079] In some embodiments, the first portion includes a second dielectric layer and a third dielectric layer; the third dielectric layer is located between the first dielectric layer and the second dielectric layer; the vertical conductive structure passes through the second dielectric layer; the vertical conductive structure passes through the third dielectric layer; the first guard ring is located in the second dielectric layer but not in the third dielectric layer; the second guard ring is located in the third dielectric layer but not in the second dielectric layer.

[0080] In some embodiments, the first dielectric layer is an ultra low-k dielectric.

[0081] According to some embodiments, a method for forming a semiconductor device includes: forming a first guard ring in a first dielectric layer; and forming a vertical conductive structure having a tapered sidewall, the vertical conductive structure passing through the first dielectric layer and surrounded by the first guard ring.

[0082] In some embodiments, the method includes forming a second guard ring in the first dielectric layer, wherein the second guard ring surrounds the first guard ring.

[0083] In some embodiments, the method includes forming a first guard ring in the second dielectric layer, wherein forming the vertical conductive structure includes forming the vertical conductive structure to pass through the second dielectric layer.

[0084] In some embodiments, forming the first guard ring includes forming a first metal layer in the first dielectric layer, and forming a first via in the first dielectric layer and contacting the first metal layer.

[0085] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purpose as the embodiments described herein or to achieve the same advantages. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and variations may be made without departing from the spirit and scope of the present disclosure.

[0086] Although the subject matter has been described in specific language with respect to structural features or methodological acts, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

[0087] Various operations of the embodiments are provided herein. The order in which some or all operations are described should not be interpreted as implying that these operations are necessarily related to the order. With the benefit of this description, it will be appreciated that alternative orders may be present. In addition, it should be understood that not all operations must be present in each embodiment provided herein. Moreover, it should be understood that not all operations are necessary in some embodiments.

[0088] It should be understood that in some embodiments, for example, for the purpose of simplicity and ease of understanding, the layers, features, elements, etc. depicted herein are shown with specific dimensions relative to each other (e.g., structural dimensions or directions), and their actual dimensions are substantially different from the dimensions shown herein. In addition, there are a variety of techniques for forming the layers, regions, components, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD).

[0089] In addition, "exemplary" is used herein to mean used as an example, instance, illustration, etc., and is not necessarily advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, "a" and "an" used in this application and the appended claims are generally interpreted as meaning "one or more", unless otherwise specified or clearly pointed to the singular form from the context. Moreover, at least one of A and B and / or the like generally means A, or B, or both A and B. In addition, in the case of using "includes", "having", "has", "with", or its variants, these terms are intended to be included in a manner similar to the term "comprising". In addition, unless otherwise specified, "first", "second", etc. are not intended to imply time, space, order, etc. On the contrary, such terms are only used as identifiers, names, etc. for parts, elements, articles, etc. For example, the first element and the second element generally correspond to element A and element B, or two different elements, or two identical elements, or the same element.

[0090] Moreover, although the present invention has been shown and described with respect to one or more embodiments, other persons of ordinary skill in the art will be able to conceive of equivalent changes and modifications based on reading and understanding of this specification and the accompanying drawings. The present invention includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions implemented by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe such components are intended to correspond to any component (e.g., a functionally equivalent component) that implements the specified function of the component, even if it is not structurally equivalent to the disclosed structure. In addition, although a specific feature of the present invention may be disclosed only with respect to one embodiment of several embodiments, the feature may be combined with one or more other features of other embodiments, which is desirable and advantageous for any given or specific application.

Claims

1. A semiconductor device comprising: The first part includes: a first passivation layer; a first dielectric layer, located above the first passivation layer; a first substrate, located above the first dielectric layer; A first conductive layer, located above the first substrate; a first guard ring, located in the first dielectric layer; a third dielectric layer, wherein the first guard ring is located in the third dielectric layer; and a fourth dielectric layer, located between the first dielectric layer and the third dielectric layer, wherein the first guard ring is not in the fourth dielectric layer; The second part is located below the first part, and the second part includes: a second passivation layer; a second conductive layer, located in the second passivation layer; a second dielectric layer disposed below the second passivation layer; and a second substrate disposed below the second dielectric layer; and A vertical conductive structure passes through the first substrate, the first dielectric layer, the third dielectric layer, the fourth dielectric layer and the first passivation layer, wherein the vertical conductive structure contacts the first conductive layer and the second conductive layer and is surrounded by the first guard ring.

2. The semiconductor device according to claim 1, wherein The first passivation layer contacts the second passivation layer.

3. The semiconductor device according to claim 1, wherein The vertical conductive structure has a tapered sidewall.

4. The semiconductor device according to claim 1, wherein The first dielectric layer includes an ultra low-k dielectric.

5. The semiconductor device according to claim 1, wherein The first conductive layer covers a portion of the first substrate.

6. The semiconductor device according to claim 1, wherein The vertical conductive structure is spaced apart from the first guard ring.

7. The semiconductor device according to claim 1, wherein The first portion includes a second guard ring in the first dielectric layer and surrounding the first guard ring.

8. The semiconductor device according to claim 7, wherein: The first guard ring and the second guard ring are not connected to each other.

9. A semiconductor device comprising: The first part includes: a first dielectric layer; and a first guard ring located in the first dielectric layer, wherein the first guard ring includes a first metal layer connected to a first via in the first dielectric layer; a second dielectric layer, wherein the first guard ring is located in the second dielectric layer; and a third dielectric layer, located between the first dielectric layer and the second dielectric layer, wherein the first guard ring is not in the third dielectric layer; The vertical conductive structure passes through the first dielectric layer, the second dielectric layer and the third dielectric layer and is close to the first guard ring.

10. The semiconductor device according to claim 9, wherein The vertical conductive structure is surrounded by the first guard ring.

11. The semiconductor device according to claim 10, wherein The first guard ring includes a second metal layer connected to a second via in the second dielectric layer.

12. The semiconductor device according to claim 10, wherein: The vertical conductive structure is spaced apart from the first guard ring.

13. The semiconductor device according to claim 9, wherein: The first metal layer has a first width, and the first via has a second width that is smaller than the first width.

14. The semiconductor device according to claim 9, wherein The first portion also includes a second guard ring located in the first dielectric layer and surrounding the first guard ring.

15. The semiconductor device according to claim 14, wherein: The second guard ring is located in the third dielectric layer but not in the second dielectric layer.

16. The semiconductor device according to claim 9, wherein The first dielectric layer includes an ultra low-k dielectric.

17. A method of forming a semiconductor device, comprising: forming a first guard ring in a first dielectric layer and a second dielectric layer, wherein a third dielectric layer is located between the first dielectric layer and the second dielectric layer, and the first guard ring is not formed in the third dielectric layer; and A vertical conductive structure having a tapered sidewall is formed, the vertical conductive structure passing through the first dielectric layer, the second dielectric layer, and the third dielectric layer, and surrounded by the first guard ring.

18. The method according to claim 17, comprising: A second guard ring is formed in the first dielectric layer, wherein the second guard ring surrounds the first guard ring.

19. The method according to claim 18, wherein: The first guard ring and the second guard ring are not connected to each other.

20. The method according to claim 17, wherein: Forming the first guard ring includes: forming a first metal layer in the first dielectric layer; and A first via is formed in the first dielectric layer and in contact with the first metal layer.

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