Semiconductor device package and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer having a feeding area and an insulating layer disposed on the antenna layer. The insulating layer has a first portion in contact with the antenna layer and a second portion on the first portion. The first portion and the second portion of the insulating layer define a stepped structure exposing the feeding area of the antenna layer. A method of manufacturing a semiconductor device package is also disclosed.

Description

Technical Field

[0001] The present disclosure generally relates to a semiconductor device package and a method of manufacturing the same, and to a semiconductor device package including an antenna and an insulating layer. Background Art

[0002] The development of mobile communication has created a need for high data rates and stable communication quality, and high-frequency wireless transmission (e.g., 28 GHz, 39 GHz, or 60 GHz) has become one of the most important issues in the mobile communication industry. To achieve such high-frequency wireless transmission, signals must be transmitted in a frequency band with a wavelength of about ten millimeters to about one millimeter (“millimeter wave” or “mmWave”). However, signal attenuation is one of the main problems in millimeter wave transmission. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device package includes an antenna layer having a feeding region and an insulating layer disposed on the antenna layer. The insulating layer has a first portion in contact with the antenna layer and a second portion on the first portion. The first portion and the second portion of the insulating layer define a stepped structure exposing the feeding region of the antenna layer.

[0004] In one or more embodiments, a semiconductor device package includes a first antenna layer having a feeding region and an insulating layer disposed on the first antenna layer. The insulating layer defines a first opening for exposing the feeding region of the first antenna layer and a second opening above the first opening. The ratio of the width of the second opening to the width of the first opening is from about 1.2 to about 2.4.

[0005] In one or more embodiments, a method of manufacturing a semiconductor device package includes: providing an antenna layer having a feeding region; and disposing an insulating layer on the antenna layer. The method further includes removing a portion of the insulating layer to form a first opening exposing the feeding region and a second opening above the first opening. Brief Description of the Drawings

[0006] When read in conjunction with the accompanying Figure 1 drawings, various aspects of the present disclosure can be readily understood from the following detailed description. It should be noted that the various features may not be drawn to scale. For the sake of clarity of discussion, the dimensions of the various features may be increased or decreased arbitrarily.

[0007] Figure 1 A cross-sectional view of a semiconductor device package in accordance with some embodiments of the present disclosure is shown.

[0008] Figure 2 A semiconductor device package in accordance with some embodiments of the present disclosure is shown. Figure 1An enlarged view of the portion within the dashed box A shown.

[0009] Figure 3A Shows one or more stages of a method of manufacturing a semiconductor device package in accordance with some embodiments of the present disclosure.

[0010] Figure 3B Shows one or more stages of a method of manufacturing a semiconductor device package in accordance with some embodiments of the present disclosure.

[0011] Figure 3C Shows one or more stages of a method of manufacturing a semiconductor device package in accordance with some embodiments of the present disclosure.

[0012] Figure 3D Shows one or more stages of a method of manufacturing a semiconductor device package in accordance with some embodiments of the present disclosure.

[0013] Figure 3E Shows one or more stages of a method of manufacturing a semiconductor device package in accordance with some embodiments of the present disclosure.

[0014] Throughout the drawings and the detailed description, common reference numerals are used to indicate the same or like elements. The present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings. Detailed Description

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In the present disclosure, references to forming a first feature on or over a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0017] Figure 1 Shows a cross-sectional view of a semiconductor device package 1 in accordance with some embodiments of the present disclosure. The semiconductor device package 1 includes substrates 10 and 11, electrical contacts 12, 13, 17, and 19, an insulating layer 14, antenna layers 15 and 16, and an electronic component 18.

[0018] The substrate 10 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. The substrate 10 has a surface 101 and a surface 102 opposite to the surface 101. In some embodiments, the substrate 10 may be a single-layer or multi-layer substrate including a core layer with the placement surfaces 101 and 102 and conductive materials and / or structures. The conductive materials and / or structures may include multiple traces. For example, the substrate 10 includes an interconnect structure 10r, such as a redistribution layer (RDL) or a grounding element. The substrate 10 includes one or more conductive pads 10c that are close to the surface 101 of the substrate 10, adjacent to or embedded in the surface and exposed at the surface. The substrate 10 includes a dielectric layer 10d on the surface 101 of the substrate 10, and the dielectric layer is used to completely expose the conductive pad 10c or expose at least a part of the conductive pad, so as to achieve electrical connection. For example, the dielectric layer 10d may cover a part of the conductive pad 10c. In some embodiments, the dielectric layer 10d may include a solder mask or a solder mask layer.

[0019] The substrate 11 is disposed on the substrate 10 and spaced apart from the substrate 10. In some embodiments, the substrate 11 may be the same as or different from the substrate 10, depending on the design specifications. The substrate 11 has a surface 111 and a surface 112 opposite to the surface 111. The surface 112 of the substrate 11 faces the surface 101 of the substrate 10. In some embodiments, the surface 101 of the substrate 10 is parallel to the surface 112 of the substrate 11. The substrate 11 includes an interconnect structure 11r, such as an RDL or a grounding element. The substrate 11 includes one or more conductive pads 11c that are close to the surface 112 of the substrate 11, adjacent to or embedded in the surface and exposed at the surface.

[0020] The antenna layer 15 is disposed on the surface 112 of the substrate 11. The antenna layer 16 is disposed on the surface 111 of the substrate 11 (or exposed from the surface), corresponding to (e.g., disposed above) the antenna layer 15 disposed on the surface 112 of the substrate 11. For example, the antenna layer 16 faces the antenna layer 15. For example, the antenna layer 16 may be aligned with the antenna layer 15. In some embodiments, the antenna layer 15 includes multiple antenna elements. For example, the antenna layer 15 may include an antenna element array. In some embodiments, the antenna layer 15 may include an M×N antenna element array, where M and N are integers greater than 0. In some embodiments, the antenna layer 16 may also include multiple antenna elements.

[0021] In some embodiments, the antenna layers 15 and 16 may include conductive materials such as metals or metal alloys. Examples of the conductive materials include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or their alloys.

[0022] In some embodiments, the semiconductor device package 1 is designed for high-frequency wireless transmission (28 GHz, 39 GHz, or 60 GHz). The widths of the antenna layers 15 and 16 can be less than about 3.0 millimeters (mm). For example, the widths of the antenna layers 15 and 16 can be about 2.8 mm, 2.6 mm, 2.4 mm, 2.2 mm, 2.0 mm, 1.8 mm, 1.6 mm, 1.4 mm, 1.2 mm, 1.0 mm, 0.8 mm, or less. In some embodiments, the width of the antenna layer can be measured in a direction parallel to the surface 111 of the substrate 11. In some embodiments, the number of antenna layers can be changed according to design requirements.

[0023] The insulating layer 14 is disposed on the surface 112 of the substrate 11 to cover at least a portion of the antenna layer 15. For example, the feeding region of the antenna layer 15 is exposed from the insulating layer 14. The feeding region of the antenna layer 15 is exposed to be electrically connected to the substrate 10 (and the interconnect structure 10r therein) through the electrical contact 12, while another region of the antenna layer 15 is covered or protected by the insulating layer 14. In some embodiments, the insulating layer 14 can also be referred to as a protective layer, a dielectric layer, or a position-defining layer.

[0024] The insulating layer 14 includes a portion (or sub-layer) 14a in contact with the antenna layer 15 and a portion (or sub-layer) 14b on the portion 14a.

[0025] As Figure 1 shown, the portion 14a defines an opening that partially exposes the antenna layer 15, and the portion 14b defines another opening that is adjacent to the opening defined by the portion 14a. The width of the opening defined by the portion 14b is different from the width of the opening defined by the portion 14a. The portion 14a is partially exposed from the opening defined by the portion 14b. The opening defined by the portion 14a is smaller than the opening defined by the portion 14b. The portion 14a and the opening 14b define a stepped structure.

[0026] The feeding region of the antenna layer 15 is exposed through the opening defined by the portion 14a and the opening defined by the portion 14b.

[0027] The conductive pad 11c is adjacent to and spaced apart from the antenna layer 15.

[0028] Similar to the feeding region of the antenna layer 15, the conductive pad 11c is completely or partially exposed from the insulating layer 14. The insulating layer 14 is disposed on the surface 112 of the substrate 11 to completely expose the conductive pad 11c or expose at least a portion of the conductive pad to achieve electrical connection.

[0029] As Figure 1As shown, portions 14a and 14b define an opening for partially exposing the conductive pad 11c. In other words, the width of the opening defined by portion 14a is substantially similar to the width of the opening defined by portion 14b. The openings defined by portions 14a and 14b can be formed in the same operation. In some embodiments, the width of the opening for exposing the conductive pad 11c can be greater than Figure 2 the width w1 shown in, which will be discussed later. In some embodiments, the width of the opening for exposing the conductive pad 11c can be substantially equal to Figure 2 the width w2 shown in, which will be discussed later.

[0030] In some embodiments, the structure of the opening for exposing the conductive pad 11c can be similar to the structure of the opening for exposing the feeding area of the antenna layer 15. For example, the opening defined by portion 14a is smaller than the opening defined by portion 14b. In such embodiments, portions 14a and 14b define a stepped structure for exposing the conductive pad 11c.

[0031] In some embodiments, the insulating layer 14 can comprise a dielectric material. In some embodiments, the insulating layer 14 can comprise a solder mask or solder mask layer.

[0032] The electrical contacts 12 and 13 are disposed between the substrate 10 and the substrate 11. The electrical contacts 12 and 13 are disposed between the surface 101 of the substrate 10 and the substrate 112 of the substrate 11. The electrical contact 12 is disposed on the conductive pad 10c of the substrate 10 and the antenna layer 15. The electrical contact 12 covers the stepped structure for exposing the antenna layer 15. The electrical contact 12 is in direct contact with portions 14a and 14b. The electrical contact 12 is in direct contact with the feeding area of the antenna layer 15.

[0033] The electrical contact 13 is disposed on the conductive pad 10c of the substrate 10 and the conductive pad 11c of the substrate 11. The electrical contact 13 covers the stepped structure for exposing the conductive pad 11c. The electrical contact 13 is in direct contact with portions 14a and 14b. The electrical contact 13 is in direct contact with the conductive pad 11c.

[0034] The electrical contacts 12 and 13 are disposed between the substrates 10 and 11 to define the height, distance, or one or more cavities (e.g., air cavities) therebetween, and such cavities are designed to be from about 100 micrometers (μm) to about 400 micrometers to achieve frequency agility and increase bandwidth.

[0035] In some embodiments, each of the electrical contacts 12 and 13 may include solder balls, conductive pillars (such as Cu pillars), or a combination thereof. For example, each of the electrical contacts 12 and 13 may include Cu pillars (which may be used to control the height of the air gap between substrates 10 and 11) and solder balls that connect the Cu pillars to the feed regions or conductive pads 11c. In one embodiment, each of the electrical contacts 12 and 13 may include a solder material. In some embodiments, the number of electrical contacts may be changed according to design requirements.

[0036] The electronic component 18 is disposed on the surface 102 of the substrate 10. In some embodiments, the electronic component 18 is electrically connected to the antenna layer 15 through the interconnect structure 10r within the substrate 10. The electronic component 18 may be a chip or die that includes a semiconductor substrate, one or more integrated circuit devices, and one or more overlying interconnect structures therein. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or a combination thereof. The electronic component 18 may be electrically connected to the substrate 10 (e.g., to a conductive pad), and the electrical connection may be achieved by flip chip (e.g., through the electrical contact 19) or wire bonding technology.

[0037] The electrical contact 17 (e.g., a solder ball) is disposed on the conductive pad 10c and may provide an electrical connection between the semiconductor packaging device 1 and an external component (e.g., an external circuit or circuit board).

[0038] Figure 2 A magnified view of the portion within the dashed box A shown in accordance with some embodiments of the present disclosure Figure 1 is shown.

[0039] The portion 14a of the insulating layer 14 includes a surface 14a1 and a surface 14a2 that is substantially perpendicular to the surface 14a1. The surface 14a1 may also be referred to as the upper surface of the portion 14a, and the surface 14a2 may also be referred to as the side surface of the portion 14a. The portion 14b of the insulating layer 14 includes a surface 14b1 and a surface 14b2 that is substantially perpendicular to the surface 14b1. The surface 14b1 may also be referred to as the upper surface of the portion 14b, and the surface 14b2 may also be referred to as the side surface of the portion 14b.

[0040] The surface 14a2 of the portion 14a is connected to the surface 14b2 of the portion 14b through the surface 14a1 of the portion 14a. The surface 14a1 and surface 14a2 of the portion 14a and the surface 14b2 of the portion 14b define a stepped structure.

[0041] The surface 14a2 of the portion 14a defines an opening having a width w1. The surface 14b2 of the portion 14b defines an opening having a width w2.

[0042] In some embodiments, the difference between width w2 and width w1 is equal to or greater than about 30 μm, such as about 30 μm to about 140 μm. In some embodiments, the ratio of width w2 to width w1 is about 1.2 to about 2.4.

[0043] The size design rules of the width w2 and the width w1 provided in the description are for illustrative purposes only, and the present application is not limited thereto. In some embodiments, the size design rules of the width w2 and the width w1 can be adjusted according to design specifications.

[0044] As mentioned, the air gap between the substrates 10 and 11 is designed to be large to achieve frequency agility and improve bandwidth. For example, the air gap between the substrates 10 and 11 can be designed to be about 100 μm to about 400 μm, such as 300 μm.

[0045] Therefore, in some embodiments, the size (e.g., height) of electrical contacts 12 and 13 may be about 250 μm to about 350 μm, and the width w2 may be at least about 250 μm to maintain the structural stability of electrical contacts 12 and 13. For example, the height of electrical contact 12 may be about 300 μm, and the width w2 may be about 300 μm.

[0046] In some comparative embodiments, the stepped structure can be omitted, and the feed area of the antenna layer 15 is exposed only from one opening with an inclined or vertical sidewall. In such comparative embodiments, the size of the feed area is substantially equal to the width w2. However, the feed area may exceed the impedance matching requirements for high-frequency wireless transmission. For example, the feed area for 60 GHz wireless transmission is preferably less than 80 μm.

[0047] Since high frequency wireless transmission has become one of the most important issues in the mobile communication industry, it is desired to miniaturize the feeding area to meet the impedance matching requirement.

[0048] The dimension design rules of the stepped structure of the present application (eg, widths w1 and w2 ) not only meet the impedance matching requirements of high-frequency wireless transmission, but also maintain the air gap height.

[0049] For example, the difference between width w2 and width w1 can help maintain the structural stability of electrical contact 12 without affecting impedance matching performance. For example, the ratio of width w2 to width w1 can help maintain the structural stability of electrical contact 12 without affecting impedance matching performance.

[0050] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3EA cross-sectional view of a semiconductor device package in various manufacturing stages according to some embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of aspects of the present disclosure.

[0051] Refer to Figure 3A , a substrate strip including a substrate 11 is provided. The substrate 11 has a conductive pad 11c, and antenna layers 15 and 16 are disposed in the substrate 11. The antenna layer 15 has a surface 152 facing away from the substrate 11. A dielectric material is disposed on the substrate 11 in the form of a layer (or sub-layer) 14a to cover the surface 152 of the antenna layer 15. In some embodiments, the dielectric material can be formed by, for example, coating, lamination, or other suitable processes.

[0052] Refer to Figure 3B , the layer 14a can be partially removed (or patterned) through a photoresist film (or mask) to form an opening 14r1, and a part of the surface 152 of the antenna layer 15 can be exposed through the opening 14r1. The exposed portion of the antenna layer 15 can be the feeding area of the antenna layer 15. The opening 14r1 has a width w1.

[0053] Refer to Figure 3C , a dielectric material is disposed on the substrate 11 in the form of a layer (or sub-layer) 14b to cover the exposed portion of the surface 152 of the antenna layer 15. The layer 14b also covers the layer 14a. In some embodiments, the dielectric material can be formed by, for example, coating, lamination, or other suitable processes.

[0054] Refer to Figure 3D , the layer 14b can be partially removed or patterned through a photoresist film (or mask) to form an opening 14r2, and a part of the layer 14a is exposed through the opening 14r2. The opening 14r2 has a width w2. The width w2 is greater than the width w1. After patterning the layer 14b, the layer 14a and the layer 14b define a stepped structure.

[0055] The layer 14a and the layer 14b are partially removed or patterned through a photoresist film (or mask) to form an opening 14r3, and a part of the conductive pad 11c is exposed through the opening 14r3. The opening 14r3 has a width w3. In some embodiments, the width w3 can be greater than the width w1. In some embodiments, the width w3 can be substantially equal to the width w2.

[0056] In some embodiments, the layer 14a and the layer 14b can be partially removed in the same operation to define the opening 14r3.

[0057] Refer to Figure 3E , an electrical contact 12 is disposed on the substrate 11 to contact the exposed portion (or feeding area) of the antenna layer 15. An electrical contact 13 is disposed on the substrate 11 to contact the exposed portion of the conductive pad 11c.

[0058] Then, the structure in Figure 3E can be flipped and connected to the substrate 10 and the electronic component 18 shown in Figure 1 , and electrical connection can be obtained through the electrical contacts 12 and 13. A single cut can be performed to isolate individual semiconductor packaging devices such as Figure 1 shown. That is, the single cut is performed through a substrate strip including the substrate 11. The single cut can be performed, for example, by using a dicing saw, a laser, or other suitable cutting techniques. The final structure can be similar to the semiconductor device package 1 in Figure 1 .

[0059] As used herein, spatial relative terms such as "under", "below", "lower", "above", "upper", "left", "right", etc. may be used for ease of description to describe the relationship of one element or feature to another or other elements or features as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device when in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected to or coupled to the other element, or there may be intervening elements.

[0060] As used herein, the terms "about", "substantially", "essentially", and "approximately" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs nearly. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. Ranges herein may be expressed as one endpoint to another endpoint or between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified. The term "substantially coplanar" may refer to a positional difference between two surfaces positioned along the same plane within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm of being positioned along the same plane. When a numerical value or characteristic is referred to as being "substantially" the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of the value.

[0061] The foregoing has outlined the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure can be readily used as a basis for designing or modifying other processes and structures so as to facilitate the implementation of the same or similar purposes and / or achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device package, comprising: An antenna layer having a feeding area; And An insulating layer disposed on the antenna layer, the insulating layer having a first portion in contact with the antenna layer and a second portion on the first portion, wherein the first portion defines a first opening, the second portion defines a second opening above the first opening, and the width of the first opening is smaller than the width of the second opening; And A solder material disposed on the feeding area of the antenna layer, Wherein the first portion and the second portion of the insulating layer define a stepped structure exposing the feeding area of the antenna layer, and the solder material covers the stepped structure.

2. The semiconductor device package according to claim 1, wherein the first portion of the insulating layer has an upper surface and a side surface substantially perpendicular to the upper surface of the first portion, wherein the second portion of the insulating layer has an upper surface and a side surface substantially perpendicular to the upper surface of the second portion, and wherein the upper surface and the side surface of the first portion and the side surface of the second portion define the stepped structure.

3. The semiconductor device package according to claim 2, wherein the side surface of the first portion of the insulating layer is connected to the side surface of the second portion of the insulating layer through the upper surface of the first portion of the insulating layer.

4. The semiconductor device package according to claim 1, wherein the first portion of the insulating layer is partially exposed from the second portion of the insulating layer.

5. The semiconductor device package according to claim 1, wherein the difference between the width of the first opening and the width of the second opening is greater than 30 micrometers (μm).

6. The semiconductor device package according to claim 1, wherein the ratio of the width of the second opening to the width of the first opening is from 1.2 to 2.

4.

7. A semiconductor device package, comprising: A first antenna layer having a feeding area; And An insulating layer disposed on the first antenna layer, the insulating layer defining a first opening for exposing the feeding area of the first antenna layer and a second opening above the first opening; And An electrical contact disposed on the feeding area of the antenna layer and covering the stepped structure formed by the first opening and the second opening, Wherein the ratio of the width of the second opening to the width of the first opening is from 1.2 to 2.4, and the first opening is closer to the feeding area than the second opening.

8. The semiconductor device package according to claim 7, wherein the insulating layer has a first side surface defining the first opening, a second side surface defining the second opening, and an upper surface substantially perpendicular to the first side surface and the second side surface.

9. The semiconductor device package according to claim 8, wherein the first side surface is connected to the second side surface through the upper surface.

10. The semiconductor device package according to claim 8, Wherein the electrical contact is in direct contact with the first side and the second side.

11. The semiconductor device package according to claim 10, wherein a difference between the width of the first opening and the width of the second opening is greater than 30 μm.

12. The semiconductor device package according to claim 7, wherein the insulating layer further defines a third opening and a fourth opening above the third opening, the third opening being adjacent to the feeding area and exposing a part of the first antenna layer.

13. The semiconductor device package according to claim 12, wherein a ratio of the width of the fourth opening to the width of the third opening is from 1.2 to 2.

4.

14. The semiconductor device package according to claim 12, wherein the width of the third opening is greater than the width of the first opening, and the width of the fourth opening is substantially equal to the width of the second opening.

15. The semiconductor device package according to claim 7, further comprising: a dielectric layer having a first surface and a second surface opposite to the first surface; and a second antenna layer disposed on the first surface, wherein the first antenna layer is disposed on the second surface.

16. The semiconductor device package according to claim 15, further comprising: a substrate disposed on the first antenna layer; and a solder layer connecting the substrate to the feeding area of the first antenna layer through the second opening and the first opening.

17. A method of manufacturing a semiconductor device package, the method comprising: providing an antenna layer having a feeding area; disposing an insulating layer on the antenna layer; and removing a part of the insulating layer to form a first opening exposing the feeding area and a second opening above the first opening, wherein the first opening is closer to the feeding area than the second opening, and the width of the first opening is smaller than the width of the second opening; and disposing an electrical contact on the feeding area of the antenna layer and covering the stepped structure formed by the first opening and the second opening with the electrical contact.

18. The method according to claim 17, wherein forming the first opening comprises: removing a part of the insulating layer to expose a part of the surface of the antenna layer.

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