Memory device and method of manufacturing the same

Abstract

This invention discloses a memory device and its manufacturing method. The memory device includes channel lines, word lines, a first switch, and a second switch. The memory cells in the memory array are defined at the intersection of the channel lines and word lines. The first switch is electrically connected to the channel lines. The second switch is electrically connected to the channel lines. The first switch is electrically connected between the second switch and the memory cells.

Description

Technical Field

[0001] This invention relates to a memory device and a method for manufacturing the same. Background Technology

[0002] In recent years, the size of semiconductor devices has been gradually shrinking. In semiconductor technology, improvements in feature size, speed, performance, density, and cost per unit of integrated circuit are all crucial goals. In practical applications, while shrinking device size, it is still necessary to maintain the electrical performance of the device to meet commercial requirements. Summary of the Invention

[0003] This invention relates to a memory device and a method for manufacturing the same.

[0004] According to one aspect of the present invention, a memory device is provided, comprising channel lines, word lines, a first switch, and a second switch. Memory cells in a memory array are defined at the intersections of the channel lines and word lines. The first switch is electrically connected to the channel lines. The second switch is electrically connected to the channel lines. The first switch is electrically connected between the second switch and the memory cells.

[0005] According to another aspect of the present invention, a method for manufacturing a memory device is provided. The manufacturing method includes the following steps: forming a stacked structure. The stacked structure includes a memory array stack and a stepped stack. Forming a pillar structure. The pillar structure passes through the memory array stack. Forming a first electrode layer. The first electrode layer is on the stacked structure. Forming an insulating layer on the first electrode layer. Forming a second electrode layer on the insulating layer. Forming a pillar element on the stepped stack and passing through the first electrode layer. Forming a pillar element on the pillar structure and passing through the first electrode layer and the second electrode layer.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0007] Figure 1 It illustrates a cross-sectional view of a memory device according to an embodiment.

[0008] Figure 2 Draw Figure 1 Circuit diagram of the memory device.

[0009] Figure 3 It illustrates a cross-sectional view of a memory device according to another embodiment.

[0010] Figure 4 Draw Figure 3 Circuit diagram of the memory device.

[0011] Figures 5 to 16 A method for manufacturing a memory device according to an embodiment is illustrated.

[0012] [Symbol Explanation]

[0013] 102: Layered structure

[0014] 102A: Memory Array Stack

[0015] 102B: Stepped stacking

[0016] 104: Electrode film

[0017] 106: Insulating film

[0018] 208: Insulating material film

[0019] 310: Column Structure

[0020] 312: Storage Material Membrane

[0021] 314: Channel membrane

[0022] 315: Insulating Post

[0023] 316: Epitaxial element

[0024] 318: Epitaxial components

[0025] 420, 420-1, 420-2, 420-3, 420-4, 420-5: Insulation layer

[0026] 421: First electrode layer

[0027] 422: Second electrode layer

[0028] 430: Electrode layer

[0029] 524: Insulating element

[0030] 626: Dielectric layer

[0031] 728: Column element

[0032] 728A: First column

[0033] 728B: Second column

[0034] 728C: Third column

[0035] 728D: Fourth column

[0036] 730: Dielectric element

[0037] 732: Channel element

[0038] 734: Dielectric post

[0039] 830: Dielectric element

[0040] 832: Channel element

[0041] 834: Dielectric post

[0042] 836: Column element

[0043] 836A: First column

[0044] 836B: Second column

[0045] 836C: Third column

[0046] 940: Metal wiring layer

[0047] 4212: First electrode layer

[0048] 4222: Second electrode layer

[0049] BL: Bitline

[0050] CE1, CE12, CE2, CE22, CE3: Control electrodes

[0051] CL, CL1, CL2: Channel lines

[0052] CT1, CT11, CT12, CT1K: First Switch

[0053] CT2, CT21, CT22, CT2K: Second Switch

[0054] CT3: The Third Switch

[0055] M: Storage unit

[0056] WL: Word Line

[0057] WT: Word Line Switch

[0058] SL: Source Line

[0059] 2002: Stacked Structure

[0060] 2002A: Memory Array Stack-up

[0061] 2002B: Stepped stacking

[0062] 2050: Insulating film

[0063] 2052: The Hole

[0064] 2054: Notch

[0065] 2056: Opening

[0066] 2058: Groove

[0067] 2060: Perforation Detailed Implementation

[0068] The following description uses some embodiments. It should be noted that this invention does not show all possible embodiments, and other embodiments not presented in this invention may also be applicable. Furthermore, the dimensions in the drawings are not drawn to scale with actual products. Therefore, the description and illustrations are for illustrative purposes only and are not intended to limit the scope of protection of this invention. Additionally, the descriptions in the embodiments, such as partial structures, process steps, and material applications, are for illustrative purposes only and are not intended to limit the scope of protection of this invention. The details of the steps and structures in the embodiments can be varied and modified according to the needs of actual application processes without departing from the spirit and scope of this invention. The following description uses the same / similar symbols to denote the same / similar elements.

[0069] Please refer to Figure 1 The diagram illustrates a cross-sectional view of a memory device according to one embodiment. The memory device may be a three-dimensional vertical channel NAND memory array.

[0070] The stacked structure 102 includes electrode films 104 and insulating films 106 that are staggered in the vertical direction Z. The stacked structure 102 includes a memory array stack 102A and a stepped stack 102B. An insulating material film 208 is on the stacked structure 102. Figure 1 The electrode film 104 shown has 5 layers, but the invention is not limited thereto. The electrode film 104 may have other numbers of layers, such as 38 layers.

[0071] The pillar structure 310 can pass through the stacked structure 102 and the insulating material film 208. The pillar structure 310 may include a storage material film 312, a channel film 314, and an insulating pillar 315. The storage material film 312 may have a tubular shape and be located between the channel film 314 and the stacked structure 102. The channel film 314 may have a tubular shape and be located between the insulating pillar 315 and the storage material film 312. The pillar structure 310 may include epitaxial elements 316 and 318 on opposite sides of the channel film 314 in the vertical direction Z. The pillar structure 310 may be in the memory array stack 102A, and the memory cell M may be defined at the intersection of the channel film 314 and the electrode film 104 (e.g., an intermediate layer between the second and fifth layers) of this pillar structure 310. The pillar structure 310 may be located in a stepped stack 102B, and this pillar structure 310 may be electrically floating and considered as a dummy pillar structure.

[0072] Insulating layer 420 and electrode layer 423 may be disposed on insulating material film 208. Insulating layer 420 may include insulating layer 420-1, insulating layer 420-2, and insulating layer 420-3. Electrode layer 423 includes first electrode layer 421 and second electrode layer 422. Insulating layer 420-1 may be on insulating material film 208. First electrode layer 421 may be on insulating layer 420-1. Insulating layer 420-2 may be on first electrode layer 421. Second electrode layer 422 may be on insulating layer 420-2. Insulating layer 420-3 may be on second electrode layer 422. First electrode layer 421 is located between second electrode layer 422 and electrode film 104. Insulating element 524 may be located on the upper surface of first electrode layer 421, the sidewall surface of second electrode layer 422, and the sidewall surface of insulating layer 420-3. Dielectric layer 626 may be located on insulating element 524.

[0073] Pillar element 728 is located on the stepped stack 102B of the stacked structure 102 and electrically connected to the electrode film 104. Pillar element 728 may include a first pillar portion 728A, a second pillar portion 728B, a third pillar portion 728C, and a fourth pillar portion 728D arranged sequentially from bottom to top. The first pillar portion 728A extends vertically through the insulating material film 208 and lands on the electrode film 104. The second pillar portion 728B passes through the first electrode layer 421 and the insulating layer 420-1 below the first electrode layer 421. The second pillar portion 728B may extend into the lower portion of the insulating element 524. The second pillar portion 728B is located between the first pillar portion 728A and the third pillar portion 728C. The second pillar portion 728B may include a dielectric element 730, a channel element 732, and a dielectric pillar 734. The dielectric element 730 is located between the channel element 732 and the first electrode layer 421. Channel element 732 is located between dielectric pillar 734 and dielectric element 730. The channel element 732 and dielectric element 730 of the second pillar portion 728B may have a tubular shape. Pillar element 728 is electrically insulated from the first electrode layer 421 by dielectric element 730. Third pillar portion 728C may be located in insulating element 524 on the sidewall surface of the second electrode layer 422. Third pillar portion 728C may include dielectric element 730 and channel element 732. Dielectric element 730 may be located between channel element 732 and insulating element 524. The channel elements 732 of the first pillar portion 728A, the second pillar portion 728B, the third pillar portion 728C, and the fourth pillar portion 728D may be electrically connected to each other. In one embodiment, the first pillar portion 728A and the fourth pillar portion 728D include a barrier film and a metal film. The barrier film may include titanium nitride. The metal film may include tungsten. The channel element 732 of the second pillar 728B comprises undoped polysilicon. The channel element 732 of the third pillar 728C comprises doped polysilicon, such as heavily doped N-type impurity polysilicon. Therefore, the electrical conductivity of the first pillar 728A and the fourth pillar 728D is greater than that of the channel element 732 of the third pillar 728C, and the electrical conductivity of the channel element 732 of the third pillar 728C is greater than that of the channel element 732 of the second pillar 728B. However, the present invention is not limited thereto.

[0074] The pillar element 836 is on the memory array stack 102A of the stack structure 102. The pillar element 836 may include a first pillar portion 836A, a second pillar portion 836B and a third pillar portion 836C arranged sequentially from bottom to top.

[0075] The first pillar portion 836A can pass through the first electrode layer 421 and the insulating layer 420-1 below the first electrode layer 421, and can extend into the lower portion of the insulating layer 420-2 between the first electrode layer 421 and the second electrode layer 422. The second pillar portion 836B can pass through the second electrode layer 422 and the insulating layer 420-3 above the second electrode layer 422, and can extend into the upper portion of the insulating layer 420-2 between the first electrode layer 421 and the second electrode layer 422. The first pillar portion 836A and the second pillar portion 836B may include a dielectric element 830, a channel element 832, and a dielectric pillar 834. The channel element 832 is located between the dielectric element 830 and the dielectric pillar 834. The dielectric element 830 may have a tubular shape. The pillar element can be electrically insulated from the first electrode layer 421 and the second electrode layer 422 through the dielectric element 830.

[0076] In one embodiment, the channel element 832 of the first pillar 836A and the second pillar 836B comprises undoped polysilicon and may have a tubular shape. The top portion of the channel element 832 of the second pillar 836B may comprise doped polysilicon, such as N-type heavily doped polysilicon. The third pillar 836C may comprise a barrier film and a metal film on the barrier film. The barrier film may comprise titanium nitride. The metal film may comprise tungsten. However, the invention is not limited thereto. An epitaxial element 318 is electrically connected between the channel element 832 and the channel film 314.

[0077] Metal wiring layer 940 may be on dielectric layer 626.

[0078] Please refer to Figure 2 Its illustration Figure 1 Circuit diagram of the memory device.

[0079] The memory cell M in a NAND flash memory array is defined at the intersection of the channel line CL (including channel lines CL1 and CL2) and the word line WL. The channel line CL may include, for example,... Figure 1 The pillar structure 310 shown includes a channel membrane 314, epitaxial elements 316 and 318, and a channel element 832 and a third pillar 836C of the first pillar portion 836A and the second pillar portion 836B of the pillar element 836. The word line WL may include, for example... Figure 1 The electrode films 104 of the second to fourth layers are shown. The word line WL may also include, for example... Figure 1 The channel element 732 of the first column portion 728A, the second column portion 728B and the third column portion 728C of the column element 728 shown, and the fourth column portion 728D.

[0080] The first switch CT1, the second switch CT2, and the third switch CT3 are electrically connected to the channel line CL. The first switch CT1 is electrically connected between the second switch CT2 and the memory cell M. The second switch CT2 is electrically connected between the bit line BL and the first switch CT1. The third switch CT3 is electrically connected between the source line SL and the memory cell M. The first switch CT1 can be referred to as the first channel switch. The second switch CT2 can be referred to as the second channel switch. The first switch CT1 and the second switch CT2 can function as serial selection switches. The third switch CT3 can be used as a ground selection switch.

[0081] The first switch CT1 can be a transistor switch, including, for example... Figure 1 The first electrode layer 421 and the first pillar portion 836A of the pillar element 836 are shown as channel element 832 and dielectric element 830. The first electrode layer 421 and dielectric element 830 are respectively used as the control gate electrode (control electrode CE1) and gate dielectric of the transistor.

[0082] The second switch CT2 can be a transistor switch, including, for example... Figure 1 The second electrode layer 422 and the second pillar portion 836B of the pillar element 836 are shown as channel element 832 and dielectric element 830. The second electrode layer 422 and dielectric element 830 are respectively used as the control gate electrode (control electrode CE2) and gate dielectric of the transistor.

[0083] The word line switch WT is electrically connected to the word line WL. The word line switch WT can be electrically connected between the word line decoder (not shown) and the memory cell M. The word line switch WT can be a transistor switch, including... Figure 1 The first electrode layer 421 and the second pillar portion 728B are shown, along with the channel element 732 and the dielectric element 730. The first electrode layer 421 and the dielectric element 730 are respectively used as the control gate electrode (control electrode CE1) and the gate dielectric of the transistor.

[0084] In one embodiment, the dielectric elements 730 and 830 used as gate dielectrics are single-layer oxide layers, such as silicon oxide layers. Compared to multilayer storage material films, the dielectric elements 730 and 830 in this embodiment can have a thinner thickness. Therefore, the transistor can have a lower operating voltage and a faster operating speed. In addition, operations similar to those of the memory cell M, such as programming and erasing, can be avoided.

[0085] The first switch CT1 may include first switches CT11 and CT12 corresponding to the NAND memory serial group. The first switches CT11, CT12, and word line switch WT share a common control electrode CE1, and therefore can be simultaneously turned off or on by supplying a shared voltage to the control electrode CE1 during the operation of the memory device. No additional decoding circuitry is required for the word line switch WT. The control electrode CE1 may include, for example... Figure 1 The first electrode layer 421 shown can function as a serial select line for the NAND memory serial array and as a word line select line for the word line WL. The second switch CT2 may include second switches CT21 and CT22 corresponding to the NAND memory serial array. The second switches CT21 and CT22 may include a shared control electrode CE2, thus allowing them to be simultaneously turned off or on during the operation of the memory device. The control electrode CE2 may include, for example... Figure 1 The second electrode layer 422 shown can function as a serial selection line. Control electrode CE1 and control electrode CE2 can be controlled independently.

[0086] The third switch CT3 can be a transistor switch, which can be derived from, for example... Figure 1 The electrode film 104 of the first layer (or bottom layer) shown is defined with the storage material film 312 and the channel film 314 of the pillar structure 310. The electrode film 104 and the storage material film 312 of the first layer are used as the control gate electrode (control electrode CE3) and the gate dielectric of the transistor, respectively.

[0087] In the embodiments, the operation methods of the memory device include operation procedures such as reading, programming, or erasing procedures.

[0088] The reading procedure includes activating the control electrode CE1 corresponding to the first switch CT1 and the word line switch WT, and activating the control electrode CE2 corresponding to the second switch CT2. Additionally, it activates the selected word line WL and sets the pass voltage (V) for the unselected word line WL. pass voltage).

[0089] The programming procedure includes activating the control electrode CE1 corresponding to the first switch CT1 and the word line switch WT, and activating the control electrode CE2 corresponding to the second switch CT2. Additionally, it activates the selected word line WL and applies a pass voltage to the unselected word line WL.

[0090] The erasure procedure includes activating the control electrode CE1 corresponding to the first switch CT1 and the word line switch WT to activate the selected word line WL. It also activates the control electrode CE3 (first-layer electrode film 104) corresponding to the third switch CT3. Furthermore, it deactivates the control electrode CE2 corresponding to the second switch CT2 to block signals from the bit line BL. In this embodiment, a single string or block erasure can be performed. For a single string erasure, only one control electrode CE1 is activated. For a block erasure, all relevant control electrodes CE1 are activated. In this embodiment, the word line WL can be controlled to be on or off using the word line switch WT. Therefore, only the selected transistors are charged, while the remaining unselected transistors are not charged. This reduces the overall word line capacitance.

[0091] The memory device and its operation method of the present invention are not limited to the above embodiments and can be modified.

[0092] For example, the number of the first switch CT1, the second switch CT2, and the word line switch WT can be one or more independently, such as two, three, or other quantities.

[0093] Please refer to Figure 3 The diagram illustrates a cross-sectional view of a memory device according to another embodiment. Figure 3 memory devices and Figure 1 The differences in the memory device are explained below. Insulating layer 420 further includes insulating layers 420-4 and 420-5. Electrode layer 423 further includes a first electrode layer 4212 and a second electrode layer 4222. Insulating layer 420-4 may be on the first electrode layer 421. First electrode layer 4212 may be on insulating layer 420-4. Insulating layer 420-2 may be on the first electrode layer 4212. Insulating layer 420-5 may be on the second electrode layer 422. Second electrode layer 4222 may be on insulating layer 420-5. Insulating layer 420-3 may be on the second electrode layer 4222. The second pillar portion 728B of pillar element 728 may further penetrate insulating layer 420-4 and the first electrode layer 4212. The first pillar portion 836A of pillar element 836 may further penetrate insulating layer 420-4 and the first electrode layer 4212. The second pillar portion 836B of the pillar element 836 can further penetrate the insulating layer 420-5 and the second electrode layer 4222. The insulating element 524 is also located on the sidewall surface of the insulating layer 420-5 and the sidewall surface of the second electrode layer 4222.

[0094] Please refer to Figure 4 , it is Figure 3 Circuit diagram of the memory device. Figure 4 memory devices and Figure 2The differences in the memory device are described below. The memory device also includes a first switch CT1K, electrically connected in series between the first switch CT1 and the second switch CT2. The memory device also includes a second switch CT2K. The second switch CT2 is electrically connected in series between the first switch CT1K and the second switch CT2K. The second switch CT2K may include, for example... Figure 3 The second electrode layer 4222 is shown. The memory device also includes a word line switch WT1, electrically connected between the word line switch WT1 and a word line decoder (not shown). The first switch CT1K and the word line switch WT1 share a control electrode CE12. The control electrode CE12 may include, for example... Figure 3 The first electrode layer 4212 is shown. The first switches CT1K corresponding to different NAND memory arrays include a shared control electrode CE22. The control electrode CE22 may include, for example... Figure 3 The second electrode layer 4222 is shown.

[0095] The reading procedure includes activating the control electrode CE1 corresponding to the first switch CT1 and the word line switch WT, activating the control electrode CE12 corresponding to the first switch CT1K and the word line switch WT1, activating the control electrode CE2 corresponding to the second switch CT2, and activating the control electrode CE22 corresponding to the second switch CT2K. Additionally, it activates the selected word line WL and the pass voltage for the unselected word lines WL.

[0096] The programming procedure includes activating the control electrode CE1 corresponding to the first switch CT1 and the word line switch WT, activating the control electrode CE12 corresponding to the first switch CT1K and the word line switch WT1, activating the control electrode CE2 corresponding to the second switch CT2, and activating the control electrode CE22 corresponding to the second switch CT2K. Additionally, it activates the selected word line WL and the pass voltage for the unselected word line WL.

[0097] The erase procedure includes activating the control electrode CE1 corresponding to the first switch CT1 and the word line switch WT, and activating the control electrode CE12 corresponding to the first switch CT1K and the word line switch WT1 to activate the selected word line WL. The control electrode CE3 (the electrode film 104 of the first layer) corresponding to the third switch CT3 is also activated. Furthermore, the control electrodes CE2 and CE22 corresponding to the second switches CT2 and CT2K, respectively, are deactivated to block signals from the bit line BL. In this embodiment, using a circuit with multiple switches (in this example, two first switches and two second switches) avoids the negative impact of the erase procedure on the circuit due to the high bias voltage (floating bit line bias) of the bit line BL.

[0098] In one embodiment, control electrode CE1 and control electrode CE12 can be a shared electrode. Therefore, in the operating program of the memory device, a shutdown or on operation can be performed simultaneously by supplying a shared voltage to control electrode CE1 and control electrode CE12. Control electrode CE2 and control electrode CE22 can also be a shared electrode. Therefore, in the operating program of the memory device, a shutdown or on operation can be performed simultaneously by supplying a shared voltage to control electrode CE2 and control electrode CE22. However, the present invention is not limited thereto. Control electrodes CE1, CE12, CE2, and CE22 can also operate independently.

[0099] In one embodiment, the third switch CT3 corresponding to different NAND memory serial lines can be controlled independently.

[0100] Figures 5 to 16 A method for manufacturing a memory device according to an embodiment is illustrated.

[0101] Please refer to Figure 5 An insulating film 106 (first insulating film) and an insulating film 2050 (second insulating film) may be interleaved and stacked on a substrate (not shown). The substrate may include, for example, a silicon substrate or other suitable semiconductor material. The insulating film 106 and the insulating film 2050 may use different insulating materials. In one embodiment, the insulating film 106 comprises an oxide, such as silicon oxide. The insulating film 2050 comprises a nitride, such as silicon nitride. However, the invention is not limited thereto. The insulating film 106 and the insulating film 2050 may be patterned using a photolithography etching process to form a stacked structure 2002 including a memory array stack 2002A and a stepped stack 2002B.

[0102] Please refer to Figure 6 An insulating material film 208 can be formed on the stacked structure 2002. In one embodiment, the insulating material film 208 comprises an oxide, such as silicon oxide. However, the invention is not limited thereto. Other suitable insulating materials can be used for the insulating material film 208. The insulating material film 208 can be planarized using methods such as chemical mechanical polishing. Holes 2052 can be formed in the stacked structure 2002 using photolithography etching processes.

[0103] Please refer to Figure 7An epitaxial process can be performed to form an epitaxial element 316 on the substrate (not shown) exposed by the via 2052. A storage material film 312 can be formed on the upper surface of the epitaxial element 316 exposed by the via 2052 and on the sidewall surface of the stacked structure 2002. In one embodiment, the storage material film 312 may include any charge-trapping structure, such as an oxide-nitride-oxide (ONO) structure, an ONONO structure, an ONONO-ONO structure, or an oxide-nitride-oxide-nitride-oxide (BE-SONOS) structure, etc. For example, the charge-trapping layer may use nitrides such as silicon nitride, or other similar high-dielectric-constant materials including metal oxides, such as aluminum oxide (Al2O3), zirconium oxide (HfO2), etc. A channel film 314 can be formed on the sidewall surface of the storage material film 312. The channel film 314 may have a tubular shape, and insulating pillars 315 may be formed to fill the hollow cavity of the channel film 314. An epitaxial process can be performed to form an epitaxial element 318 on the upper surface of the channel film 314, thereby forming a pillar structure 310. In one embodiment, the epitaxial elements 316 and 318 may comprise doped polysilicon, such as heavily doped N-type impurity polysilicon.

[0104] Please refer to Figure 8 The removable insulating film 2050 forms a notch 2054. The pillar structure 310 serves as a support for the semiconductor structure, preventing collapse. In one embodiment, a slit (not shown) extending in the X and Y directions can be formed through the stacked structure 2002 using photolithography etching to expose the sidewall surfaces of the insulating film 106 and the insulating film 2050. Then, the insulating film 2050 is removed using a selective etching process (e.g., wet etching), leaving the insulating film 106.

[0105] Please refer to Figure 9 An electrode film 104 can be formed to fill the notch 2054. This forms a stacked structure 102 including a memory array stack 102A and a stepped stack 102B. The electrode film 104 may include a barrier film and a metal film formed on the barrier film. The barrier film may include titanium nitride. The metal film may include tungsten. However, the invention is not limited thereto.

[0106] Please refer to Figure 10 An opening 2056 can be formed to expose the upper surface of the electrode film 104 using photolithography etching. The opening 2056 can be filled with a conductive material to form a first pillar 728A. In one embodiment, the first pillar 728A may include a barrier film and a metal film formed on the barrier film. The barrier film may include titanium nitride. The metal film may include tungsten. However, the invention is not limited thereto. The conductive material can be planarized using methods such as chemical mechanical polishing.

[0107] Please refer to Figure 11An interleaved insulating layer 420 and electrode layer 423 can be formed on an insulating material film 208 using a deposition process. The insulating layer 420 may include insulating layers 420-1, 420-2, and 420-3. The electrode layer 423 includes a first electrode layer 421 and a second electrode layer 422. Insulating layer 420-1 may be formed on the insulating material film 208. The first electrode layer 421 may be formed on insulating layer 420-1. Insulating layer 420-2 may be formed on the first electrode layer 421. The second electrode layer 422 may be formed on insulating layer 420-2. Insulating layer 420-3 may be formed on the second electrode layer 422. The insulating layer 420 may include oxides such as silicon oxide, or other suitable insulating materials. The electrode layer 423 may include suitable conductive materials such as metals.

[0108] Please refer to Figure 12 The second electrode layer 422 and the portion of the insulating layer 420-3 above it corresponding to the stepped stack 102B can be removed using photolithography etching to form the groove 2058.

[0109] Please refer to Figure 13 An insulating material can be deposited in the groove 2058 to form an insulating element 524. The insulating element 524 may include oxides such as silicon oxide. However, the invention is not limited thereto. The insulating material can be planarized using methods such as chemical mechanical polishing.

[0110] Please refer to Figure 14 The via 2060 can be formed using photolithography etching. The via 2060 can expose the epitaxial element 318 of the pillar structure 310 in the memory array stack 102A. Alternatively, the via 2060 can expose the first pillar portion 728A on the stepped stack 102B. In one embodiment, the etching process uses a metal film (e.g., tungsten) of the epitaxial element 318 and the first pillar portion 728A as an etching stop layer.

[0111] Please refer to Figure 15A gate dielectric can be deposited in the via 2060, and anisotropic etching is performed on the gate dielectric to remove the bottom portion to form dielectric elements 730 and 830 with tubular shapes. The gate dielectric may include oxides such as silicon oxide, or other suitable dielectric materials. Channel elements 732 and 832 can be deposited on the sidewall surfaces of dielectric elements 730 and 830, respectively. Channel elements 732 and 832 may, for example, comprise undoped polysilicon. Dielectric pillars 734 and 834 can be deposited to fill the via 2060. Dielectric pillars 734 and 834 may include oxides such as silicon oxide, or other suitable dielectric materials. The top portions of channel elements 732 and 832 may be doped, so the material may include doped channel materials, such as heavily doped N-type impurity polysilicon. This forms a first pillar 836A and a second pillar 728B.

[0112] Please refer to Figure 16 The top portion of the channel element 732 on the stepped stack 102B can be deeply doped to increase the size of the doped channel material (e.g., heavily doped N-type polysilicon) in the vertical Z direction. This allows the formation of the third pillar 728C.

[0113] Please refer to Figure 1 A dielectric layer 626 can be formed using a deposition method. A metal wiring layer 940 can be formed on the dielectric layer 626.

[0114] The memory device and its manufacturing method of the present invention are not limited to the above embodiments and can be modified.

[0115] For example, in one embodiment, the substrate may use a bottom source line, such as a heavily doped N-type impurity bottom source line, and the memory device may omit features such as... Figure 1 or Figure 3 The epitaxial element 316 and the P-type doped well are shown. In one embodiment, the reference may be omitted. Figure 16 The process steps described above.

[0116] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A memory device, wherein, include: One channel line; Multiple word lines, wherein multiple memory cells of a memory serial array are defined at the intersection of the channel line and these word lines; A first switch is electrically connected to the channel line; A second switch is electrically connected to the channel line, wherein the first switch is electrically connected between the second switch and the memory cells; Multiple word line switches, each electrically connected to one of the word lines; and The first switch shares control electrodes with these word line switches.

2. The memory device according to claim 1, wherein, It also includes a bit line, and the second switch is electrically connected between the bit line and the first switch.

3. The memory device according to claim 1, wherein, Also includes: Another channel line, wherein a plurality of other memory cells of another memory array are defined at the intersection of the other channel line and these word lines; Another first switch is electrically connected to the other channel line; and Another second switch is electrically connected to the other channel line, wherein the other first switch is electrically connected between the other second switch and these other storage cells.

4. The memory device according to claim 1, wherein, It also includes a third switch electrically connected to the channel line, wherein the memory cells are electrically connected between the first switch and the third switch.

5. The memory device according to claim 1, wherein, It also includes multiple insulating films and an insulating layer, wherein each of these word lines includes an electrode film, the first switch includes a first electrode layer, the second switch includes a second electrode layer, the first electrode layer is between the second electrode layer and these electrode films, the electrode films and these insulating films are stacked alternately, and the first electrode layer and the second electrode layer are separated from each other by the insulating layer.

6. A method for manufacturing a memory device based on any one of claims 1-5, wherein, include: A stacked structure is formed, wherein the stacked structure includes a memory array stack and a ladder-like stack; A pillar structure is formed, wherein the pillar structure passes through the memory array stack; A first electrode layer is formed on the stacked structure; An insulating layer is formed on the first electrode layer; A second electrode layer is formed on the insulating layer; A pillar element is formed on the stepped stack and passes through the first electrode layer; and A pillar element is formed on the pillar structure and passes through the first electrode layer and the second electrode layer.

7. The method of manufacturing a memory device according to claim 6, wherein, It also includes forming an insulating element, wherein the insulating element is on an upper surface of the first electrode layer and on a side wall surface of the second electrode layer, and the pillar element passes through the insulating element.

8. The method of manufacturing a memory device according to claim 7, wherein, include: The second electrode layer is formed on the insulating layer on the memory array stack and the stepped stack; Forming a groove involves removing a portion of the second electrode layer from the stepped stack. and The insulating element is formed in the groove.

9. The method of manufacturing a memory device according to claim 7, wherein, include: A perforation is formed in the insulating element, the insulating layer, and the first electrode layer; and The column element is formed in the perforation.

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