Display device and manufacturing method thereof

Abstract

The present invention discloses a display device and a method for manufacturing the same. The display device includes: a main display area; a component area including a transmissive area; a peripheral area adjacent to the main display area; a substrate; a main display element disposed on a first surface of the substrate in the main display area, wherein main pixel circuits are respectively connected to the main display element; auxiliary display elements disposed on a first surface of the substrate in the component area, wherein auxiliary pixel circuits are respectively connected to the auxiliary display elements; a bottom metal layer disposed in the component area between the substrate and the auxiliary pixel circuits; and an anti-reflection layer disposed on a second surface of the substrate opposite to the first surface and overlapping the bottom metal layer in the component area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0016638, filed on February 11, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments of the present invention relate to a display device and a method of manufacturing the same, and more particularly, to a display device having improved reliability and a method of manufacturing the same. Background Art

[0004] Generally, display devices are used for various purposes. In addition, as display devices have become thinner and lighter, their scope of use has increased.

[0005] Since the display device is being used in various ways, the shape of the display device may be designed using various methods, and furthermore, more functions may be combined or associated with the display device. Summary of the Invention

[0006] According to an exemplary embodiment of the present invention, a display device includes: a main display area; a component area including a transmissive area; a peripheral area adjacent to the main display area; a substrate; a main display element arranged on a first surface of the substrate in the main display area, wherein the main pixel circuits are respectively connected to the main display elements; an auxiliary display element arranged on a first surface of the substrate in the component area, wherein the auxiliary pixel circuits are respectively connected to the auxiliary display elements; a bottom metal layer arranged between the substrate and the auxiliary pixel circuits in the component area; and an anti-reflection layer arranged on a second surface of the substrate opposite to the first surface and overlapping with the bottom metal layer in the component area.

[0007] In an exemplary embodiment of the present invention, the anti-reflection layer is directly disposed on the second surface of the substrate.

[0008] In an exemplary embodiment of the present invention, the anti-reflection layer has a first thickness of about 1 μm to about 3 μm.

[0009] In an exemplary embodiment of the present invention, the anti-reflection layer includes a positive photosensitive material.

[0010] In an exemplary embodiment of the present invention, the anti-reflection layer includes a light-shielding material.

[0011] In an exemplary embodiment of the present invention, the bottom metal layer includes a first hole corresponding to the transmission area.

[0012] In an exemplary embodiment of the present invention, the anti-reflection layer includes a second hole corresponding to the transmission area.

[0013] In an exemplary embodiment of the present invention, the first hole and the second hole overlap each other.

[0014] In an exemplary embodiment of the present invention, the display device further includes an encapsulation substrate disposed on the first surface of the substrate.

[0015] In an exemplary embodiment of the present invention, the display apparatus further includes a component arranged on the second surface of the substrate in the component area, wherein the component includes an imaging device or a sensor.

[0016] In an exemplary embodiment of the present invention, the display device further includes a protection member disposed on the second surface of the substrate in the main display area.

[0017] According to an exemplary embodiment of the present invention, a method for manufacturing a display device includes: forming a bottom metal layer on a first surface of a substrate and in a component area of ​​the substrate; forming an encapsulation substrate on the first surface of the substrate; forming a colored material layer on a second surface of the substrate opposite to the first surface in the component area; exposing a portion of the colored material layer by irradiating light onto the first surface of the substrate on which the bottom metal layer is arranged; and forming an anti-reflection layer by developing the exposed portion of the colored material layer.

[0018] In an exemplary embodiment of the present invention, in forming the colored material layer, the colored material layer is directly formed on the second surface of the substrate.

[0019] In an exemplary embodiment of the present invention, in forming the colored material layer, the colored material layer includes a positive photosensitive material.

[0020] In an exemplary embodiment of the present invention, in exposing a portion of the colored material layer, the colored material layer is exposed by using the bottom metal layer as a mask.

[0021] In an exemplary embodiment of the present invention, the anti-reflection layer is formed to overlap with the bottom metal layer.

[0022] In an exemplary embodiment of the present invention, the anti-reflection layer has a first thickness of about 1 μm to about 3 μm.

[0023] In an exemplary embodiment of the present invention, the bottom metal layer includes a first hole corresponding to the transmission area of ​​the substrate, wherein the anti-reflection layer includes a second hole corresponding to the transmission area, and the first hole and the second hole overlap each other.

[0024] In an exemplary embodiment of the present invention, the method further includes: between forming the bottom metal layer and forming the packaging substrate, forming a first thin film transistor and a first display element in the main display area of ​​the substrate, and forming a second thin film transistor and a second display element on the bottom metal layer in the component area.

[0025] In an exemplary embodiment of the present invention, the method further includes forming a protection member on the second surface of the substrate in the main display area after forming the anti-reflection layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0027] Figure 1 is a perspective view schematically showing a display device according to an exemplary embodiment of the present invention;

[0028] Figure 2 is a cross-sectional view schematically illustrating a display device according to an exemplary embodiment of the present invention;

[0029] Figure 3 is a plan view schematically showing a display device according to an exemplary embodiment of the present invention;

[0030] Figure 4 and Figure 5 is a circuit diagram of a pixel that may be included in a display device according to an exemplary embodiment of the present invention;

[0031] Figure 6 is a cross-sectional view schematically illustrating a display device according to an exemplary embodiment of the present invention; and

[0032] Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 and Figure 13 is a cross-sectional view schematically illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0033] Exemplary embodiments of the present invention will now be described more fully with reference to the accompanying drawings. It should be understood that the present invention can be embodied in different forms and therefore should not be construed as being limited to the exemplary embodiments set forth herein. It should be understood that throughout the specification, the same reference numerals may refer to the same elements and therefore redundant descriptions may be omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0034] It will be understood that although terms such as "first" and "second" may be used herein to describe various components, these components should not be limited by these terms, and these terms are only used to distinguish one component from another. Thus, the first component discussed below could be referred to as the second component without departing from the spirit and scope of the present invention.

[0035] It will be understood that when a layer, region or component is referred to as being “on” another layer, region or component, it can be “directly on” the other layer, region or component, or can be “indirectly on” the other layer, region or component with one or more intervening layers, regions or components.

[0036] For the sake of clarity, the size of the components in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings may be exaggerated for the sake of clarity, the present invention is not limited thereto.

[0037] As used herein, "A and / or B" represents the presence of A, B, or both.

[0038] It will be understood that the meaning of a line "extending in the first direction or the second direction" may include not only extending in a straight shape along the first direction or the second direction but also extending in a zigzag or curved shape.

[0039] It will be understood that when referred to as “in a plan view”, it may mean observing the target portion from above, and when referred to as “in a cross-sectional view”, it may mean observing a cross section of the target portion cut vertically from the side.

[0040] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 is a perspective view schematically illustrating a display device according to an exemplary embodiment of the present invention.

[0042] refer to Figure 1The display device 1 may include a display area DA and a peripheral area DPA outside the display area DA. The display area DA may include a component area CA and a main display area MDA at least partially surrounding the component area CA. For example, the substrate of the display device 1 (eg, Figure 3 The display device 100 may include a peripheral area DPA, an assembly area CA, and a main display area MDA. For example, the assembly area CA and the main display area MDA may display images individually or together. The peripheral area DPA may be a non-display area in which no display elements are arranged. The display area DA may be at least partially surrounded by the peripheral area DPA. For example, the display area DA may be completely surrounded by the peripheral area DPA.

[0043] Figure 1 It is shown that one component area CA is located in the main display area MDA. In an exemplary embodiment of the present invention, the display device 1 may include two or more component areas CA, and the shapes and sizes of the component areas CA may be different from each other. When viewed in a direction substantially perpendicular to the top surface of the display device 1, the component area CA may have various shapes, such as a circular shape, an elliptical shape, a polygonal shape such as a quadrilateral shape, a star shape, or a diamond shape. In addition, Figure 1 The component area CA is shown as being arranged in the upper center (in the +y direction) of the substantially rectangular main display area MDA when viewed in a direction substantially perpendicular to the top surface of the display device 1. However, the component area CA may be arranged on one side of the rectangular main display area MDA, for example, on the upper right or upper left side thereof. For example, the component area CA is closer to the upper side of the main display area MDA than to the lower side of the main display area MDA.

[0044] The display device 1 may provide an image by using a plurality of main sub-pixels Pm arranged in the main display area MDA and a plurality of auxiliary sub-pixels Pa arranged in the component area CA.

[0045] As referenced below Figure 2As described, in component area CA, components 40, such as electronic components, may be arranged below substrate 100 to correspond to component area CA. For example, component 40 may include an imaging device, such as a camera using infrared light or visible light. Furthermore, component 40 may include a solar cell, a flash, or a sensor such as an illumination sensor, a proximity sensor, and an iris sensor. Furthermore, component 40 may have a function of receiving sound. For example, component 40 may be a speaker and / or a microphone. To minimize restrictions on the functionality of component 40, component area CA may include a transmissive area TA that transmits light and / or sound output from component 40 to the outside or propagating from the outside toward component 40. In the case of a display device 1 according to an exemplary embodiment of the present invention, when light passes through component area CA, its transmittance may be approximately 10% or greater, for example, approximately 40% or greater, approximately 25% or greater, approximately 50% or greater, approximately 85% or greater, or approximately 90% or greater.

[0046] A plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. The plurality of auxiliary sub-pixels Pa may provide a predetermined image by emitting light. The image displayed in the component area CA may be an auxiliary image and may have a lower resolution than the image displayed in the main display area MDA. For example, the component area CA may include a transmissive area TA through which light and sound can pass, and when no sub-pixels are arranged in the transmissive area TA, the number of auxiliary sub-pixels Pa that may be arranged per unit area in the component area CA may be less than the number of main sub-pixels Pm arranged per unit area in the main display area MDA.

[0047] Figure 2 is a cross-sectional view schematically illustrating a display device according to an exemplary embodiment of the present invention.

[0048] refer to Figure 2 The display device 1 may include a display panel 10 and a component 40 overlapping the display panel 10. A cover window for protecting the display panel 10 may be disposed above the display panel 10.

[0049] The display panel 10 may include an element area CA and a main display area MDA in which a main image is displayed. Furthermore, the element area CA may overlap with the element 40. The display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, an optical function layer OFL, and a protective member PB. The display layer DISL may be disposed on the substrate 100, and the protective member PB may be disposed below the substrate 100.

[0050] The display layer DISL may include a circuit layer PCL, a display element layer EDL, and an encapsulation member ENCM. The circuit layer PCL may include thin film transistors TFT and TFT', and the display element layer EDL may include light-emitting elements ED and ED', which may function as display elements. The encapsulation member ENCM may be an encapsulation substrate. Insulation layers IL and IL' may be disposed within the display layer DISL and between the substrate 100 and the display layer DISL, respectively.

[0051] The substrate 100 may include an insulating material such as glass, quartz, or polymer resin. The substrate 100 may include a rigid substrate or a flexible substrate that can be bent, folded, or rolled.

[0052] The main thin film transistor TFT and the main light emitting element ED connected to the main thin film transistor TFT may be arranged in the main display area MDA of the display panel 10 to implement the main sub-pixel Pm, and the auxiliary thin film transistor TFT′ and the auxiliary light emitting element ED′ connected to the auxiliary thin film transistor TFT′ may be arranged in the component area CA to implement the auxiliary sub-pixel Pa. The region in the component area CA in which the auxiliary sub-pixel Pa is arranged may be referred to as an auxiliary display region.

[0053] In addition, a transmissive area TA in which no display element is arranged may be arranged in the component area CA. The transmissive area TA may be an area through which light / signals output from or input to the component 40 arranged corresponding to the component area CA pass. Auxiliary display areas and the transmissive area TA may be alternately arranged in the component area CA.

[0054] A bottom metal layer (BML) may be disposed in the component area (CA). The bottom metal layer (BML) may be disposed to correspond to the bottom of the auxiliary thin-film transistor (TFT'). For example, the bottom metal layer (BML) may be disposed between the auxiliary thin-film transistor (TFT') and the substrate 100. The bottom metal layer (BML) may block external light from reaching the auxiliary thin-film transistor (TFT'). In an exemplary embodiment of the present invention, a constant voltage or signal may be applied to the bottom metal layer (BML) to prevent damage to the pixel circuit due to electrostatic discharge.

[0055] The anti-reflection layer 200 may be disposed in the component area CA. The anti-reflection layer 200 may be disposed to correspond to the bottom metal layer BML. For example, the bottom metal layer BML and the anti-reflection layer 200 may be disposed to overlap each other, with the substrate 100 located therebetween. The anti-reflection layer 200 may prevent light emitted from the component 40 from being reflected by the bottom metal layer BML and causing light spots.

[0056] The display element layer EDL may be covered by an encapsulation member ENCM. For example, the encapsulation member ENCM may include an encapsulation substrate. For example, the encapsulation substrate may be arranged to face the substrate 100, with the display element layer EDL between the encapsulation substrate and the substrate 100. For example, there may be a gap between the encapsulation substrate and the display element layer EDL. The encapsulation substrate may include glass. A sealant including glass frit or the like may be arranged between the substrate 100 and the encapsulation substrate, and the sealant may be arranged in the above-mentioned peripheral area DPA. The sealant arranged in the peripheral area DPA may surround the display area DA to prevent moisture from penetrating its side surfaces.

[0057] The touch screen layer TSL may be configured to obtain coordinate information based on external input (e.g., a touch event). The touch screen layer TSL may include touch electrodes and touch lines connected to the touch electrodes. For example, the touch screen layer TSL may sense external input using a self-capacitance method or a mutual capacitance method.

[0058] The touch screen layer TSL may be disposed on the encapsulation member ENCM. Alternatively, the touch screen layer TSL may be formed separately on the touch substrate and then bonded to the encapsulation member ENCM via an adhesive layer such as an optically clear adhesive (OCA). In an exemplary embodiment of the present invention, the touch screen layer TSL may be formed directly on the encapsulation member ENCM, and in this case, no adhesive layer may be provided between the touch screen layer TSL and the encapsulation member ENCM.

[0059] In an exemplary embodiment of the present invention, the optical function layer OFL may include a polarizing film. The optical function layer OFL may include an opening OFL_OP corresponding to the component area CA. Therefore, the light transmittance of the transmissive area TA of the component area CA can be significantly improved. The opening OFL_OP may be filled with a transparent material, such as an optically clear resin (OCR).

[0060] In an exemplary embodiment of the present invention, the optical function layer OFL may be provided as a color filter including a black matrix and a color filter.

[0061] A cover window may be disposed over the display panel 10 to protect the display panel 10. The optical functional layer OFL may be attached to the cover window with an optically transparent adhesive, or may be attached to the touch screen layer TSL with an optically transparent adhesive.

[0062] A protective member PB may be attached below the substrate 100 to support and protect the substrate 100. The protective member PB may include an opening PB_OP corresponding to the component area CA. For example, the opening PB_OP may overlap the component area CA. The protective member PB including the opening PB_OP may improve light transmittance in the component area CA. The protective member PB may include polyethylene terephthalate (PET) or polyimide (PI).

[0063] The area of ​​the component area CA may be greater than that of the component 40. Therefore, the area of ​​the opening PB_OP included in the protection member PB may not match that of the component 40. For example, the area of ​​the opening PB_OP may be greater than that of the component 40.

[0064] In addition, a plurality of components 40 may be arranged in the component area CA. The plurality of components 40 may have different functions. For example, the plurality of components 40 may include at least two of a camera (e.g., an imaging device), a solar cell, a flash, a proximity sensor, an illumination sensor, and an iris sensor.

[0065] Figure 3 is a plan view schematically illustrating a display device according to an exemplary embodiment of the present invention.

[0066] refer to Figure 3 Various components constituting the display device 1 may be arranged on a substrate 100. The substrate 100 may include a display area DA and a peripheral area DPA surrounding the display area DA. The display area DA may include a main display area MDA in which a main image is displayed, and a component area CA including a transmissive area TA in which an auxiliary image is displayed. The auxiliary image may form an entire image together with the main image, or may be an image independent of the main image.

[0067] A plurality of primary subpixels Pm may be arranged in the main display area MDA. Each of the primary subpixels Pm may be implemented by a display element such as an organic light-emitting diode (OLED). Each primary subpixel Pm may emit, for example, red, green, blue, or white light. The main display area MDA may be covered by an encapsulation member to protect it from external air or moisture.

[0068] As described above, the component area CA may be located on one side of the main display area MDA, or may be arranged within the display area DA and surrounded by the main display area MDA. A plurality of auxiliary sub-pixels Pa may be arranged in the component area CA. Each of the plurality of auxiliary sub-pixels Pa may be implemented by a display element such as an organic light-emitting diode (OLED). Each auxiliary sub-pixel Pa may emit, for example, red light, green light, blue light, or white light. The component area CA may be covered by an encapsulation member to be protected from external air or moisture.

[0069] In addition, the component area CA may include a transmission area TA. The transmission area TA may be arranged to surround the plurality of auxiliary sub-pixels Pa. In addition, the transmission area TA may be arranged in a lattice form with the plurality of auxiliary sub-pixels Pa.

[0070] Because the component area CA includes the transmissive area TA, the resolution of the component area CA may be lower than that of the main display area MDA. For example, the resolution of the component area CA may be approximately 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For example, the resolution of the main display area MDA may be approximately 400 ppi or higher, while the resolution of the component area CA may be approximately 200 ppi or approximately 100 ppi.

[0071] Each of the pixel circuits driving the sub-pixels Pm and Pa may be electrically connected to a peripheral circuit disposed in the peripheral area DPA. A first scan driving circuit SDRV1, a second scan driving circuit SDRV2, a terminal portion PAD, a driving voltage supply line 11, and a common voltage supply line 13 may be disposed in the peripheral area DPA.

[0072] The first scan drive circuit SDRV1 can apply scan signals to each of the pixel circuits driving the subpixels Pm and Pa via scan lines SL. The first scan drive circuit SDRV1 can apply emission control signals to each pixel circuit via emission control lines EL. The second scan drive circuit SDRV2 can be located on an opposite side of the first scan drive circuit SDRV1 relative to the main display area MDA and can be substantially parallel to the first scan drive circuit SDRV1. The pixel circuits of some of the primary subpixels Pm in the main display area MDA can be electrically connected to the first scan drive circuit SDRV1, while the pixel circuits of the remaining primary subpixels Pm can be electrically connected to the second scan drive circuit SDRV2. The pixel circuits of some of the auxiliary subpixels Pa in the component area CA can be electrically connected to the first scan drive circuit SDRV1, while the pixel circuits of the remaining auxiliary subpixels Pa can be electrically connected to the second scan drive circuit SDRV2. However, the present invention is not limited to this. For example, the second scan drive circuit SDRV2 can be omitted, and all of the subpixels Pm and Pa can be electrically connected to the first scan drive circuit SDRV1.

[0073] The terminal portion PAD may be disposed on one side of the substrate 100. The terminal portion PAD may be exposed by not being covered by the insulating layer and may be connected to the display circuit board 30. The display driver 32 may be disposed on the display circuit board 30.

[0074] The display driver 32 may generate control signals transmitted to the first scan driving circuit SDRV1 and the second scan driving circuit SDRV2. The display driver 32 may generate data signals, and the generated data signals may be transmitted to the pixel circuits of the sub-pixels Pm and Pa through the fan-out lines FW and the data lines DL connected to the fan-out lines FW.

[0075] The display driver 32 can provide the driving voltage ELVDD (see Figure 4 ) is supplied to the driving voltage supply line 11, and the common voltage ELVSS (see Figure 4 ) is provided to a common voltage supply line 13. The driving voltage ELVDD can be applied to the pixel circuits of the sub-pixels Pm and Pa through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS can be supplied to the common voltage supply line 13 to be applied to the counter electrode of the display element. For example, the counter electrode can be a common electrode.

[0076] The driving voltage supply line 11 may be provided to extend in the x-direction below the main display area MDA in a plan view. The common voltage supply line 13 may have a ring shape with one side open to partially surround the main display area MDA.

[0077] Figure 4 and Figure 5 is a circuit diagram of a pixel that may be included in a display device according to an exemplary embodiment of the present invention.

[0078] refer to Figure 4 Pixel circuit PC can be connected to the organic light-emitting diode OLED to achieve sub-pixel light emission. Pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, and a storage capacitor Cst. Switching thin-film transistor T2 may be connected to a scan line SL and a data line DL and may be configured to transmit a data signal Dm input through the data line DL to the driving thin-film transistor T1 based on a scan signal Sn input through the scan line SL.

[0079] The storage capacitor Cst may be connected to the switching thin film transistor T2 and the driving voltage line PL and may store a voltage corresponding to a difference between a voltage received from the switching thin film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL.

[0080] The driving thin film transistor T1 may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a predetermined brightness according to the driving current.

[0081] although Figure 4 It is shown that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the present invention is not limited thereto.

[0082] refer to Figure 5 The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, a second initialization thin film transistor T7 and a storage capacitor Cst.

[0083] although Figure 5 Each pixel circuit PC is shown to include signal lines SL, SL-1, SL+1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL, but the present invention is not limited thereto. In an exemplary embodiment of the present invention, at least one of the signal lines SL, SL-1, SL+1, EL, and DL and / or the initialization voltage line VL may be shared by adjacent pixel circuits.

[0084] The drain electrode of the driving thin film transistor T1 can be electrically connected to the pixel electrode of the light emitting element ED via the emission control thin film transistor T6. The driving thin film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin film transistor T2 and supply the driving current to the light emitting element ED in response to the switching operation.

[0085] The gate electrode of the switching thin film transistor T2 is connected to the scan line SL, and the source electrode thereof is connected to the data line DL. The drain electrode of the switching thin film transistor T2 is connected to the driving voltage line PL via the operation control thin film transistor T5 and is connected to the source electrode of the driving thin film transistor T1.

[0086] The switching thin film transistor T2 may be turned on according to the scan signal Sn received through the scan line SL to perform a switching operation of transmitting the data signal Dm to the source electrode of the driving thin film transistor T1 through the data line DL.

[0087] The gate electrode of the compensation thin-film transistor T3 can be connected to the scan line SL. The source electrode of the compensation thin-film transistor T3 can be connected to the pixel electrode of the light-emitting element ED via the emission control thin-film transistor T6, and can also be connected to the drain electrode of the driving thin-film transistor T1. The drain electrode of the compensation thin-film transistor T3 can be connected to any one electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 can be turned on in response to the scan signal Sn received via the scan line SL to connect the gate electrode and drain electrode of the driving thin-film transistor T1 to each other, thereby diode-connecting the driving thin-film transistor T1.

[0088] The gate electrode of the first initialization thin film transistor T4 can be connected to the previous scan line SL-1. The drain electrode of the first initialization thin film transistor T4 can be connected to the initialization voltage line VL. The source electrode of the first initialization thin film transistor T4 can be connected to any one electrode of the storage capacitor Cst, the drain electrode of the compensation thin film transistor T3, and the gate electrode of the driving thin film transistor T1. The first initialization thin film transistor T4 can be turned on in response to the previous scan signal Sn-1 received through the previous scan line SL-1 to perform an initialization operation of initializing the voltage of the gate electrode of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the gate electrode of the driving thin film transistor T1 via the initialization voltage line VL.

[0089] The gate electrode of the operation control thin film transistor T5 can be connected to the emission control line EL. The source electrode of the operation control thin film transistor T5 can be connected to the driving voltage line PL. The drain electrode of the operation control thin film transistor T5 can be connected to the source electrode of the driving thin film transistor T1 and the drain electrode of the switching thin film transistor T2.

[0090] The gate electrode of the emission control thin film transistor T6 can be connected to the emission control line EL. The source electrode of the emission control thin film transistor T6 can be connected to the drain electrode of the drive thin film transistor T1 and the source electrode of the compensation thin film transistor T3. The drain electrode of the emission control thin film transistor T6 can be electrically connected to the pixel electrode of the light-emitting element ED. The operation control thin film transistor T5 and the emission control thin film transistor T6 can be turned on simultaneously in response to the emission control signal En received via the emission control line EL, so that the driving voltage ELVDD can be transmitted to the light-emitting element ED and a driving current can flow through the light-emitting element ED.

[0091] The gate electrode of the second initialization thin film transistor T7 may be connected to the next scan line SL+1. The source electrode of the second initialization thin film transistor T7 may be connected to the pixel electrode of the light-emitting element ED. The drain electrode of the second initialization thin film transistor T7 may be connected to the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on according to the next scan signal Sn+1 received through the next scan line SL+1 to initialize the pixel electrode of the light-emitting element ED.

[0092] although Figure 5 The first initialization thin film transistor T4 and the second initialization thin film transistor T7 are shown as being connected to the previous scan line SL-1 and the next scan signal SL+1, respectively, but the present invention is not limited thereto. In an exemplary embodiment of the present invention, both the first initialization thin film transistor T4 and the second initialization thin film transistor T7 may be connected to the previous scan line SL-1 to be driven according to the previous scan signal Sn-1.

[0093] The other electrode of the storage capacitor Cst may be connected to the driving voltage line PL. Any one electrode of the storage capacitor Cst may be connected to the gate electrode of the driving thin film transistor T1, the drain electrode of the compensation thin film transistor T3, and the source electrode of the first initialization thin film transistor T4.

[0094] A common voltage ELVSS may be supplied to an opposite electrode (eg, a cathode) of the light emitting element ED, and the light emitting element ED may emit light by receiving a driving current from the driving thin film transistor T1.

[0095] The pixel circuit PC is not limited to the reference Figure 5 The number and circuit design of the thin film transistors and storage capacitors are described, and the number and circuit design thereof may be variously modified. The pixel circuit PC driving the main subpixel Pm and the auxiliary subpixel Pa may be provided in the same manner or may be provided differently from each other.

[0096] Figure 6 is a cross-sectional view schematically showing a display device according to an exemplary embodiment of the present invention. Figure 6 is a schematic cross-sectional view illustrating a portion of the display device 1 according to an exemplary embodiment of the present invention, and is a cross-sectional view schematically illustrating a main display area MDA and an element area CA.

[0097] refer to Figure 6 The display device 1 may include a main display area MDA and a component area CA. The main sub-pixel Pm may be arranged in the main display area MDA, and the auxiliary sub-pixel Pa may be arranged in the component area CA. The component area CA may include a transmission area TA.

[0098] The main pixel circuit PC and the main organic light-emitting diode OLED may be arranged in the main display area MDA. The main pixel circuit PC may include a main thin-film transistor TFT and a main storage capacitor Cst, and the main organic light-emitting diode OLED may be a display element connected to the main pixel circuit PC. The auxiliary pixel circuit PC' and the auxiliary organic light-emitting diode OLED' may be arranged in the component area CA. The auxiliary pixel circuit PC' may include an auxiliary thin-film transistor TFT' and an auxiliary storage capacitor Cst', and the auxiliary organic light-emitting diode OLED' may be a display element connected to the auxiliary pixel circuit PC'.

[0099] In the present embodiment, an organic light emitting diode is used as the display element; however, in an exemplary embodiment of the present invention, an inorganic light emitting element, a quantum dot light emitting element, or the like may be used as the display element.

[0100] Hereinafter, a structure in which components included in the display device 1 are stacked will be described. The display device 1 may include a stack of a substrate 100, a buffer layer 111, a circuit layer PCL, a display element layer EDL, and an encapsulation member ENCM.

[0101] As described above, the substrate 100 may include an insulating material such as glass, quartz, or a polymer resin. The substrate 100 may include a rigid substrate or a flexible substrate that can be bent, folded, or rolled. For example, the buffer layer 111, the circuit layer PCL, the display element layer EDL, and the encapsulation member ENCM may be stacked on one surface 100a of the substrate 100.

[0102] The buffer layer 111 may be located on the substrate 100 to reduce or block the penetration of foreign matter, moisture, or external air from the bottom of the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite, and may include a single layer or a multilayer structure of an inorganic material and an organic material. A barrier layer for blocking the penetration of external air may be further included between the substrate 100 and the buffer layer 111. In an exemplary embodiment of the present invention, the buffer layer 111 may include silicon oxide (SiO2) or silicon nitride (SiN x ). The buffer layer 111 disposed in the component area CA may include an opening corresponding to the transmission area TA.

[0103] In the component area CA, a bottom metal layer BML may be arranged between the substrate 100 and the buffer layer 111. The bottom metal layer BML may be arranged on one surface 100a of the substrate 100 in the component area CA. For example, the bottom metal layer BML may be arranged directly on one surface 100a of the substrate 100 in the component area CA. In an exemplary embodiment of the present invention, the buffer layer may be located between the bottom metal layer BML and one surface 100a of the substrate 100. The bottom metal layer BML may be arranged below the auxiliary pixel circuit PC' to prevent light emitted from components, etc. from degrading the characteristics of the auxiliary thin film transistor TFT'. In addition, the bottom metal layer BML may prevent light emitted from components, etc. or light directed to components from being diffracted through the gaps between the lines connected to the auxiliary pixel circuit PC'. The bottom metal layer BML may not be in the transmission area TA.

[0104] The bottom metal layer BML can be connected to a bias line arranged in another layer through a contact hole. The bottom metal layer BML can receive a constant voltage or signal from the bias line. For example, the bottom metal layer BML can receive a bias voltage. The bias voltage can have a different level than the driving voltage ELVDD. However, the present invention is not limited to this. For example, the bias voltage can have the same level as the driving voltage ELVDD.

[0105] By receiving a bias voltage, the bottom metal layer (BML) can significantly reduce the likelihood of electrostatic discharge. The bottom metal layer (BML) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The bottom metal layer (BML) may be provided as a single layer or multiple layers of the above materials.

[0106] The bottom metal layer BML of the component area CA may be provided to correspond to the component area CA. For example, the bottom metal layer BML may correspond to the entire component area CA. In this case, the bottom metal layer BML may include a first hole H1 corresponding to the transmission area TA. In an exemplary embodiment of the present invention, the shape and size of the transmission area TA may be formed by the shape and size of the first hole H1 formed by the bottom metal layer BML.

[0107] In an exemplary embodiment of the present invention, the bottom metal layer BML may not be disposed in the main display area MDA. When the bottom metal layer BML is provided at the front surface of the substrate 100 or a corresponding portion thereof, defects may occur in a process of crystallizing the first semiconductor layer A1 of the main thin film transistor TFT by using laser.

[0108] In this embodiment, the bottom metal layer BML may be arranged to correspond to the component area CA, so that the process defect rate can be reduced. For example, the bottom metal layer BML may be provided only in the component area CA, and the process defect rate can be reduced.

[0109] In the component area CA, an anti-reflection layer 200 may be disposed on the substrate 100. For example, the anti-reflection layer 200 may be disposed below the substrate 100. For example, in the component area CA, the anti-reflection layer 200 may be disposed on the other surface 100b of the substrate 100, which is opposite to the one surface 100a of the substrate 100, so as to overlap with the bottom metal layer BML disposed on the one surface 100a of the substrate 100. For example, the anti-reflection layer 200 may be disposed directly on the other surface 100b of the substrate 100.

[0110] The anti-reflection layer 200 may overlap with the bottom metal layer BML, with the substrate 100 being between the anti-reflection layer 200 and the bottom metal layer BML. In an exemplary embodiment of the present invention, the width of the bottom metal layer BML may be smaller than the width of the anti-reflection layer 200, and therefore, when projected in a direction perpendicular to the substrate 100, the bottom metal layer BML may completely overlap with the anti-reflection layer 200.

[0111] Since the anti-reflection layer 200 is arranged to overlap with the bottom metal layer BML, the occurrence of light spots can be prevented. For example, since the anti-reflection layer 200 is arranged to overlap with the bottom metal layer BML, the occurrence of light spots due to the light from the component 40 (see Figure 2 )The light emitted is reflected by the bottom metal layer BML and produces a light spot.

[0112] The anti-reflection layer 200 may include a colored material. For example, the anti-reflection layer 200 may include a colored pigment, for example, a pigment of a certain color such as white or black. In an exemplary embodiment of the present invention, the anti-reflection layer 200 may have a black color. For example, the anti-reflection layer 200 may include a polyimide (PI)-based adhesive and red, green, and blue pigments mixed therein. In addition, the anti-reflection layer 200 may include a mixture of an anthracene-based adhesive resin and a lactam-based black pigment and a blue pigment. In addition, the anti-reflection layer 200 may include carbon black or a light-shielding material. Since the anti-reflection layer 200 is composed of the colored material layer 200M described below (see Figure 11 ) is formed, so it can include positive photosensitive materials.

[0113] Since the anti-reflection layer 200 includes a color pigment, carbon black, or a light-shielding material, it is possible to prevent reflection of external light, improve the contrast of the display device 1, and prevent the occurrence of light spots.

[0114] The anti-reflection layer 200 may have a first thickness t1 in the z direction and may be disposed on the other surface 100b of the substrate 100. For example, the first thickness t1 may be about 0.5 μm to about 5 μm, or about 0.5 μm to about 4 μm, and may have various modifications, such as about 1 μm to about 4 μm. For example, the first thickness t1 may be about 1 μm to about 3 μm.

[0115] The anti-reflection layer 200 of the component area CA may be provided to correspond to the entire component area CA. The anti-reflection layer 200 may include a second hole H2 corresponding to the transmissive area TA. The second hole H2 formed in the anti-reflection layer 200 may overlap with the first hole H1 formed in the bottom metal layer BML. For example, the second hole H2 formed in the anti-reflection layer 200 and the first hole H1 formed in the bottom metal layer BML may overlap with each other, with the substrate 100 between the second hole H2 and the first hole H1. In an exemplary embodiment of the present invention, the second hole H2 in the anti-reflection layer 200 may be equal to or narrower than the first hole H1 in the bottom metal layer BML.

[0116] The circuit layer PCL may be disposed on the buffer layer 111 and may include pixel circuits PC and PC′, a first insulating layer 112, a second insulating layer 113, a third insulating layer 115, and a planarization layer 117. The main pixel circuit PC may include a main thin film transistor TFT and a main storage capacitor Cst, and the auxiliary pixel circuit PC′ may include an auxiliary thin film transistor TFT′ and an auxiliary storage capacitor Cst′.

[0117] A main thin-film transistor (TFT) and an auxiliary thin-film transistor (TFT') may be disposed on the buffer layer 111. The main thin-film transistor (TFT) may include a first semiconductor layer (A1), a first gate electrode (G1), a first source electrode (S1), and a first drain electrode (D1). The auxiliary thin-film transistor (TFT') may include a second semiconductor layer (A2), a second gate electrode (G2), a second source electrode (S2), and a second drain electrode (D2). The main thin-film transistor (TFT) may be connected to the main organic light-emitting diode (OLED) to drive the main organic light-emitting diode (OLED). The auxiliary thin-film transistor (TFT') may be connected to the auxiliary organic light-emitting diode (OLED') to drive the auxiliary organic light-emitting diode (OLED').

[0118] The first semiconductor layer A1 and the second semiconductor layer A2 may be disposed on the buffer layer 111 and may include polycrystalline silicon. In an exemplary embodiment of the present invention, the first semiconductor layer A1 and the second semiconductor layer A2 may include amorphous silicon. In an exemplary embodiment of the present invention, the first semiconductor layer A1 and the second semiconductor layer A2 may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The first semiconductor layer A1 and the second semiconductor layer A2 may include a channel region, a source region doped with a dopant, and a drain region.

[0119] The second semiconductor layer A2 may overlap the bottom metal layer BML with the buffer layer 111 between the second semiconductor layer A2 and the bottom metal layer BML. In an exemplary embodiment of the present invention, the width of the second semiconductor layer A2 may be smaller than the width of the bottom metal layer BML, and thus, when projected in a direction perpendicular to the substrate 100, the second semiconductor layer A2 may be completely overlapped by the bottom metal layer BML.

[0120] The first insulating layer 112 may cover the first semiconductor layer A1 and the second semiconductor layer A2. The first insulating layer 112 may include an inorganic insulating material, such as silicon oxide (SiO2), silicon nitride (SiN x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2). The first insulating layer 112 may include a single layer or multiple layers including the above inorganic insulating materials.

[0121] The first gate electrode G1 and the second gate electrode G2 may be arranged on the first insulating layer 112 to overlap with the first semiconductor layer A1 and the second semiconductor layer A2, respectively. The first gate electrode G1 and the second gate electrode G2 may include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single layer or multiple layers. In an exemplary embodiment of the present invention, the first gate electrode G1 and the second gate electrode G2 may both include molybdenum (Mo) and may both be single layers.

[0122] The second insulating layer 113 may cover the first gate electrode G1 and the second gate electrode G2. The second insulating layer 113 may include an inorganic insulating material, such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2). The second insulating layer 113 may include a single layer or multiple layers including the above inorganic insulating materials.

[0123] A first upper electrode CE2 of the main storage capacitor Cst and a second upper electrode CE2 ′ of the auxiliary storage capacitor Cst′ may be disposed on the second insulating layer 113 .

[0124] In the main display area MDA, the first upper electrode CE2 may overlap the first gate electrode G1 disposed therebelow. The overlapping first gate electrode G1 and first upper electrode CE2 may constitute a main storage capacitor Cst, with the second insulating layer 113 located between the first gate electrode G1 and the first upper electrode CE2. The first gate electrode G1 may be integrally formed with the first lower electrode CE1 of the main storage capacitor Cst. In an exemplary embodiment of the present invention, the main storage capacitor Cst may not overlap with the main thin-film transistor TFT, and the first lower electrode CE1 of the main storage capacitor Cst may be an independent component separate from the first gate electrode G1 of the main thin-film transistor TFT.

[0125] In the component area CA, the second upper electrode CE2' may overlap with the second gate electrode G2 disposed therebelow. The second gate electrode G2 and the second upper electrode CE2' overlapping each other may constitute an auxiliary storage capacitor Cst', with the second insulating layer 113 located between the second gate electrode G2 and the second upper electrode CE2'. The second gate electrode G2 may be integrally provided with the second lower electrode CE1' of the auxiliary storage capacitor Cst'. In an exemplary embodiment of the present invention, the auxiliary storage capacitor Cst' may not overlap with the auxiliary thin film transistor TFT', and the second lower electrode CE1' of the auxiliary storage capacitor Cst' may be an independent component separated from the second gate electrode G2 of the auxiliary thin film transistor TFT'.

[0126] The first upper electrode CE2 and the second upper electrode CE2' may include, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu), and may include a single layer or multiple layers of the above materials.

[0127] The third insulating layer 115 may be formed to cover the first upper electrode CE2 and the second upper electrode CE2'. The third insulating layer 115 may include, for example, silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2). The third insulating layer 115 may include a single layer or multiple layers including the above inorganic insulating materials.

[0128] When the first insulating layer 112, the second insulating layer 113, and the third insulating layer 115 are collectively referred to as the inorganic insulating layer IL, the inorganic insulating layer IL may have a third hole H3 corresponding to the transmission area TA. The third hole H3 may expose a portion of the top surface of the substrate 100. Furthermore, when the buffer layer 111 is arranged in the transmission area TA, the third hole H3 may expose a portion of the top surface of the buffer layer 111. The third hole H3 may be formed by an opening in the first insulating layer 112, an opening in the second insulating layer 113, and an opening in the third insulating layer 115 to correspond to the transmission area TA, and the openings in the first insulating layer 112, the second insulating layer 113, and the third insulating layer 115 may overlap with each other. These openings may be formed separately through separate processes or simultaneously through the same process. For example, when these openings are formed in separate processes, the inner surface of the third hole H3 may not be smooth and may have a stepped or uneven surface.

[0129] The source electrodes S1 and S2 and the drain electrodes D1 and D2 may be disposed on the third insulating layer 115. The source electrodes S1 and S2 and the drain electrodes D1 and D2 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single layer or multiple layers including the above materials. For example, the source electrodes S1 and S2 and the drain electrodes D1 and D2 may include a multilayer structure of Ti / Al / Ti.

[0130] The planarization layer 117 may be disposed to cover the source electrodes S1 and S2 and the drain electrodes D1 and D2 . The planarization layer 117 may have a flat top surface so that the first and second pixel electrodes 121 and 121 ′ disposed on the planarization layer 117 may be formed on a flat surface.

[0131] The planarization layer 117 may include an organic material or an inorganic material and may have a single-layer structure or a multi-layer structure. The planarization layer 117 may include a first planarization layer 117a and a second planarization layer 117b. Therefore, a conductive pattern such as a line may be formed between the first planarization layer 117a and the second planarization layer 117b, which may improve integration.

[0132] The planarization layer 117 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a paraxylene-based polymer or a vinyl alcohol-based polymer. In addition, the planarization layer 117 may include an inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2). When the planarization layer 117 is formed, chemical mechanical polishing can be performed on the top surface of the layer after the layer is formed to provide a flat top surface.

[0133] The first planarization layer 117a may be arranged to cover the pixel circuits PC and PC'. The second planarization layer 117b may be arranged on the first planarization layer 117a and may have a flat top surface so that the pixel electrodes 121 and 121' may be flatly formed when formed on the second planarization layer 117b.

[0134] The organic light emitting diodes OLED and OLED' may be disposed on the second planarization layer 117b. The pixel electrodes 121 and 121' of the organic light emitting diodes OLED and OLED' may be connected to the pixel circuits PC and PC', respectively, through corresponding connection electrodes CM and CM' disposed on the first planarization layer 117a.

[0135] The connection electrodes CM and CM' may be disposed between the first planarization layer 117a and the second planarization layer 117b. The connection electrodes CM and CM' may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single layer or multiple layers of the above materials. For example, the connection electrodes CM and CM' may include a multilayer structure of Ti / Al / Ti.

[0136] The planarization layer 117 may include a fourth hole H4 corresponding to the transmission area TA. The fourth hole H4 may overlap the third hole H3. Figure 6 In an exemplary embodiment of the present invention, the planarization layer 117 may be provided to cover the edge of the third hole H3 of the inorganic insulating layer IL so that the area of ​​the fourth hole H4 may be smaller than that of the third hole H3.

[0137] The planarization layer 117 may include a through hole for exposing either the first source electrode S1 or the first drain electrode D1 of the main thin-film transistor TFT, and the first pixel electrode 121 may be electrically connected to the main thin-film transistor TFT by contacting the first source electrode S1 or the first drain electrode D1 of the main thin-film transistor TFT via the through hole. In addition, the planarization layer 117 may include a through hole for exposing either the second source electrode S2 or the second drain electrode D2 of the auxiliary thin-film transistor TFT', and the second pixel electrode 121' may be electrically connected to the auxiliary thin-film transistor TFT' by contacting the second source electrode S2 or the second drain electrode D2 of the auxiliary thin-film transistor TFT' via the through hole.

[0138] The first pixel electrode 121 and the second pixel electrode 121' may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The first pixel electrode 121 and the second pixel electrode 121' may include a reflective layer containing, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or any compound thereof. For example, the first pixel electrode 121 and the second pixel electrode 121' may have a structure including a layer formed of ITO, IZO, ZnO or In2O3 above / below the reflective layer. In this case, the first pixel electrode 121 and the second pixel electrode 121' may have a stacked structure of ITO / Ag / ITO.

[0139] The pixel defining layer 119 may cover edges of the first and second pixel electrodes 121 and 121' on the planarization layer 117 and may include first and second openings OP1 and OP2 for exposing central portions of the first and second pixel electrodes 121 and 121'. The first and second openings OP1 and OP2 may provide emission areas of the organic light emitting diodes OLED and OLED', for example, the size and shape of the sub-pixels Pm and Pa.

[0140] The pixel defining layer 119 can increase the distance between the edges of the pixel electrodes 121 and 121' and the counter electrode 123 provided on the pixel electrodes 121 and 121' to prevent arcing, etc. from occurring at the edges of the pixel electrodes 121 and 121'. The pixel defining layer 119 can be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), or phenolic resin by spin coating, etc.

[0141] The pixel defining layer 119 may include a fifth hole H5 located in the transmissive area TA. The fifth hole H5 may overlap the third hole H3 and the fourth hole H4. The third to fifth holes H3 to H5 may increase light transmittance in the transmissive area TA. A portion of the counter electrode 123, described below, may be disposed on inner surfaces of the third to fifth holes H3 to H5.

[0142] The first emission layer 122b and the second emission layer 122b' formed to correspond to the first pixel electrode 121 and the second pixel electrode 121', respectively, may be respectively disposed within the first opening OP1 and the second opening OP2 of the pixel defining layer 119. For example, the first emission layer 122b and the second emission layer 122b' may include a high molecular weight material or a low molecular weight material and may emit red light, green light, blue light, or white light.

[0143] The organic functional layer 122e may be disposed above and / or below the first emission layer 122b and the second emission layer 122b'. The organic functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. However, the present invention is not limited thereto. For example, the first functional layer 122a or the second functional layer 122c may be omitted, or a third functional layer may be provided.

[0144] The first functional layer 122a may be arranged below the first emission layer 122b and the second emission layer 122b'. The first functional layer 122a may include a single layer or multiple layers containing organic materials. The first functional layer 122a may include a hole transport layer (HTL) having a single layer structure. In addition, the first functional layer 122a may include a hole injection layer (HIL) and a hole transport layer (HTL). The first functional layer 122a may be integrally formed to correspond to the organic light emitting diodes OLED and OLED' included in the main display area MDA and the component area CA.

[0145] The second functional layer 122c may be disposed above the first emission layer 122b and the second emission layer 122b'. The second functional layer 122c may include a single layer or multiple layers containing organic materials. The second functional layer 122c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 122c may be integrally formed to correspond to the organic light emitting diodes OLED and OLED' included in the main display area MDA and the component area CA.

[0146] The counter electrode 123 may be arranged above the second functional layer 122c. The counter electrode 123 may include a conductive material having a low work function. For example, the counter electrode 123 may include a (semi) transparent layer comprising, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or any alloy thereof. In addition, the counter electrode 123 may further include a layer such as ITO, IZO, ZnO or In2O3 on the (semi) transparent layer comprising the above-mentioned materials. The counter electrode 123 may be integrally formed to correspond to the organic light emitting diodes OLED and OLED' included in the main display area MDA and the component area CA.

[0147] The first pixel electrode 121, the first emission layer 122b, the organic functional layer 122e, and the counter electrode 123 formed in the main display area MDA may constitute a main organic light-emitting diode OLED. The second pixel electrode 121', the second emission layer 122b', the organic functional layer 122e, and the counter electrode 123 formed in the component area CA may constitute an auxiliary organic light-emitting diode OLED'.

[0148] A top layer 150 including an organic material may be formed on the counter electrode 123. The top layer 150 may be provided to protect the counter electrode 123 and to improve light extraction efficiency. For example, the top layer 150 may include an organic material having a higher refractive index than the counter electrode 123. In addition, the top layer 150 may include a stack of layers having different refractive indices from each other. For example, the top layer 150 may include a stack of a high refractive index layer, a low refractive index layer, and a high refractive index layer. For example, the refractive index of the high refractive index layer may be about 1.7 or greater, and the refractive index of the low refractive index layer may be about 1.3 or less. For example, the top layer 150 may further include LiF. In addition, the top layer 150 may further include a silicon oxide (SiO2) or a silicon nitride (SiN x In an exemplary embodiment of the present invention, the roof layer 150 may be omitted.

[0149] The first functional layer 122a, the second functional layer 122c, the opposing electrode 123, and the roof layer 150 may include a transmissive hole TAH corresponding to the transmissive area TA. For example, the first functional layer 122a, the second functional layer 122c, the opposing electrode 123, and the roof layer 150 may include an opening corresponding to the transmissive area TA. The areas of the openings of the first functional layer 122a, the second functional layer 122c, the opposing electrode 123, and the roof layer 150 may be substantially equal to each other. For example, the area of ​​the opening of the opposing electrode 123 may be substantially equal to the area of ​​the transmissive hole TAH.

[0150] For example, the transmission hole TAH overlaps the transmission area TA. In this case, the area of ​​the transmission hole TAH may be smaller than the area of ​​the third hole H3 formed in the inorganic insulating layer IL. The minimum width Wt of the transmission area TA may be smaller than the width of the transmission hole TAH. In an exemplary embodiment of the present invention, the minimum width Wt of the transmission area TA may be equal to the width of the transmission hole TAH. Although Figure 6 The opening formed in the buffer layer 111 is shown to correspond to the minimum width Wt of the transmission area TA, but the openings formed in the first and second functional layers 122a and 122c, the opposing electrode 123, and the roof layer 150 may correspond to the minimum width Wt of the transmission area TA.

[0151] Due to the transmission hole TAH, a portion of the counter electrode 123 may not be in the transmission area TA, and therefore, the transmittance in the transmission area TA may be significantly improved. The counter electrode 123 including the transmission hole TAH may be formed in various ways. In an exemplary embodiment of the present invention, a material for forming the counter electrode 123 may be formed on the front surface of the substrate 100, and a portion of the material corresponding to the transmission area TA may be removed by laser stripping to form the counter electrode 123 including the transmission hole TAH. In an exemplary embodiment of the present invention, the counter electrode 123 including the transmission hole TAH may be formed by a metal self-patterning (MSP) process. In an exemplary embodiment of the present invention, the counter electrode 123 including the transmission hole TAH may be formed by depositing the counter electrode 123 using a fine metal mask (FMM).

[0152] The main organic light emitting diode OLED of the main display area MDA and the auxiliary organic light emitting diode OLED' of the component area CA may be covered by an encapsulation member ENCM. For example, the encapsulation member ENCM may include an encapsulation substrate. The encapsulation substrate may be arranged to face the substrate 100, and a gap may be located between the encapsulation substrate and the display element layer EDL. The encapsulation substrate may include glass. A sealant including glass frit or the like may be arranged between the substrate 100 and the encapsulation substrate, and the sealant may be arranged in the above-mentioned peripheral area DPA. The sealant arranged in the peripheral area DPA may surround the display area DA to prevent moisture from penetrating the side surface of the display area DA.

[0153] Figures 7 to 13 is a cross-sectional view schematically illustrating a method of manufacturing a display device according to an exemplary embodiment of the present invention.

[0154] In the following, reference will be made to Figures 7 to 13 A method of manufacturing a display device is sequentially described.

[0155] As a method for manufacturing a display device according to an exemplary embodiment of the present invention, the method for manufacturing a display device including a main display area MDA, a component area CA including a transmission area TA, and a peripheral area surrounding the main display area MDA may include: forming a bottom metal layer BML on one surface 100a of a substrate 100 to correspond to the component area CA; forming an encapsulation substrate on one surface 100a of the substrate 100; forming a colored material layer 200M on another surface 100b opposite to the one surface 100a of the substrate 100 to correspond to the component area CA; exposing a portion of the colored material layer 200M by irradiating light onto one surface 100a of the substrate 100 on which the bottom metal layer BML is arranged; and forming an anti-reflection layer 200 by developing the exposed colored material layer 200M.

[0156] Between forming the bottom metal layer (BML) and forming the package substrate, the method may further include forming a main thin-film transistor (TFT) and a main display element on one surface 100a of the substrate 100, corresponding to the main display area (MDA). Furthermore, the method may further include forming an auxiliary thin-film transistor (TFT') and an auxiliary display element on the bottom metal layer (BML), corresponding to the component area (CA). Furthermore, after forming the anti-reflection layer 200, the method may further include forming a protective member (PB) on the other surface 100b of the substrate 100, corresponding to the main display area (MDA).

[0157] refer to Figure 7 In the process of forming a bottom metal layer BML on one surface 100a of the substrate 100 to correspond to the component area CA, the bottom metal layer BML can be formed on the one surface 100a of the substrate 100 including glass. The bottom metal layer BML can be arranged to correspond to the bottom of the auxiliary thin film transistor TFT' described below. For example, the bottom metal layer BML can overlap with the auxiliary thin film transistor TFT'. For example, the bottom metal layer BML can be arranged between the auxiliary thin film transistor TFT' and the substrate 100.

[0158] The bottom metal layer BML of the component area CA may be formed to correspond to the component area CA. For example, the entire bottom metal layer BML may be disposed in the component area CA. The bottom metal layer BML may include a first hole H1 corresponding to the transmission area TA. In an exemplary embodiment of the present invention, the shape and size of the transmission area TA may be formed by the shape and size of the first hole H1 formed in the bottom metal layer BML.

[0159] refer to Figure 8 After forming the bottom metal layer BML on one surface 100a of the substrate 100 to correspond to the component area CA, an operation of forming the main thin film transistor TFT and the main display element may be performed. In addition, after forming the bottom metal layer BML on one surface 100a of the substrate 100 to correspond to the component area CA, an operation of forming the auxiliary thin film transistor TFT′ and the auxiliary display element may be performed.

[0160] A buffer layer 111 and an inorganic insulating layer IL may be disposed on one surface 100 a of the substrate 100 in the main display area MDA, and a main thin film transistor TFT including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode may be provided in the inorganic insulating layer IL.

[0161] A buffer layer 111 and an inorganic insulating layer IL may be disposed on the bottom metal layer BML in the component area CA, and an auxiliary thin film transistor TFT' including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode may be provided in the inorganic insulating layer IL.

[0162] A main light emitting element ED as a main display element may be formed on a main thin film transistor TFT, and an auxiliary light emitting element ED′ as an auxiliary display element may be formed on an auxiliary thin film transistor TFT′.

[0163] The main light emitting element ED may be electrically connected to the main thin film transistor TFT, and the auxiliary light emitting element ED′ may be electrically connected to the auxiliary thin film transistor TFT′.

[0164] The main thin film transistor TFT and the main light emitting element ED connected to the main thin film transistor TFT may be arranged in the main display area MDA to implement the main sub-pixel Pm, and the auxiliary thin film transistor TFT′ and the auxiliary light emitting element ED′ connected to the auxiliary thin film transistor TFT′ may be arranged in the component area CA to implement the auxiliary sub-pixel Pa. The region of the component area CA in which the auxiliary sub-pixel Pa is arranged may be referred to as an auxiliary display area.

[0165] In addition, a transmission area TA in which no display element is arranged may be arranged in the component area CA. The transmission area TA may be a portion of the component 40 (see FIG. 1 ) arranged to correspond to the component area CA. Figure 2 ) is an area through which light / signals output from or input to the component 40 are transmitted. The auxiliary display area and the transmission area TA may be alternately arranged in the component area CA.

[0166] refer to Figure 9 After forming the main thin film transistor TFT and the main display element on one surface 100a of the substrate 100, an encapsulation substrate may be further formed on the one surface 100a of the substrate 100. Furthermore, after forming the auxiliary thin film transistor TFT' and the auxiliary display element on the bottom metal layer BML, an encapsulation substrate may also be formed on the one surface 100a.

[0167] The main display elements of the main display area MDA and the auxiliary display elements of the component area CA may be covered by an encapsulation member ENCM. For example, the encapsulation member ENCM may include an encapsulation substrate. The encapsulation substrate may be arranged to face the substrate 100, and a gap may be located between the encapsulation substrate and the display elements. The encapsulation substrate may include glass. A sealant including glass frit or the like may be arranged between the substrate 100 and the encapsulation substrate, and the sealant may be arranged in the aforementioned peripheral area. The sealant arranged in the peripheral area may surround the display area DA to prevent moisture from penetrating the side surfaces of the display area DA.

[0168] refer to Figure 10After forming the package substrate on one surface 100a of the substrate 100, the colored material layer 200M may be formed on the other surface 100b of the substrate 100. For example, the colored material layer 200M may be directly formed on the other surface 100b of the substrate 100.

[0169] The colored material layer 200M may include a colored pigment, for example, a pigment of a certain color such as white or black. In an exemplary embodiment of the present invention, the colored material layer 200M may have a black color. For example, the colored material layer 200M may include a polyimide (PI) adhesive and a red, green, and blue pigment mixed therein. In addition, the colored material layer 200M may include a mixture of a cation ring adhesive resin and a lactam black pigment and a blue pigment. In addition, the colored material layer 200M may include carbon black or a light-shielding material. The colored material layer 200M may include a positive photosensitive material.

[0170] refer to Figure 11 After the operation of forming the colored material layer 200M on the other surface 100 b of the substrate 100 , an operation of exposing a portion of the colored material layer 200M by irradiating light onto the one surface 100 a of the substrate 100 may be performed.

[0171] In a structure in which the bottom metal layer BML is arranged in the component area CA, since light emitted from the component may be reflected by the bottom metal layer BML, light spots causing image quality degradation may occur.

[0172] According to an exemplary embodiment of the present invention, by forming the anti-reflection layer 200 on the other surface 100b opposite to the one surface 100a of the substrate 100 to overlap the bottom metal layer BML disposed on the one surface 100a of the substrate 100, light spots may be prevented from occurring.

[0173] In this case, when the anti-reflection layer 200 is formed to overlap with the bottom metal layer BML, the colored material layer 200M is patterned by using the bottom metal layer BML arranged on one surface 100a of the substrate 100 as a reflective layer (e.g., a mask), and the anti-reflection layer 200 overlapping with the bottom metal layer BML can be formed without using an additional mask.

[0174] In the operation of exposing a portion of the colored material layer 200M, light may be irradiated onto one surface 100a of the substrate 100 on which the bottom metal layer BML is disposed. For example, light for exposing a portion of the colored material layer 200M may be irradiated onto one surface 100a of the substrate 100 on which the bottom metal layer BML, thin film transistors TFT and TFT′, a display element, and an encapsulation member ENCM are formed.

[0175] In the operation of exposing a portion of the colored material layer 200M, the portion of the colored material layer 200M can be exposed by using the bottom metal layer BML disposed on one surface 100a of the substrate 100 as a mask, rather than exposing a portion of the colored material layer 200M by adding a mask in the conventional process. For example, the bottom metal layer BML disposed on one surface 100a of the substrate 100 can be used as a mask to expose a portion of the colored material layer 200M. In this case, because the colored material layer 200M may include a positive photosensitive material, in the operation of developing the exposed colored material layer 200M described below, the portion of the colored material layer 200M that was exposed to light can be removed to form the anti-reflection layer 200 overlapping the bottom metal layer BML.

[0176] refer to Figure 12 After exposing a portion of the colored material layer 200M by irradiating light onto one surface 100a of the substrate 100 where the bottom metal layer BML is disposed, forming the anti-reflection layer 200 by developing the exposed colored material layer 200M may be performed.

[0177] For example, the colored material layer 200M may include a positive photosensitive material. Since the colored material layer 200M includes the positive photosensitive material, when exposing the colored material layer 200M, light may be irradiated onto the colored material layer 200M that does not overlap with the bottom metal layer BML, and when developing the exposed colored material layer 200M, the colored material layer 200M irradiated with light may be removed to pattern the anti-reflection layer 200.

[0178] The anti-reflection layer 200 may overlap the bottom metal layer BML with the substrate 100 between the anti-reflection layer 200 and the bottom metal layer BML. In an exemplary embodiment of the present invention, the width of the bottom metal layer BML may be smaller than the width of the anti-reflection layer 200, and therefore, the bottom metal layer BML may be completely overlapped by the anti-reflection layer 200 in a direction perpendicular to the substrate 100.

[0179] The anti-reflection layer 200 may include a second hole H2 corresponding to the transmissive area TA. The second hole H2 formed in the anti-reflection layer 200 may overlap with the first hole H1 formed in the bottom metal layer BML. For example, the second hole H2 formed in the anti-reflection layer 200 and the first hole H1 formed in the bottom metal layer BML may overlap with each other, with the substrate 100 between the second hole H2 and the first hole H1. In an exemplary embodiment of the present invention, the second hole H2 in the anti-reflection layer 200 may be equal to or narrower than the first hole H1 in the bottom metal layer BML.

[0180] refer to Figure 13After the operation of forming the anti-reflection layer 200 by developing the exposed colored material layer 200M, an operation of forming a protection member PB on the other surface 100b of the substrate 100 to correspond to the main display area MDA may be performed.

[0181] A protection member PB may be attached to the other surface 100 b of the substrate 100 to support and protect the substrate 100 .

[0182] According to an exemplary embodiment of the present invention, in order to prevent light spots that may cause image quality degradation due to light reflected by the bottom metal layer provided on one surface of the substrate, an anti-reflection layer may be patterned on the other surface of the substrate to overlap with the bottom metal layer. In this case, by patterning the anti-reflection layer using the bottom metal layer arranged on one surface of the substrate as a reflective layer (e.g., a mask), the anti-reflection layer overlapping with the bottom metal layer can be patterned without using an additional mask.

[0183] According to an exemplary embodiment of the present invention, by using the bottom metal layer disposed on one surface of the substrate as a reflective layer, it is possible to prevent light spots from occurring by patterning an anti-reflective layer on the other surface of the substrate opposite to the one surface without an additional mask. However, the scope of the present invention is not limited to these effects.

[0184] Although the present invention has been described with reference to exemplary embodiments thereof, workers skilled in the art will recognize that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A display device comprising: Main display area; a component area including a transmissive area; a peripheral area adjacent to the main display area; substrate; main display elements arranged on the first surface of the substrate in the main display area, wherein main pixel circuits are respectively connected to the main display elements; auxiliary display elements arranged on the first surface of the substrate in the component area, wherein auxiliary pixel circuits are respectively connected to the auxiliary display elements; a bottom metal layer disposed in the component area between the substrate and the auxiliary pixel circuit; as well as an anti-reflection layer disposed on a second surface of the substrate opposite the first surface and overlapping the bottom metal layer in the component area, wherein the bottom metal layer includes a first hole corresponding to the transmission area, wherein the anti-reflection layer includes a second hole corresponding to the transmission area, and The first hole and the second hole overlap each other.

2. The display device according to claim 1, wherein The anti-reflection layer is directly disposed on the second surface of the substrate.

3. The display device according to claim 2, wherein: The anti-reflection layer has a first thickness of 1 μm to 3 μm.

4. The display device according to claim 2, wherein The anti-reflection layer includes a positive photosensitive material.

5. The display device according to claim 2, wherein The anti-reflection layer includes a light-shielding material.

6. The display device according to claim 1, further comprising: A packaging substrate is disposed on the first surface of the substrate.

7. The display device according to claim 1, further comprising: a component arranged on the second surface of the substrate in the component area, Wherein, the component includes an imaging device or a sensor.

8. The display device according to claim 1, further comprising: A protective member is disposed on the second surface of the substrate in the main display area.

9. A method for manufacturing a display device, the method comprising: forming a bottom metal layer on the first surface of the substrate and in a component area of ​​the substrate; forming a packaging substrate on the first surface of the substrate; forming a colored material layer on a second surface of the substrate opposite to the first surface in the component region; exposing a portion of the colored material layer by irradiating light onto the first surface of the substrate on which the bottom metal layer is disposed; as well as forming an anti-reflection layer by developing the exposed portion of the colored material layer, Wherein, in exposing the portion of the colored material layer, the colored material layer is exposed by using the bottom metal layer as a mask.

10. The method according to claim 9, wherein: In forming the colored material layer, the colored material layer is directly formed on the second surface of the substrate.

11. The method according to claim 9, wherein In forming the colored material layer, the colored material layer includes a positive photosensitive material.

12. The method according to claim 9, wherein The anti-reflection layer is formed to overlap the bottom metal layer.

13. The method according to claim 9, wherein: The anti-reflection layer has a first thickness of 1 μm to 3 μm.

14. The method according to claim 9, wherein The bottom metal layer includes a first hole corresponding to a transmission area of ​​the substrate, wherein the anti-reflection layer includes a second hole corresponding to the transmission area, and the first hole and the second hole overlap each other.

15. The method according to claim 9, further comprising: Between forming the bottom metal layer and forming the package substrate, a first thin film transistor and a first display element are formed in the main display area of ​​the substrate, and a second thin film transistor and a second display element are formed on the bottom metal layer in the component area.

16. The method according to claim 15, further comprising: After forming the anti-reflection layer, a protection member is formed on the second surface of the substrate in the main display area.

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