Drive circuit

Abstract

The present invention provides a driving circuit capable of suppressing the voltage drop of a driving signal. The driving circuit includes: a driving signal output circuit, which outputs a pulse signal input to the gate terminal of a first field effect transistor as a driving signal from a signal output terminal, wherein the first field effect transistor drives a device to be controlled; a switching circuit having a switching element and an electrostatic capacitor, wherein the switching element is connected between the gate terminal and the signal output terminal, switches the power-on state between the gate terminal and the signal output terminal, and the electrostatic capacitor applies a voltage corresponding to the accumulated charge to the signal terminal of the switching element; a delay circuit, which switches the state of the switching element between an on state and an off state, delaying the input of the driving signal to the gate terminal; and a reverse current suppression unit, which suppresses the reverse flow of current flowing from the electrostatic capacitor to the driving signal output circuit.

Description

Technical Field

[0001] The invention relates to a driving circuit. Background Art

[0002] Research and development of drive circuits for driving a controlled device that is an object of control are underway.

[0003] In contrast, a drive circuit that drives a controlled device using a field effect transistor is known (see Patent Document 1).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2010-051105 Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] The driving circuit described in Patent Document 1 drives the controlled device by inputting a pulse signal to the gate terminal of the field effect transistor. Here, the driving circuit sometimes includes a delay circuit to delay the input of the pulse signal to the gate terminal. However, when the driving circuit uses the delay circuit to delay the input, the voltage of the pulse signal sometimes drops, and the controlled device cannot be driven at the desired timing.

[0009] The present invention has been made in view of such circumstances, and a technical object of the present invention is to provide a drive circuit capable of suppressing a voltage drop of a drive signal.

[0010] Technical solutions for solving technical problems

[0011] One embodiment of the present invention is a driving circuit, which includes: a driving signal output circuit, which outputs a pulse signal input to the gate terminal of a first field effect transistor from a signal output terminal as a driving signal, wherein the first field effect transistor drives a device as an object to be controlled; a switching circuit having a switching element and an electrostatic capacitor, wherein the switching element is connected between the gate terminal and the signal output terminal, switches the power-on state between the gate terminal and the signal output terminal, and the electrostatic capacitor applies a voltage corresponding to the accumulated charge to the signal terminal of the switching element; a delay circuit, which switches the state of the switching element between an on state and an off state, delaying the input of the driving signal to the gate terminal; and a reverse current suppression unit, which suppresses the reverse flow of current flowing from the electrostatic capacitor to the driving signal output circuit.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to suppress a voltage drop of a driving signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a diagram showing an example of the configuration of the driving circuit 1 according to the embodiment.

[0015] Figure 2 1 is a diagram showing an example of a timing chart when the drive circuit 1 operates.

[0016] Description of Reference Numerals

[0017] 1……driving circuit, C1, C2, C3……capacitor, D1……backflow suppression unit, DC……delay circuit, DCE1, SCE1……first terminal, DCE2, SCE2……second terminal, DCE3, SCE3……third terminal, DCE4, SCE4……fourth terminal, DCE5, SCE5……fifth terminal, G1……gate terminal, GG1, GG2, GG3……gate voltage graph, H1, H2, H3, H4, L1, L2, L3, L4……voltage value, PS……driving signal output circuit, PSE1……first terminal, PSE2……second terminal, R1, R2, R3……resistance element, S1, S2……switch element, SC……switch circuit, SG……driving signal graph, Vth1, Vth2……threshold value. DETAILED DESCRIPTION

[0018] <Implementation Method>

[0019] Below, the embodiments of the present invention are described with reference to the accompanying drawings. Here, in the embodiments, the conductor that transmits an electrical signal corresponding to direct current power or an electrical signal corresponding to alternating current power is referred to as a transmission path for description. The transmission path may be, for example, a conductor printed on a substrate, a wire in which the conductor is formed into a linear shape, or other conductors. In addition, in the embodiments, when referred to as voltage, it refers to the potential difference with the potential serving as a prescribed reference, and the illustration and description of the potential serving as a reference are omitted. Here, the potential serving as a reference may also be an arbitrary potential. In the embodiments, as an example, a case where the potential serving as a reference is a ground potential is described. In addition, in the embodiments, for the sake of convenience of description, the voltage applied to the gate terminal of a field effect transistor is referred to as the gate voltage of the field effect transistor for description.

[0020] <Overview of Driving Circuit>

[0021] First, an overview of the drive circuit of the embodiment is described. The drive circuit includes a drive signal output circuit, a switch circuit, a delay circuit, and a reverse current suppression unit. The drive signal output circuit is a circuit that outputs a pulse signal input to the gate terminal of the first field effect transistor as a drive signal from the signal output terminal. The first field effect transistor is a field effect transistor that drives a device that is an object to be controlled. The switch circuit is connected between the gate terminal and the signal output terminal. The switch circuit is a circuit having a switch element and an electrostatic capacitor. The switch element switches the power-on state between the gate terminal and the signal output terminal. The electrostatic capacitor applies a voltage corresponding to the accumulated charge to the signal terminal of the switch element. The delay circuit is a circuit that switches the state of the switch element between an on state and an off state, delaying the input of the drive signal to the gate terminal. The reverse current suppression unit suppresses the reverse flow of current from the electrostatic capacitor to the drive signal output circuit.

[0022] Therefore, the drive circuit of the embodiment can suppress the voltage drop of the drive signal. Hereinafter, the circuit structure of the drive circuit will be described in detail.

[0023] <Circuit Structure of Driving Circuit>

[0024] Below, refer to Figure 1 , a circuit structure of the driving circuit 1 according to the embodiment will be described. Figure 1 It is a diagram showing an example of the configuration of the driving circuit 1 according to the embodiment.

[0025] The driving circuit 1 is an example of the above-mentioned driving circuit. Figure 1 In the example shown, the drive circuit 1 is connected to the gate terminal G1 of the first field effect transistor. The first field effect transistor is a field effect transistor that drives the controlled device. The controlled device is a device that is controlled by the drive circuit 1. That is, the drive circuit 1 is a circuit that drives the controlled device using the connected first field effect transistor.

[0026] The controlled device is, for example, a motor. In addition, the controlled device may not be a motor but may be another device that can be driven by the drive circuit 1 . Figure 1 In order to avoid complicating the figure, the structure other than the gate terminal G1 of the first field effect transistor is omitted.

[0027] The drive circuit 1 includes, for example, a drive signal output circuit PS, a switch circuit SC, a resistor element R1, a resistor element R2, a delay circuit DC, and a backflow suppression unit D1. In addition, the drive circuit 1 may also include other elements, other circuits, other devices, etc. within the scope of not destroying the function of the drive circuit 1 described below.

[0028] The drive signal output circuit PS has a first terminal PSE1 and a second terminal PSE2. The switch circuit SC has a first terminal SCE1, a second terminal SCE2, a third terminal SCE3, a fourth terminal SCE4, and a fifth terminal SCE5. The delay circuit DC has a first terminal DCE1, a second terminal DCE2, a third terminal DCE3, a fourth terminal DCE4, and a fifth terminal DCE5.

[0029] The first terminal PSE1 of the drive signal output circuit PS is connected to one of the two terminals of the resistor R1 via a transmission path, and the other of the two terminals of the resistor R1 is connected to the first terminal SCE1 of the switch circuit SC via a transmission path.

[0030] In addition, the first terminal DCE1 of the delay circuit DC is connected to the transmission path connecting the drive signal output circuit PS and the resistor element R1 via another transmission path. In addition, the second terminal DCE2 of the delay circuit DC is connected to one of the two terminals of the resistor element R2 via the transmission path. In addition, the other of the two terminals of the resistor element R2 is connected to one of the two terminals of the backflow suppression unit D1 via the transmission path. In addition, the other of the two terminals of the backflow suppression unit D1 is connected to the second terminal SCE2 of the switch circuit SC via the transmission path. In addition, Figure 1 In the example shown, the backflow suppression unit D1 is a diode. Therefore, in this example, the resistor R2 is connected to the anode of the backflow suppression unit D1. In addition, in this example, the second terminal SCE2 of the switch circuit SC is connected to the cathode of the backflow suppression unit D1.

[0031] In addition, the third terminal SCE3 of the switch circuit SC is connected to the third terminal DCE3 of the delay circuit DC via a transmission path. In addition, the transmission path connecting the reverse current suppression unit D1 and the second terminal SCE2 of the switch circuit SC is connected to the transmission path connecting the third terminal SCE3 of the switch circuit SC and the third terminal DCE3 of the delay circuit DC via another transmission path. In addition, the fourth terminal SCE4 of the switch circuit SC is connected to the fourth terminal DCE4 of the delay circuit DC via a transmission path. In addition, the fifth terminal DCE5 of the delay circuit DC is connected to the second terminal PSE2 of the drive signal output circuit PS via a transmission path. In addition, the transmission path connecting the fifth terminal DCE5 of the delay circuit DC and the second terminal PSE2 of the drive signal output circuit PS is connected to ground via another transmission path. Moreover, the fifth terminal SCE5 of the switch circuit SC is connected to the gate terminal G1 of the first field effect transistor via a transmission path.

[0032] Here, the switch circuit SC includes a switch element S1 , a capacitor C1 , and a capacitor C2 .

[0033] The switch element S1 is, for example, a field effect transistor. In addition, the switch element S1 may be other transistors such as a bipolar transistor instead of a field effect transistor. In addition, the switch element S1 may be other switch elements. However, the other switch element has a signal terminal such as a gate terminal of a field effect transistor or a base terminal of a bipolar transistor to which a voltage for controlling the switching of the other switch element is applied.

[0034] The gate terminal of the switching element S1 is connected to the second terminal SCE2 of the switching circuit SC via a transmission path. In addition, the drain terminal of the switching element S1 is connected to the first terminal SCE1 of the switching circuit SC via a transmission path. In addition, the source terminal of the switching element S1 is connected to the fifth terminal SCE5 of the switching circuit SC via a transmission path. In addition, the transmission path connecting the source terminal of the switching element S1 and the fifth terminal SCE5 of the switching circuit SC is connected to one of the two terminals of the capacitor C2 via another transmission path. In addition, the other of the two terminals of the capacitor C2 is connected to the fourth terminal SCE4 of the switching circuit SC via a transmission path. In addition, the transmission path connecting the switching element S1 and the fifth terminal SCE5 of the switching circuit SC is connected to one of the two terminals of the capacitor C1 via another transmission path. In addition, the other of the two terminals of the capacitor C1 is connected to the third terminal SCE3 of the switching circuit SC via a transmission path.

[0035] In addition, the delay circuit DC has a switch element S2, a capacitor C3, and a resistance element R3.

[0036] The switch element S2 is, for example, a field effect transistor. In addition, the switch element S2 may be other transistors such as a bipolar transistor instead of a field effect transistor. In addition, the switch element S2 may be other switch elements. However, the other switch element has a signal terminal such as a gate terminal of a field effect transistor or a base terminal of a bipolar transistor to which a voltage for controlling the switching of the other switch element is applied.

[0037] The gate terminal of the switch element S2 is connected to one of the two terminals of the capacitor C3 via a transmission path. In addition, the other of the two terminals of the capacitor C3 is connected to the first terminal DCE1 of the delay circuit DC via a transmission path. In addition, the transmission path connecting the first terminal DCE1 of the delay circuit DC and the capacitor C3 is connected to the second terminal DCE2 of the delay circuit via another transmission path. In addition, the transmission path connecting the gate terminal of the switch element S2 and the capacitor C3 is connected to one of the two terminals of the resistor R3 via another transmission path. In addition, the other of the two terminals of the resistor R3 is connected to the fifth terminal DCE5 of the delay circuit DC via a transmission path. In addition, the source terminal of the switch element S2 is connected to the fourth terminal DCE4 of the delay circuit DC via a transmission path. In addition, the transmission path connecting the fifth terminal DCE5 of the delay circuit DC and the resistor R3 is connected to the transmission path connecting the source terminal of the switch element S2 and the fourth terminal DCE4 of the delay circuit DC via another transmission path. Furthermore, a drain terminal of the switch element S2 is connected to a third terminal DCE3 of the delay circuit DC via a transmission path.

[0038] Here, the drive signal output circuit PS is, for example, an IC (Integrated Circuit) that outputs a pulse signal. In addition, the drive signal output circuit PS may not be an IC, but may be another circuit or another device that can output a pulse signal. The drive signal output circuit PS outputs the pulse signal output to the gate terminal G1 of the first field effect transistor as a drive signal from the first terminal PSE1.

[0039] In addition, if Figure 1 As shown, the switch element S1 is connected between the gate terminal G1 of the first field effect transistor and the first terminal PSE1 of the drive signal output circuit PS. Therefore, the switch element S1 is a switch element that switches the power-on state between the gate terminal G1 and the first terminal PSE1. When the gate voltage of the switch element S1 is above a predetermined threshold value Vth1, the switch element S1 electrically conducts between the gate terminal G1 and the first terminal PSE1. In other words, in this case, the state of the switch element S1 is the on state. In addition, when the gate voltage of the switch element S1 is lower than the threshold value Vth1, the switch element S1 electrically insulates between the gate terminal G1 and the first terminal PSE1. In other words, in this case, the state of the switch element S1 is the off state. Here, the threshold value Vth1 is a value determined according to the characteristics of the switch element S1.

[0040] Capacitor C1 is a capacitor having a predetermined electrostatic capacitance. Capacitor C1 applies a voltage corresponding to the charge accumulated in the electrostatic capacitance to the gate terminal of the switching element S1. In addition, when the parasitic capacitance of the switching element S1 is greater than the electrostatic capacitance of the capacitor C1, the switching circuit SC may also be a structure without the capacitor C1. This is because, in this case, the parasitic capacitance of the switching element S1 acts as a substitute for the electrostatic capacitance of the capacitor C1. In the following, for the sake of convenience, the electrostatic capacitance of the capacitor C1 and the parasitic capacitance of the switching element S1 are collectively referred to as the electrostatic capacitance of the switching circuit SC.

[0041] The capacitor C2 sets the voltage applied to the gate terminal of the switching element S1 to a predetermined threshold value Vth1 or higher according to the capacitive voltage division of the parasitic capacitance of the switching element S1 and the electrostatic capacitance of the capacitor C1. In addition, when the parasitic capacitance between the gate terminal of the first field effect transistor and the source terminal of the first field effect transistor is sufficiently large, the switching circuit SC may be configured without the capacitor C2.

[0042] Here, depending on the electrostatic capacitance of the switch circuit SC, the voltage of the third terminal SCE3 of the switch circuit SC may become higher than the voltage of the first terminal PSE1 of the drive signal output circuit PS. In this case, a reverse flow of current from the third terminal SCE3 to the first terminal PSE1 occurs. In other words, in this case, a reverse flow of current from the electrostatic capacitance of the switch circuit SC to the drive signal output circuit PS occurs. The reverse flow suppression unit D1 suppresses the reverse flow of current from the electrostatic capacitance of the switch circuit SC to the drive signal output circuit PS. Figure 1 In the example shown, the backflow suppressor D1 is a diode as described above. In addition, the backflow suppressor D1 may not be a diode but may be another element (eg, a switching element) capable of suppressing the backflow of the current flowing from the electrostatic capacitance of the switching circuit SC to the drive signal output circuit PS.

[0043] The delay circuit DC switches the state of the switch element S1 between the on state and the off state. More specifically, the delay circuit DC switches the state of the switch element S1 between the on state and the off state according to the state of the switch element S2. Thus, the delay circuit DC delays the input of the drive signal from the drive signal output circuit PS to the gate terminal G1 of the first field effect transistor.

[0044] In this manner, the delay circuit DC and the backflow suppression unit D1 are connected between the first terminal PSE1 and the gate terminal of the switching element S1 .

[0045] According to the above circuit structure, the driving circuit 1 suppresses the voltage drop of the driving signal. Figure 2 The operation of the drive circuit 1 will be described in more detail. In addition, the drive circuit 1 may be configured not to include at least one of the resistance element R1 and the resistance element R2.

[0046] <Operation of the driving circuit>

[0047] Figure 2 FIG. 1 is a diagram showing an example of a timing chart when the drive circuit 1 operates. Figure 2 In the figure, the driving signal curve SG, the gate voltage curve GG1, the gate voltage curve GG2, and the gate voltage curve GG3 are respectively Figure 2 Arranged in order from top to bottom. Here, the drive signal graph SG is a graph showing the change in the voltage value of the pulse signal output from the first terminal PSE1 of the drive signal output circuit PS as a drive signal. The gate voltage graph GG1 is a graph showing the change in the voltage value of the gate voltage of the switching element S2. The gate voltage graph GG2 is a graph showing the change in the voltage value of the gate voltage of the switching element S1. The gate voltage graph GG3 is a graph showing the change in the voltage value of the gate voltage of the first field effect transistor. In addition, the vertical axis of the drive signal graph SG, the gate voltage graph GG1, the gate voltage graph GG2, and the gate voltage graph GG3 respectively represents the voltage value. In addition, the vertical axis of the drive signal graph SG, the gate voltage graph GG1, the gate voltage graph GG2, and the gate voltage graph GG3 respectively represents the elapsed time. In addition, in the gate voltage graph GG3, in order to clearly represent the action of the first field effect transistor, the change in the voltage value of the gate voltage of the first field effect transistor that does not exceed the threshold value of the voltage value is omitted. Here, the threshold value is a voltage value of the gate voltage that is a limit of switching the state of the first field effect transistor from an off state to an on state.

[0048] Here, hereinafter, for the convenience of explanation, the maximum value of the voltage value in the drive signal curve graph SG (for example, 4.5 [V]) is referred to as voltage value H1 for explanation. In addition, hereinafter, for the convenience of explanation, the minimum value of the voltage value is referred to as voltage value L1 for explanation. In addition, hereinafter, for the convenience of explanation, the maximum value of the voltage value in the gate voltage curve graph GG1 is referred to as voltage value H2 for explanation. In addition, hereinafter, for the convenience of explanation, the minimum value of the voltage value is referred to as voltage value L2 for explanation. In addition, hereinafter, for the convenience of explanation, the maximum value of the voltage value in the gate voltage curve graph GG2 is referred to as voltage value H3 for explanation. In addition, hereinafter, for the convenience of explanation, the minimum value of the voltage value is referred to as voltage value L3 for explanation. In addition, hereinafter, for the convenience of explanation, the maximum value of the voltage value in the gate voltage curve graph GG3 (for example, above 3.5 [V]) is referred to as voltage value H4 for explanation. In addition, hereinafter, for the convenience of explanation, the minimum value of the voltage value is referred to as voltage value L4 for explanation.

[0049] In the drive circuit 1, as described above, when the voltage value of the gate voltage of the switching element S1 is greater than the threshold value Vth1, the state of the switching element S1 is the on state. On the other hand, when the voltage value is lower than the threshold value Vth1, the state of the switching element S1 is the off state. In addition, in the drive circuit 1, when the voltage value of the gate voltage of the switching element S2 is greater than the threshold value Vth2, the state of the switching element S2 is the on state. On the other hand, when the voltage value is lower than the threshold value Vth2, the state of the switching element S2 is the off state. Moreover, in the drive circuit 1, the drive signal output circuit PS outputs the drive signal, thereby accumulating charge in the electrostatic capacitance of the switch circuit SC.

[0050] Here, when charges are accumulated in the electrostatic capacitor of the switch circuit SC and the switch element S2 is in the off state, there is no path for the charges accumulated in the electrostatic capacitor of the switch circuit SC to flow to the ground in the drive circuit 1. Therefore, in the drive circuit 1, when charges are accumulated in the electrostatic capacitor of the switch circuit SC, as long as the switch element S2 is in the off state, the state of the switch element S1 remains in the on state except when the gate voltage of the switch element S1 rises. As a result, Figure 2 In the timing chart shown, when the gate voltage of the switching element S2 is lower than the threshold value Vth2, the gate voltage of the switching element S1 is maintained at the voltage value H3 except when the gate voltage of the switching element S1 rises.

[0051] In addition, in the driving circuit 1, the voltage value of the gate voltage of the switching element S2 of the delay circuit DC begins to increase as the output of the driving signal from the first terminal PSE1 by the driving signal output circuit PS increases. Then, when the voltage value becomes greater than the threshold value Vth2, the state of the switching element S2 becomes the on state. However, the increase in the voltage value of the gate voltage of the switching element S2 of the delay circuit DC is generated in the following manner, that is, the high-frequency component of the driving signal output by the driving signal output circuit PS increases the current flowing to the resistor element R3 through the capacitor C3. Therefore, the high-frequency component passing through the capacitor C3 begins to decrease and the current flowing to the resistor element R3 decreases, and the voltage value of the gate voltage of the switching element S2 of the delay circuit DC begins to decrease. For this reason, in Figure 2 In the period when the voltage value exceeds the threshold value Vth2, the voltage value changes in an upward convex shape. Figure 2 In the figure, the period during which the switch element S2 is turned on due to the high frequency component passing through the capacitor C3 is represented as "Delay Time (Dead Time)". Hereinafter, for convenience of explanation, this period will be referred to as delay time.

[0052] In addition, in the drive circuit 1, as the voltage value of the gate voltage of the switch element S2 increases, the voltage value of the gate voltage of the switch element S1 decreases to a voltage value L3. As a result, the state of the switch element S1 becomes an off state. Therefore, during the delay time, the state of the switch element S1 remains in an off state except when the voltage value of the gate voltage of the switch element S2 increases. Here, the delay time starts according to the rise of the output of the drive signal from the first terminal PSE1 by the drive signal output circuit PS. That is, when the drive signal output circuit PS outputs the drive signal, the drive circuit 1 maintains the voltage value of the gate voltage of the first field effect transistor at a voltage value L4 from the moment when the drive signal is output to the time when the delay time passes. In other words, the drive circuit 1 delays the input of the drive signal to the gate terminal of the first field effect transistor from that moment to the time when the delay time passes.

[0053] Then, after the delay time, the voltage value of the gate voltage of the switching element S2 is lower than the threshold value Vth2. Therefore, the voltage value of the gate voltage of the switching element S1 increases to a voltage value H3. As a result, the voltage value of the gate voltage of the first field effect transistor exceeds the threshold value Vth1 and increases to a voltage value H4. As a result, after the delay time, the drive circuit 1 inputs a pulse signal of a voltage having a voltage value of H4 to the gate terminal G1 of the first field effect transistor. In addition, in the drive circuit 1, the period during which the voltage value of the gate voltage is maintained at a voltage value H4 can be adjusted by adjusting the pulse width of the drive signal output from the drive signal output circuit PS. That is, by adjusting the pulse width, the drive circuit 1 can input the drive signal after the pulse width is adjusted to the desired pulse width to the gate terminal G1 of the first field effect transistor. Below, the drive signal after the pulse width is adjusted to the desired pulse width is referred to as an effective drive signal for explanation.

[0054] In addition, when the current flows back from the electrostatic capacitor of the switch circuit SC to the drive signal output circuit PS, the voltage of the effective drive signal will drop. As a result, when the effective drive signal is input to the gate terminal G1, the state of the first field effect transistor sometimes does not become the on state. However, in the drive circuit 1, the reverse flow of the current from the electrostatic capacitor of the switch circuit SC to the drive signal output circuit PS is suppressed by the reverse flow suppression unit D1. That is, in the drive circuit 1, the voltage of the effective drive signal will not drop due to the reverse flow of the current from the electrostatic capacitor of the switch circuit SC to the drive signal output circuit PS. As a result, the drive circuit 1 can suppress the situation where the state of the first field effect transistor cannot be switched from the off state to the on state at the desired time.

[0055] As described above, the driving circuit 1 can suppress the voltage drop of the effective driving signal. As a result, for example, in the driving circuit 1, even when the voltage value of the driving signal is low, pulse missing can be suppressed and the state of the first field effect transistor can be switched from the off state to the on state at a desired time.

[0056] In addition, in a drive circuit different from the drive circuit 1, for example, an IC such as a drive signal output circuit PS is used to generate a drive signal. However, the minimum pulse width that can be generated by the IC is determined for each individual according to the characteristics of the IC. Therefore, the drive circuit sometimes supplies excessive electric energy to the device driven by the drive circuit. As a result, a malfunction sometimes occurs in the device. In contrast, the drive circuit 1 is capable of inputting an effective drive signal of a desired pulse width to the gate terminal G1 of the first field effect transistor as described above. This means that the drive circuit 1 is capable of inputting a pulse signal that is shorter than a pulse signal of the minimum pulse width that can be generated by the drive signal output circuit PS as an effective drive signal to the gate terminal G1. As a result, the drive circuit 1 is capable of suppressing the excessive supply of electric energy to the device driven by the first field effect transistor. In addition, in Figure 2 The period indicated by "Min On Time" in FIG. 1 is an example of the minimum pulse width that can be generated by the drive signal output circuit PS. Figure 2 In the example shown, the pulse width of the effective drive signal is shorter than the minimum pulse width that can be generated by the drive signal output circuit PS.

[0057] According to the structure and operation as described above, the drive circuit 1 can suppress the voltage drop of the drive signal. In addition, the drive circuit 1 can also be regarded as a circuit that generates an effective drive signal and supplies the effective drive signal to the gate terminal G1 of the first field effect transistor using two pulse signals, wherein the two pulse signals are a pulse signal through a transmission path connected between the first terminal PSE1 of the drive signal output circuit PS and the first terminal SCE1 of the switch circuit SC, and a pulse signal through a transmission path connected between the first terminal PSE1 and the first terminal DCE1 of the delay circuit DC. When regarded as such, the drive circuit 1 of the embodiment is an example of a drive circuit 1 in which the two pulse signals are generated by branching from one pulse signal. In addition, in this case, the two pulse signals can also be output from signal sources different from each other.

[0058] In addition, the driving circuit 1 described above can also be synchronized with the signals output by other circuits and output a driving signal of a desired pulse width to the controlled device by adjusting the delay time based on the delay circuit DC and the pulse width of the driving signal based on the driving signal output circuit PS.

[0059] As described above, the driving circuit of the embodiment (in the example described above, the driving circuit 1) includes: a driving signal output circuit (in the example described above, the driving signal output circuit PS), which outputs a pulse signal input to the gate terminal of the first field effect transistor (in the example described above, the gate terminal G1) as a driving signal from the signal output terminal (in the example described above, the first terminal PSE1), wherein the first field effect transistor drives a device that is an object to be controlled (in the example described above, the controlled device); a switching circuit having a switching element (in the example described above, the switching element S1) and an electrostatic capacitor (in the example described above, the electrostatic capacitor of the switching circuit SC) (In the example described above, the switch circuit SC), wherein the switch element is connected between the gate terminal and the signal output terminal, and the power-on state between the gate terminal and the signal output terminal is switched, and the electrostatic capacitor applies a voltage corresponding to the accumulated charge to the signal terminal of the switch element (in the example described above, the gate terminal of the switch element S1 or the base terminal of the switch element S1); a delay circuit (in the example described above, the delay circuit DC), which switches the state of the switch element between the on state and the off state, delaying the input of the drive signal to the gate terminal; a backflow suppression unit (in the example described above, the backflow suppression unit D1), which suppresses the backflow of the current flowing from the electrostatic capacitor to the drive signal output circuit. As a result, the drive circuit can suppress the voltage drop of the drive signal.

[0060] In the drive circuit, the switching element may be a second field effect transistor (in the example described above, the switching element S1 is a field effect transistor), and the signal terminal may be a gate terminal of the second field effect transistor.

[0061] In the drive circuit, the switching element may be a transistor (in the example described above, the switching element S1 may be a transistor other than a field effect transistor such as a bipolar transistor) and the signal terminal may be a base terminal of the transistor.

[0062] In the drive circuit, a configuration may be adopted in which the switch circuit includes a capacitor (capacitor C1 in the example described above) that is separate from the switch element, and the capacitance of the switch circuit includes the capacitance of the capacitor.

[0063] In addition, in the driving circuit, a configuration may be adopted in which the electrostatic capacitance of the switching circuit includes the parasitic capacitance of the switching element.

[0064] In addition, in the driving circuit, a delay circuit and a backflow suppressing section may be connected between the signal output terminal and the signal terminal, and the backflow suppressing section may be a diode.

[0065] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the specific structure is not limited to the embodiments and changes, replacements, deletions, etc. may be made without departing from the concept of the invention.

Claims

1. A driving circuit, characterized in that: include: A driving signal output circuit having a signal output terminal; Switching circuit; Delay circuit; as well as Backflow suppression unit, The drive signal output circuit outputs a pulse signal input to a gate terminal of a first field effect transistor from the signal output terminal, wherein the first field effect transistor drives a device to be controlled; The switch circuit includes a switch element, the switch element includes a first terminal for inputting the pulse signal from the signal output terminal, a second terminal for outputting the pulse signal to the gate terminal, and a control terminal for controlling a conduction state between the first terminal and the second terminal, and the switch circuit includes an electrostatic capacitor between the second terminal and the control terminal. The delay circuit is connected between the signal output terminal and the control terminal to delay the pulse signal and output it to the control terminal. The backflow suppression unit is connected between the signal output terminal and the control terminal, and suppresses a backflow of current flowing from the control terminal to the signal output terminal.

2. The driving circuit according to claim 1, wherein: The switching element is a second field effect transistor, The control terminal is a gate terminal of the second field effect transistor.

3. The driving circuit according to claim 1, wherein: The switching element is a transistor, The control terminal is a base terminal of the transistor.

4. The driving circuit according to any one of claims 1 to 3, characterized in that: The switch circuit includes a capacitor separate from the switch element. The electrostatic capacitance of the switch circuit includes the electrostatic capacitance of the capacitor.

5. The driving circuit according to any one of claims 1 to 3, characterized in that: The electrostatic capacitance of the switching circuit includes the parasitic capacitance of the switching element.

6. The driving circuit according to claim 4, characterized in that: The electrostatic capacitance of the switching circuit includes the parasitic capacitance of the switching element.

7. The driving circuit according to any one of claims 1 to 3, characterized in that: The delay circuit and the backflow suppression unit are connected between the signal output terminal and the control terminal. The backflow suppression unit is a diode.

8. The driving circuit according to claim 4, wherein: The delay circuit and the backflow suppression unit are connected between the signal output terminal and the control terminal. The backflow suppression unit is a diode.

9. The driving circuit according to claim 5, characterized in that: The delay circuit and the backflow suppression unit are connected between the signal output terminal and the control terminal. The backflow suppression unit is a diode.

10. The driving circuit according to claim 6, wherein: The delay circuit and the backflow suppression unit are connected between the signal output terminal and the control terminal. The backflow suppression unit is a diode.

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