Device for automatic detection and calibration of loop gain

Abstract

The present invention discloses a device for automatically detecting and calibrating loop gain. The device includes a phase detector, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector detects a clock offset between a reference signal and an input signal. The charge pump circuit converts the clock offset into a voltage. The sample and hold circuit samples the voltage at a first time and holds the sampled voltage until a second time. The comparator (i) detects the loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjusting the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling the operations of the phase detector, the comparator, and the sample and hold circuit.

Description

Technical Field

[0001] The technology described in the embodiments of the present invention generally relates to electronic systems, and more specifically, to a circuit system for automatically calibrating loop gain using a loop gain detector. Background Art

[0002] Loop gain can be used to analyze the signal flow through a control system such as a circuit. Loop gain is a mathematical representation of the circuit behavior. A loop gain of 1 indicates that the control system is operating optimally. Summary of the Invention

[0003] Embodiments of the present invention provide an apparatus for automatically detecting and calibrating loop gain, including: a first phase detector configured to detect a clock offset between a reference signal and an input signal; a charge pump circuit configured to convert the clock offset into a voltage; a sample and hold circuit configured to sample the voltage at a first time and hold the sampled voltage until a second time; a comparator configured to (i) detect the loop gain associated with the input signal based on the sampled voltage and the voltage detection, and (ii) output a loop gain signal for adjusting the input signal; and a controller coupled to the first phase detector, the comparator, and the sample and hold circuit, the controller being configured to generate a plurality of control signals for automatically controlling the operations of the first phase detector, the comparator, and the sample and hold circuit. Brief Description of the Drawings

[0004] Various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0005] Figure 1 An exemplary block diagram of a loop gain calibration system according to various embodiments described herein is shown.

[0006] Figure 2 An exemplary block diagram of a loop gain detector according to various embodiments described herein is shown.

[0007] Figure 3 An exemplary timing diagram of a phase detector signal according to various embodiments described herein is shown.

[0008] Figure 4 An exemplary circuit schematic of a charge pump circuit according to various embodiments described herein is shown.

[0009] Figure 5Shows an exemplary timing diagram of signals of an exemplary controller of a loop gain detector and an exemplary loop gain detector according to various embodiments set forth herein.

[0010] Figure 6 Shows another exemplary timing diagram of signals of a loop gain detector according to various embodiments set forth herein.

[0011] Figure 7 Shows an exemplary block diagram of a loop gain calibration system according to various embodiments set forth herein.

[0012] Figure 8 Shows an exemplary flowchart of various tunings of a calibration controller according to various embodiments set forth herein.

[0013] Figure 9 Shows an exemplary graph of tuning loop gain according to various embodiments set forth herein.

[0014] Figure 10 Shows according to various embodiments set forth herein, with Figure 9 An exemplary flowchart of the operation of a calibration controller corresponding to the graph of.

[0015] Figure 11 Shows an exemplary block diagram of a multi-stage loop gain calibration system according to various embodiments set forth herein.

[0016] Figure 12 Shows a process flowchart of loop gain automatic calibration of a delta-sigma time-to-digital converter (ΔΣ TDC) according to various embodiments set forth herein. Detailed Description

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature "on" or "above" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. This reuse is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] It may be difficult to determine the loop gain of a control system in real time, which requires precise voltage measurements within a specific time frame (e.g., pico-granularity is required). Manual detection of loop gain can be both difficult and time-consuming. Additionally, appropriately modifying the control system to adjust the gain may require manual intervention. Using a loop gain detector as described herein can provide automatic measurement and proper adjustment of the loop gain.

[0019] Figure 1 FIG. shows an exemplary block diagram of a loop gain calibration system 100 according to various embodiments described herein. The loop gain calibration system 100 may include a circuit 110, a loop gain detector 120, and in some embodiments, a calibration controller 130. The circuit 110 may be a time-to-digital converter (TDC) in some embodiments. The TDC is used in a circuit device to monitor circuit events and output a digital representation of the corresponding times at which these events occur. The TDC can be used in a variety of applications, including detecting and / or measuring the noise of a circuit having, for example, a phase-locked loop (PLL). The circuit 110 receives input signals, such as a reference signal Fref and signals having various clock offsets Δθ (e.g., Fref + Δθ, Fref - Δθ). The circuit 110 detects the phase difference between these signals in the time domain. The phase difference is converted by the circuit 110 into a digital output signal DO (e.g., logic low '0' or logic high '1'). The loop gain detector 120 is coupled to the circuit 110. The loop gain detector 120 can automatically detect the loop gain associated with the circuit 110. Based on the detected loop gain, the loop gain detector 120 can generate an adjustment indicator (e.g., com_out), which the circuit 110 uses to adjust the loop gain. In some embodiments, the calibration controller 130 is coupled between the loop gain detector 120 and the circuit 110. The calibration controller 130 can provide coarse and / or fine tune adjustments to the gain based on the adjustment indicator. In an alternative embodiment, the adjustment indicator (e.g., com_out) can be provided to the circuit 110 to modify the loop gain.

[0020] Figure 2 FIG. shows an exemplary block diagram of a loop gain detector 200 according to various embodiments described herein. The loop gain detector 200 detects the loop gain of the circuit 110 to which it is coupled and outputs an indicator signal (e.g., com_out) back to the circuit 110. The indicator signal indicates whether the circuit 110 needs to be adjusted to increase or decrease the gain, as in Figure 7This is elaborated in more detail below. The indicator signal is a logical output. When the indicator signal is logic high, circuit 110 is adjusted to reduce the gain. When the indicator signal is logic low, circuit 110 is adjusted to increase the gain. Loop gain detector 200 includes a controller 210, at least two phase detectors (PDs) 220, 230, a charge pump (CP) 240, a capacitor 250, a sample-and-hold (S / H) component 260, and a comparator 270.

[0021] Controller 210 generates various control signals for controlling PDs 220, 230, the sample-and-hold component 260, and comparator 270. Controller 210 receives a reference signal Fref. Using the reference signal Fref, controller 210 generates a plurality of control signals, including an S / H control signal (e.g., FSH) for the S / H component 260, a PD control signal (e.g., FUP) for PD 220, another PD control signal (e.g., FDN) for PD 230, and a comparator control signal (e.g., FCOM) for comparator 270. PDs 220, 230 detect various phase errors or clock offsets (e.g., Δθ, Δα, and Δβ), and output a rising signal (e.g., UP) and a falling signal (e.g., DN), respectively. As elaborated in Figure 3 more detail below, CP 240 receives the rising signal or the falling signal, and converts the detected clock offset into a voltage change ΔV.

[0022] The sample-and-hold (S / H) circuit 260 is a standby voltage holder. When triggered by an input signal (e.g., FSH), the S / H circuit 260 operates. When operating, the S / H circuit 260 samples the voltage of the loop at a specific time, and holds and outputs the voltage VSH until the next sampling. In other words, when operating, the output voltage of the S / H circuit 260 is equal to the voltage measured across the capacitor 250 (e.g., VC). Comparator 270 compares the capacitor voltage VC with the previous voltage VSH sampled by the S / H circuit 260. Through this comparison, comparator 270 detects the loop gain of the system from which the input signal FD originates. Comparator 270 outputs an adjustment indicator (e.g., com_out) that reflects the loop gain of circuit 110. The loop gain signal can be used as the adjustment indicator. The loop gain signal is fed back to circuit 110, as elaborated in Figure 7 more detail below.

[0023] Figure 3Exemplary timing diagram 300 of the phase detector signals of phase detectors 220, 230 in accordance with various embodiments set forth herein is shown. The timing diagram 300 includes a series of graphs (a) through (f) showing various signals within the phase detectors 220, 230. Graph (a) shows the reference signal Fref - Δθ with a negative offset constant clock offset. Graph (b) shows the reference signal Fref. Graph (c) shows the reference signal Fref + Δθ with a positive offset constant clock offset. Graph (d) shows the input signal FD. Graph (e) shows the output signal from PD 220. Graph (f) shows the output signal from PD 230.

[0024] PD 220 is used to detect the falling edge (e.g., a transition from logic high to logic low) of the reference signal Fref. PD 220 determines the clock offset associated with the falling edge by taking the difference between the reference signal Fref in graph (b) and the input signal FD in graph (d). For example, as Figure 3 shown, the falling edges of the reference signal Fref occur at points 310, 340. When the input signal FD of PD 220 lags behind the reference signal Fref, a clock offset Δβ occurs. When one signal reaches its maximum peak after another signal reaches its maximum peak, the signal is said to be "lagging". The clock offset Δβ is approximately equal to the distance between the falling edge of the reference signal Fref at point 310 and the falling edge of the input signal FD at point 320. When the input signal FD of PD 220 leads the reference signal Fref, a clock offset Δα occurs. When one signal reaches its maximum peak before another signal reaches its maximum peak, the signal is said to be "leading". The clock offset Δα is approximately equal to the distance between the falling edge of the input signal FD at point 330 and the falling edge of the reference signal Fref at point 340. PD 220 detects these clock offsets Δβ or Δα and outputs a signal UP that reflects the detected clock offset. For example, as shown in graph (e), between points 310 and 320, the clock offset Δβ is reflected. Similarly, in the signal UP of graph (e), between points 330 and 340, the clock offset Δα is reflected. The signal UP is provided to CP 240 to control its operation, as more Figure 4 detailedly elaborated in

[0025] PD 230 outputs a signal DN based on the difference between the reference signal Fref in graph (b) and the reference signal offset by a constant clock offset Δθ. Since this difference is the constant clock offset Δθ, as shown in graph (f), the DN signal outputs Δθ between points 310 and 350. The signal DN is provided to CP 240 to control its operation, as more Figure 4 detailedly elaborated in

[0026] Figure 4 Exemplary circuit schematic of CP 400 showing various embodiments described herein. CP 400 converts the clock offsets output by PDs 220, 230 into voltages. CP 400 may belong to circuit 110 and / or loop gain detector 200. When used in loop gain detector 200, CP 400 is coupled between PDs 220, 230 and capacitor 250. When clock offsets Δα and / or Δβ are detected, CP 400 charges capacitor 450. When clock offset Δθ is detected, CP 400 discharges capacitor 450. CP 400 includes switches 410, 420 and current sources 430, 440. When there is a clock offset Δα or Δβ in the signal UP from PD 220, switch 410 closes and current source 430 (e.g., I) drives current into capacitor 450. The presence of this current charges capacitor 450. This in turn generates a voltage VC across capacitor 450. The charge Q generated by the current driven by signal UP UP can be expressed as follows:

[0027] Q UP = I(Δ∝) + I(Δβ) (1)

[0028] When there is a constant clock offset Δθ in the signal DN from PD 220, switch 420 closes and current source 440 (e.g., I) reduces the current in capacitor 450. This reduction discharges capacitor 450. The presence of this current also reduces the voltage VC across capacitor 450. The discharge Q generated by the current driven by signal DN DN can be expressed as follows:

[0029] Q DN = I(Δθ) (2)

[0030] There may be times when both clock offsets (i) Δα or Δβ and (ii) Δθ are present simultaneously (e.g., between point 320 and point 350 in Figure 3 ). Under these conditions, both switches 410 and 420 are closed. The voltage across capacitor 450 remains at the voltage level just before both switches 410 and 420 are closed. This is because the charging rate of capacitor 450 is approximately equal to the discharging rate. In other words, the following expression holds:

[0031] Q DN = Q UP (3)

[0032] When coupled to a system of the loop gain detector (e.g., system 100 in Figure 1 or Figure 7When the loop gain of the system 700) is equal to 1, the above expression will occur. When the loop gain of the system is equal to 1, the following expression also holds:

[0033] Δ∝ + Δβ = Δθ (4)

[0034] Figure 5 FIG. 500 is an exemplary timing diagram showing the controller 210 and the loop gain detector 200 in accordance with various embodiments described herein. The controller 210 generates approximately four different control signals: an S / H control signal (e.g., FSH) for the S / H component 260, a PD control signal (e.g., FUP) for the PD 220, another PD control signal (e.g., FDN) for the PD 230, and a comparator control signal (e.g., FCOM) for the comparator 270. Each control signal controls various operations of the loop gain detector 200: a sample and hold operation, a discharge operation, a charge operation, and a comparison operation. Graphs (g) through (k) show various signals associated with the controller 210. Graph (g) shows the reference signal Fref. Graph (h) shows the control signal (e.g., FSH) for the sample and hold operation. Graph (i) shows the control signal (e.g., FDN) for the discharge operation. The control signal (e.g., FUP) for the charge operation is shown in graph (j). The comparison operation control signal (e.g., FCOM) is shown in graph (k).

[0035] Graphs (l) through (n) show the signals generated by the loop gain detector 200. Graph (l) shows the output signal UP from the PD 220. Graph (m) shows the output signal DN from the PD 230. The voltage signal VC generated by the capacitor 250 and the voltage signal generated by the S / H component 260 are shown in graph (n).

[0036] Each control signal is generated by the controller 210 based on the reference signal Fref. As shown in graph (g), the reference signal Fref iterates through a plurality of cycles (e.g., 510, 520, 530, 540, 550, 560). During each cycle, the reference signal Fref is logic high (e.g., '1') for approximately half a cycle and logic low (e.g., '0') for approximately half a cycle. During the first cycle 510, the controller 210 generates a logic high for the control signal FSH. When FSH is logic high, the S / H component 260 operates. The operation of the S / H component 260 samples its input voltage (e.g., the voltage VC of the capacitor 250). When sampling occurs, the S / H component 260 outputs a voltage VSH equal to the voltage VC of the capacitor 250 (as Figure 5as shown in the graph (n). When the control signal FSH is logic high, sampling occurs throughout the duration of cycle 510. In this example, when the controller 210 generates a logic low for the control signal FSH, sampling stops at the start of cycle 520. The S / H component 260 holds the last sampled voltage until the next sampling cycle. As shown by the solid line in graph (n), the voltage level VSH output by the S / H component 260 is held during cycles 510 to 550. The controller 210 holds the logic low of the control signal FSH until cycle 560. When cycle 560 starts, the controller 210 generates another logic high for the control signal FSH, and sampling starts again. During cycle 560, the S / H control signal FSH returns to logic high. At this time, the voltage output by the S / H component 260 increases to the same voltage VC held by the capacitor 250, as shown by the dashed line in graph (n).

[0037] After the first sample and hold operation, the capacitor 450 discharges during cycle 520. To facilitate the discharge, as Figure 4 described, it is necessary to detect a constant clock offset Δθ, which triggers the closing of the switch 420. The detection of Δθ occurs when the PD 230 is operating. The control signal FDN controls the operation of the PD 230. When the control signal FDN is logic high, for example, during cycle 520, the PD 230 operates. As Figure 4 described, when a constant clock offset Δθ is detected (e.g., when the output signal DN of the PD 230 is logic high), the capacitor 450 discharges. As shown in graph (m), during cycle 520, a constant clock offset Δθ is detected at approximately half way to the cycle. As shown in graph (n), the corresponding voltage drop across the capacitor 450 (e.g., VC) occurs when the constant clock offset Δθ is detected, where the dashed line is the capacitor voltage VC and the solid line is the voltage output by the S / H component 260. For one cycle of the reference signal Fref (e.g., cycle 520), the operation of the PD 230 is enabled by the control signal DN.

[0038] During the next two cycles of the reference signal Fref (e.g., cycles 530, 540), the capacitor 450 is charged. These two cycles allow the detection of two different clock offsets (e.g., Δα and Δβ). The controller 210 generates a logic high for the control signal FUP, which controls the operation of the PD 220, as shown in graph (j). When the control signal FUP is logic high, the PD 220 is operating. As Figure 4As discussed in detail, when switch 410 is closed, capacitor 450 is charged. The closing of switch 410 is triggered when clock offsets Δα or Δβ are detected. When clock offsets Δα or Δβ are detected, PD 220 generates an output signal reflecting the offset, as shown in graph (l). When there are clock offsets Δα or Δβ, switch 410 closes and capacitor 450 is charged. Charging capacitor 450 in turn increases the capacitor voltage VC. As shown in graph (n), when clock offset Δα is detected in graph (l) during period 530, the capacitor voltage VC, shown by the dashed line in graph (n), also increases. When clock offset Δα is no longer detected (e.g., when signal UP is logic low), the voltage level VC of the capacitor is held. When clock offset Δβ is detected during period 540, capacitor 450 is also charged. This charging is illustrated by the increase in the capacitor voltage VC in graph (n) during period 540.

[0039] Once capacitor 450 is charged, controller 210 can generate a logic high for control signal FCOM of comparator 270. When there is a logic high control signal FCOM, comparator 270 operates. As previously described in Figure 2 Comparator 270 compares the voltage levels between capacitor voltage VC (e.g., the current capacitor voltage) and S / H component voltage VSH (e.g., the previous capacitor voltage). In other words, comparator 270 evaluates the signal difference between the solid line and the dashed line in graph (n). If capacitor voltage VC is less than S / H component output voltage VSH, then the following expression applies:

[0040] Δ∝ + Δβ < Δθ (5)

[0041] The expression in Equation (5) indicates that the loop gain needs to be reduced. The output of comparator 270 (e.g., com_out) is set to logic high. If capacitor voltage VC is greater than S / H component output voltage VSH, then the following expression applies:

[0042] Δ∝ + Δβ > Δθ (6)

[0043] The expression in Equation (6) indicates that the loop gain needs to be increased. The output of comparator 270 (e.g., com_out) is set to logic low. The loop gain adjustment continues until the ideal loop gain reflected by Equation (4) is achieved.

[0044] Figure 6 Another exemplary timing diagram 600 of loop gain detector 200 according to various embodiments described herein is shown. Graphs (o) to (s) are similar to Figure 5 graphs (g) to (k) described in Figure 5The curves (l) to (n) described in. Under actual operating conditions, the comparator 270 may not function as an ideal comparator. The voltage difference ΔV between the capacitor voltage VC and the S / H component voltage VSH may be too small for the comparator 270 to detect correctly. In other words, the comparator 270 may not be able to correctly identify the voltage difference ΔV. To avoid too small a voltage difference ΔV, in some embodiments, the controller 210 may accumulate the charge of the capacitor 250 (e.g., Q UP and Q DN ) over a large number of cycles (e.g., 100 to 1000 cycles, 800 to 8000 cycles, 7000 to 17000 cycles). The controller 210 may be designed to make the operation cycles of Q UP and Q DN more flexible. In this embodiment, the number of cycles of the reference signal Fref between cycles 610 and 620 may be a large number (e.g., 100 to 1000 cycles, 800 to 8000 cycles, 7000 to 17000 cycles).

[0045] Figure 7 FIG. shows an exemplary block diagram of a loop gain calibration system 700 according to various embodiments described herein. In this embodiment, the circuit 110 is a delta-sigma (ΔΣ) TDC. The ΔΣ TDC is a negative feedback control system that receives signals as inputs and outputs a digital representation (e.g., logic "0" or "1") of any phase difference between these signals. The loop gain calibration system 700 is an example of a first-order negative feedback system that utilizes a loop gain detector 200.

[0046] In Figure 7 the embodiment shown, the loop gain calibration system 700 includes a ΔΣ TDC 710, a loop gain detector 720, and an optional calibration controller 730. The loop gain detector 720 detects and adjusts the loop gain of the ΔΣ TDC 710 accordingly. The calibration controller 730 provides additional improvement of the loop gain through Figure 8 the coarse tuning 832, coarse lock 834, fine tuning 836, and fine lock 838 shown in, where in Figure 9Each of the coarse adjustment 832, coarse lock 834, fine adjustment 836, and fine lock 838 is described in more detail below. The ΔΣ TDC 710 includes a multiplexer 714, a PD 704, a CP 706, a filter (capacitor) 708, a voltage controlled delay line (VCDL) 718, an inverter 716, and a TDC 712. The multiplexer 714 receives a reference frequency signal Fref with various clock offsets Δθ. In some embodiments, the multiplexer 714 receives a first clock offset signal Fref - Δθ at a first input of the multiplexer 714 and a second clock offset signal Fref + Δθ at a second input of the multiplexer 714. The multiplexer 714 is triggered based on the output signal TDC of the TDC 712 fed back to the multiplexer 714. The output of the multiplexer 714 is either the first clock offset signal Fref – Δθ or the second clock offset signal Fref + Δθ, depending on the output signal TDC of the TDC 712. out The phase detector 704 detects the phase error Δθ between the reference signal Fref and the output of the multiplexer 714. The phase error Δθ is then provided to the CP 706. The CP 706 generates a current Icp based on the phase error Δθ and then provides the current Icp to the capacitor 708. The CP 706 and the capacitor 708 perform an integration function to convert the phase error Δθ into a tuning voltage ΔV proportional to the phase error Δθ. The tuning voltage can be expressed by the following expression: out .

[0047] where C is the capacitance of the capacitor 708. The tuning voltage ΔV is provided to a first input of the VCDL 718. A second input of the VCDL 718 is the reference voltage Fref. The VCDL 718 determines a slope K based on how much the input phase of the VCDL 718 leads the phase of the reference signal Fref.

[0048]

[0049] The slope K also reflects the number of input stages of the VCDL 718. In some embodiments, the slope K is determined to ensure that the tuning voltage ΔV leads the reference signal Fref, thus reserving sufficient timing margin for the VCDL 718 timing delay ΔT. The VCDL 718 outputs a timing delay ΔT that is an input to the TDC 712. The timing delay ΔT can be expressed by the following expression: VCDL . The slope K VCDL also reflects the number of input stages of the VCDL 718. In some embodiments, the slope K is determined VCDL to ensure that the tuning voltage ΔV leads the reference signal Fref, thus reserving sufficient timing margin for the VCDL 718 timing delay ΔT. The VCDL 718 outputs a timing delay ΔT that is an input to the TDC 712. The timing delay ΔT can be expressed by the following expression:

[0050] ΔT = ΔVK VCDL (8)

[0051] VCDL 718 converts the voltage change between the reference signal Fref and the timing delay ΔT. K VCDL is the slope of the timing delay ΔT and the tuning voltage ΔV, which is very sensitive to any change. The loop gain detector 720 can monitor and measure the slope K VCDL 。In various embodiments, depending on the structure of the VCDL 710, the timing delay ΔT can be proportional or inversely proportional to the magnitude of the tuning voltage ΔV.

[0052] The timing delay output ΔT of the VCDL 718 is provided as a first input to the TDC 712 and the loop gain detector 720. In some embodiments, the TDC 712 can be one-bit. The inverted reference signal -Fref output from the inverter 716 is provided as a second input to the TDC 712. The TDC 712 functions as a comparator in the time domain and compares the timing difference between the timing delay ΔT and the inverted reference signal -Fref. In some embodiments, the TDC 712 includes a D flip-flop, where the timing delay ΔT is input to the D input of the flip-flop, and the inverted reference signal -Fref is input to the clock input of the flip-flop. In this embodiment, the TDC 712 detects any early or late information between the reference signal Fref and the timing delay ΔT. In some embodiments, when the timing delay ΔT leads the inverted reference signal -Fref, the output of the TDC 712 is logic high. When the timing delay ΔT lags the inverted reference signal -Fref, the output is logic low.

[0053] Under ideal conditions, if the loop gain of the ΔΣ TDC 710 is approximately equal to 1, then the following expression is true:

[0054]

[0055] The expression can be simplified to the following:

[0056]

[0057] Figure 8 Exemplary flowchart 800 showing various tunings (e.g., coarse tuning 832, coarse lock 834, fine tuning 836, and fine lock 838) of the calibration controller 730 according to various embodiments described herein.

[0058] Figure 9Shows an exemplary graph 900 of loop gain tuning in accordance with various embodiments set forth herein. The x-axis of graph 900 represents a target loop gain of approximately 1. The y-axis of graph 900 represents the actual loop gain of the ΔΣ TDC 710. The coarse tuning 832 and coarse lock 834 operations occur during time points ① to ④ shown in graph 900. The fine tuning 836 and fine lock 838 occur during time point ⑤ shown in graph 900. During the coarse tuning 832, a specific coarse tuning code within the calibration controller 730 controls the loop filter capacitor value (e.g., capacitor 708). During the fine tuning 836, a specific fine tuning code within the calibration controller 730 controls the charge pump current I of the CP 706 CP .

[0059] Figure 10 Shows, in accordance with various embodiments set forth herein, an exemplary flowchart 1000 of the operation of the calibration controller 730 corresponding to graph 900 of Figure 9 . The calibration controller 730 is used to adjust the slope K VCDL such that it is as close as possible to the condition expressed by Equation (10). For example, if the comparator output (e.g., com_out) is logic high, then the calibration controller will adjust the coarse / fine tuning to reduce the loop gain. If the comparator output is logic low, then the calibration controller will adjust the coarse / fine tuning to increase the loop gain. Initially, at time point ① of graph 900, the fine tuning can be set to an initial fine tuning value, which in turn sets the current of the CP 706 (e.g., step 1002). At time point ② of graph 900, the coarse tuning can be set to an initial coarse tuning value, which in turn sets the value of the capacitor 708. During each of the time points ③ to ④ of graph 900, the coarse tuning of the various capacitance values of the capacitor 708 can be continuously adjusted by increasing and decreasing to strive to achieve Equation (10) (e.g., steps 1006, 1008, 1010). These adjustments are based on the output of the comparator within the loop gain detector 720. When the output of the capacitor 708 changes several times, the loop gain approaches the target condition of Equation (10), and the coarse code is locked (e.g., step 1012). Then the fine tuning is started (e.g., step 1014). Through the fine tuning, the current of the CP 706 is modified until the condition of Equation (10) is achieved (e.g., steps 1016, 1018, 1020, 1022). Once the condition of Equation (10) is achieved, the fine tuning code is locked (e.g., step 1026).

[0060] Figure 11Exemplary block diagram showing a multi-stage loop gain calibration system 1100 in accordance with various embodiments set forth herein. The multi-stage loop gain calibration system 1100 includes a first ΔΣ TDC 1110, a second ΔΣ TDC 1120, a third ΔΣ TDC 1130, and a system controller 1140. The first ΔΣ TDC 1110 includes a PD 1111, a CP 1112, an S / H component 1113, a comparator 1114, a VCDL 1115, a TDC 1116, and a capacitor 1117. The second ΔΣ TDC 1120 includes a PD 1121, a CP 1122, an S / H component 1123, a comparator 1124, a VCDL 1125, a TDC 1126, and a capacitor 1127. The third ΔΣ TDC 1130 includes a PD 1131, a CP 1132, an S / H component 1133, a comparator 1134, a VCDL 1135, a TDC 1136, and a capacitor 1137. In this embodiment, the components of the second ΔΣ TDC 1120 can be used to calibrate the first ΔΣ TDC 1110. In other words, some of the components of the second ΔΣ TDC 1120 form a loop gain detector for the first ΔΣ TDC 1110. More specifically, the output from the VCDL 1115 is provided to the second ΔΣ TDC 1120 as an input (e.g., the input signal FD to the PD 1121). The PD 1121, the CP 1122, the S / H component 1123, the capacitor 1127, and the comparator 1124 form a loop gain detector and are used to calibrate the first ΔΣ TDC 1110.

[0061] Similarly, the third ΔΣ TDC 1130 can be used for the second ΔΣ TDC 1120. In other words, some of the components of the third ΔΣ TDC 1130 form a loop gain detector for the second ΔΣ TDC 1120. More specifically, the output from the VCDL 1125 is provided to the third ΔΣ TDC 1130 as an input (e.g., the input signal FD to the PD 1131). The PD 1131, the CP 1132, the S / H component 1133, the capacitor 1137, and the comparator 1134 provide calibration to the second ΔΣ TDC 1120. Since Figure 11 the embodiment shown is a three-stage multi-stage system, there is no additional ΔΣ TDC to provide calibration for the third ΔΣ TDC 1130. Instead, the system controller 1140 provides the calibration through software code. Using the multi-stage ΔΣ TDC as a loop gain detector can reduce the total chip space because the components can be reused for calibration in addition to their intended purpose. In addition to saving chip space, the overall power consumption is also lower. It should be noted that although Figure 11Three levels are described, but this description is for ease of understanding. Any number of levels can be coupled together as shown in Figure 11 to achieve multi-level calibration.

[0062] Figure 12 FIG. 1200 is a process flow diagram for loop gain detection and automatic calibration in accordance with various embodiments described herein. A phase detector circuit detects a clock offset between a reference signal and an input signal (e.g., step 1210). A charge pump circuit converts the clock offset into a voltage (e.g., step 1220). A sample and hold circuit samples the voltage at a first time (e.g., step 1230). The sample and hold circuit holds the sampled voltage until a second time (e.g., step 1240). A comparator detects a loop gain associated with the input signal based on the sampled voltage and the voltage (e.g., step 1250). The comparator outputs a loop gain signal to adjust the input signal (e.g., step 1260). A controller generates a plurality of control signals for automatically controlling the operation of the phase detector, the comparator, and the sample and hold circuit (e.g., step 1270).

[0063] Using various circuits and configurations as described herein can provide many advantages. For example, using the loop gain detector described herein can provide automatic detection of the slope K VCDL and proper gain adjustment to achieve an ideal loop gain of approximately 1. Using a multi-level calibration system with two or more loop gain detectors coupled together can reduce the total power consumption of the loop gain detector and reduce the total chip area occupied by the loop gain detector.

[0064] In one embodiment, an apparatus for automatic detection and calibration of a loop gain includes a first phase detector, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The first phase detector is configured to detect a clock offset between a reference signal and an input signal. The charge pump circuit is configured to convert the clock offset into a voltage. The sample and hold circuit is configured to sample the voltage at a first time and hold the sampled voltage until a second time. The comparator is configured to: (i) detect a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time, and (ii) output a loop gain signal for adjusting the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller is configured to generate a plurality of control signals for automatically controlling the operation of the phase detector, the comparator, and the sample and hold circuit.

[0065] In related embodiments, the reference signal includes a plurality of cycles, and the plurality of control signals include: a sample-and-hold circuit control signal configured to operate the sample-and-hold circuit during a first cycle of the plurality of cycles; a first phase detector control signal configured to operate the first phase detector during a second cycle and a third cycle of the plurality of cycles; a second phase detector control signal configured to operate the second phase detector during a fourth cycle of the plurality of cycles; and a comparator control signal configured to operate the comparator during a fifth cycle of the plurality of cycles.

[0066] In related embodiments, the controller is further configured to automatically adjust one or more of the plurality of control signals based on the loop gain.

[0067] In related embodiments, the apparatus further includes a capacitor coupled between the sample-and-hold circuit and the charge pump circuit, wherein a voltage passes through the capacitor.

[0068] In related embodiments, the charge pump circuit includes: a first switch configured to close based on detecting the clock offset; and a second switch configured to close based on detecting a constant clock offset.

[0069] In related embodiments, (i) closing the first switch charges the capacitor and increases the voltage, (ii) closing the second switch discharges the capacitor and decreases the voltage, and (iii) closing both the first switch and the second switch simultaneously holds the charge of the capacitor and holds the voltage.

[0070] In related embodiments, the apparatus further includes a second phase detector configured to detect the constant clock offset, and the controller is coupled to the second phase detector.

[0071] In related embodiments, the clock offset indicates (i) the reference signal leading the input signal, or (ii) the reference signal lagging the input signal.

[0072] In another embodiment, a system for automatically detecting and calibrating loop gain includes a first delta-sigma time-to-digital converter (ΔΣ TDC) and a first loop gain detector. The first delta-sigma time-to-digital converter is configured to receive a reference signal. The first loop gain detector is coupled to the first delta-sigma time-to-digital converter and is configured to detect the loop gain of the first delta-sigma time-to-digital converter. The first loop gain detector includes a first phase detector, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The first phase detector is configured to detect a clock offset between the reference signal and a timing delay signal generated by the first delta-sigma time-to-digital converter. The charge pump circuit is configured to convert the clock offset into a voltage. The sample and hold circuit is configured to sample the voltage at a first time and hold the sampled voltage until a second time. The comparator is configured to: (i) detect the loop gain of the first delta-sigma time-to-digital converter based on the sampled voltage and the voltage, and (ii) provide a loop gain signal to the first delta-sigma time-to-digital converter for adjusting the timing delay signal. The controller is coupled to the first phase detector, the comparator, and the sample and hold circuit and is configured to generate a plurality of control signals for automatically controlling the operations of the first phase detector, the comparator, and the sample and hold circuit.

[0073] In a related embodiment, the first delta-sigma time-to-digital converter and the first loop gain detector coupled together form a first-order negative feedback loop.

[0074] In a related embodiment, the reference signal includes a plurality of cycles, and the plurality of control signals include: a sample and hold circuit control signal configured to operate the sample and hold circuit during a first cycle of the plurality of cycles; a first phase detector control signal configured to operate the first phase detector during a second cycle and a third cycle of the plurality of cycles; a second phase detector control signal configured to operate a second phase detector during a fourth cycle of the plurality of cycles; and a comparator control signal configured to operate the comparator during a fifth cycle of the plurality of cycles.

[0075] In a related embodiment, the controller is further configured to automatically adjust one or more of the plurality of control signals based on the loop gain.

[0076] In a related embodiment, the first loop gain detector further includes a capacitor coupled between the sample and hold circuit and the charge pump circuit, wherein the voltage passes through the capacitor.

[0077] In related embodiments, the charge pump circuit includes: a first switch configured to close based on detecting the clock offset; and a second switch configured to close based on detecting a constant clock offset.

[0078] In related embodiments, (i) closing the first switch charges the capacitor and increases the voltage, (ii) closing the second switch discharges the capacitor and decreases the voltage, and (iii) closing both the first switch and the second switch simultaneously holds the charge of the capacitor and holds the voltage.

[0079] In related embodiments, the first loop gain detector further includes a second phase detector configured to detect the constant clock offset, and the controller is coupled to the second phase detector.

[0080] In related embodiments, the clock offset indicates (i) the reference signal leading the timing delay signal, or (ii) the reference signal lagging the timing delay signal.

[0081] In related embodiments, the system further includes a second ΔΣ time-to-digital converter, the second ΔΣ time-to-digital converter including the first phase detector, the charge pump circuit, a sample-and-hold component, and the comparator.

[0082] In related embodiments, the system further includes a calibration circuit coupled between the first loop gain detector and the first ΔΣ time-to-digital converter, wherein the calibration circuit is configured to provide at least one of the following: (i) a coarse adjustment of the current of the charge pump circuit or (ii) a fine adjustment of the capacitor of the first ΔΣ time-to-digital converter.

[0083] A method for automatic detection and calibration of loop gain includes detecting, by a phase detector, a clock offset between a reference signal and an input signal. A charge pump circuit converts the clock offset into a voltage. A sample-and-hold circuit samples the voltage at a first time. The sample-and-hold circuit holds the sampled voltage until a second time. A comparator detects the loop gain associated with the input signal based on the sampled voltage and the voltage. The comparator outputs a loop gain signal for adjusting the input signal. A controller generates a plurality of control signals for automatically controlling the operations of the phase detector, the comparator, and the sample-and-hold circuit.

[0084] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. An apparatus for automatic detection and calibration of loop gain, comprising: A first phase detector configured to detect a clock offset between a reference signal and an input signal; A charge pump circuit configured to convert the clock offset into a voltage; A sample and hold circuit configured to sample the voltage at a first time and hold the sampled voltage until a second time; A comparator configured to i. detect the loop gain associated with the input signal based on the sampled voltage and the voltage detection, and ii. output a loop gain signal for adjusting the input signal; A controller coupled to the first phase detector, the comparator, and the sample and hold circuit, the controller being configured to generate a plurality of control signals for automatically controlling the operations of the first phase detector, the comparator, and the sample and hold circuit; And A capacitor coupled between the sample and hold circuit and the charge pump circuit, wherein the voltage passes through the capacitor, wherein the charge pump circuit includes: A first switch configured to close based on detecting the clock offset; And A second switch configured to close based on detecting a constant clock offset.

2. The device according to claim 1, wherein the reference signal comprises a plurality of periods, and the plurality of control signals comprise: A sample and hold circuit control signal configured to operate the sample and hold circuit during a first period of the plurality of periods; A first phase detector control signal configured to operate the first phase detector during a second period and a third period of the plurality of periods; A second phase detector control signal configured to operate a second phase detector during a fourth period of the plurality of periods; and a comparator control signal configured to operate the comparator during a fifth period of the plurality of periods.

3. The apparatus according to claim 2, wherein the controller is further configured to automatically adjust one or more of the plurality of control signals based on the loop gain.

4. The apparatus according to claim 1, wherein i. closing the first switch charges the capacitor and increases the voltage, ii. closing the second switch discharges the capacitor and decreases the voltage, and iii. closing both the first switch and the second switch simultaneously maintains the charge of the capacitor and maintains the voltage.

5. The apparatus according to claim 1, further comprising a second phase detector configured to detect the constant clock offset, the controller being coupled to the second phase detector.

6. The apparatus according to claim 1, wherein the clock offset indicates i. the reference signal leading the input signal, or ii. the reference signal lagging the input signal.

7. A system for automatic detection and calibration of loop gain, comprising: A first ΔΣ time - digital converter configured to receive a reference signal; And A first loop gain detector coupled to the first ΔΣ time - digital converter and configured to detect the loop gain of the first ΔΣ time - digital converter, the first loop gain detector including: A first phase detector configured to detect a clock offset between the reference signal and a timing delay signal generated by the first ΔΣ time-to-digital converter; A charge pump circuit configured to convert the clock offset into a voltage; A sample and hold circuit configured to sample the voltage at a first time and hold the sampled voltage until a second time; A comparator configured to: i. detect the loop gain of the first ΔΣ time-to-digital converter based on the sampled voltage and the voltage, and ii. provide a loop gain signal for adjusting the timing delay signal to the first ΔΣ time-to-digital converter; and A controller coupled to the first phase detector, the comparator, and the sample and hold circuit, and configured to generate a plurality of control signals for automatically controlling the operations of the first phase detector, the comparator, and the sample and hold circuit.

8. The system according to claim 7, wherein the first ΔΣ time-to-digital converter and the first loop gain detector coupled together form a first-order negative feedback loop.

9. The system according to claim 7, wherein the reference signal includes a plurality of cycles, and the plurality of control signals include: A sample and hold circuit control signal configured to operate the sample and hold circuit during a first cycle of the plurality of cycles; A first phase detector control signal configured to operate the first phase detector during a second cycle and a third cycle of the plurality of cycles; A second phase detector control signal configured to operate a second phase detector during a fourth cycle of the plurality of cycles; And A comparator control signal configured to operate the comparator during a fifth cycle of the plurality of cycles.

10. The system according to claim 9, wherein the controller is further configured to automatically adjust one or more of the plurality of control signals based on the loop gain.

11. The system according to claim 7, wherein the first loop gain detector further includes a capacitor coupled between the sample and hold circuit and the charge pump circuit, and the voltage passes through the capacitor.

12. The system according to claim 11, wherein the charge pump circuit comprises: A first switch configured to close based on detecting the clock offset; And a second switch configured to close based on detecting a constant clock offset.

13. The system according to claim 12, wherein i. closing the first switch charges the capacitor and increases the voltage, ii. closing the second switch discharges the capacitor and decreases the voltage, and iii. closing both the first switch and the second switch simultaneously maintains the charge of the capacitor and the voltage.

14. The system according to claim 12, wherein the first loop gain detector further includes a second phase detector configured to detect the constant clock offset, and the controller is coupled to the second phase detector.

15. The system according to claim 7, wherein the clock offset indicates i. the reference signal leading the timing delay signal, or ii. the reference signal lagging the timing delay signal.

16. The system according to claim 7, further comprising a second ΔΣ time-to-digital converter, the second ΔΣ time-to-digital converter including the first phase detector, the charge pump circuit, the sample-and-hold component, and the comparator.

17. The system according to claim 7, further comprising a calibration circuit coupled between the first loop gain detector and the first ΔΣ time-to-digital converter, wherein the calibration circuit is configured to provide at least one of the following: i. a coarse adjustment of the current of the charge pump circuit or ii. a fine adjustment of the capacitor of the first ΔΣ time-to-digital converter.

18. A method for automatic detection and calibration of loop gain, comprising: detecting, by a phase detector, a clock offset between a reference signal and an input signal; converting, by a charge pump circuit, the clock offset into a voltage; sampling, by a sample-and-hold circuit, the voltage at a first time; holding, by the sample-and-hold circuit, the sampled voltage until a second time; detecting, by a comparator, the loop gain associated with the input signal based on the sampled voltage and the voltage; outputting, by the comparator, a loop gain signal for adjusting the input signal; and generating, by a controller, a plurality of control signals for automatically controlling the operations of the phase detector, the comparator, and the sample-and-hold circuit, wherein a capacitor is coupled between the sample-and-hold circuit and the charge pump circuit, and the voltage passes through the capacitor, wherein the charge pump circuit includes: a first switch configured to close based on detecting the clock offset; and a second switch configured to close based on detecting a constant clock offset.

19. An apparatus for automatic detection and calibration of loop gain, comprising: a first phase detector configured to detect a clock offset between a reference signal and an input signal; a charge pump circuit configured to convert the clock offset into a voltage; a sample-and-hold circuit configured to sample the voltage and hold the sampled voltage; a comparator configured to detect the loop gain associated with the input signal based on the sampled voltage and the voltage, and output a loop gain signal for adjusting the input signal; and a capacitor coupled between the sample-and-hold circuit and the charge pump circuit, and the voltage passes through the capacitor, wherein the charge pump circuit includes: a first switch configured to close based on detecting the clock offset; and a second switch configured to close based on detecting a constant clock offset.

20. The apparatus according to claim 19, further comprising: a controller coupled to the first phase detector, the comparator, and the sample-and-hold circuit, the controller being configured to generate a plurality of control signals for automatically controlling the operations of the first phase detector, the comparator, and the sample-and-hold circuit, wherein the reference signal includes a plurality of cycles, and the plurality of control signals include: a sample-and-hold circuit control signal configured to operate the sample-and-hold circuit during a first cycle of the plurality of cycles; a first phase detector control signal configured to operate the first phase detector during a second cycle and a third cycle of the plurality of cycles; a second phase detector control signal configured to operate a second phase detector during a fourth cycle of the plurality of cycles; and a comparator control signal configured to operate the comparator during a fifth cycle of the plurality of cycles.

21. The apparatus according to claim 20, wherein the controller is further configured to automatically adjust one or more of the plurality of control signals based on the loop gain.

22. The apparatus according to claim 19, wherein i. closing the first switch charges the capacitor and increases the voltage, ii. closing the second switch discharges the capacitor and decreases the voltage, and iii. closing both the first switch and the second switch simultaneously holds the charge of the capacitor and holds the voltage.

23. The apparatus according to claim 20, further comprising a second phase detector configured to detect the constant clock offset, the controller being coupled to the second phase detector.

24. The apparatus according to claim 19, wherein the clock offset indicates i. the reference signal leading the input signal, or ii. the reference signal lagging the input signal.

25. A system for automatic detection and calibration of loop gain, comprising: a first ΔΣ time-to-digital converter configured to receive a reference signal; and a first loop gain detector coupled to the first ΔΣ time-to-digital converter and configured to detect the loop gain of the first ΔΣ time-to-digital converter, the first loop gain detector including: a first phase detector configured to detect a clock offset between the reference signal and a timing delay signal generated by the first ΔΣ time-to-digital converter; a charge pump circuit configured to convert the clock offset into a voltage; a sample-and-hold circuit configured to sample the voltage and hold the sampled voltage; and a comparator configured to detect the loop gain of the first ΔΣ time-to-digital converter based on the sampled voltage and the voltage, and to provide a loop gain signal for adjusting the timing delay signal to the first ΔΣ time-to-digital converter.

26. The system according to claim 25, wherein the first ΔΣ time-to-digital converter and the first loop gain detector coupled together form a first-order negative feedback loop.

27. The system according to claim 25, further comprising: a controller coupled to the first phase detector, the comparator, and the sample-and-hold circuit, the controller being configured to generate a plurality of control signals for automatically controlling the operations of the first phase detector, the comparator, and the sample-and-hold circuit wherein the reference signal includes a plurality of cycles, and the plurality of control signals include: a sample-and-hold circuit control signal configured to operate the sample-and-hold circuit during a first cycle of the plurality of cycles; a first phase detector control signal configured to operate the first phase detector during a second cycle and a third cycle of the plurality of cycles; a second phase detector control signal configured to operate a second phase detector during a fourth cycle of the plurality of cycles; and a comparator control signal configured to operate the comparator during a fifth cycle of the plurality of cycles.

28. The system according to claim 27, wherein the controller is further configured to automatically adjust one or more of the plurality of control signals based on the loop gain.

29. The system according to claim 27, wherein the first loop gain detector further includes a capacitor coupled between the sample-and-hold circuit and the charge pump circuit, wherein a voltage passes through the capacitor.

30. The system according to claim 29, wherein the charge pump circuit includes: a first switch configured to close based on detecting the clock offset; and a second switch configured to close based on detecting a constant clock offset.

31. The system according to claim 30, wherein i. closing the first switch charges the capacitor and increases the voltage, ii. closing the second switch discharges the capacitor and decreases the voltage, and iii. closing both the first switch and the second switch simultaneously maintains the charge of the capacitor and maintains the voltage.

32. The system according to claim 30, wherein the first loop gain detector further includes a second phase detector configured to detect the constant clock offset, and the controller is coupled to the second phase detector.

33. The system according to claim 25, wherein the clock offset indicates i. the reference signal leading the timing delay signal, or ii. the reference signal lagging the timing delay signal.

34. The system according to claim 25, further comprising a second ΔΣ time-to-digital converter, the second ΔΣ time-to-digital converter including the first phase detector, the charge pump circuit, a sample-and-hold component, and the comparator.

35. The system according to claim 25, further comprising a calibration circuit coupled between the first loop gain detector and the first ΔΣ time-to-digital converter, wherein the calibration circuit is configured to provide at least one of: i. a coarse adjustment of the current of the charge pump circuit or ii. a fine adjustment of the capacitor of the first ΔΣ time-to-digital converter.

36. A method for automatic detection and calibration of loop gain, comprising: detecting, by a phase detector, a clock offset between a reference signal and an input signal; converting, by a charge pump circuit, the clock offset into a voltage; sampling, by a sample-and-hold circuit, the voltage; holding, by the sample-and-hold circuit, the sampled voltage; A comparator determines the loop gain associated with the input signal based on the sampled voltage and the voltage detection; and The comparator outputs a loop gain signal for adjusting the input signal, wherein a capacitor is coupled between the sample-and-hold circuit and the charge pump circuit, and the voltage passes through the capacitor, wherein the charge pump circuit includes: A first switch configured to close based on detecting the clock offset; and A second switch configured to close based on detecting a constant clock offset.

37. An apparatus for automatic detection and calibration of loop gain, comprising: A first phase detector configured to detect a clock offset between a reference signal and an input signal; A charge pump circuit configured to convert the clock offset into a voltage; A comparator configured to determine the loop gain associated with the input signal based on the voltage detection and output a loop gain signal for adjusting the input signal; And A capacitor coupled between a sample-and-hold circuit and the charge pump circuit, and the voltage passes through the capacitor, wherein the charge pump circuit includes: A first switch configured to close based on detecting the clock offset; And A second switch configured to close based on detecting a constant clock offset.

38. The apparatus according to claim 37, further comprising: A sample-and-hold circuit configured to sample the voltage and hold the sampled voltage, wherein the comparator is further configured to determine the loop gain based on the sampled voltage; and A controller coupled to the first phase detector, the comparator, and the sample-and-hold circuit, the controller being configured to generate a plurality of control signals for automatically controlling the operations of the first phase detector, the comparator, and the sample-and-hold circuit, wherein the reference signal includes a plurality of cycles, and the plurality of control signals include: A sample-and-hold circuit control signal configured to operate the sample-and-hold circuit during a first cycle of the plurality of cycles; A first phase detector control signal configured to operate the first phase detector during a second cycle and a third cycle of the plurality of cycles; A second phase detector control signal configured to operate a second phase detector during a fourth cycle of the plurality of cycles; and A comparator control signal configured to operate the comparator during a fifth cycle of the plurality of cycles.

39. The apparatus according to claim 38, wherein the controller is further configured to automatically adjust one or more of the plurality of control signals based on the loop gain.

40. The apparatus according to claim 38, wherein i. closing the first switch charges the capacitor and increases the voltage, ii. closing the second switch discharges the capacitor and decreases the voltage, and iii. closing both the first switch and the second switch simultaneously maintains the charge of the capacitor and maintains the voltage.

41. The apparatus according to claim 38, further comprising a second phase detector configured to detect the constant clock offset, and the controller is coupled to the second phase detector.

42. The apparatus according to claim 37, wherein the clock offset indicates i. the reference signal leading the input signal, or ii. the reference signal lagging the input signal.

43. A system for automatic detection and calibration of loop gain, comprising: a first ΔΣ time-to-digital converter configured to receive a reference signal; and a first loop gain detector coupled to the first ΔΣ time-to-digital converter and configured to detect the loop gain of the first ΔΣ time-to-digital converter, the first loop gain detector comprising: a first phase detector configured to detect a clock offset between the reference signal and a timing delay signal generated by the first ΔΣ time-to-digital converter; a charge pump circuit configured to convert the clock offset into a voltage; and a comparator configured to detect the loop gain of the first ΔΣ time-to-digital converter based on the voltage and provide a loop gain signal for adjusting the timing delay signal to the first ΔΣ time-to-digital converter.

44. The system according to claim 43, wherein the first ΔΣ time-to-digital converter and the first loop gain detector coupled together form a first-order negative feedback loop.

45. The system according to claim 43, further comprising: a sample and hold circuit configured to sample the voltage and hold the sampled voltage, wherein the comparator is further configured to detect the loop gain based on the sampled voltage; and a controller coupled to the first phase detector, the comparator, and the sample and hold circuit, the controller being configured to generate a plurality of control signals for automatically controlling the operations of the first phase detector, the comparator, and the sample and hold circuit, wherein the reference signal includes a plurality of cycles, and the plurality of control signals include: a sample and hold circuit control signal configured to operate the sample and hold circuit during a first cycle of the plurality of cycles; a first phase detector control signal configured to operate the first phase detector during a second cycle and a third cycle of the plurality of cycles; a second phase detector control signal configured to operate a second phase detector during a fourth cycle of the plurality of cycles; and a comparator control signal configured to operate the comparator during a fifth cycle of the plurality of cycles.

46. The system according to claim 45, wherein the controller is further configured to automatically adjust one or more of the plurality of control signals based on the loop gain.

47. The system according to claim 45, wherein the first loop gain detector further includes a capacitor coupled between the sample and hold circuit and the charge pump circuit, and the voltage passes through the capacitor.

48. The system according to claim 47, wherein the charge pump circuit includes: A first switch configured to close based on detecting the clock offset; and A second switch configured to close based on detecting a constant clock offset.

49. The system according to claim 48, wherein i. closing the first switch charges the capacitor and increases the voltage, ii. closing the second switch discharges the capacitor and decreases the voltage, and iii. closing both the first switch and the second switch simultaneously maintains the charge of the capacitor and maintains the voltage.

50. The system according to claim 48, wherein the first loop gain detector further includes a second phase detector configured to detect the constant clock offset, and the controller is coupled to the second phase detector.

51. The system according to claim 43, wherein the clock offset indicates i. the reference signal leading the timing delay signal, or ii. the reference signal lagging the timing delay signal.

52. The system according to claim 45, further comprising a second ΔΣ time-to-digital converter, the second ΔΣ time-to-digital converter including the first phase detector, the charge pump circuit, the sample-and-hold component, and the comparator.

53. The system according to claim 43, further comprising a calibration circuit coupled between the first loop gain detector and the first ΔΣ time-to-digital converter, wherein the calibration circuit is configured to provide at least one of the following: i. a coarse adjustment of the current of the charge pump circuit or ii. a fine adjustment of the capacitor of the first ΔΣ time-to-digital converter.

54. A method for automatic detection and calibration of loop gain, comprising: Detecting, by a phase detector, a clock offset between a reference signal and an input signal; Converting, by a charge pump circuit, the clock offset into a voltage; Sampling, by a sample-and-hold circuit, the voltage; Detecting, by a comparator, the loop gain associated with the input signal based on the voltage; and Outputting, by the comparator, a loop gain signal for adjusting the input signal, wherein a capacitor is coupled between the sample-and-hold circuit and the charge pump circuit, and the voltage passes through the capacitor, wherein the charge pump circuit includes: A first switch configured to close based on detecting the clock offset; and A second switch configured to close based on detecting a constant clock offset.

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