Stream access memory device, system and method

Abstract

Embodiments of the present disclosure relate to stream access memory devices, systems, and methods. A system includes a random access memory organized into individually addressable words. A stream access control circuit device is coupled to a word line of the random access memory. The stream access control circuit device responds to a request for accessing a plurality of individually addressable words of a determined area of ​​the random access memory by generating a control signal to drive the word line to stream access the plurality of individually addressable words of the determined area. The request indicates an offset associated with the determined area and a mode associated with the stream access.

Description

Technical Field

[0001] The present disclosure generally relates to a word line selection circuit for a memory array. For example, the present disclosure relates to a memory system used in artificial neural network (ANN) and streaming applications. Background Art

[0002] Processing cores and devices and systems including processing cores (such as processors, mobile phones, tablets, laptops, desktop computers, embedded processing systems, etc.) may typically include one or more memories (such as cache memory, main memory, secondary memory, etc.). The memory may be volatile or non-volatile.

[0003] The memory may be a shared memory that may be used, for example, by multiple processing cores (such as a host processing core and an application accelerator core), multiple processes (such as a host system process, an application process, etc.). Such a processing system may be implemented using one or more integrated circuits. The integrated circuit may include, for example, a processing core, a memory array, a memory controller, discrete circuit devices, etc., and various combinations thereof.

[0004] The memory may be organized into an array of rows and columns of bits. Each row may have a line for accessing the smallest addressable unit of the memory, often called a word line, that spans all columns or a set of columns of the array. The set of columns corresponding to a word may span an entire row of the array, or each row may contain multiple words (e.g., columns 0-7 correspond to a first word, columns 8-15 correspond to a second word; columns 0-15 correspond to a first word, columns 16-31 correspond to a second word; and so on). Each column may have a bit line that spans the row. By asserting a word line, all bits in the corresponding row of the set of columns corresponding to that word may be accessed. Summary of the invention

[0005] In one embodiment, a device includes: one or more inputs configured to receive a stream access request for accessing a plurality of individually addressable words of a determined region of a random access memory, the request indicating an offset associated with the determined region and a mode of the stream access; a plurality of outputs configured to be coupled to a word line of the random access memory; and a stream access control circuit device coupled to the one or more inputs and the plurality of outputs and configured to respond to the stream access request by generating a control signal to drive the word line to access the plurality of individually addressable words of the determined region. The request may include an offset associated with the determined region. The request may include an indication of a sequence of stream accesses. The stream access control circuit device may identify the determined region based on the offset and the indication of the sequence of stream accesses. The stream access control circuit device may include a memory configured to store stream access control information, and the indication is a command to perform a stream access based on the stored stream access control information. The request may indicate a plurality of offsets defining the determined region. The stream access control circuit device may include: a stream control circuit device, which is configured to generate a control signal to drive a word line, the stream control circuit device includes a plurality of shift registers and a multiplexer group coupled to the plurality of shift registers; and a configuration control circuit device, which is configured to generate register data and control signals to control loading the register data into the plurality of shift registers and shifting the plurality of shift registers. The first data input of each multiplexer of the multiplexer group can be coupled to a corresponding output of one of the plurality of shift registers, and the selection input of each multiplexer of the multiplexer group can be coupled to a corresponding output of another shift register in the plurality of shift registers. The second data input of each multiplexer of the multiplexer group can be coupled to the output of an adjacent multiplexer in the multiplexer group, and the plurality of outputs can be coupled to the corresponding outputs of the multiplexers in the multiplexer group. The random access memory can be addressable in a three-dimensional address space. In one embodiment, the stream access request includes a sequential access request.

[0006] In one embodiment, a system includes: a stream access memory organized into individually addressable words; and a stream access control circuit device coupled to a word line of the stream access memory, wherein the stream access control circuit device responds to a request for accessing multiple individually addressable words of a determined area of ​​the stream access memory by generating a control signal to drive the word line to access multiple individually addressable words of the determined area, wherein the request indicates an offset associated with the determined area and an indication of an access mode to the stream access memory. The request may include an offset associated with the determined area. The request may include an indication of a sequence of accesses to the stream access memory. The stream access control circuit device may identify the determined area based on the offset and the indication of the sequence of accesses to the stream access memory. The request may indicate multiple offsets associated with the determined area. Multiple offsets may define the determined area. The stream access control circuit device may include: a stream control circuit device configured to generate control signals to drive word lines, the stream control circuit device including a plurality of shift registers and a multiplexer group coupled to the plurality of shift registers; a configuration control circuit device configured to generate register data and control signals to control loading the register data into the plurality of shift registers and shifting the plurality of shift registers. The stream access memory may be addressable in a three-dimensional address space. In one embodiment, the system includes a random access control circuit device coupled to a word line of a random access memory, wherein the random access control circuit device responds to a request for accessing a word line of the random access memory in operation. In one embodiment, the system includes one or more convolution accelerators, the one or more convolution accelerators being coupled to the stream access control circuit device and the random access memory, wherein in operation, the one or more convolution accelerators provide a request for accessing a plurality of individually addressable words of a determined area of ​​the random access memory to the stream access control circuit device and receive a response to the request from the stream access memory. In one embodiment, the stream access memory is a random access memory. The system may include a plurality of stream access memories coupled together in series or in parallel.

[0007] In one embodiment, a method includes: receiving a stream access request by a stream access control circuit device of a stream access memory to access multiple individually addressable words of a determined area of ​​a random access memory, the request indicating an offset associated with the determined area and a mode of the stream access; and responding to the request by the stream access control circuit device by generating a control signal, the control signal being used to drive a word line of the random access memory to access the multiple individually addressable words of the determined area. The request may include an offset associated with the determined area. The request may include an indication of a sequence of stream accesses. The method may include: identifying the determined area by the stream access control circuit device based on the offset and the indication of the mode associated with the stream access. The method may include: storing access mode control information in the memory of the stream access control circuit device, wherein the indication is a command for performing an access based on the stored access mode control information. The request may indicate multiple offsets defining the determined area. The stream access memory may be addressable in a three-dimensional address space.

[0008] In one embodiment, the contents of a non-transitory computer readable medium configure a stream access controller of a stream access memory to perform a method comprising: receiving a stream access request for accessing a plurality of individually addressable words of a determined region of the stream access memory, the request indicating an offset and an access mode associated with the determined region; and responding to the request by generating a control signal to drive a word line of the stream access memory to access the plurality of individually addressable words of the determined region. The request may include an indication of an offset associated with the determined region and a mode of stream access. The stream access memory may be addressable in a three-dimensional address space, and the determined region may be a three-dimensional region in the three-dimensional address space. The contents may include a lookup table storing a register and timing information used by the stream access controller to generate a control signal for driving the word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Reference will now be made to the accompanying drawings by way of example. In the drawings, the same reference numerals represent similar elements or actions unless the context indicates otherwise. However, in some of the drawings, different reference numerals may be used to represent the same or similar elements. The sizes and relative positions of the elements in the drawings are not necessarily drawn to scale. Some of these elements may be enlarged and positioned to improve graphic clarity. The specific shapes of the depicted elements are not necessarily intended to convey any information about the actual shape of the specific element and are selected only for ease of identification in the drawings.

[0010] Figure 1 is a functional block diagram of an embodiment of an electronic device or system having a processing core and a memory and implementing an artificial neural network.

[0011] Figure 2 is a functional block diagram of an embodiment of an electronic device or system that implements an artificial neural network.

[0012] Figure 3 is a functional block diagram of an embodiment of a configurable accelerator framework (CAF).

[0013] Figure 4 is a functional block diagram of an embodiment of a convolution accelerator.

[0014] Figure 5 is a functional block diagram of an embodiment of a random access memory.

[0015] Figure 6 is a functional block diagram of an embodiment of a random access decoding circuit device of a random access memory.

[0016] Figure 7 is a functional block diagram of an embodiment of a stream access memory.

[0017] Figure 8 The access regions of a memory array are conceptually organized into two dimensions.

[0018] Fig. 9 Conceptually illustrates an access region of a multidimensional data structure in a stream access memory.

[0019] Fig.10 is a functional block diagram of an embodiment of streaming access control circuitry that may be employed in a streaming access memory.

[0020] Fig.11 is a functional block diagram of an embodiment of flow control circuitry that may be employed in a flow access controller.

[0021] Fig.12 is a functional block diagram of an embodiment of a shared memory having random access decoding circuitry and stream access control circuitry.

[0022] Fig.13 An embodiment of a method of accessing a memory is shown. DETAILED DESCRIPTION

[0023] In the following description, certain details are set forth in order to provide a thorough understanding of various embodiments of devices, systems, methods and articles. However, it will be appreciated by those skilled in the art that other embodiments may be practiced without these details. In other cases, known structures and methods associated with, for example, circuits (such as transistors, multipliers, adders, dividers, comparators, integrated circuits, logic gates, finite state machines, memories, interfaces, bus systems, etc.) are not shown or described in detail in some of the accompanying drawings to avoid unnecessarily confusing the description of the embodiments.

[0024] Unless the context requires otherwise, throughout the following specification and claims, the word "comprise" and variations thereof (e.g., "comprising" and "including") are to be interpreted in an open, inclusive sense, i.e., "including but not limited to." References to "at least one" are to be interpreted as meaning either or both disjunctive and inclusive, unless the context dictates otherwise.

[0025] Throughout this specification, references to "an embodiment" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Thus, the phrases "in an embodiment" or "in one embodiment" appearing in various places throughout this specification are not necessarily referring to the same embodiment or all embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments to obtain further embodiments.

[0026] These headings are provided for convenience only and do not interpret the scope or meaning of the disclosure.

[0027] Even if random access decoding circuitry is used to access the random access memory, video streaming and artificial neural network systems may typically use streaming memory access rather than random memory access. Examples of memory access methods for these applications include line buffer and kernel buffer memory access. Typically, streaming access to the random access memory is performed by setting an initial row and providing cyclic serial memory access through the entire array using random access decoding circuitry.

[0028] The inventors have appreciated that when data is stored in random access memory, word line selection circuitry for stream access may be simpler and more area efficient than word line selection circuitry for random memory access. In other words, the random access decoding process and associated circuitry and delays may be avoided by instead using stream access control techniques and circuitry to access a stored data stream.

[0029] In one embodiment, a more flexible type of word line selection may be provided that facilitates time savings by accessing the memory array starting from the memory array row where the target data structure begins and ending at the memory array row where the target data structure ends. Embodiments may facilitate streaming memory accesses by various processes simultaneously while facilitating avoiding the time and area penalties that may occur when implementing streaming accesses using random memory access techniques.

[0030] Figure 11 is a functional block diagram of an embodiment of an electronic device or system 100 of the type to which the embodiments to be described may be applied. The system 100 includes one or more processing cores or circuits 102. The processing core 102 may include, for example, one or more processors, state machines, microprocessors, programmable logic circuits, discrete circuit devices, logic gates, registers, etc., and various combinations thereof. The processing core may control the overall operation of the system 100, the application programs executed by the system 100, etc.

[0031] The system 100 includes one or more memories, such as one or more volatile and / or non-volatile memories, which may store, for example, all or part of instructions and data related to the control of the system 100, applications and operations executed by the system 100, etc. As shown, the system 100 includes one or more cache memories 104, one or more main memories 106, and one or more secondary memories 108, each including a memory management circuit device or MMU 110. One or more of the memories 104, 106, 108 include a memory array (e.g., see Figure 2 The memory array 208, Figure 7 The memory array 708 may be shared by one or more processes executed by the system 100 during operation.

[0032] The system 100 may include one or more sensors 120 (e.g., accelerometers, pressure sensors, temperature sensors, etc.), one or more interfaces 130 (e.g., wireless communication interfaces, wired communication interfaces, etc.), one or more ANN circuits (such as the illustrated convolutional neural network (CNN) accelerator circuit 140 and other circuits 150, which may include other functional circuits, antennas, power supplies, etc.), and a main bus system 160. The main bus system 160 may include one or more data, address, power, and / or control buses coupled to various components of the system 100. The system 100 may also include other bus systems, such as a bus system 162 that communicatively couples the cache memory 104 and the processing core 102, a bus system 164 that communicatively couples the cache memory 104 and the main memory 106, a bus system 166 that communicatively couples the main memory 106 and the processing core 102, and a bus system 168 that communicatively couples the main memory 106 and the secondary memory 108.

[0033] The one or more main memories 106 are typically working memories of the system 100 (e.g., one or more memories on which the processing core 102 works or on which a coprocessor such as the CNN accelerator circuit device 140 works), and may be typically volatile memories of limited size (e.g., DRAM) that store code and data related to the processing performed by the system 100. For convenience, references herein to data stored in a memory may also refer to code stored in the memory. In one embodiment, non-volatile memories such as SRAM, ReRAM, PCM, MRAM, FRAM, multi-level memory, etc. may be used as or in one or more main memories. The secondary memory 108 may be typically non-volatile memory that stores instructions and data that may be retrieved and stored in the main memory 106 when needed by the system 100. The cache memory 104 may be a relatively fast memory compared to the secondary memory 108 and may typically have a limited size, which may be larger than the size of the main memory 106.

[0034] The buffer memory 104 temporarily stores code and data for later use by the system 100. Instead of retrieving the required code or data from the secondary memory 108 for storage in the main memory 106, the system 100 may first check the cache memory 104 to see if the data or code is already stored in the cache memory 104. The cache memory 104 may significantly improve the performance of a system (e.g., the system 100) by reducing the time and other resources required to retrieve data and code for use by the system 100. When code and data are retrieved (e.g., from the secondary memory 108) for use by the system 100, or when data or code is written (e.g., to the main memory 106 or the secondary memory 108), a copy of the data or code may be stored in the cache memory 104 for later use by the system 100. Various cache management routines may be employed to control the data stored in one or more cache memories 104.

[0035] Figure 2 2 is a functional block diagram of an embodiment of an electronic device or system 200 of the type to which the embodiments to be described may be applied. System 200 may be used, for example, to implement an ANN to classify sensor data. Note that Figure 1 The embodiments can be used to implement Figure 2 An embodiment of the present invention may include a system on a chip (SoC).

[0036] The system 200 includes a global memory 202 that can be used, for example, as main memory for an ANN 203 process or cluster, and for a host system 204 process or cluster (see Figure 1206). Global memory 202 includes memory management circuitry 206 and one or more shared memory arrays 208. Memory management circuitry 206, in operation, employs one or more memory management routines to allocate regions of global memory 202 (e.g., regions of shared memory array 208) to various processes executed by system 200 and to control access to global memory 202, such as access to regions of shared memory array 208.

[0037] The memory array 208 may include nonvolatile memory cells, static memory cells, resistive (ReRAM) memory cells, multi-level ReRam memory cells, ferroelectric (FRAM) memory cells, programmable memory (PROM), electrically erasable memory, modified bit cells with storage and computing elements, etc., and various combinations thereof.

[0038] For example, moving data can cost a lot of energy. Flow and data flow affect how data moves. In addition to moving data, computations can also be performed in memory to reduce energy consumption. Using memory cells that have both storage and computational elements can greatly reduce power consumption. The computational element can be, for example, an adder or a sensing circuit that sums the data stored in a region of the memory array (e.g., sums the values ​​in a cluster defined by one or more rows of one or more columns of the region). The computational / logic element can provide XNOR / XOR-like functions in the bit cell or elsewhere in the memory array, and in the case of BNN (binary neural network), it can be used to implement multiplication. Enhanced functions inside or around the bit cell can also be used to implement garbled circuits for encryption and description, such as in neural network computing. The use of memory with computational and storage elements can facilitate increased system security; when data is transmitted through the system, its actual value will be encrypted. Modified bit cell memory schemes and their arrangement as computational elements may also lead to cross-bar (multiple bit lines and word lines accessed in parallel) architectures to facilitate high-throughput in-memory computation operations.

[0039] In one embodiment, the management routines, access types, and control circuitry for accessing the memory array may be based on request type information, such as referenced Figures 7 to 12 discussed in more detail.

[0040] As shown, ANN 203 includes one or more data movers 210, one or more memory bridges 220, one or more sensors 230 and corresponding sensor interfaces 232, one or more convolutional accelerator engines 240, and one or more fully connected engines 250, which can be implemented and operated in other conventional manners to produce classification output 260.

[0041] Efficient low-power operation can be facilitated by using a hierarchical memory system and efficient reuse of local data. Accelerated CDNN convolutional layers may account for more than 90% of the total operations. Efficiently balancing compute and memory resources for bandwidth and area can achieve better throughput without reaching the relevant upper limits. A design-time configurable accelerator framework (CAF) (such as Figure 3 As shown), the configurable data mover source / sink is an I / O interface (e.g., a camera), a memory hierarchy, and various types of accelerators, including a convolutional accelerator (CA).

[0042] The data mover 210 moves data flows between IO (e.g., sensor interface 232), memory hierarchy (e.g., global memory 202, memory bridge 220), convolution accelerator 240, and fully connected engine 250 in operation. In one embodiment, a fully functional backpressure mechanism handles data flow control and stream multicasting, facilitating reuse of data flows at multiple block instances. Link lists can control fully autonomous processing of entire convolutional layers in the ANN. Multiple accelerators can be combined or chained to process various sizes of feature map data and multiple kernels in parallel.

[0043] In one embodiment, the convolution accelerator engine 240 may include an array of clustered multiply-accumulate (MAC) units or circuits that implement convolution layer processing in the ANN in operation. The convolution accelerator engine may include a line buffer to fetch multiple feature map data words in parallel with a single memory access. A register-based kernel buffer may be used that provides multiple read ports, with multiple multi-bit fixed-point MAC units or circuits performing multiple MAC operations in each clock cycle. An adder tree may be used to sum the MAC results for each kernel column. Column-based overlapping computation of MAC operations facilitates optimal reuse of feature map data for multiple MACs and reduces power consumption associated with redundant memory accesses.

[0044] In some embodiments, system 100 or system 200 may include more components than shown, may include fewer components than shown, may divide the components shown into separate components, may combine the components shown, etc., as well as various combinations thereof. For example, in addition to or in place of internal secondary memory, Figure 1 The secondary memory 108 of the system 100 may include an external memory coupled to the system 100 through an interface. In some embodiments, the main memory 106 and the secondary memory 108 may be combined into a single memory. In some embodiments, the cache memory 104 may be omitted. In another example, in addition to or in lieu of a separate MMU 110, one or more main memories 106 may share a common memory management circuit device.

[0045] In the context of an embedded ANN system, a large amount of on-chip memory of the ANN system may be required to store frequently accessed kernel data, intermediate portions, and feature data, while only a smaller portion may be required to store less frequently accessed configuration / layer sequence data. Therefore, accessing shared memory based on the type of memory request (e.g., streaming memory access by an ANN accelerator circuit device) can significantly reduce processing time. The inventors have realized that conventional streaming memory access based on random access routines has a built-in time penalty, thereby slowing down access time. For example, a memory array initialized at the first row may unnecessarily access rows until the row with the required data or instructions is reached. Repeated access to the same data makes the time penalty more expensive. Memory access by concurrent processes may be hindered by having to wait for the accessing process to complete its memory access.

[0046] Figure 3 is a functional block diagram of an embodiment of a configurable accelerator framework (CAF) 300, which, when implemented as a SOC, may be organized as an image and deep convolutional neural network (DCNN) coprocessor subsystem of the SoC, e.g. Figure 2 System 200. As described herein, CAF 300 includes a reconfigurable data stream accelerator structure that connects a high-speed camera interface to any one or more of a sensor processing pipeline, a cropper, a color converter, a feature detector, a video encoder, an eight-channel digital microphone interface, a stream DMA, and a plurality of convolution accelerators. In short, CAF 300 receives incoming image data, such as from a camera interface or other sensor, and distributes the incoming data to various components of CAF 300 (e.g., convolution accelerators) and / or one or more DSPs of a plurality of DSPs to employ a DCNN and recognize objects in the incoming image.

[0047] CAF 300 utilizes unidirectional links to transfer data streams from different types of source components or to different types of sink components through configurable, fully connected switches. For example, the configurable, fully connected switch can transfer data to the SoC global memory through direct memory access (DMA) (see Figure 2 global memory 202), I / O interfaces (e.g., cameras), and various types of accelerators (e.g., convolution accelerators (CA)).

[0048] In each CA, a register-based core buffer provides multiple read ports (e.g., 36), and multiple fixed-point multiply-accumulate (MAC) units (e.g., 36 16-bit MAC units) perform multiple MAC operations per clock cycle (e.g., up to 36 operations per clock cycle). An adder tree accumulates MAC results for each core column. Column-based overlapping calculations of MAC operations allow acceptable reuse of feature map data for multiple MACs, thereby reducing power consumption associated with redundant memory accesses.

[0049] The kernel set is split into batches that are processed sequentially, and intermediate results can be stored in the SoC global memory (see Figure 2 A single CA instance can handle various kernel sizes (e.g., up to 12×12), various batch sizes (e.g., up to 16), and parallel kernels (e.g., up to 4), but the accumulator input can accommodate kernels of any size.

[0050] Configurable batch size and variable number of parallel cores enable trade-offs between available input and output bandwidth shared among different units and available compute logic resources.CAF 300 includes a flow switch 302 that provides a runtime reconfigurable accelerator interconnect framework of design-time parameters to support dataflow-based processing chains.

[0051] Figure 4 A convolution accelerator (CA) embodiment 400 is shown, which may be used, for example, in Figure 1 Embodiments of the system 100 Figure 2 Embodiments of the system 200, or use as Figure 3 CA 400 includes three input data interfaces and one output data interface, each of which is arranged to be coupled to a flow switch 302 (see Figure 3). The first CA input data interface 402 is arranged to couple to a first flow switch output port, the second CA input data interface 404 is arranged to couple to a second flow switch output port, and the third CA input data interface 406 is arranged to couple to a third flow switch output port. The CA output data interface 408 is arranged to couple to a selected flow switch input port.

[0052] In an exemplary embodiment, a first CA input data port 402 is arranged to pass a batch data stream to the CA 400, a second CA input data port 404 is arranged to pass a kernel data stream to the CA 400, and a third CA input data port 406 is used to pass a feature data stream into the CA 400. An output data port 408 is arranged to pass an output data stream from the CA 400.

[0053] CA 400 includes several internal memory buffers. In some embodiments, the internal memory buffers may share a common memory space. In other embodiments, some or all of the internal memory buffers may be separate and distinct from one another. The internal memory buffers may be formed as registers, flip-flops, static or dynamic random access memory (SRAM or DRAM), or some other structural configuration. In some cases, the internal memory buffers may be formed using a multi-port architecture that allows, for example, one device to perform a data "store" operation in memory while another device performs a data "read" operation in memory.

[0054] The first CA internal buffer 410 is physically or virtually aligned with the first CA input data interface 402. In this way, batches of data flowing into the CA 400 can be automatically stored in the first CA internal buffer 410 until the data is passed to a specific math unit in the CA 400, such as the adder tree 422. The first CA internal buffer 410 can be fixed to a size determined at design time. Alternatively, the first CA internal buffer 410 can be defined as a variable size that is programmatically determined at boot time or run time. The first CA internal buffer 410 can be 64 bytes, 128 bytes, 256 bytes, or some other size.

[0055] A second CA internal buffer 412 and a third CA internal buffer 414 are formed along the line of the first CA internal buffer 410. That is, the second and third CA internal buffers 412, 414 can each have their own fixed size determined at design time. Alternatively, the second and third CA internal buffers 412, 414 can have a variable size that is programmatically determined at boot time or run time. The second and third CA internal buffers 412, 414 can be 64 bytes, 128 bytes, 256 bytes or other sizes. The second CA internal buffer 412 is physically or virtually arranged in line with the second CA input data interface 404 to automatically store the kernel data of the stream until the kernel data is passed to the dedicated fourth CA internal buffer 416 dedicated to storing kernel buffer data. The third CA internal buffer 414 is physically or virtually arranged in line with the adder tree 422 to automatically store the summed data until it can be passed through the CA output interface 404.

[0056] The fourth CA internal buffer 416 is a dedicated buffer arranged to desirably store kernel data and apply the stored kernel data to a plurality of CA multiply-accumulate (MAC) units 420 .

[0057] The fifth CA internal buffer is a feature line buffer 418, which is arranged to receive the feature data streamed through the third CA input interface 406. Once stored in the feature line buffer, the feature data is applied to a plurality of CA MAC units 420. The feature and kernel buffer data applied to the CA MAC units 420 are mathematically combined according to a convolution operation, and the output results from the CA MAC units 420 are passed to a CA adder tree 422. The CA adder tree 422 mathematically combines (e.g., sums) the incoming MAC unit data and batch data passed through the first CA input data port.

[0058] In some cases, CA 400 also includes an optional CA bus port interface 424. When CA bus port interface 424 is included, CA bus port interface 424 can be used to transfer data from SoC global memory (see Figure 2 400) or some other location to or from the CA 400. In some cases, the CA 400 may also include CA configuration logic 426.

[0059] Figure 55 is a top view of an embodiment of a random access memory (RAM) 500 having a memory array 502, address decoding logic 504, which includes pre-decoding logic 506 and post-decoding logic 508 as shown. The memory array 502 is organized in rows and columns. Address and clock signals are provided to the address pre-decoding logic 506, which decodes the address to generate control signals to control the post-decoding logic 508. The post-decoding logic drives the word line buffer 520, which in turn drives the row or enable word line (not shown). The enabled word line can allow access (read or write) to the bit content of the corresponding row of the memory array. The random access memory 500 typically employs a large amount of combinational logic circuitry dedicated to the address pre-decoding logic 506 and the address post-decoding logic 508 to convert the input storage address to the word line output to the memory array 502.

[0060] Figure 6 An example embodiment of conventional address decoding logic 604 is shown, including pre-decoding logic 606 and post-decoding logic 608. The decoding logic 604 includes a plurality of logic gates 610, 612 that affect the area and power for word line selection and the delay associated with selecting a word line in response to a memory access. The gates 610, 612 may be dynamic, static, or various combinations thereof, depending on various power, performance, and area tradeoffs.

[0061] The inventors have recognized that accessing a memory array using a deterministic or defined pattern in the context of streaming access can help avoid the large layout area and high power consumption associated with conventionally accessing RAM in a sequential manner from an initial starting address. For example, accessing an ANN line buffer (see Figure 4 The feature line buffer 418) and the kernel buffer (see Figure 4 The kernel buffer 416 of the memory array). A mode that promotes streaming access, serial access, or other streaming access to the memory array can be used to simplify the circuit device for accessing the memory array, reduce the related time delay and power cost, etc. The embodiment can use a dedicated memory with a simplified access circuit device (for example, one or more memory arrays dedicated to storing data for streaming access, such as access associated with ANN line buffers, kernel buffers, etc., whose address circuit device accesses the memory in a streaming manner based on a defined mode), or a shared memory with a conventional RAM access circuit device and an access circuit device that accesses the memory in a streaming manner based on a deterministic or defined mode (for example, a shared memory with a portion dynamically allocated to processes using conventional RAM access and processes using streaming access and processes using corresponding access circuit devices to respond to such access requests), etc.

[0062] Figure 7 7 is a top view of an embodiment of a stream access memory 700, which includes a random access memory array 702 organized in rows and columns. A word line buffer 720 drives the word lines. An enabled word line may allow access (reading or writing) to the bit contents of a corresponding row of the memory array 702. A stream access control circuit device 704 includes a configuration control circuit device 708 and a stream control circuit device 710, and controls the generation of word line signals. The stream access control circuit device 704 may use much less area than the address decoding logic for a conventional RAM memory array. The offset information and the stream access configuration information are provided to the configuration control circuit device 708, and the configuration control circuit device 708 may generate a control signal to control the stream control circuit device 710 based on the offset information and the stream access configuration information. The offset and configuration information may include one or more offset addresses to define the region of the memory to be accessed (e.g., an offset for identifying the starting row of the access, an offset for identifying the ending row of the access request, an offset for identifying the starting column of the access, an offset for identifying the ending column of the access, a z-axis offset for identifying the starting slice of the three-dimensional memory array, a z-axis offset for identifying the ending slice of the three-dimensional memory array, an offset for identifying the region associated with the stride access, etc., and various combinations thereof), and one or more access request types to define the type of access (e.g., access request size, access stride distance, backward access indication, and re-access or repeated access, etc.). For temporary serial access, the configuration information may include information identifying multi-stream access and arrival time thresholds. The configuration information may include computational operations to be performed (e.g., adding values ​​stored in a region of the memory such as a row of the access region, an XOR function to be applied to data stored in a region of the stream access memory, etc.). Such computational operations may be implemented as in-memory computational operations (e.g., in bit cells, elsewhere in the memory), or separate from the memory. Based on the control signals generated by configuration control circuitry 708 in response to the offset address and configuration information, flow control circuitry 710 generates signals to control activation of the bit lines and word lines, for example, via word line buffers 720 (see Fig.10 ).

[0063] As described above, the memory can be organized into an array of rows and columns. Each row can have a line for accessing the smallest addressable unit of the memory, usually called a word line, which spans all columns or a set of columns of the array. The set of columns corresponding to a word can span an entire row of the array, or each row can contain multiple words (for example, columns 0-7 correspond to the first word, columns 8-15 correspond to the second word; columns 0-15 correspond to the first word, columns 16-31 correspond to the second word; etc.). Each column can have a bit line across the row. By asserting one or more word lines, all bits in the corresponding row of the set of columns corresponding to one or more words can be accessed. Typically, one word corresponds to 16 bits or columns. However, words of a size other than 16 bits can be configured for random access memory.

[0064] In addition, the memory can be organized as a collection of arrays. Thus, an address or set of addresses in a memory can be specified, for example, by one or more z or depth offsets (e.g., an offset that specifies that one or more arrays of a collection of arrays contain the set of cells to be accessed), by one or more x or column or word offsets (e.g., which columns or words contain the set of cells to be accessed), and by one or more y or row offsets (e.g., which rows of an identified array contain the set of cells to be accessed). Alternative ways of defining the set of cells to be accessed can be used (e.g., using a starting offset and some arrays, rows, columns, or words that the set of cells to be accessed spans). Frames consisting of blocks of arrays can also be used. For example, the memory can be logically or physically organized into frames, each frame comprising a set of Z arrays, each Z array having X columns (bits, words, or bytes) and Z rows (bits, words, or bytes). Cascaded arrays of stream access memories can be used, in which data flows between stream access memories.

[0065] Figure 8 A two-dimensional representation of a portion of a memory array 802 and an example region of the memory array that can be accessed in a stream manner are shown. For ease of illustration, a two-dimensional array is shown, but a three-dimensional array may be used in some embodiments. As shown, rows 0 to 13 of columns 0 to 15 are shown. As shown, columns 0 to 7 of a row correspond to a first word, and columns 8 to 15 of a row correspond to a second word.

[0066] The first example region 840 of memory cells to be stream-accessed spans cells from the cell at row 1 and column 2 to the cell at row 11 and column 5. The offset information provided to the configuration control circuit device 708 may indicate the offset addresses of rows 1 and 11, may indicate the offset address of row 1 and the size of row 11, etc., as well as various other types of offset information to indicate to the configuration control circuit that the desired access is a stream access to region 840. The offset information may also indicate the offset address of the desired column (e.g., in the case where the memory array is addressable bit by bit rather than word by word), or the output of the unneeded column may be simply ignored in the output word in response to the access request. When the array stores multiple sets of words in a column, a column or word offset may also be employed to identify the word storing the bits of the desired region. For example, word 0 may be represented by an offset. The configuration information may also include in-memory computation information (e.g., functions to be applied to the data to be streamed, such as addition, encryption functions, etc.). Default configuration information may be employed, such as automatically applying an encryption function in the memory when streaming data.

[0067] A second example region 842 of memory cells to be stream-accessed spans cells from cells at row 3 and column 8 to cells at row 13 and column 8. The offset information provided to the configuration control circuitry 708 may indicate the offset addresses of rows 3 and 13, may indicate the offset address of row 3 and the size of row 11, etc., as well as various other types of offset information to indicate to the configuration control circuitry that the desired access is a stream access to region 840. The offset information may also indicate the offset address of the desired column 8 (e.g., in the case of a bit-addressable memory array), or that the output of a word (e.g., word 1) and undesired columns may be simply ignored in the output word in response to the access request.

[0068] A third example region 844 of memory cells to be stream-accessed spans cells from a cell at row 1, column 7 to a cell at row 2, column 13. The offset information provided to the configuration control circuitry 708 may indicate the offset addresses of rows 1 and 2, may indicate the offset address of row 1 and the size of 2 rows, etc., as well as various other types of offset information to indicate to the configuration control circuitry that the desired access is a stream access to the region 840. The offset information may also indicate the desired offset addresses of columns 7 through 13, or the offset of column 7 and the number of columns 7 (e.g., in the case of a bit-addressable memory array), or words (e.g., words 0 and 1, since the region to be accessed spans two words, or the offset of word 0, and the number of words 2) and the output of unneeded columns may simply be ignored in the output word in response to the access request.

[0069] The request may include configuration information indicating, for example, that the desired stream access should be repeated a certain number of times. For example, in one embodiment, the request to access region 840 may be repeated four times so that the data stored in each column 2-5 of the row region may be streamed to the adder tree. Other types of configuration information such as those discussed elsewhere herein may be employed.

[0070] The concept of streaming memory access to a region of memory can be extended to a three-dimensional representation of a region of memory. Fig. 9 A three-dimensional representation of a portion of memory 900 and an example area of ​​a cell of memory 900 that can be accessed in a streaming manner are shown. As shown, the memory is organized into F frames 950 (three frames F are shown). As shown, each frame has: a depth or z dimension 952, which represents the number Z of arrays 954 in frame 950 (four arrays per frame, as shown); a width or x dimension 956, which represents the pixel (word) width X of each array (five pixels as shown); and a height or y dimension 958, which represents the line height Y of each array (5 lines as shown). The frame offset 960 indicates the number of arrays between the array of the first frame and the corresponding array of the adjacent frame in bytes (as shown, the frame offset is 5). Elements (pixels) in the array can be accessed by specifying a frame offset f, a depth offset z, a width offset x, and a height offset y (e.g., offset {f, z, x, y}). The region to be accessed in the stream access can be defined by specifying the frame f, the starting z offset z1, the ending z offset z2, the starting x offset x1, the ending x offset x2, the starting y offset y1, and the ending y offset y2 (for example, a region can be defined by {f, z1, z2, x1, x2, y1, y2}). Fig. 9 As shown, area 970 (only a portion of it is shown) can be represented by parameters {2 (frame), 1 (start frame offset), 2 (end frame offset), 1 (start width offset), 4 (end width offset), 0 (start row offset), 2 (end row offset)}.

[0071] Instead of specifying an ending offset, a distance may be specified. For example, a region to be visited may be defined by specifying a frame f, a starting z offset z1, a number of arrays zn, a starting x offset x1, a number of pixels xn, a starting y offset y1, and a number of lines yn (e.g., a region may be defined by {f, z1, zn, x1, xn, y1, yn}). Hexadecimal notation may be used to specify offsets and distances. Parameters may be specified in various sequences.

[0072] The omitted information may be defined to indicate that the offset range of a particular parameter is not applicable. For example, a region defined only by the number of frames parameter may be defined to indicate that the region includes the entire frame. In another example, a region defined by the frame, depth offset, and pixel offset without specifying any line offset may be defined to include all lines at a specified depth including a specified pixel. In another example, a region defined by the number of frames, depth offset, pixel offset, and start row offset may indicate that the region includes all rows starting with the start row offset. Other definitions may be used to interpret parameters for a region within a specified memory.

[0073] Other configuration information or parameters may be specified to indicate how to access a defined region. For example, parameters may be provided to: indicate that the region is to be processed in a particular sequence; indicate that each column or row is to be repeatedly accessed a particular number of times; indicate that every other row is to be accessed instead of every row in the region; etc.

[0074] In another example, a stride parameter may be set to indicate that a first region of a given size is to be accessed, then an adjacent region of the same size is to be accessed, a region a certain distance from the first region is to be accessed, etc. A sliding window may be defined, and the contiguous regions in memory to be accessed may be specified with a step size corresponding to overlapping or non-overlapping regions of the defined size.

[0075] Fig. 9 This can be viewed as an illustration of a sliding window or striding application, where the window size is the frame. The first visit will process the first frame of pixels defined by the frame size parameters Z, X, and Y (e.g., starting at the specified pixel 0,0,0). The starting pixel is moved by a frame offset (e.g., 960), and the frame size parameters are used to define the second region for the second visit. The process is repeated to define the third region for the third visit, and so on, until the specified number of frames (regions) have been processed.

[0076] Fig.10 It is shown that, for example, Figure 7 1004 is a functional block diagram of a stream access control circuit device 1004 used as the access control circuit device 704 in an embodiment of the present invention. The access control circuit device 1004 includes a configuration control circuit device 1008 and a stream control circuit device 1010. The stream control circuit device includes a shift register 1014 with multiple circles 1012, a group 1016 of multiplexers 1018, and a word line buffer group 1020, which drives a word line 1022 coupled to the memory array 1002. In some embodiments, the access control circuit device 1004 can be coupled to multiple memory arrays, for example, logically or physically organized into a three-dimensional memory (see Fig. 9 ).

[0077] Configuration control circuitry 1008 receives offset information 1030 (eg, one or more offsets defining a memory region or a starting point in a memory, such as a memory organized in a three-dimensional space (see Fig. 9 )) and configuration information 1032 (e.g., a sequence of memory cells of a defined region in memory or starting from a defined starting point in memory), in-memory computation information (e.g., a function to be applied to the data to be accessed), and as shown includes a clock generation or control circuit device 1028. Based on the received offset information 1030 and the received configuration information 1032, the configuration control circuit device generates a register data 1034 to be loaded into the shift register 1014 and a flow control signal 1036 that controls the clock, initialization / loading and shifting (increment / decrement) of the shift register 1014. The register data 1034 and the control signal can be loaded into the shift register group 1012 in a parallel or serial manner (e.g., via multiple lines coupled to the corresponding inputs of the shift registers 1014 of the shift register group 1012). The output 1038 of the shift register is coupled to the corresponding input and selection line of the multiplexer 1018 of the multiplexer group 1016. The lookup table may be used to generate the register data 1034 and the control signals provided by the configuration control circuitry 1008 to the shift register bank 1012. The output 1040 of the multiplexer bank is coupled to the individual word line buffers of the word line buffer bank 1020.

[0078] As shown, the configuration control circuit device 1008 includes a configuration control memory 1060, which is used to store information about one or more data regions in the memory array 1002. For example, region definitions, sizes, shapes, access control parameters, in-memory calculation parameters, etc. can be stored in the configuration control memory 1060 (e.g., input through offset information 1030 and configuration information 1032) and retrieved or activated by commands provided to the configuration control circuit device 1008. Memory maps can be stored in the configuration control memory 1060 and used to control streaming access to the memory array 1002.

[0079] Multiple processes may utilize access control circuitry 1004 to access memory array 1002. Configuration control circuitry 1008 may determine a process accessing one or more memory arrays 1002 and determine a memory region associated with the process and a stream access algorithm associated with the process (e.g., by identifying a stored region definition and a stored access algorithm (which may include an in-memory computation operation) associated with the identified process).

[0080] Fig.11 It is shown Fig.101014a and 1014b. Shift register group 1012 includes shift registers 1014a and 1014b. Shift registers 1014a and 1014b are coupled to configuration control circuit device 1008 via flow control signal line 1036, controlling the reception of register data 1034 and the shifting of data contained in shift registers 1014a and 1014b. Shift register 1014A includes M data bits coupled together so that when the select signal is asserted and a valid clock edge occurs, the bits of shift register 1014a are shifted to adjacent bit cells in the direction indicated by the up / down control signal of flow control line 1036. Shift register 1014a can be configured to shift contents cyclically so that the first bit of shift register 1014a can receive the contents of the last bit of shift register 1014a, or vice versa depending on the direction of the shift. Shift register 1014b is coupled to configuration control circuitry 1008 via configuration control or flow control line 1036 and is configured in a similar manner as shift register 1014a.

[0081] The output of the shift register 1014b is coupled to a corresponding first multiplexer input 1076 of the multiplexer bank 1016. The contents of the shift register 1014b are output to the word line 1022 when the first multiplexer input 1076 of the array of multiplexers 1016 is selected.

[0082] The set of multiplexers 1016 is coupled between the shift register set 1012 and the memory array(s) 1002. Each multiplexer 1018 in the multiplexer set 1016 has an output 1078 that is coupled to a corresponding word line 1022 in the memory array(s) 1002 via a corresponding buffer in the buffer set 1020. Each bit output of the shift register 1014a is coupled to a multiplexer control input 1080 of a corresponding multiplexer 1018 of the multiplexer set 1016. The multiplexers 1018 of the multiplexer set 1016 are coupled together in a cyclic manner, with the corresponding second input of each multiplexer coupled to the output of an adjacent multiplexer in the multiplexer set.

[0083] Fig.12 is a functional block diagram illustrating an embodiment of a memory 1202 employing an access control circuit device 1204, the access control circuit device 1204 including a random access control circuit device 504 (similar to Figure 5 Random access control circuit device 504) and stream access control circuit device 1004 (similar to Fig.10In response to receiving a memory access request (e.g., a random access request or a streaming access request that specifies an address to be accessed in the memory array 1208), the access control circuit device 1204 determines the type of the access request and processes the request according to the determined type of the access request. For example, the type of process that initiates the memory access request may indicate the type of request; the control line on which the request is received may indicate the type of request; the request format may indicate the type of request; and so on. In response to determining that the request is a random access request, the access control circuit device 1204 uses the random access control circuit device 504 to access an address in the memory array 1208. In response to determining that the request is a streaming access request, the access control circuit uses the streaming access control circuit device 1004 to access a region of memory in the memory array 1208. Fig.12 Embodiments of the memory 1202 may be used, for example, as a shared memory, for example, as Figure 2 The global memory 202 may provide higher throughput for streaming memory accesses at a lower power cost than using random access control circuitry to perform streaming accesses to memory.

[0084] Embodiments of memory 1202 may include more components than shown, may include fewer components than shown, may combine the components shown, and may separate the components shown in various ways. For example, an embodiment may include multiplexing circuitry to selectively couple one of random access control circuitry 504 and stream access control circuitry 1004 to address lines of multiple memory arrays 1208. In another example, random access control circuitry 504 and stream access control circuitry 1004 may be combined in one embodiment.

[0085] Fig.13 An embodiment of a method 1300 for accessing a random access memory is shown. The random access memory may be accessed by, for example, Figure 1 System 100, Figure 2 System 200, Figure 7 System 700, or Fig.12 For convenience, reference will be made to Figure 7 and Figure 10-12 To describe Fig.13 Method 1300.

[0086] Method 1300 begins at 1302. For example, in response to a condition such as Fig.12Method 1300 begins by powering up a random access memory, such as random access memory 1208, to respond to a request for accessing the random access memory. Method 1300 proceeds from 1302 to 1304.

[0087] At 1304, method 1300 receives a request to access a random access memory. The request may be received, for example, from a host system such as Figure 2 host system 204), from a data mover associated with a convolution accelerator engine (such as Figure 2 A data mover 210 associated with a convolution accelerator engine 240 of the convolution accelerator, or a process associated with the convolution accelerator (such as Figure 4 The convolution accelerator 400 of the present invention receives the request. The method 1300 proceeds from 1304 to 1306.

[0088] At 1306, the method 1300 determines whether the request is a random access request or a stream access request. As discussed elsewhere herein, this can be done, for example, based on the source of the request, the format of the request, etc., and various combinations thereof.

[0089] When it is determined at 1306 that the request is a random access request, method 1300 proceeds from 1306 to 1308, where the random access request is performed. The random access request may be performed in a conventional manner, for example, as described above with reference to Figure 5 , Figure 6 and Fig.12 As discussed. The method proceeds from 1308 to 1316.

[0090] When it is determined at 1306 that the request is a stream access request, method 1300 proceeds from 1306 to 1310. At 1310, the method determines an offset associated with the determined region of random access memory and a mode of the stream access request based on the stream access request. This operation can be performed, for example, based on an explicit indication included in the stream access request, based on stored information associated with a command included in the stream access request, based on a default setting, based on a lookup table, based on the source of the stream access request, etc., as well as various combinations thereof. Action 1310 can be performed, for example, by Figure 7 The stream access control circuit device 704 is composed of Fig.10 and Fig.12 The stream access control circuit device 1004 executes.

[0091] At 1312, method 1300 performs the stream access request based on the determined offset associated with the determined region of random access memory and the determined pattern of the stream access request. For example, this operation can be accomplished by identifying the determined region based on the offset or based on the offset and the pattern, and activating word lines of the random access memory to access words of the determined region according to the pattern. Action 1312 can be performed, for example, by Figure 7 The stream access control circuit device 704 is composed of Fig.10 and Fig.12 The stream access control circuit device 1004 executes. The method 1300 proceeds from 1312 to 1316. Executing the stream access request may include performing an in-memory computation operation, such as adding data stored in the memory region, performing XOR on the data stream, and the like.

[0092] At 1316 , method 1300 optionally performs other processing associated with the received request to access the random access memory, such as processing indicating that the random access memory can process another request. From 1316 , method 1300 proceeds to 1318 .

[0093] At 1318, method 1300 determines whether method 1300 is complete or should continue, such as in response to a host control signal. When it is determined at 1318 that processing of the memory access request is complete ("yes" at 1318), method 1300 proceeds to 1320. At 1320, method 1300 may terminate, other processing (e.g., error processing) may be performed, etc. When it is determined at 1318 that processing of the memory access request is not complete, method 1300 returns to 1304 to wait for another request to access the random access memory.

[0094] Embodiments of the method for processing access requests to random access memory may include other behaviors not shown in FIG. 13 and may not include Fig.13 All actions shown in the Fig.13 1300 and may be modified in various aspects. For example, when the memory is dedicated to streaming memory access requests, method 1300 may omit actions 1306 and 1308.

[0095] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer readable medium is provided, which includes a computer program suitable for performing one or more of the above methods or functions. The medium may be a physical storage medium (such as, for example, a read-only memory (ROM) chip), or a disk (such as a digital versatile disk (DVD-ROM), a compact disk (CD-ROM), a hard disk), a memory, a network, or a portable media product read by an appropriate drive or by an appropriate connection (including encodings encoded as one or more bar codes or other related codes, which are stored on one or more such computer readable media and can be read by an appropriate reader device).

[0096] In addition, in some embodiments, some or all of the methods and / or functions may be implemented or provided in other ways, such as at least partially in firmware and / or hardware, including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices employing RFID technology and various combinations thereof.

[0097] The various embodiments described above can be combined to provide other embodiments. Aspects of the embodiments can be modified if necessary to employ the concepts of the various embodiments and publications to provide other embodiments.

[0098] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. A device comprising: one or more inputs configured to receive a streaming access request for accessing a plurality of individually addressable words of a determined region of a random access memory, the request indicating an offset associated with the determined region and a mode associated with the streaming access; a plurality of outputs configured to be coupled to word lines of the random access memory; as well as stream access control circuitry coupled to the one or more inputs and the plurality of outputs and configured to: respond to the stream access request by generating a control signal for driving the word line to access the plurality of individually addressable words of the determined region; The stream access control circuit device includes a plurality of shift registers and a configuration control circuit device, wherein the configuration control circuit device is configured to generate register data and a register control signal, wherein the register control signal is used to control: loading the register data into the plurality of shift registers and shifting the plurality of shift registers. 2 . The apparatus of claim 1 , wherein the request comprises the offset associated with the determined area.

3. The apparatus of claim 2, wherein the request comprises an indication of the mode associated with the stream access. 4 . The apparatus of claim 3 , wherein the stream access control circuitry identifies the determination region based on the offset and the indication of the mode associated with the stream access.

5. The apparatus of claim 3, wherein the stream access control circuitry comprises a memory configured to store stream access control information, and the indication is a command to perform stream access based on the stored stream access control information. The apparatus of claim 1 , wherein the request indicates a plurality of offsets defining the determined region.

7. The apparatus of claim 1 , wherein the stream access control circuitry further comprises: A flow control circuit device is configured to generate the control signal for driving the word line, and the flow control circuit device also includes a multiplexer group, and the multiplexer group is coupled to the plurality of shift registers.

8. The apparatus of claim 7 , wherein a first data input of each multiplexer in the multiplexer group is coupled to a corresponding output of one of the plurality of shift registers, and a select input of each multiplexer in the multiplexer group is coupled to a corresponding output of another of the plurality of shift registers.

9. The apparatus of claim 8, wherein the second data input of each multiplexer in the multiplexer group is coupled to the output of an adjacent multiplexer in the multiplexer group, and the plurality of outputs are coupled to respective outputs of the multiplexers in the multiplexer group.

10. The apparatus of claim 1, wherein the random access memory is addressable in a three-dimensional address space.

11. The apparatus of claim 1, wherein the stream access control circuitry is configured to generate a control signal for performing one or more in-memory compute operations associated with the stream access request.

12. A system comprising: Random access memory, organized into individually addressable words; as well as streaming access control circuitry coupled to a wordline of the random access memory, wherein the streaming access control circuitry is operative to respond to a request for streaming access to a plurality of individually addressable words of a determined region of the random access memory by generating a control signal for driving the wordline to access the plurality of individually addressable words of the determined region, wherein the request indicates an offset associated with the determined region and a mode associated with the streaming access; The stream access control circuit device includes a plurality of shift registers and a configuration control circuit device, wherein the configuration control circuit device is configured to generate register data and a register control signal, wherein the register control signal is used to control: loading the register data into the plurality of shift registers and shifting the plurality of shift registers.

13. The system of claim 12, wherein the request includes the offset associated with the determined area.

14. The system of claim 13, wherein the request includes an indication of a sequence of the stream accesses.

15. The system of claim 14, wherein the stream access control circuitry identifies the certain region based on the offset and the indication of the sequence of the stream accesses.

16. The system of claim 12, wherein the request indicates a plurality of offsets associated with the determined area.

17. The system of claim 12, wherein the request indicates a plurality of offsets defining the determined area.

18. The system of claim 12, wherein the stream access control circuitry further comprises: A flow control circuit device is configured to generate the control signal for driving the word line, and the flow control circuit device also includes a multiplexer group, and the multiplexer group is coupled to the plurality of shift registers.

19. The system of claim 12, wherein the random access memory is addressable in a three-dimensional address space.

20. The system of claim 12, comprising random access control circuitry coupled to the word lines of the random access memory, wherein the random access control circuitry is operative to respond to requests for access to individually addressable words of the random access memory.

21. The system of claim 12, comprising one or more convolution accelerators coupled to the stream access control circuit device and the random access memory, wherein in operation, the one or more convolution accelerators provide requests to the stream access control circuit device for stream access to multiple individually addressable words of a determined area of ​​the random access memory, and receive responses to the requests from the random access memory.

22. The system of claim 12, wherein the random access memory comprises a storage element and one or more in-memory computing elements, and the stream access control circuit device is operative to respond to a stream access request associated with an in-memory computing operation by generating a control signal for performing an in-memory computing operation using the in-memory computing element of the random access memory.

23. A method comprising: receiving, by a stream access control circuitry of a random access memory, a stream access request for accessing a plurality of individually addressable words of a determined region of the random access memory, the request indicating an offset associated with the determined region and a mode associated with the stream access; responding, by the streaming access control circuitry, to the request by generating control signals for driving word lines of the random access memory to access the plurality of individually addressable words of the determined region; as well as Register data and register control signals are generated by the stream access control circuit device, and the register control signals are used to control: loading the register data into a plurality of shift registers of the stream access control circuit device and shifting the plurality of shift registers. The method of claim 23 , wherein the request includes the offset associated with the determined area.

25. The method of claim 24, wherein the request includes an indication of the mode of access to the stream.

26. The method according to claim 25, comprising: The specific region is identified, by the stream access control circuitry, based on the offset and the indication of the pattern of the stream accesses.

27. The method according to claim 25, comprising: Stream access control information is stored in a memory of the stream access control circuitry, wherein the indication is a command for performing stream access based on the stored stream access control information.

28. The method of claim 23, wherein the request indicates a plurality of offsets defining the determined area.

29. The method of claim 23, wherein the random access memory is addressable in a three-dimensional address space.

30. The method of claim 23, wherein the stream access request is associated with an in-memory compute operation, and the method comprises: The in-memory computation operation is performed as part of the response to the stream access request.

31. A non-transitory computer readable medium having content, the content configuring a stream access controller of a random access memory to perform a method comprising: receiving a streaming access request for accessing a plurality of individually addressable words of a determined region of the random access memory, the request indicating an offset associated with the determined region and a mode associated with the streaming access; responding to the request by generating control signals for driving word lines of the random access memory to access the plurality of individually addressable words of the determined region; as well as Register data and register control signals are generated, wherein the register control signals are used to control: loading the register data into a plurality of shift registers of the stream access controller and shifting the plurality of shift registers.

32. The non-transitory computer-readable medium of claim 31, wherein the request comprises the offset associated with the determined region and an indication of the mode of the stream access.

33. The non-transitory computer readable medium of claim 31, wherein the random access memory is addressable in a three-dimensional address space, and the determined area is a three-dimensional area in the three-dimensional address space.

34. The non-transitory computer readable medium of claim 31, wherein the content comprises a lookup table storing a register table and timing information used by the streaming access controller to generate the control signal for driving the word line.

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