Error correction bit flip scheme

Abstract

The subject application relates to an error correction bit flipping scheme. An error correction bit flipping scheme may include methods, systems, and apparatus for performing error correction of one or more bits (e.g., flipped bits) and efficiently transmitting error correction information. The data bits and the flipped bits (e.g., error-corrected flipped bits) may be directly transmitted (e.g., transmitted to a flip decision component). The flipped bits may be transmitted to the flip decision component via a dedicated and / or unidirectional line that is different from one or more other lines that carry data bits (e.g., carry them to the flip decision component).

Description

[0001] Cross-references

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 058141, filed by Kwak on October 25, 2019, entitled “ERROR CORRECTION BIT FLIPPING SCHEME,” which claims priority to U.S. Patent Application No. 16 / 199,773, filed by Kwak on November 26, 2018, entitled “ERROR CORRECTION BIT FLIPPING SCHEME,” each of which has been assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to an error correction bit flipping scheme. Background Art

[0004] The following relates generally to operating memory devices, and more particularly to an error correction bit flipping scheme.

[0005] Memory devices are widely used to store information in various electronic devices (e.g., computers, wireless communication devices, cameras, digital displays, etc.). Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, usually represented by a logical 1 or a logical 0. In other devices, more than two states can be stored. To access the stored information, a component of the device can read or sense at least one stored state in the memory device. To store information, a component of the device can write or program a state in the memory device.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logical state for a long time even in the absence of external power. Volatile memory devices (e.g., DRAM) may lose their storage state over time unless they are periodically refreshed by an external power source. FeRAM can use a device architecture similar to volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices.

[0007] A memory device may invert a data bit stored at one or more memory cells (e.g., for reliability reasons). A certain bit may indicate that the logic state stored at one or more specific memory cells is inverted. However, error correction of bits associated with the inversion may delay other operations, and propagation delays may exacerbate such delays, thereby introducing significant latency. Enhanced schemes related to bit flipping and error correction operations are desired. Summary of the invention

[0008] A method is described. The method may include receiving an indication at a flipped bit error correction component whether a flipped bit should be corrected; based at least in part on receiving the indication whether the flipped bit should be corrected, processing the flipped bit at the flipped bit error correction component, the processing including correcting the flipped bit at the flipped bit error correction component or passing the flipped bit through the flipped bit error correction component; and based at least in part on processing the flipped bit, transmitting the processed flipped bit directly to a flip decision component via an output line.

[0009] An apparatus is described. The apparatus may include a flip bit error correction component coupled to an error locator component; and a flip decision component directly coupled to the flip bit error correction component via an output line, the flip bit error correction component to: receive an indication of a flip bit error of a flip bit from the error locator component; correct the flip bit error based at least in part on receiving the indication of the flip bit error; and transmit the corrected flip bit directly to the flip decision component via the output line.

[0010] A method is described. The method may include, at a flip decision component, directly receiving an error-corrected flip bit from a flip bit error correction component via a first output line; at the flip decision component, receiving one or more data bits from a data bit error correction component via a second output line; and at the flip decision component, determining whether to invert the one or more data bits based at least in part on receiving the error-corrected flip bit and receiving the one or more data bits.

[0011] A device is described. The device may include a flip decision component; a flip bit error correction component coupled to the flip decision component and configured to directly transmit one or more flip bits to the flip decision component via a first output line coupling the flip bit error correction component and the flip decision component; and a data bit error correction component coupled to the flip decision component and configured to transmit one or more data bits to the flip decision component via a second output line. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 An example of a system for operating a memory device supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown.

[0013] Figure 2 An example of a device supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown.

[0014] Figure 3 An example of a device supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown.

[0015] Figure 4 An example of a device supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown.

[0016] Figure 5 An example of a device supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown.

[0017] Figure 6 An example of a block diagram of an apparatus supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown.

[0018] Figure 7 A block diagram of an apparatus supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown.

[0019] Figures 8 to 10 A flow chart is shown illustrating a method of supporting an error correction bit flipping scheme according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0020] The memory device may invert data bits stored at one or more memory cells (e.g., for reliability reasons). After inverting one or more data bits of the one or more memory cells, the memory device may set an inversion bit to indicate that the logic state stored at the one or more memory cells is inverted. When reading data from the memory, the memory device may perform error correction on one or more bits (e.g., data bits, inversion bits), and may determine (e.g., based on the corresponding corrected inversion bits) whether any data bits have been inverted. However, performing error correction on data bits and inversion bits may delay the read operation, and propagation delays may exacerbate such delays based on the indirect routing of bits from one component to another (e.g., routing the corrected inversion bits through a data bit error correction component so that the data bits must wait for the corrected inversion bits before being transmitted to the data bus inversion component), thereby introducing significant latency into the memory system.

[0021] In some instances of such indirect routing, memory applications may employ inversion bits or flipped bits and error correction components that may correct different bits including data bits and flipped bits. In some instances, the error correction component may correct the flipped bit before transmitting other information (e.g., data) to a data bus flip component, which may be an instance of a flip decision component or may include a flip decision component. In this case, latency may be introduced into data access time because the data must wait for the flipped bit to be corrected and then additionally wait for the corrected flipped bit to propagate to all data bit error correction components before transmitting the data.

[0022] As disclosed herein, latency in a memory system can be reduced by transmitting the corrected flip bit directly to a data bus inversion component or a flip decision component. This can be achieved by transmitting the corrected flip bit on a dedicated line that transmits information directly from the flip bit error correction component to the flip decision component. The dedicated line can be a read-only line or a unidirectional line that can have a faster transmission speed than a bidirectional line (e.g., a data bit transmission line). Because the corrected flip bit can be transmitted directly to the flip decision component, the error correction data component may not need to receive the corrected flip bit at the data bit error correction component, and the data bit can be transmitted directly to the flip decision component on another or more lines.

[0023] In some examples, instead of waiting for the memory array data bits to be corrected for the flipped bits, and instead of adopting alternative schemes (e.g., majority voting schemes, which in some cases may change the physical size of the components), a data bus inversion component or a flip decision component (e.g., which may be located at the global data bus) may be used to determine whether the data bits have been flipped and flip the data bits as needed. In some examples, the flip decision component and the data bus inversion component may be the same component or included in the same component.

[0024] In some examples, by using a flip decision component, once the error correction component corrects any single data bit containing a flip bit, the data can be transmitted over the data bus without having to wait for the corrected flip bit to be received at the data bit error correction component. The data bit (e.g., in some cases, it may be corrected) and the corrected flip bit can be transmitted directly to the flip decision component, so that the data bit may not have to wait for the corrected flip bit before being transmitted to the flip decision component. The flip decision component can then determine whether the data has been inverted based on receiving the corrected flip bit directly from the flip bit error correction component and receiving the data bit from the data bit error correction component, and then invert the data as needed.

[0025] The features of the present disclosure introduced above are further described herein in the context of a memory system. Specific examples of apparatus and methods for performing error correction according to an error correction bit flipping scheme are described. These and other features of the present disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flow charts related to an enhanced error correction bit flipping scheme.

[0026] Figure 1 An exemplary memory array supporting an error correction bit flipping scheme according to various embodiments of the present disclosure is shown. The memory array 100 can be used to store digital information (e.g., binary information) and can also be referred to as an electronic memory device. The memory array 100 includes memory cells 105 that can be programmed to store different states. Each memory cell 105 can be programmed to store two states represented as logic 0 and logic 1. In some cases, the memory cell 105 is configured to store more than two logic states.

[0027] The memory cell 105 may include a memory element having a programmable state. The memory cell 105 in a DRAM or FeRAM architecture may store a charge representing a programmable state in a capacitor; for example, a charged and uncharged capacitor may represent two logic states, respectively. The DRAM architecture may generally use this design, and may use a capacitor containing a dielectric material and having a linear electric polarization property as a memory element. The FeRAM architecture may also use this design, but the capacitor used as the memory element may contain a ferroelectric material having a nonlinear polarization property. The memory cell 105 in a PCM or isolation-based memory (SBM) architecture may change the resistivity (e.g., resistance or threshold voltage) of the material, where different resistivities may represent different logic states. The PCM and / or SBM architecture may use a chalcogenide material having an electronically programmable resistance as a memory element. In some cases, the memory cell 105 in the PCM architecture is programmed by changing the phase of the memory material. In some cases, the memory cell 105 in the SBM architecture is programmed by causing ion movement within the memory material.

[0028] Operations (e.g., reading and writing) can be performed on the memory cell 105 by activating or selecting the appropriate access line 110 and digit line 115. The access line 110 may also be referred to as a word line 110, and the digit line 115 may also be referred to as a bit line 115. Activating or selecting a word line 110 or a digit line 115 may include applying a voltage to the corresponding line. The word line 110 and the digit line 115 are made of conductive materials. For example, the word line 110 and the digit line 115 may be made of metal (e.g., copper, aluminum, gold, tungsten, etc.), metal alloys, other conductive materials, etc. According to Figure 1In the example of FIG. 1 , each row of memory cells 105 is connected to a single word line 110, and each column of memory cells 105 is connected to a single digit line 115. By activating one word line 110 and one digit line 115 (e.g., applying a voltage to the word line 110 or the digit line 115), a single memory cell 105 can be accessed at its intersection. Accessing a memory cell 105 can include reading or writing to the memory cell 105. The intersection of a word line 110 and a digit line 115 can be referred to as the address of the memory cell.

[0029] In some architectures, the logical storage device (e.g., capacitor) of the cell can be electrically isolated from the digital line by a selection component. The word line 110 can be connected to the selection component and can control the selection component. For example, the selection component can be a transistor, and the word line 110 can be connected to the gate of the transistor. Activating the word line 110 results in an electrical connection or closed circuit between the capacitor of the memory cell 105 and its corresponding digital line 115. The digital line can then be accessed to read or write the memory cell 105.

[0030] Access to the memory cells 105 may be controlled by a row decoder 120 and a column decoder 130. In some examples, the row decoder 120 receives a row address from the memory controller 140 and activates the appropriate word line 110 based on the received row address. Similarly, the column decoder 130 receives a column address from the memory controller 140 and activates the appropriate digital line 115. For example, the memory array 100 may include a plurality of word lines 110 labeled WL_1 to WL_M and a plurality of digital lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, by activating a word line 110 and a digital line 115 (e.g., WL_3 and DL_N), the memory cells 105 at their intersections may be accessed.

[0031] When accessed, the memory cell 105 can be read or sensed by the sensing component 125 to determine the storage state of the memory cell 105. For example, after accessing the memory cell 105, the capacitor of the memory cell 105 can be discharged to its corresponding digital line 115. The discharge of the capacitor can be based on biasing or applying a voltage to the capacitor. The discharge can cause a change in the voltage of the digital line 115, which the sensing component 125 can compare with a reference voltage (not shown) to determine the storage state of the memory cell 105. For example, if the digital line 115 has a higher voltage than the reference voltage, the sensing component 125 can determine that the storage state in the memory cell 105 is a logic 1, and vice versa.

[0032] The reliability of the sensing operation may depend on the sensing window resulting from reading the memory cell 105. For example, a larger sensing window may be associated with fewer bit errors than a smaller sensing window. The sensing window may be determined as the difference between the voltage of the digit line 115 resulting from reading the memory cell 105 when storing a logic 1 and the voltage of the digit line 115 resulting from reading the memory cell when storing a logic 0. The sensing component 125 may include various transistors or amplifiers to detect and amplify the difference in the signal, which may be referred to as latching. The detected logic state of the memory cell 105 may then be output as an input / output 135 by the column decoder 130.

[0033] The memory cells 105 may be set or written to by activating the associated word lines 110 and digit lines 115. As discussed herein, activating the word lines 110 electrically connects the memory cells 105 of the corresponding row to their corresponding digit lines 115. By controlling the associated digit lines 115 when the word lines 110 are activated, the memory cells 105 may be written to, e.g., a logic value may be stored in the memory cells 105. The column decoders 130 may accept data (e.g., input / output 135) to be written to the memory cells 105.

[0034] The memory controller 140 can control the operation (e.g., read, write, rewrite, refresh, etc.) of the memory cells 105 through various components (e.g., row decoder 120, column decoder 130, and sensing component 125). The memory controller 140 can generate row and column address signals in order to activate the desired word lines 110 and digit lines 115. The memory controller 140 can also generate and control various voltage potentials used during the operation of the memory array 100. In general, the amplitude, shape, or duration of the applied voltages discussed herein can be adjusted or changed and can be different for various operations of operating the memory array 100. In addition, one, multiple, or all memory cells 105 within the memory array 100 can be accessed simultaneously; multiple or all cells of the memory array 100 can be accessed simultaneously during a reset operation, in which all memory cells 105 or a group of memory cells 105 are set to a single logic state.

[0035] In some cases, the memory array 100 may flip the logic state of the memory cell 105, such as changing the logic value stored in the memory cell 105 from one value (e.g., logic 1) to another logic value (logic 0). The memory array 100 may perform the flipping internally and may not notify other external devices or components that the logic state of the memory cell has been flipped. The memory array 100 may flip the memory cell to save power, increase the reliability of the device, etc. For example, for FeRAM, a ferroelectric memory cell may be flipped to mitigate the effects of imprinting (e.g., drift of ferroelectric domains due to long-term exposure to or storage of the same charge), which may reduce the reliability of the memory cell over time. A memory cell 105 that stores a logic state different from the original logic state (e.g., a logic state expected to be stored at the memory cell by an external device or component) may be referred to as being in an inverted state. A bit indicating whether the data has been inverted may be referred to as a flip bit herein.

[0036] A device (e.g., a host device, a controller) may issue an access command for data. Before the information or data is transmitted back to the host device, certain information (e.g., data bits, parity bits, flip bits) may be corrected for errors. The data bits, parity bits, and flip bits may be received at an error correction component for error correction to facilitate such error correction. In addition, it may be determined whether the data has been inverted. In some instances, a logic component that detects whether the data contains more than four 1s may be used to determine whether the data has been inverted by checking the data bits.

[0037] During error correction, error correction information may be received from the decoder by an error correction component, which may include one or more error correction components to correct one or more errors (e.g., those related to data and / or flip bits). In some cases, the flip bit may have an error correction component, and each bit in the data bit set and the parity bit may have a corresponding error correction component. In some cases, the flip bit may be error corrected, and the error-corrected flip bit may be transmitted to the flip decision component. The error-corrected flip bit may be directly transmitted to the flip decision component, which may be transmitted on a dedicated unidirectional line in some cases. In some cases, one or more data bits may be additionally or alternatively error corrected. Once the flip bit is error corrected, the data bit (which may have been previously error corrected or not) may be directly transmitted to the flip decision component through a second line (e.g., different from the first line on which the error-corrected flip bit is transmitted). The flip decision component may determine whether the data bit has been reversed based on receiving the error-corrected flip bit and / or one or more data bits, and if so, the data bit may be reversed.

[0038] Figure 2An example of a device 200 supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown. In some examples, the device 200 may include a device 200 as described herein. Figure 1 For example, the device 200 may include one or more components described in Figure 2 The error correction component 230 described above may include the decoder 205 and the flip decision component 270.

[0039] In some examples, one or more data bits, one or more parity bits, and one or more toggle bits may be received on lines 250-a, 250-b, and 250-c (e.g., from memory array 220). In some examples, a memory controller (e.g., reference Figure 1 2. The memory controller 140 (described above) may initiate the transmission of one or more data bits, one or more parity bits, and / or one or more toggle bits from the memory array 220. In some examples, the memory controller 140 may be a local memory controller, an external memory controller, or a host device controller. After transmission from the memory array 220, the one or more data bits, one or more parity bits, and / or one or more toggle bits may be received by the error correction code (ECC) decoder 225 on lines 250-a, 250-b, and 250-c. The lines 250-a, 250-b, and 250-c may be lines that carry toggle bits, data bits, and parity bits, respectively.

[0040] In some instances, the ECC decoder 225 may be or may include or may be coupled to a binary decoder (not shown) that may function to locate one or more errors in one or more bits. In some instances, the ECC decoder 225 may decode one or more data bits, one or more parity bits, and / or one or more flip bits to determine errors associated with the one or more data bits, one or more parity bits, and / or one or more flip bits. Then, in some instances, the ECC decoder 225 may transmit the one or more bits (e.g., one or more data bits, one or more parity bits, and / or one or more flip bits) that may include decoded data to the error correction component 230 (e.g., one or more error correction components) on line 260. In some instances, ECC decoder 225 may transmit an indication on line 260 that may include one or more bits of decoded data (e.g., one or more data bits, one or more parity bits, and / or one or more toggle bits) to error correction component 230 (e.g., one or more error correction components).

[0041] In some examples, the error correction component 230 can transmit the error-corrected data directly to the flip decision component 270. In some examples, the error-corrected flipped bits can be transmitted directly to the flip decision component 270 on the line 255-a. For example, this can be done on a dedicated line 255-a between the error correction component 230 and the flip decision component 270 (e.g., without transmitting the error-corrected flipped bits to the data bit error correction component, as previously discussed). For example, this can be done on a unidirectional line 255-a between the error correction component 230 and the flip decision component 270.

[0042] In some examples, the error correction component 230 can transmit the data bit directly to the flip decision component 270 on line 255-b. Transmitting the data bit can be based on processing the flip bit, or transmitting the processed flip bit to the flip decision component, or transmitting the processed flip bit directly to the flip decision component through the flip bit line, or any combination thereof. Although line 255-b is Figure 2 255 - b is indicated as a single line, but this is for illustrative purposes only and is not limiting, as other alternatives are also contemplated. In some examples, line 255 - b may be multiple lines for transmitting data bits from multiple error correction components to the flip decision component. Figure 2 The line 255-b of the flip bit transmission line 255-a can be a separate line from the flip bit transmission line 255-a. In addition, the line 255-b can be a read / write line or a bidirectional line. After the flip decision component 270 receives the data bit and the error-corrected flip bit, the flip decision component can determine whether the data bit has been inverted.

[0043] In some examples, the error correction component 230 can determine one or more errors associated with a data bit in the plurality of data bits and correct the errors associated with the data bit. The errors can be corrected based in part on determining the errors at the ECC decoder 225. In some examples, the error correction component 230 can determine that the data bit may not be error corrected.

[0044] Figure 3 An example of a device 300 supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown. In some examples, the device 300 may include a device 300 as described herein. Figure 1 and / or one or more components described in 2. For example, the device 300 may include reference Figure 2The apparatus 300 may include a decoder 305, a flip bit error correction component 310, one or more data bit error correction components 315-a, 315-b ... 315-n, a flip decision component 320, and a data bus decision component 325. In some examples, the flip decision component 320 may be a data bus inversion component. In some examples, the flip decision component 320 may include a logic component of the data bus decision component 325, so that the flip decision component 320 and the data bus decision component 325 may be the same component.

[0045] exist Figure 3 In the embodiment of the present invention, the device 300 may include a decoder 305 which may be one or more components. In some instances, the decoder 305 may be or include an ECC decoder coupled to a binary decoder. In some cases, the decoder 305 may be able to locate errors in the information decoded by the decoder 305 (e.g., may be used as an error locator). The decoder 305 may receive information (e.g., at an ECC decoder) comprising one or more data bits, one or more parity bits, and / or one or more flip bits. Although other correction components (e.g., parity bit error correction components) are not shown, these other components may perform functions similar to the data bits and flip bit error correction components discussed herein. Although one or more flip bits (e.g., until the flip bit error correction components) may be received, processed, and transmitted at the decoder, a single flip bit will be discussed herein for discussion purposes only.

[0046] Information received at the ECC decoder may be processed and then transmitted to a binary decoder, which may determine the location of one or more errors (eg, in one or more data bits, one or more parity bits, and / or one or more toggled bits).

[0047] After locating one or more errors in the received bits, decoder 305 may transmit one or more data bits, one or more parity bits, and / or one or more flipped bits to corresponding bit error correction components. In this example, decoder 305 may locate an error in one or more bits (e.g., in data [0]). Decoder 305 may then transmit the error location to data bit error correction component 315-a. Although in Figure 3 Only four data bit error correction components 315 are shown, but for each set of data bits, there may be a corresponding data bit error correction component as needed.

[0048] The flipped bit error correction component 310 can receive (e.g., from the decoder 305) an indication of whether the flipped bit should be corrected. In some examples, the flipped bit error correction component 310 can receive an indication that the flipped bit can be corrected, and the flipped bit error correction component 310 can correct the flipped bit based on receiving the indication. The flipped bit error correction component 310 can then transmit the flipped bit directly to the flip decision component 320.

[0049] In some examples, by transmitting the corrected flipped bits directly to the flip decision component 320, the memory system can avoid various aspects that may be included in other error correction schemes, such as increasing the physical size of the component (and using additional memory array data bits), or introducing latency into the memory system by requiring the data correction component to wait for the corrected flipped bits before transmitting to the flip decision component 320.

[0050] In some instances, the flip bit can be transmitted directly to the flip decision component 320 on a line, which can be a dedicated line that couples the flip bit error correction component 310 with the flip decision component 320. In some cases, the flip bit line is a read-only and unidirectional line. Because the flip bit line can be read-only and unidirectional, data transmission on the flip bit line can be faster than on a read / write bidirectional line. In some instances, because the flip bit line can have a faster data transmission speed and / or other advantageous features, the transmitted error correction flip bit can be advantageously received by the flip decision component 320 before receiving the data bit. Because the error-corrected flip bit can be transmitted on a line separate from the data bit, the data bit component may not have to wait to receive the error correction flip bit at the error correction component before transmitting it to the flip decision component 320, thereby reducing latency and achieving other advantages.

[0051] In some examples, the error-corrected flipped bits may be received in parallel or simultaneously with at least one of the data bits by the flip decision component 320. The flip decision component 320 may be configured to determine whether the received data bits have been flipped based on at least a subset of the received data bits, or the flip decision component 320 may be configured to wait until all data bits have been received and then determine whether the data bits have been flipped.

[0052] Similarly, additional or alternative indicated errors in the data bits can be corrected (e.g., at the data bit error correction component 315), and the corrected data bits can then be transmitted directly to the flip decision component 320 and to the data bus decision component 325. In some instances, the data bits can be transmitted directly to the flip decision component 320 and can be transmitted on a separate line from the corrected flip bits. Because the corrected flip bits can be transmitted on a separate line from the data bits, the data bits may not have to wait for the corrected flip bits to be received at the error correction component before being transmitted to the flip decision component 320. In some instances, at least some of the data bits can be received at the flip decision component 320 after receiving the flip bits.

[0053] The flip decision component 320 can determine whether one or more data bits and / or one or more flip bits have been inverted. In some instances, the flip decision component 320 can directly receive the flip bit from the flip bit error correction component 310 (e.g., via a dedicated flip bit line). The data bits can be transmitted from the data bit error correction component via corresponding local buses 315-a, 315-b, ... 315-n, and can be received at the flip decision component 320 and the data bus decision component 325, which are described with reference to other figures in this article. In some instances, the flip decision component 320 can use configuration logic criteria to determine the output value based on the received data bits and the corrected flip bits.

[0054] In some instances, after locating one or more errors, decoder 305 may transmit one or more data bits, one or more parity bits, and / or one or more flipped bits to a corresponding error correction component. In some instances, decoder 305 may locate one or more errors (if any) in the received data bits and transmit this information to a corresponding data bit error correction component. In this instance, decoder 305 may locate an error in one or more bits (e.g., in data[0]). Decoder 305 may then transmit this error location to data bit error correction component 315-a. Although in Figure 3 Only four data bit error correction components 315 are shown, but for each set of data bits, there may be a corresponding data bit error correction component as needed.

[0055] Figure 4 An example of a device 400 supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown. In some examples, the device 400 may include a device 400 as described herein. Figure 1-3 For example, the device 400 may include one or more components described in Figure 2 and 3The device 400 may include a decoder 405, a flip bit error correction component 410, data bit error correction components 415-a, 415-b...415-n, a flip decision component 420, and a data bus decision component 425.

[0056] exist Figure 4 In the embodiment of the present invention, the ECC decoder 403 can receive one or more data bits, one or more parity bits, and one or more toggle bits, and in some cases, the ECC decoder 403 can be coupled with the binary decoder 405. In some examples, the ECC decoder 403 can decode multiple data bits and multiple parity bits. The decoding process associated with the ECC decoder 403 can facilitate the determination of errors associated with at least one of the one or more data bits, the one or more parity bits, and the one or more toggle bits.

[0057] In some instances, the ECC decoder 403 may transmit one or more data bits, one or more parity bits, and one or more flipped bits to the binary decoder 405. In some instances, the binary decoder 405 may transmit error information to each corresponding error correction component. In some instances, the binary decoder 405 may determine error information about multiple data bits. The binary decoder 405 may transmit error information about multiple data bits to each corresponding data bit error correction component 415-a, 415-b...415-n. In some instances, the binary decoder may determine error information about at least one flipped bit and transmit the error information (e.g., an indication of an error and / or an error location) to the flipped bit error correction component 410. In some instances, the binary decoder 405 may determine error information about at least one of the multiple parity bits and may transmit the error information (e.g., an indication of an error and / or an error location) to the parity bit error correction component ( Figure 4 ), the parity bit error correction component may be similar to the data bit error correction components 415 - a , 415 - b . . . 415 - n and / or the flip bit error correction component 410 .

[0058] In some examples, binary decoder 405 can transmit error information of the first data bit set DATA[0] on the data line to data bit error correction component 415. The data bit can then be transmitted to flip decision component 420 on local bus 407-a LBUS[0] via data bus decision component 425. The data bit can be transmitted without waiting for a trigger (e.g., receiving a flipped bit that has been corrected). Once any single bit error (whether it is a data bit or a flipped bit that can be corrected) is corrected by any error correction component, the data bit can be transmitted.

[0059] In some examples, data bits can be transmitted from error correction component 415-a to flip decision component 420 and data bus decision component 425 via local bus LBUS[0] on line 407-a. Each data bit error correction component can transmit data bits via the corresponding local bus LBUS[n]. In addition, all local bus lines 407-a, 407-b...407-n can be transmitted on one or more universal local bus lines LBUS[127:0], where one or more universal local bus lines LBUS[127:0] can be input lines to flip decision component 420 and data bus decision component 425. Although in Figure 4 Only one of the universal local bus lines LBUS[127:0] is depicted in FIG, but more than one universal local bus may be employed to transfer data bits from the error correction component to the flip decision component 420 and the data bus decision component 425.

[0060] In some instances, data bus decision component 425 can receive data bit as input. By passing the data bit through non-inversion logic component and inversion logic component, one or more operations (e.g., the value of the data bit can be refreshed) can be performed. Then, the output of the non-inversion and inversion logic components can be passed to the multiplexer. The multiplexer can receive the data bit from the non-inversion and inversion logic components, and receive the output value from the flip decision component. The output value from the flip decision component 420 can be an indicator of whether the data bit can be inverted at the multiplexer. These inputs can be multiplexed together to generate correct data to output to one or more global bus lines GBUS[127:0]. In some instances, the multiplexer of the data bus decision component 425 can be coupled with one or more global data bus lines GBUS[127:0].

[0061] In some instances, the error correction components 415-a, 415-b ... 415-n and 410 can correct errors associated with at least one of the plurality of bits. In some instances, the errors can be corrected based in part on determining the error at the binary decoder 405 or in response to a decoding process occurring at the ECC decoder 403, among other things.

[0062] In some examples, the flipped bit can be processed or error corrected at the flipped bit error correction component 410. Based on the information received from the binary decoder 405 and one or more operations (e.g., such as determination) performed at the flipped bit error correction component 410 in some cases, the flipped bit can be processed (e.g., processing the flipped bit can include correcting the flipped bit or not correcting the flipped bit and passing the flipped bit through the error correction component) or corrected, and can then be transmitted directly to the flip decision component 420 on the flipped bit line 412. By transmitting the processed or error-corrected flipped bit directly to the flip decision component 420, the data bit may not have to wait to receive the error-corrected flipped bit before transmitting it to the flip decision component 420. Because the data bit can be transmitted directly to the flip decision component 420 and transmitted on a different line from the error-corrected flipped bit, the memory system can operate faster and more efficiently due to reduced transmission time. Furthermore, because the error-corrected flipped bits are received at the flip decision component 420 on a faster unidirectional line, the decision at the flip decision component 420 can be made once at least some of the data bits are received at the flip decision component 420 .

[0063] In some instances, flip bit line 412 can be a line (e.g., a dedicated line) that couples flip bit error correction component 410 with flip decision component 420. In some cases, flip bit line 412 can be a unidirectional line. Additionally or alternatively, data bit lines 407-a, 407-b...407-n can be bidirectional lines. In some instances, flip bit line 412 can have a lower capacitive load than data bit lines 407-a, 407-b...407-n. In addition, flip bit line 412 can be configured as a read-only line, while the data bit line can be configured as a read / write line. Furthermore, in some cases, flip bit line 412 can be configured to have a faster transmission speed than data bit lines 407-a, 407-b...407-n. In some examples, because the toggle bit line 412 can have faster data transmission speeds and / or other advantageous features, the transmitted error-corrected toggle bits can be advantageously received by the toggle decision component 420 before receiving the data bits (e.g., which may have already been error corrected). Because the error-corrected toggle bits can be transmitted on a separate line from the data bits, the data bits may not have to wait to receive the error-corrected toggle bits at the error correction component before being transmitted to the toggle decision component 320, thereby reducing latency in the memory system.

[0064] In some examples, the error-corrected flipped bits may be received in parallel or simultaneously with at least one of the data bits by the flip decision component 420. The flip decision component 420 may be configured to determine whether the received data bits have been flipped based on a subset of the received data bits, or the flip decision component 420 may be configured to wait until all data bits have been received and then determine whether the data bits have been flipped.

[0065] Figure 5 An example of a device 500 supporting an error correction bit flipping scheme according to various aspects of the present disclosure is shown. In some examples, the device 500 may include a device 500 as described herein. Figure 2 , 3 and 4. In some examples, the device 500 can include a flip decision component 520, similar to Figure 4 The flip decision component 420 and Figure 3 The flip decision component 320.

[0066] Figure 5 An example of the components of the flip decision component 520 is shown. Figure 4 As discussed, data bits (eg, which may be error corrected in some cases) may be received at the flip decision component 420. Figure 5 As shown in , one of the data bits can be received at the corresponding logic components 530-a, 530-b, ... 530-n. The logic component (e.g., logic component 530-a) can determine the output of the data bit based on one or more operations (e.g., determination, comparison) performed. In some examples, as shown in reference Figure 4 As discussed, the output of the toggle decision component 520 may be an indicator of whether to invert the toggle bit at the multiplexer of the data bus decision component 425 .

[0067] In some examples, the flip decision component 520 can use configuration logic criteria to determine whether the received data bit should be inverted. In some examples, the configuration logic criteria can be stored in the flip decision component 520.

[0068] In some instances, this can be achieved by determining whether the received data bits can include more than four 1s. Since the configuration logic criteria used in the flip decision component 520 can be an evaluation based on bytes, the exemplary threshold value (four 1s) here can be used. Since there are eight bits in a byte, after viewing half or four bits of the data bits, the flip decision component 520 can make a decision about the inverted data bits. This is just an example, and other technologies and alternatives can be considered in particular. In some instances, the flip decision component 520 can evaluate the received data bits, and determine whether there are less than or equal to four bits for a certain logical value (e.g., a value or a zero value) in each byte, and determine whether to invert the received data bits. In some instances, the configuration logic criteria can include the decision whether the received data bits can include more than four 0s. Although the data bits can be evaluated to determine whether they are greater than four 1s, any number or value can be used. In some instances, the data bits can be evaluated to determine whether there are more than five 1s, five 0s, six 1s, six 0s, seven 1s, seven 0s, etc. Because the fewer data bits that can be evaluated, the less power may be consumed, so using four ones in this example can ensure low power consumption when processing data bits at flip decision component 520. In general, the determination can be based on any set of configuration logic criteria internal or external to the logic component.

[0069] In some instances, a determination may be made that more than half of the data bits should be inverted at the inversion decision component 520. However, inverting the data bits at the inversion decision component 520 may consume too much power, so an indicator of the data bits that should be inverted may be sent to the multiplexer of the data bus decision component for inversion to reduce power consumption of the memory device.

[0070] The output of logic components 530 (e.g., logic components 530-a, 530-b, ... 530-n) can be transmitted to other logic components 540 (e.g., logic components 540-a, 540-b, ... 540-n), which in some cases can include exclusive OR (XOR) components. Although only three logic components 530 and three logic components 540 are shown, for each set of received data bits corresponding to one or more data error correction components (e.g., 415-a to 415-n), there can be a corresponding logic component 540 and a corresponding logic component 530.

[0071] Additionally, the error-corrected flipped bit can be received at the flip decision component 520. In some examples, the error-corrected flipped bit can be an input to the component 540. The output of the component 540 can provide an output value that can be transmitted to a data bus decision component (not shown), such as with respect to Figure 3 and 4Any suitable logic may be used to achieve a similar logic output as component 540, for example, data bits may be inverted and then input to an XNOR component to produce a similar result, among other embodiments.

[0072] In some examples, the flip decision component 520 can determine whether the data bit has been inverted. The logic component 530 can output a determination that the received data bit may contain multiple bits with a given logic state (e.g., there are more than four 1s). The output value from the flip decision component 520 can be transmitted to the data bus decision component ( Figure 5 ), and the output value may be an indicator of whether the data bit can be inverted at the multiplexer. These inputs may be multiplexed together to generate the correct data to output to the global bus GBUS[127:0].

[0073] The flip decision component 520 may include any appropriate logic component or configuration logic criteria that can determine whether the received data bit should be reversed. In one example, the flip decision component 520 may include logic or configuration logic criteria that analyzes whether the data bit has more than four 1s to determine whether the data bit should be reversed. Although any number of logic schemes can be used to determine data inversion, a logic scheme that consumes less power when processing data bits may be desirable. In some examples, the flip decision component 520 may compare the received data bit with the configuration logic criteria to determine that the number of logic states of the received data bit meets a threshold. The flip decision component may then output an indication that the number of logic states of the received data bit meets a threshold. The configuration logic criteria will be discussed in further detail herein.

[0074] As a first example, in the case where the received data bit contains less than or equal to four 1s and the flip bit value is 0, the decision can indicate that the data bit has not been inverted and the flip decision component 520 can transmit an indication to the data bus decision component to not invert the data bit. As a second example, in the case where the logic component 530 can output the decision that the received data bit can contain less than or equal to four 1s and the flip bit value is 1, the decision can indicate that the data bit has been inverted and the flip decision component 520 can transmit an indication to the data bus decision component to invert the data bit. As a third example, in the case where the logic component 530 can output the decision that the received data bit can contain more than four 1s and the flip bit value is 0, the decision can indicate that the data bit has been inverted. Therefore, the flip decision component 520 can transmit an indication to the data bus decision component to invert the data bit. As a fourth example, in the case where the logic component 530 can output the decision that the received data bit can contain more than four 1s and the flip bit value is 1, the decision can indicate that the data bit has not been inverted and the flip decision component 520 can transmit an indication to the data bus decision component to not invert the data bit. When the data bit is compared to the logic components of the flip decision component 520, a determination may be made as to whether the data bit should be inverted. Once a determination is made at the flip decision component 520, an indication of the determination may be transmitted to the data bus decision component ( Figure 5 (not shown) for reversal.

[0075] Figure 6 600 is a block diagram of a memory array supporting an error correction bit flipping scheme according to various embodiments of the present disclosure. The block diagram 600 may include a memory array 100-a, which may be a reference Figure 1 100-a. The memory array 100-a may be referred to as an electronic memory device and may include a memory controller 140-a, word lines 110-a, bit lines 115-a, sensing components 125-a, and one or more memory cells 105-a (which may be referenced Figure 1 100 - a ). The memory array 100 - a may also include a reference component 620 , a latch 625 , and a read component 650 . The components of the memory array 100 - a may be in electronic communication with each other and may perform reference operations. Figure 1-5 Describes the functionality.

[0076] The memory controller 140-a may, in combination with other components, apply voltages across the memory array 100-a, write data to the memory cells 105-a, read data from the memory cells 105-a, and generally operate the memory array 100-a, such as Figure 1-5Memory controller 140-a may include bias component 610 and timing component 615. In some cases, memory controller may include bit flip component 645. Memory controller 140-a may be in electronic communication with one or more memory cells 105-a, sense component 125-a, and reference component 620.

[0077] The bias component 610 can be configured (e.g., by the memory controller 140-a) to activate the word line 110-a or the bit line 115-a by applying voltages to those various nodes. For example, the bias component 610 can be configured to apply voltages to read or write the memory cell 105-a described herein. In some cases, the memory controller 140-a can include a row decoder, a column decoder, or both, as described in reference to Figure 1 This may enable the memory controller 140-a to access one or more memory cells 105. The bias component 810 may also provide a voltage potential to the reference component 620 to generate a reference signal for the sense component 125-a. Additionally, the bias component 610 may provide a voltage potential for the operation of the sense component 125-a.

[0078] Timing component 615 can be configured to control the timing of various word line selections or plate biases, including the timing of switches and application of voltages to perform memory functions (eg, read and write) discussed herein. In some cases, timing component 615 can control the operation of bias component 610.

[0079] The reference component 620 may include various components to generate a reference signal for the sensing component 125-a. The reference component 620 may include circuitry configured to generate a reference signal.

[0080] The sensing component 125-a may compare a signal from one or more memory cells 105-a to a reference signal from the reference component 620. Upon determining a logic state, the sensing component may then store an output in a latch 625 where the output may be used in accordance with the operation of an electronic device of which the memory array 100-a is a part. In some cases, the reference component 620, the sensing component 125-a, and the latch 825 may be components of a memory controller 140-a.

[0081] The bit flip component 645 can be used to manage various aspects of the error correction bit flipping scheme. For example, the bit flip component 645 can be used to provide timing information to the bias component 610 and / or the timing component 615 to perform a bit flipping operation. The bit flip component 645 can also include a flip bit generation component and / or a bit flipping component.

[0082] Read component 650 may be used to process the information bits stored at latch 625. Read component 650 may include a reference Figure 2 Various aspects of device 200 are discussed.

[0083] For example, after a read command can be transmitted from the storage controller 140-a and received at the memory unit 105-a, the error correction component 655 can receive the flip bit and the data bit from the memory unit 105-a. In some instances, there may be multiple error correction components, which may each correspond to at least one subset of the data bit and / or the flip bit. Although a single flip bit can be discussed in this example, this is for illustrative purposes because multiple flip bits can be received at the error correction component 655. In some instances, the error correction component 655 can correct the received flip bit and data bit. After the error correction flip bit is corrected, the corrected flip bit can be directly transmitted to the flip decision component (not shown). In some cases, the corrected flip bit can be transmitted to the flip decision component on a dedicated, unidirectional and / or read-only line. In addition, the corrected data bit can also be transmitted to the flip decision component. The corrected data bit can be transmitted on a line different from the corrected flip bit, and its transmission speed may be slower than the flip bit line because the data bit line may be a read / write line. Thus, the error-corrected data bit may arrive at the flip decision component in parallel with the flip bit or after the flip bit.After receiving the error-corrected flip bit and the error-corrected data bit, the flip decision component may determine whether the error-corrected data bit may be inverted.

[0084] In some examples, the bit flip component 645 can flip the data bits received at the memory array 100-a. The flipped data bits can be stored at the memory array 100-a, and in the event of a command (e.g., a read command) from a host device (or controller, etc.), the memory array 100-a can flip the data bits. The flipped data bits can include an inversion bit or a flip bit that can indicate that the data bits have been flipped.

[0085] In some instances, the data bits, flip bits, and parity bits can be provided from the memory array 100-a to a decoder, then to an error correction component, and then to a flip decision component, which can determine whether the data bits should be inverted, as previously discussed with respect to the error correction component 655.

[0086] Figure 7 A system supporting an error correction bit flipping scheme according to various embodiments of the present disclosure is shown. System 700 includes a device 705, which may be or include a printed circuit board to connect or physically support various components. Device 705 includes a memory array 100-b, which may be a reference Figure 1 and 61. The memory array 100-b may include a memory controller 140-b and one or more memory cells 105-b (which may be reference Figure 1 and 6 1 and 105). Device 705 may also include processor 710, BIOS component 715, one or more peripheral components 720, and input / output control component 725. The components of device 705 may electronically communicate with each other via bus 730.

[0087] Processor 710 may be configured to operate memory array 100-b via memory controller 140-b. In some cases, processor 710 may refer to Figure 1 and 6 The functions of the memory controller 140 described herein are described herein. In other cases, the memory controller 140-b may be integrated into the processor 710. The processor 710 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components, and the processor 710 may perform the various functions described herein. The processor 710 may, for example, be configured to execute computer readable instructions stored in the memory array 100-b to cause the device 705 to perform various functions or tasks.

[0088] The BIOS component 715 may be a software component including a basic input / output system (BIOS) operating as firmware that may initialize and run the various hardware components of the system 700. The BIOS component 715 may also manage the flow of data between the processor 710 and various components (e.g., peripheral components 720, input / output control components 725, etc.). The BIOS component 715 may include a program or software stored in a read-only memory (ROM), a flash memory, or any other non-volatile memory.

[0089] The one or more peripheral components 720 may be any input or output device, or an interface to such a device, integrated into the device 705. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot (e.g., a Peripheral Component Interconnect (PCI) or Accelerated Graphics Port (AGP) slot).

[0090] The input / output control component 725 can manage data communications between the processor 710 and one or more peripheral components 720, input 735, or output 740. The input / output control component 725 can also manage peripheral devices that are not integrated into the device 905. In some cases, the input / output control component 725 can represent a physical connection or port for an external peripheral device.

[0091] Input 735 can represent a device or signal external to device 705 that provides input to device 705 or its components. This can include a user interface or an interface with other devices or between other devices. In some cases, input 735 can be a peripheral device connected to the device 705 interface via one or more peripheral components 720, or can be managed by input / output control component 725.

[0092] Output 740 can represent a device or signal external to device 705 that is configured to receive an output from device 705 or any of its components. Examples of output 740 can include a display, an audio speaker, a printing device, another processor or printed circuit board, etc. In some cases, output 740 can be a peripheral device that interfaces with device 705 via one or more peripheral components 720, or can be managed by input / output control component 725.

[0093] The error correction component 745 can receive flip bits, data bits, and / or parity bits from the memory array 100-b. In some instances, there can be corresponding error correction components for the data bits and flip bits. There can also be error correction components for one or more parity bits. In addition, there can be multiple flip bits received at the error correction component, but in this example, a single flip bit will be discussed. The error correction component can, for example, correct the received flip bits and data bits after a read command can be received at the memory array 100-b.

[0094] After the flipped bit is corrected, the corrected flipped bit can be directly transmitted to the flip decision component ( Figure 7 ). The error correction flip bit can be transmitted to the flip decision component on a dedicated, unidirectional and / or read-only line. In addition, the error corrected data bit can also be transmitted to the flip decision component. The error corrected data bit can be transmitted on a different line from the error corrected flip bit, and due to the slower speed of the read / write line, the error corrected data bit can arrive in parallel with the flip bit or after the flip bit. After receiving the error corrected flip bit and the error corrected data bit, the flip decision component can determine whether the error corrected data bit should be inverted.

[0095] The components of memory controller 140-b, device 705, and memory array 100-b may be comprised of circuitry designed to perform their functions. This may include various circuit elements, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or non-active elements, configured to perform the functions described herein.

[0096] Figure 8 800 is a flowchart illustrating a method 800 for supporting an error correction bit flipping scheme according to various aspects of the present disclosure. Among other examples, the operations of the method 800 may be implemented by a controller or components thereof as described herein. For example, the operations of the method 800 may be implemented by reference to Figures 1 to 5 The controller or host device described herein may be used to perform. In some examples, the controller may execute a set of instructions to control the functional elements of the controller to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform various aspects of the functions described herein.

[0097] At 805, the component may receive an indication at a flipped bit error correction component whether a flipped bit should be corrected. The operation of 805 may be performed according to the methods described herein. In some examples, various aspects of the operation of 805 may be described with reference to Figures 1 to 5 The error correction components described are performed.

[0098] At 810, the component controller may process the flipped bit at the flipped bit error correction component based on receiving the indication of whether the flipped bit should be corrected, the processing including correcting the flipped bit at the flipped bit error correction component or passing the flipped bit through the flipped bit error correction component. The operations of 810 may be performed according to the methods described herein. In some examples, various aspects of the operations of 810 may be described with reference to Figures 1 to 5 The error correction components described are performed.

[0099] At 815, the component may transmit the processed flipped bit directly to the flip decision component via an output line based on the processed flipped bit. The operation of 815 may be performed according to the methods described herein. In some examples, various aspects of the operation of 815 may be described by reference to Figures 1 to 5 The flipping decision component described is performed.

[0100] A device is described. The device may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executable by the processor to cause the device to receive an indication at a flip bit error correction component whether a flip bit should be corrected, process the flip bit at the flip bit error correction component based on receiving the indication whether the flip bit should be corrected (the processing includes correcting the flip bit at the flip bit error correction component or passing the flip bit through the flip bit error correction component), and based on processing the flip bit, transmit the processed flip bit directly to the flip decision component via an output line.

[0101] Another apparatus is described. The apparatus may include means for receiving an indication at a flipped bit error correction component whether a flipped bit should be corrected, processing the flipped bit at the flipped bit error correction component based on receiving the indication whether the flipped bit should be corrected (the processing includes correcting the flipped bit at the flipped bit error correction component or passing the flipped bit through the flipped bit error correction component), and transmitting the processed flipped bit directly to the flip decision component via an output line based on processing the flipped bit.

[0102] A non-transitory computer-readable medium for storing code is described. The code may include instructions executable by a processor to receive an indication at a flipped bit error correction component whether a flipped bit should be corrected, process the flipped bit at the flipped bit error correction component based on receiving the indication whether the flipped bit should be corrected (the processing includes correcting the flipped bit at the flipped bit error correction component or passing the flipped bit through the flipped bit error correction component), and based on processing the flipped bit, transmit the processed flipped bit directly to a flip decision component via an output line.

[0103] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, receiving the indication may include an operation, feature, means, or instruction for receiving an indication that a flipped bit should be corrected, and wherein processing the flipped bit includes correcting an error of the flipped bit at a flipped bit error correction component.

[0104] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for transmitting the set of data bits to the toggle decision component via a second output line based on processing the toggle bit.

[0105] Some examples of methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for transmitting the set of data bits to the toggle decision component over a second output line based on transmitting the processed toggle bits to the toggle decision component.

[0106] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, operations, features, means, or instructions for transmitting a set of data bits to a flip decision component through a second output line based on transmitting the processed flipped bits directly to the flip decision component through the output line may be further included.

[0107] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for receiving a second indication at a data bit error correction component as to whether the data bit should be error corrected, correcting the data bit at the data bit error correction component based on receiving the second indication, and transmitting the corrected data bit to the flip decision component via a second output line.

[0108] Fig. 9 , a flowchart is shown that illustrates a method 900 for supporting an error correction bit flipping scheme according to various aspects of the present disclosure. The operations of the method 900 may be implemented by a controller or components thereof as described herein. For example, the operations of the method 900 may be implemented by reference to Figures 1 to 5 The controller or host device described herein may be used to perform. In some examples, the controller may execute a set of instructions to control the functional elements of the controller to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform various aspects of the functions described herein.

[0109] At 905, the component may receive the corrected flipped bit directly from the flipped bit error correction component via the first output line at the flip decision component. The operation of 905 may be performed according to the methods described herein. In some examples, various aspects of the operation of 905 may be described by reference to Figures 1 to 5 The flipping decision component described is performed.

[0110] At 910, the component may receive one or more data bits from the data bit error correction component via a second output line at the flip decision component. The operation of 910 may be performed according to the methods described herein. In some examples, various aspects of the operation of 910 may be described by reference to Figures 1 to 5 The flipping decision component described is performed.

[0111] At 915, the component may determine whether to invert the data bit at the inversion decision component based on receiving the error-corrected inversion bit and receiving one or more data bits. The operation of 915 may be performed according to the methods described herein. In some examples, various aspects of the operation of 915 may be described by reference to Figures 1 to 5 The flipping decision component described is performed.

[0112] A device is described. The device may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executable by the processor to cause the device to directly receive an error-corrected flip bit from a flip bit error correction component via a first output line at a flip decision component, receive one or more data bits from a data bit error correction component via a second output line at the flip decision component, and determine whether to invert the data bit at the flip decision component based on receiving the error-corrected flip bit and receiving the one or more data bits.

[0113] Another apparatus is described. The apparatus may include means for directly receiving an error-corrected flip bit at a flip decision component via a first output line from a flip bit error correction component, means for receiving one or more data bits at the flip decision component from a data bit error correction component via a second output line, and means for determining at the flip decision component whether to invert the data bit based on receiving the error-corrected flip bit and receiving the one or more data bits.

[0114] A non-transitory computer-readable medium for storing code is described. The code may include instructions executable by a processor to directly receive an error-corrected flipped bit from a flip bit error correction component at a flip decision component via a first output line, receive one or more data bits from a data bit error correction component at the flip decision component via a second output line, and determine whether to invert the data bit at the flip decision component based on receiving the error-corrected flipped bit and receiving the one or more data bits.

[0115] In some examples of methods, apparatus, and non-transitory computer-readable media described herein, receiving the one or more data bits via the second output line may include operations, features, means, or instructions for receiving at least some of the one or more data bits after receiving the toggle bit.

[0116] Fig.10 1 shows a flow chart illustrating a method 1000 for supporting an error correction bit flipping scheme according to various aspects of the present disclosure. The operations of the method 1000 may be implemented by a controller or components thereof as described herein. For example, the operations of the method 1000 may be implemented by reference to Figures 1 to 5 The controller or host device described herein may be used to perform. In some examples, the controller may execute a set of instructions to control the functional elements of the controller to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform various aspects of the functions described herein.

[0117] At 1005, the component may receive the corrected flipped bit directly from the flipped bit error correction component via the first output line at the flip decision component. The operation of 1005 may be performed according to the methods described herein. In some examples, various aspects of the operation of 1005 may be described with reference to Figures 1 to 5The flipping decision component described is performed.

[0118] At 1010, the component may receive the error-corrected flipped bit via a unidirectional output line. The operation of 1010 may be performed according to the methods described herein. In some examples, various aspects of the operation of 1010 may be described with reference to Figures 1 to 5 The flipping decision component described is performed.

[0119] At 1015, the component may receive one or more data bits from the data bit error correction component via the second output line at the flip decision component. The operation of 1015 may be performed according to the methods described herein. In some examples, various aspects of the operation of 1015 may be described by reference to Figures 1 to 5 The flipping decision component described is performed.

[0120] At 1020, the component may receive one or more data bits via a bidirectional output line. The operation of 1020 may be performed according to the methods described herein. In some examples, various aspects of the operation of 1020 may be described by reference to Figures 1 to 5 The flipping decision component described is performed.

[0121] At 1025, the component may determine whether to invert the data bit at the inversion decision component based on receiving the error-corrected inversion bit and receiving one or more data bits. The operation of 1025 may be performed according to the methods described herein. In some examples, various aspects of the operation of 1025 may be described with reference to Figures 1 to 5 The flipping decision component described is performed.

[0122] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, operations, features, means, or instructions for receiving the error-corrected flipped bit via a unidirectional output line may be further included, and wherein receiving the one or more data bits via a second output line includes receiving the one or more data bits via a bidirectional output line.

[0123] In some examples of methods, apparatus, and non-transitory computer-readable media described herein, receiving the error-corrected flipped bit and receiving one or more data bits may include operations, features, means, or instructions for receiving the flipped bit and at least some of the one or more data bits in parallel.

[0124] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for determining an output value at a toggle decision component based on receiving one or more data bits and an error-corrected toggle bit using configuration logic criteria, and transmitting an indicator of the output value to a data bus decision component.

[0125] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for transmitting, from the toggle decision component, a second indicator of whether to invert the data bit based on the output value and the error-corrected toggle bit.

[0126] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, using configuration logic criteria at a flip decision component to determine an output value may include operations, features, components, or instructions for comparing received data bits to the configuration logic criteria to determine whether the number of logic states of the received first type of data bits can be greater than a threshold.

[0127] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, using configuration logic criteria at a flip decision component to determine an output value may include operations, features, components, or instructions for comparing at least some of the one or more data bits to an error-corrected flipped bit using a logic component including an XOR component.

[0128] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for inverting a data bit at a flip decision component based on determining whether to invert the data bit and outputting the inverted data bit.

[0129] A method is described. The method may include: receiving an indication at a flipped bit error correction component whether a flipped bit should be corrected; processing the flipped bit at the flipped bit error correction component based on receiving the indication whether the flipped bit should be corrected; the processing includes correcting the flipped bit at the flipped bit error correction component or passing the flipped bit through the flipped bit error correction component; and transmitting the processed flipped bit directly to the flip decision component via an output line based on processing the flipped bit.

[0130] A device is described. The device may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executable by the processor to cause the device to receive an indication at a flip bit error correction component whether a flip bit should be corrected, process the flip bit at the flip bit error correction component based on receiving the indication whether the flip bit should be corrected (the processing includes correcting the flip bit at the flip bit error correction component or passing the flip bit through the flip bit error correction component), and based on processing the flip bit, transmit the processed flip bit directly to the flip decision component via an output line.

[0131] Another apparatus is described. The apparatus may include means for receiving an indication at a flipped bit error correction component whether a flipped bit should be corrected, means for processing the flipped bit at the flipped bit error correction component based on receiving the indication whether the flipped bit should be corrected (the processing includes correcting the flipped bit at the flipped bit error correction component or passing the flipped bit through the flipped bit error correction component), and means for transmitting the processed flipped bit directly to the flip decision component via an output line based on processing the flipped bit.

[0132] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to receive an indication at a flipped bit error correction component whether a flipped bit should be corrected, process the flipped bit at the flipped bit error correction component based on receiving the indication whether the flipped bit should be corrected (the processing includes correcting the flipped bit at the flipped bit error correction component or passing the flipped bit through the flipped bit error correction component), and based on processing the flipped bit, transmit the processed flipped bit directly to a flip decision component via an output line.

[0133] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, receiving the indication may include an operation, feature, means, or instruction for receiving an indication that a flipped bit should be corrected, and wherein processing the flipped bit includes correcting an error of the flipped bit at a flipped bit error correction component.

[0134] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for transmitting the set of data bits to the toggle decision component via a second output line based on processing the toggle bit.

[0135] Some examples of methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for transmitting the set of data bits to the toggle decision component over a second output line based on transmitting the processed toggle bits to the toggle decision component.

[0136] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, transmitting the set of data bits to the flip decision component via the second output line may include operations, features, components, or instructions for transmitting the set of data bits directly to the flip decision component via the second output line based on transmitting the processed flipped bits directly to the flip decision component via the output line.

[0137] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for receiving a second indication at a data bit error correction component as to whether the data bit should be error corrected, correcting the data bit at the data bit error correction component based on receiving the second indication, and transmitting the corrected data bit to the flip decision component via a second output line.

[0138] A method is described. The method may include: receiving a corrected flip bit directly from a flip bit error correction component via a first output line at a flip decision component; receiving one or more data bits from a data bit error correction component via a second output line at the flip decision component; and determining whether to invert the one or more data bits based on receiving the corrected flip bit and receiving the one or more data bits at the flip decision component.

[0139] An apparatus is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executable by the processor to cause the apparatus to directly receive an error-corrected flip bit from a flip bit error correction component via a first output line at a flip decision component, receive one or more data bits from a data bit error correction component via a second output line at the flip decision component, and determine whether to invert the one or more data bits based on receiving the error-corrected flip bit and receiving the one or more data bits at the flip decision component.

[0140] Another apparatus is described. The apparatus may include means for directly receiving an error-corrected flip bit from a flip bit error correction component via a first output line at a flip decision component, means for receiving one or more data bits from a data bit error correction component via a second output line at the flip decision component, and means for determining whether to invert the one or more data bits based on receiving the error-corrected flip bit and receiving the one or more data bits at the flip decision component.

[0141] A non-transitory computer-readable medium storing code is described. The code may include instructions executable by a processor to directly receive an error-corrected flip bit from a flip bit error correction component via a first output line at a flip decision component, receive one or more data bits from a data bit error correction component via a second output line at the flip decision component, and determine whether to invert the one or more data bits based on receiving the error-corrected flip bit and receiving the one or more data bits at the flip decision component.

[0142] In some examples of methods, apparatus, and non-transitory computer-readable media described herein, receiving one or more data bits via a second output line may include operations, features, means, or instructions for receiving at least some of the one or more data bits after receiving the error-corrected flipped bit.

[0143] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, receiving the error-corrected flipped bit via a first output line may include operations, features, means, or instructions for receiving the error-corrected flipped bit via a unidirectional output line, and wherein receiving the one or more data bits via a second output line includes receiving the one or more data bits via a bidirectional output line.

[0144] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, receiving the error-corrected flipped bit and receiving one or more data bits may include operations, features, means, or instructions for receiving the error-corrected flipped bit and at least some of the one or more data bits in parallel.

[0145] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for determining an output value at a toggle decision component based on receiving one or more data bits and an error-corrected toggle bit using configuration logic criteria, and transmitting an indicator of the output value to a data bus decision component.

[0146] Some examples of the methods, apparatus, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for transmitting, from the toggle decision component, a second indicator of whether to invert one or more data bits based on the output value and the error-corrected toggle bit.

[0147] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, using configuration logic criteria at a flip decision component to determine an output value may include operations, features, components, or instructions for comparing received data bits to the configuration logic criteria to determine whether the number of logic states of the received first type of data bits can be greater than a threshold.

[0148] In some examples of the methods, apparatus, and non-transitory computer-readable media described herein, using configuration logic criteria at a flip decision component to determine an output value may include operations, features, components, or instructions for comparing at least some of the one or more data bits to an error-corrected flipped bit using a logic component including an XOR component.

[0149] An apparatus is described. The apparatus may include: a flip bit error correction component coupled to an error locator component; and a flip decision component directly coupled to the flip bit error correction component via an output line, the flip bit error correction component configured to receive an indication of a flip bit error of a flip bit from the error locator component, correct the flip bit error based on receiving the indication of the flip bit error, and transmit the corrected flip bit error directly to the flip decision component via the output line.

[0150] In some examples, the output line may include operations, features, components, or instructions of a dedicated output line between the flip bit error correction component and the flip decision component, wherein the flip bit error correction component may be operable to transmit the corrected flip bit error directly to the flip decision component through the dedicated output line.

[0151] In some examples, the output line may include operations, features, components, or instructions of a unidirectional output line between a flip bit error correction component and a flip decision component, wherein the flip bit error correction component may be operable to transmit the corrected flip bit error directly to the flip decision component via the unidirectional output line.

[0152] A device is described. The device may include: a flip decision component; a flip bit error correction component coupled to the flip decision component and configured to directly transmit one or more flip bits to the flip decision component via a first output line coupling the flip bit error correction component and the flip decision component; and a data bit error correction component coupled to the flip decision component and configured to transmit one or more data bits to the flip decision component via a second output line.

[0153] Some examples may further include determining whether the one or more data bits should be inverted based on at least one of the one or more data bits received via the second output line or the one or more flipped bits received via the first output line.

[0154] In some examples, the data bit error correction component can be directly coupled to the flip decision component via the second output line.

[0155] Some examples may further include receiving an indication of the error correction status and, in response to receiving the indication, transmitting one or more data bits via the second output line and transmitting one or more toggled bits via the first output line, respectively.

[0156] In some examples, the data bit error correction component and the toggle bit error correction component can be respectively configured to simultaneously receive one or more data bits and one or more toggle bits.

[0157] In some instances, the flip decision component may include operations, features, components, or instructions configured to output a storage logic criterion indicating whether to flip one or more data bits, and the device further includes a data bus decision component, which is coupled to the flip decision component and configured to receive an indicator of the output value from the flip decision component.

[0158] Some examples may further include comparing the received data bits to the configuration logic criteria to determine that the number of logic states of the received first type of data bits satisfies a threshold, and outputting an indication that the number of logic states of the received first type of data bits satisfies the threshold.

[0159] In some examples, the first output line can have a first transmission speed, and the second output line can have a second transmission speed that can be slower than the first transmission speed.

[0160] It should be noted that the methods described herein describe possible embodiments, and that operations and steps may be rearranged or otherwise modified, and other embodiments are possible. Furthermore, various aspects from two or more methods may be combined.

[0161] The information and signals described herein may be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above specification may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, one of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have various bit widths.

[0162] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled to each other) if there is any conductive path between the components that can readily support the flow of signals between the components. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be open or closed based on the operation of the device containing the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components (e.g., switches, transistors, or other components). In some cases, the flow of signals between the connected components may be interrupted for a period of time, such as using one or more intermediate components (e.g., switches or transistors).

[0163] The term "coupling" refers to a state of changing from an open circuit relationship between components, in which signals cannot currently communicate between components through conductive paths, to a closed circuit relationship between components, in which signals can communicate between components through conductive paths. When one component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between other components through conductive paths that previously did not allow signals to flow.

[0164] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from each other if there is an open circuit between them. For example, two components that are isolated by a switch located between them are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller affects a change that prevents the signal from flowing between the components using the conductive path that previously allowed the signal to flow.

[0165] The term "layer" as used herein refers to a layer or sheet of a geometric structure, each of which can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer can be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a film. A layer can contain different elements, components, and / or materials. In some cases, a layer can be composed of two or more sublayers. In some drawings, two dimensions of a three-dimensional layer are depicted for illustrative purposes. However, those skilled in the art will recognize that the layer is three-dimensional in nature.

[0166] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0167] The switch assembly or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. Each end may be connected to other electronic components by a conductive material (e.g., a metal). The source and drain may be conductive and may include a heavily doped (e.g., degenerate) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (e.g., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0168] In conjunction with the accompanying drawings, the description set forth herein describes exemplary configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "used as an example (example / instance) or illustration", rather than "preferred" or "better than other examples". The detailed description contains specific details to provide an understanding of the described technology. However, these technologies can be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid making the concepts of the described examples unclear.

[0169] In the drawings, similar components or features may have the same reference number. In addition, various components of the same type may be distinguished by following the reference number with a dash and a second reference that distinguishes between the similar components. If only the first reference number is used in the specification, the description applies to any of the similar components having the same first reference number, regardless of the second reference number.

[0170] The information and signals described herein may be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above specification may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0171] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0172] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the function can be stored on a computer-readable medium as one or more instructions or codes or transmitted by a computer-readable medium. Other examples and embodiments are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software, hardware, firmware, hard wiring, or any combination of these executed by a processor. The features of the implementation functions can also be physically located in various locations, including being distributed so that the parts of the functions are implemented at different physical locations. In addition, as used herein (included in the claims), the "or" used in the project list (for example, a project list starting with a phrase such as "at least one" or "one or more") indicates an inclusive list, such as a list of at least one of A, B, or C refers to A or B or C or AB or AC or BC or ABC (for example, A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed condition set. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" can be based on condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0173] Computer-readable media include non-transitory computer storage media and communication media, and the communication media include any media that promotes the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. As an example and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, disk storage or other magnetic storage device, or can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any non-transitory media. Moreover, any connection is appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (e.g., infrared, radio and microwave) is used to transmit software from a website, server or other remote source, the definition of the media includes the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (e.g., infrared, radio and microwave). Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0174] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a memory device, comprising: receiving, at a flipped bit error correction component, an indication of whether the flipped bit should be corrected; processing the flipped bit at the flipped bit error correction component based at least in part on receiving the indication of whether the flipped bit should be corrected, the processing comprising correcting the flipped bit at the flipped bit error correction component or passing the flipped bit through the flipped bit error correction component; Based at least in part on processing the toggled bit, transmitting the processed toggled bit directly to a toggle decision component via a unidirectional output line; and A plurality of data bits are transmitted to the flip decision component via a bidirectional output line, wherein the plurality of data bits are received at the flip decision component after the processed flipped bit is received at the flip decision component.

2. The method of claim 1 , wherein receiving the indication comprises: An indication that the flipped bit should be corrected is received, and wherein processing the flipped bit includes correcting an error of the flipped bit at the flipped bit error correction component.

3. The method according to claim 1, further comprising: receiving, at the data bit error correction component, a second indication of whether data bits of the plurality of data bits should be error corrected; and Based at least in part on receiving the second indication, correcting the data bits at the data bit error correction component, wherein transmitting the plurality of data bits to the flip decision component comprises: The corrected data bits are transmitted to the flip decision component via the bidirectional output line.

4. A memory device comprising: a flip bit error correction component coupled to the error locator component; A flip decision component is directly coupled to the flip bit error correction component through a unidirectional output line, and the flip bit error correction component is used to: receiving an indication of a flipped bit error of a flipped bit from the error locator component; based at least in part on receiving the indication of the flipped bit error, correcting the flipped bit; and transmitting the corrected flipped bit directly to the flip decision component via the unidirectional output line; and A data bit error correction component is coupled to the flip decision component and is operable to transmit one or more data bits to the flip decision component through a bidirectional output line, wherein the one or more data bits are received at the flip decision component after the corrected flipped bit is received at the flip decision component.

5. The memory device of claim 4 , wherein the unidirectional output line is a dedicated output line between the flip bit error correction component and the flip decision component, wherein the flip bit error correction component is operable to transmit the corrected flip bit directly to the flip decision component through the dedicated output line.

6. A method for operating a memory device, comprising: At the flip decision component, the corrected flip bit is directly received from the flip bit error correction component via a unidirectional output line; receiving, at the flip decision component, one or more data bits from a data bit error correction component via a bidirectional output line, wherein the one or more data bits are received at the flip decision component after the error-corrected flipped bit is received at the flip decision component; and At the flip decision component, a determination is made whether to invert the one or more data bits based at least in part on receiving the error-corrected flipped bit and receiving the one or more data bits.

7. The method according to claim 6, further comprising: at the toggle decision component, determining an output value using a configuration logic criterion based at least in part on receiving the one or more data bits and the error-corrected toggle bit; and An indicator of the output value is transmitted to a data bus determining component.

8. The method according to claim 7, further comprising: Based at least in part on the output value and the error-corrected toggle bit, a second indicator is transmitted from the toggle decision component whether to invert the one or more data bits.

9. The method of claim 7, wherein at the flip decision component, using the configuration logic criteria to determine the output value comprises: The received data bits are compared to the configuration logic criteria to determine whether a number of logic states of the received data bits of the first type is greater than a threshold.

10. The method of claim 9, wherein at the rollover decision component, using the configuration logic criteria to determine the output value comprises: At least some of the one or more data bits and the error-corrected flipped bits are compared using logic components including exclusive-OR (XOR) components.

11. A memory device comprising: Flip decision component; a flip bit error correction component coupled to the flip decision component and configured to transmit one or more flip bits directly to the flip decision component via a unidirectional output line coupling the flip bit error correction component and the flip decision component; and A data bit error correction component is coupled to the flip decision component and is configured to transmit one or more data bits to the flip decision component through a bidirectional output line, wherein the one or more data bits are received at the flip decision component after the one or more flip bits are received at the flip decision component.

12. The memory device of claim 11 , wherein the flip decision component is configured to: Based at least in part on at least one of the one or more data bits received via the bidirectional output line or the one or more toggle bits received via the unidirectional output line, it is determined whether the one or more data bits should be inverted.

13. The memory device of claim 11, wherein the data bit error correction component is directly coupled to the toggle decision component through the bidirectional output line.

14. The memory device of claim 11, wherein the data bit error correction component and the flip bit error correction component are configured to: An indication of an error correction status is received, and in response to receiving the indication, the one or more data bits are transmitted through the bidirectional output line and the one or more toggled bits are transmitted through the unidirectional output line, respectively.

15. The memory device of claim 14, wherein the data bit error correction component and the flip bit error correction component are respectively configured to simultaneously receive the one or more data bits and the one or more flip bits.

16. The memory device of claim 11, wherein the flip decision component comprises: storing logic criteria configured to output a data bit inversion decision indicating whether to invert the one or more data bits, the memory device further comprising: A data bus decision component, coupled to the toggle decision component, is configured to receive an indicator of an output value from the toggle decision component.

17. The memory device of claim 16, wherein the flip decision component is configured to: comparing the received data bits to the stored logic criteria to determine that a number of logic states of the received data bits of the first type satisfies a threshold; and An indication is output that a number of logic states of the received data bits of the first type meets the threshold.

18. The memory device of claim 11, wherein the unidirectional output line has a first transmission speed, and the bidirectional output line has a second transmission speed that is slower than the first transmission speed.

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