Method for manufacturing an optoelectronic device and optoelectronic device

Abstract

A method for manufacturing an optoelectronic device (1) is proposed, the method having the following steps: - providing a semiconductor wafer (2) having a functional semiconductor layer (3) and a growth layer (5), the functional semiconductor layer having an electronic control element (4); - generating a plurality of recesses (6) in the semiconductor wafer (2), the recesses locally exposing the growth layer (5); and - epitaxially growing a plurality of semiconductor layer stacks (7) on the exposed growth layer (6). Furthermore, an optoelectronic device (1) is proposed.

Description

Technical Field

[0001] A method for manufacturing optoelectronic devices is proposed. In addition, an optoelectronic device is proposed. Summary of the Invention

[0002] The object to be achieved is to propose a simplified method for manufacturing optoelectronic devices. In addition, an optoelectronic device should be proposed, which can dissipate heat particularly easily.

[0003] The object is achieved by a method for manufacturing optoelectronic devices having the features of the present invention and by an optoelectronic device having the features of the present invention.

[0004] Advantageous embodiments of the method for manufacturing optoelectronic devices and the optoelectronic device are the subject of the following description.

[0005] According to at least one embodiment of the method, a semiconductor wafer having a growth layer and a functional semiconductor layer is provided, the functional semiconductor layer having an electronic control element. The semiconductor wafer preferably has a main extension plane. The lateral direction is preferably oriented parallel to the main extension plane and the vertical direction is oriented perpendicular to the lateral direction. The functional semiconductor layer and the growth layer are preferably stacked one above the other in the vertical direction. Preferably, the functional semiconductor layer has a lateral extension that is smaller than the lateral extension of the growth layer. The semiconductor wafer preferably has the shape of a disk. The disk preferably has a diameter between at least 150 mm and at most 350 mm. The semiconductor wafer has a thickness of, for example, at least 10 nm and at most 2000 nm, in particular at least 100 nm and at most 1500 nm, at least 50 nm and at most 200 nm or at least 12 nm and at most 15 nm. The thickness of the functional semiconductor layer is, for example, at least 5 nm and at most 2000 nm.

[0006] The functional semiconductor layer preferably comprises Si or GaN. The growth layer preferably comprises or consists of Si or GaN.

[0007] For example, at least one control element is embedded in the functional layer. "Embedded" here can mean that the control element is partly within the functional layer and / or at least a part of it is surrounded by the functional layer on the outside. Preferably, the control element is completely surrounded by the functional layer except for at least one contact surface.

[0008] According to at least one embodiment of the method, a plurality of recesses are produced in the semiconductor wafer, the recesses locally exposing the growth layer. The recesses are produced, for example, by removing material from the semiconductor wafer. The recesses are produced, for example, by means of a chemical etching process or a laser process. The recesses preferably extend in the vertical direction. Preferably, the recesses are produced starting from the functional semiconductor layer.

[0009] The recess preferably completely penetrates the functional semiconductor layer. In this case, the side surfaces of the recess are preferably formed by the exposed side surfaces of the functional semiconductor layer. Additionally, it is also feasible that the recess partially penetrates the growth layer. The recess preferably originates from the functional semiconductor layer, preferably completely penetrates the functional semiconductor layer and extends into the growth layer. In this case, the side surfaces of the recess are preferably formed by the exposed side surfaces of the functional semiconductor layer and the exposed side surfaces of the growth layer, respectively. Additionally, the bottom surface of the recess is formed by the growth layer.

[0010] The recesses are preferably arranged in a matrix, that is, arranged along columns and rows. Preferably, the recesses are arranged at the grid points of a regular pattern. The regular pattern can be a triangular pattern, a quadrilateral pattern, a hexagonal pattern or a polygonal pattern. The recesses are preferably arranged spaced apart from each other laterally. The recesses preferably each have a triangular, quadrilateral, hexagonal, circular, oval or elliptical shape. The maximum extension in the lateral direction of the recess is preferably at least 50 nanometers and at most 100 micrometers, particularly preferably between at least 200 nanometers and at most 5000 nanometers, especially between at least 500 nanometers and at most 2500 nanometers.

[0011] According to at least one embodiment of the method, a plurality of semiconductor layer stacks are epitaxially grown on the exposed growth layer. Preferably, one semiconductor layer stack is produced in each of the plurality of recesses. Preferably, the semiconductor layer stacks completely fill the recesses respectively.

[0012] The semiconductor layer stack is, for example, based on a group III-V compound semiconductor material. The group III-V compound semiconductor material is, for example, a phosphide compound semiconductor material. The phosphide compound semiconductor material is a compound semiconductor material containing phosphorus, such as a material from the system In x Al y Ga 1-x-y P, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1.

[0013] The group III-V compound semiconductor material can also be an arsenic compound semiconductor material. The arsenic compound semiconductor material is a compound semiconductor material containing arsenic, such as a material from the system In x Al y Ga 1-x-y As, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1.

[0014] The group III-V compound semiconductor material can also be an antimony halide compound semiconductor material. The antimony halide compound semiconductor material is a compound semiconductor material containing antimony, such as a material from the system In x Al y Ga 1-x-y Sb, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1.

[0015] Preferably, the III-V compound semiconductor material is a nitride compound semiconductor material. A nitride compound semiconductor material is a compound semiconductor material containing nitrides, such as materials from the system In x Al y Ga 1-x-y N, where 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1.

[0016] The semiconductor layer stack may have dopants and additional components. For simplicity, however, only the main components of the lattice of the semiconductor layer stack are illustrated, i.e., Al, Ga, In, N, As, Sb or P, even when these main components may be partially replaced and / or supplemented by small amounts of other substances.

[0017] According to one embodiment, the semiconductor layer stack respectively includes an active region that generates or detects electromagnetic radiation during operation. The electromagnetic radiation generated during the operation of the active region may be near-ultraviolet radiation, visible light, and / or near-infrared radiation. Alternatively, it is feasible that the electromagnetic radiation detected during the operation of the active region is near-ultraviolet radiation, visible light, and / or near-infrared radiation.

[0018] If the optoelectronic device is configured to generate electromagnetic radiation, then the optoelectronic device is, for example, a light-emitting diode chip or a laser diode. If the optoelectronic device is configured to detect electromagnetic radiation, then the optoelectronic device is, for example, a photodetector.

[0019] According to one embodiment, a method for manufacturing an optoelectronic device includes the following steps:

[0020] - Providing a semiconductor wafer having a functional semiconductor layer and a growth layer, the functional semiconductor layer having an electronic control element; and

[0021] - Generating a plurality of recesses in the semiconductor wafer, the recesses locally exposing the growth layer;

[0022] - Epitaxially growing a plurality of semiconductor layer stacks on the exposed growth layer.

[0023] The concept of the method for manufacturing optoelectronic devices described herein is further that a semiconductor wafer is provided, which has a functional semiconductor layer and a growth layer. The epitaxial semiconductor layer stack can thus advantageously be produced in the recess of the functional semiconductor layer without the costly transport process of semi-finished products. Advantageously, the semiconductor layer stack can be associated with one or more electronic control elements of the functional semiconductor layer respectively. Advantageously, the costly adjustment of the semiconductor layer stack on the control element is eliminated. In the case where the cross-section of the recess in the lateral direction is relatively small, the semiconductor layer stack can also have a relatively small cross-section. Advantageously, a very low dislocation density in the semiconductor layer stack can thus be achieved.

[0024] In addition, a compact optoelectronic device can be simply manufactured by means of this method, in which a plurality of semiconductor layer stacks are used side by side. Advantageously, the device can be, for example, a miniaturized display (microdisplay), the semiconductor layer stack of which can be rapidly controlled. In addition, the warping caused by stress is advantageously reduced in the manufacturing method.

[0025] According to at least one embodiment of the method, at least one electronic control element has an integrated circuit. For example, one electronic control element can be associated with one semiconductor layer stack in the semiconductor layer stacks respectively. Alternatively, it is feasible that one electronic control element is associated with a plurality of semiconductor layer stacks, or one electronic control element is associated with all semiconductor layer stacks. It is also feasible that all semiconductor layer stacks can be controlled separately from each other by means of a single electronic control element.

[0026] The integrated circuit is formed by or has, for example, an integrated electric circuit (abbreviation "IC" in English "integrated circuit"). The integrated circuit includes, for example, a control unit, an evaluation unit and / or a control unit. The control unit and the evaluation unit respectively read and check the state of the associated semiconductor layer stack, for example. The control unit can, for example, control the state of the associated semiconductor layer stack and turn it on or off, for example.

[0027] The semiconductor layer stack configured as a photodetector can be read, for example, by means of an integrated circuit such as a control unit and an evaluation unit. The semiconductor layer stack configured as a light-emitting diode can be controlled, for example, by means of an integrated circuit or a control unit.

[0028] According to at least one embodiment of the method, an insulating connection layer is provided between the functional semiconductor layer and the growth layer. The insulating connection layer preferably contacts the functional semiconductor layer and the growth layer integrally and directly. The insulating connection layer preferably promotes a mechanically stable connection between the functional semiconductor layer and the growth layer. The insulating connection layer preferably includes or consists of SiO2.

[0029] Preferably, the recess completely penetrates the insulating connection layer. In this case, the sides of the recess are formed by the exposed sides of the functional semiconductor layer, the exposed sides of the growth layer, and the exposed sides of the insulating connection layer, respectively. Alternatively, the sides of the recess are formed by the exposed sides of the functional semiconductor layer and the exposed sides of the insulating connection layer, respectively. In this case, the recess does not penetrate the growth layer.

[0030] According to at least one embodiment of the method, the surface of the exposed growth layer is used as the growth surface for the semiconductor layer stack. The bottom surface of the recess preferably forms the surface of the exposed growth layer. The semiconductor layer stack can preferably be epitaxially deposited on the growth surface. The semiconductor layer stack is preferably epitaxially grown on the exposed growth layer by means of chemical vapor deposition.

[0031] According to at least one embodiment of the method, the growth surface has a surface with a {111} orientation or is a surface with a {111} orientation. Generally, the direction in the crystal lattice is clearly defined by the Miller indices h, k, l. In addition, the crystal plane family (hkl) can be defined by means of the directions h, k, l. That is to say, the crystal plane family (hkl) is clearly defined by means of the Miller indices. The crystal plane family (hkl) is preferably represented by the label {hkl} to denote all symmetry-equivalent lattice planes. Preferably, the semiconductor layer stack can only grow on a surface with a {111} orientation.

[0032] The functional semiconductor layer preferably has a surface with a {100} orientation, wherein the surface with a {100} orientation of the functional semiconductor layer preferably extends parallel to the main extension plane of the semiconductor wafer. A semiconductor layer stack based on a III-V compound semiconductor material preferably cannot grow on a surface with a {100} orientation or can only grow very poorly on a surface with a {100} orientation.

[0033] Alternatively, the functional semiconductor layer can have a surface with a {111} orientation. In this case, when manufacturing the semiconductor wafer, the functional semiconductor layer is applied to the growth layer having a growth surface. The crystal orientations of the functional semiconductor layer and the growth layer are preferably oriented substantially the same in this case. "Substantially" means that the crystal orientation can be twisted around the surface normal in the vertical direction. For example, the crystal orientations of the functional semiconductor layer and the growth layer can differ by an angle of at least 0.1° to a maximum of 0.5°. Thereby, the crystal orientations of the semiconductor layer stack and the functional semiconductor layer can also differ by an angle of at least 0.1° to a maximum of 0.5° around the surface normal.

[0034] The crystal orientation of the semiconductor layer stack can preferably be oriented the same around the surface normal with a deviation of 0.04°.

[0035] According to at least one embodiment of the method, the growth surface extends parallel to the main extension plane of the semiconductor wafer. In this case, the growth layer typically has a surface with a {111} orientation, which is arranged parallel to the main extension plane of the semiconductor wafer. The exposed growth surface is typically used as the starting surface for the epitaxial process for epitaxially growing a semiconductor layer stack in this case. Preferably, the semiconductor layer stack is grown entirely on the growth surface.

[0036] According to at least one embodiment of the method, the growth surface extends inclined with respect to the main extension plane of the semiconductor wafer. The inclined growth surface is produced by means of an anisotropic etching process. Before the inclined growth surface is produced, the growth layer has a surface with a {100} orientation, which extends parallel to the main extension plane of the semiconductor wafer. That is to say, a surface with a {111} orientation is produced by using an anisotropic etching process. Depending on the crystal system of the growth layer, the growth surface can have an angle of at least 10° and at most 80° with respect to the main extension plane of the semiconductor wafer.

[0037] Preferably, the inclined growth surface of the recess has a first region and a second region. For example, the inclined growth surface extends in the first region from a first side surface of the recess in the first region into the central region of the recess. Furthermore, the inclined growth surface preferably extends in the second region from a second side surface of the recess in the second region, which is opposite to the first side surface, into the central region of the recess. The growth surface preferably has a wedge-shaped shape in cross section. The opposite surfaces of the growth surface preferably enclose an angle of less than 160° and greater than 20°.

[0038] According to one embodiment, chambers are respectively produced in the growth layer in the recess, preferably starting from the bottom surface of the recess. In the transverse direction, the chambers respectively preferably have a smaller cross section than the recess. The remaining bottom surface of the recess and the side surfaces of the chambers have a stepped shape in this case. In other words, the remaining bottom surface of the recess and the side surfaces of the chambers formed in the bottom surface of the recess preferably adjoin each other such that edges are formed.

[0039] Preferably, the growth surface is planarized after being produced. For example, the growth surface with a surface having a {111} orientation is planarized by hydrofluoric acid preferably buffered with ammonium fluoride. The growth surface is advantageously typically atomically flat and step-free after such treatment. Thereby, the formation of reverse transformation domains during the epitaxial growth of the semiconductor layer stack is advantageously suppressed.

[0040] According to at least one embodiment of the method, the barrier layer is applied over the sidewalls of the recess. Preferably, the barrier layer is applied to the sidewalls of the recess before the semiconductor layer stack is produced. Preferably, the barrier layer completely covers the sidewalls of the recess. In addition, the barrier layer can completely cover the sidewalls of the recess and the sidewalls of the chamber. The barrier layer includes, for example, AlN, SiO2 or Si3N4 or consists of them. Advantageously, the barrier layer prevents impurity atoms from migrating into the epitaxial semiconductor layer stack during the growth of the epitaxial semiconductor layer stack.

[0041] If the recesses each have a chamber, then the remaining bottom surface of the recess and the sidewalls of the chamber are preferably covered by the barrier layer. The bottom surface of the chamber preferably forms the growth surface for the growth layer of the semiconductor layer stack. In this case, the growth surface preferably extends inclined to the main extension plane of the semiconductor wafer.

[0042] If the bottom surface of the chamber forms the growth surface of the growth layer, then the growth surface is formed relatively small. For example, the growth surface of the semiconductor layer stack is relatively small compared to the cross-section along the lateral direction of the recess and thus the resulting semiconductor layer stack. For example, the area of the growth surface is at least 0.2 smaller than the cross-section along the lateral direction of the recess. Preferably, the area of the growth surface is at least 0.4 smaller than the cross-section along the lateral direction of the recess. Advantageously, this enables relatively defect-free, for example dislocation-free, epitaxial growth of the semiconductor layer stack.

[0043] Alternatively, it is feasible that the growth surface is formed relatively large. For example, the growth surface of the semiconductor layer stack is relatively large compared to the cross-section along the lateral direction of the recess. In this case, the recess is removed by an etching process, wherein the growth layer is drilled so as to have a relatively large cross-section.

[0044] According to at least one embodiment of the method, the reflective layer is applied over the sidewalls of the recess. Preferably, the reflective layer is applied to the sidewalls of the recess before the semiconductor layer stack is produced. Preferably, the reflective layer completely covers the sidewalls of the recess. In addition, the reflective layer can completely cover the sidewalls of the recess and the sidewalls of the chamber. The reflective layer is preferably applied before the barrier layer.

[0045] If the reflective layer is applied before the barrier layer, then the barrier layer is preferably formed to be transparent to the generated electromagnetic radiation.

[0046] Alternatively, it is feasible that the reflective layer is applied on the barrier layer after the barrier layer is applied. In this case, the reflective layer completely covers the barrier layer.

[0047] The reflective layer is configured to reflect the electromagnetic radiation of the semiconductor layer stack. The reflective layer preferably has a reflectivity of at least 90%, in particular 95% or 99%, for the generated electromagnetic radiation.

[0048] The reflective layer is, for example, a metal reflector and preferably comprises or consists of a metal. The reflective layer comprises, for example, at least one of the following metals or consists of at least one of the following metals: silver, aluminum, rhodium, nickel, copper or gold.

[0049] Alternatively, it is feasible that the reflective layer is a Bragg mirror, which consists of layers of alternately arranged materials with high and low refractive indices. In this case, the reflective layer is configured to be electrically insulating and comprises, for example, or consists of a dielectric material.

[0050] In addition, the reflective layer can be a combination of a metal material and a dielectric material.

[0051] According to at least one embodiment of the method, the growth layer is removed such that the first main surface of the semiconductor layer stack is exposed. The first main surface of the semiconductor layer stack is preferably arranged opposite to the second main surface. Preferably, the growth layer is completely removed. In addition to the growth layer, preferably also a part of the semiconductor layer stack is removed. Subsequently, the semiconductor layer stack is preferably planarized.

[0052] Preferably, the growth layer and a part of the semiconductor layer stack are removed such that the first main surface and the bottom surface of the insulating connection layer lie in a common plane. Preferably, the growth layer and / or a part of the semiconductor layer stack are removed by means of mechanical grinding and / or polishing, for example by means of chemical mechanical polishing. The first main surface has grinding and / or polishing marks in this case.

[0053] Alternatively, the growth layer and / or a part of the semiconductor layer stack are removed by means of a chemical etching process. In this case, the insulating connection layer is preferably configured as an etch stop layer.

[0054] In addition, it is feasible to completely remove the insulating connection layer.

[0055] Preferably, the semiconductor layer stack is planarized after epitaxial growth. The semiconductor layer stack has a second main surface in this case, which faces away from the growth layer. In this case, it is feasible that the coverage area of the functional semiconductor layer and the second main surface are arranged in a common plane. Preferably, the planarization is produced by means of mechanical grinding and / or polishing. The second main surface has planarization marks in this case.

[0056] According to at least one embodiment of the method, the semiconductor layer stack is arranged on an auxiliary carrier after removing the growth layer. The semiconductor layer stack is preferably applied to the auxiliary carrier by means of the second main surface in this case.

[0057] According to at least one embodiment of the method, a protective layer is applied to the functional semiconductor layer before the recess is produced. Preferably, the protective layer is applied to the cover surface of the functional semiconductor layer facing away from the growth layer. The recess is preferably produced in the semiconductor wafer after the protective layer is applied. The recess completely penetrates the protective layer and the functional semiconductor layer here. Preferably, the recess completely penetrates the protective layer, the functional semiconductor layer, and the insulating connection layer. The protective layer preferably comprises or consists of SiO2.

[0058] According to at least one embodiment of the method, an epitaxial semiconductor layer sequence is deposited by growing laterally beyond the protective layer. In this case, it is feasible that the semiconductor layer stack does not completely fill the recess. The second main surface is arranged, for example, in the region of the protective layer in the vertical direction. The second main surface preferably forms another growth surface for the semiconductor layer sequence here. For example, the semiconductor layer sequences applied to the second main surface can be connected to each other above the protective layer between adjacent semiconductor layer stacks in the lateral direction. Thereby, the epitaxial semiconductor layer sequence grows laterally beyond the protective layer.

[0059] The semiconductor layer sequence preferably is based on the III-V compound semiconductor materials described in connection with the semiconductor layer stack.

[0060] Subsequently, the epitaxial semiconductor layer sequence can be structured. The epitaxial semiconductor layer sequence can be structured, for example, by means of a wet chemical process, a dry chemical process, or a laser process. It is also feasible that the following multiple processes can be combined: a wet chemical process, a dry chemical process, and a laser process. The structured semiconductor layer sequence can have elements that are arranged matrix-wise, that is, along columns and rows. Preferably, the elements of the structured semiconductor layer sequence are arranged at the grid points of a regular pattern. The elements of the structured semiconductor layer sequence are preferably arranged laterally spaced apart from each other here.

[0061] Electronic control elements can be respectively associated with the elements of the structured semiconductor layer sequence. Alternatively, it is feasible that an electronic control element is associated with multiple elements of the structured semiconductor layer sequence, or an electronic control element is associated with all elements of the structured semiconductor layer sequence. It is also achievable that, by means of at least one electronic control element, all elements of the structured semiconductor layer sequence can be controlled separately from each other.

[0062] In addition, a contact layer can be applied above the semiconductor layer sequence. Preferably, the contact layer comprises or consists of a transparent conductive oxide (English "transparent conductive oxide", abbreviated as "TCO").

[0063] According to at least one embodiment of the method, a conductive connection is applied to the semiconductor layer stack and the functional semiconductor layer, and the conductive connection electrically connects the semiconductor layer stack and the functional semiconductor layer to each other.

[0064] If the optoelectronic device only has a semiconductor layer stack, the conductive connection can be applied to the second major surface of the semiconductor layer stack. In this case, the conductive connection electrically connects the second major surface of the semiconductor layer stack to the functional semiconductor layer.

[0065] If the optoelectronic device has a semiconductor layer sequence, the conductive connection can be applied to the first major surface of the semiconductor layer stack. In this case, the conductive connection electrically connects the first major surface of the semiconductor layer stack to the functional semiconductor layer. Alternatively, the conductive connection can be applied to the semiconductor layer sequence. In this case, the conductive connection electrically connects the semiconductor layer sequence to the functional semiconductor layer.

[0066] If a contact layer is also applied to the semiconductor layer sequence, the contact layer can be electrically connected to the functional semiconductor layer by means of one of the conductive connections.

[0067] In addition, an opaque cover can be provided on the conductive connection. Preferably, this is the case when the conductive connection electrically connects the second major surface of the semiconductor layer stack to the functional semiconductor layer. Advantageously, the electronic control elements are protected from light-induced interference.

[0068] In addition, an optoelectronic device is proposed, which can be manufactured by the method described herein. All features and embodiments disclosed in connection with the method can thus also be combined with the optoelectronic device and vice versa.

[0069] According to at least one embodiment, the optoelectronic device includes an epitaxial semiconductor layer stack.

[0070] According to at least one embodiment, the optoelectronic device includes a functional semiconductor layer having an electronic control element for controlling the semiconductor layer stack.

[0071] According to at least one embodiment, the functional semiconductor layer is arranged beside the semiconductor layer stack. In this case, the functional semiconductor layer is arranged at a distance from the semiconductor layer stack in the lateral direction.

[0072] According to at least one embodiment, in a top view, the functional semiconductor layer does not overlap with the first major surface of the semiconductor layer stack. Advantageously, the functional semiconductor layer is thermally decoupled from the semiconductor layer stack, such that the generated heat loss powers of the functional semiconductor layer and the semiconductor layer stack do not add up on the same surface element in the top view. This optoelectronic device advantageously has improved heat dissipation.

[0073] According to at least one embodiment, the first main surface is configured as a radiation-transmissive surface. The first main surface typically has marks produced by a grinding process and / or a polishing process or an etching process here.

[0074] According to at least one embodiment, the semiconductor layer stack has an active region that generates or detects electromagnetic radiation during operation. For example, the semiconductor layer stack emits red, yellow, green, or blue light. In addition, the optoelectronic device may include a plurality of semiconductor layer stacks. In this case, the semiconductor layer stacks are grouped into sub-pixels, and each of the sub-pixels includes, for example, three semiconductor layer stacks that preferably emit red, green, and blue light respectively.

[0075] The sub-pixel preferably includes three semiconductor layer stacks, one of which emits blue light, one emits green light, and one emits red light.

[0076] The three semiconductor layer stacks of the sub-pixel can be arranged at the corner points of a triangle.

[0077] It is also feasible that a plurality of sub-pixels are arranged in a matrix, that is, along columns and rows. Preferably, a plurality of sub-pixels are arranged at the grid points of a regular pattern. The regular pattern can be a triangular pattern, a quadrilateral pattern, a hexagonal pattern, or a polygonal pattern.

[0078] According to at least one embodiment, an epitaxial semiconductor layer sequence is provided on the epitaxial semiconductor layer stack and the functional semiconductor layer. In this embodiment, the epitaxial semiconductor layer sequence has an active region that generates or detects electromagnetic radiation during operation. In a top view, the semiconductor layer sequence preferably completely overlaps with the semiconductor layer stack. In addition, the epitaxial semiconductor layer sequence partially overlaps with the functional semiconductor layer.

[0079] According to at least one embodiment, a protective layer is provided between the functional semiconductor layer and the epitaxial semiconductor layer sequence.

[0080] In addition, a barrier layer can be provided between the functional semiconductor layer and the semiconductor layer stack. Additionally, a reflective layer can be provided between the functional semiconductor layer and the semiconductor layer stack. The reflective layer can be provided between the semiconductor layer stack and the barrier layer or between the barrier layer and the functional semiconductor layer.

[0081] For example, the barrier layer is configured in multiple layers. In this case, it is feasible that the reflective layer is provided between two layers of the barrier layer.

[0082] It is also feasible that the reflective layer preferably completely surrounds the semiconductor layer stack. For example, the reflective layer completely covers the bottom surface of the insulating connection layer. The first main surface preferably does not have a reflective layer here.

[0083] Furthermore, it is feasible that the barrier layer preferably completely surrounds the semiconductor layer stack. In this case, the barrier layer completely covers the bottom surface of the insulating connection layer. The first main surface preferably does not have a barrier layer here. Description of the Drawings

[0084] Below, a method for manufacturing an optoelectronic device and an optoelectronic device will be described in detail according to embodiments.

[0085] The drawings show:

[0086] Figure 1 , 2 and 3 show a schematic cross-sectional view of the method steps of a method for manufacturing an optoelectronic device according to an embodiment;

[0087] Figure 4 and 5 show schematic cross-sectional views of the method steps of a method for manufacturing an optoelectronic device according to respective embodiments;

[0088] Figure 6 shows a schematic cross-sectional view of an optoelectronic device according to an embodiment;

[0089] Figure 7 , 8 , 9, 10, 11 and 12 show schematic cross-sectional views of the method steps of a method for manufacturing an optoelectronic device according to an embodiment; and

[0090] Figure 13 shows a schematic cross-sectional view of an optoelectronic device according to an embodiment.

[0091] Identical, similar or functionally identical elements are provided with the same reference numerals in the drawings. The size relationships between the drawings and the elements shown in the drawings should not be regarded as being to scale. Rather, individual elements may be shown exaggerated for better visibility and / or for better understanding. Detailed Description of the Embodiments

[0092] In the method according to the Figure 1 , 2 and 3 embodiments, as shown in Figure 1 , a semiconductor wafer 2 having a functional semiconductor layer 3 with an electronic control element 4 is provided. Furthermore, the semiconductor wafer 2 includes a growth layer 5 and an insulating connection layer 8. The insulating connection layer 8 is provided between the functional semiconductor layer 3 and the growth layer 5 and promotes a mechanically stable connection between the functional semiconductor layer 3 and the growth layer 5.

[0093] The insulating connection layer 8 is preferably formed of SiO2.

[0094] According toFigure 2 In a next method step, a plurality of recesses 6 (only a single unique recess 6 of the recesses 6 is shown by way of example) are produced in the semiconductor wafer 2, the recesses locally exposing the growth layer 5. The recesses 6 are produced starting from the functional semiconductor layer 3. The recesses 6 completely penetrate the functional semiconductor layer 3 and the insulating connection layer 8.

[0095] Furthermore, the recesses 6 partially penetrate the growth layer 5. The side surfaces 6b of the recesses are each formed by the exposed side surfaces of the functional semiconductor layer 3, the exposed side surfaces of the growth layer 5, and the exposed side surfaces of the insulating connection layer 8. Furthermore, the bottom surface 6a of the recesses is formed by the growth layer 5.

[0096] A barrier layer 11 is applied over the side surfaces 6b of the recesses. The barrier layer 11 completely covers the side surfaces 6b of the recesses. The barrier layer 11 comprises, for example, or is formed of AlN.

[0097] In a next method step, as shown in Figure 3 , a plurality of semiconductor layer stacks 7 epitaxially grow on the exposed growth layer 5.

[0098] The semiconductor layer stacks 7 each comprise an active region which generates or detects electromagnetic radiation during operation. The semiconductor layer stacks 7 each completely fill the recesses 6.

[0099] The semiconductor layer stacks 7 are preferably planarized after growth, for example by means of mechanical grinding and / or polishing. The semiconductor layer stacks 7 have a second major surface 7b which faces away from the growth layer 5. The covering surface 3a of the functional semiconductor layer and the second major surface 7b are arranged in a common plane.

[0100] The surface 5a of the exposed growth layer serves as a growth surface 9 for the semiconductor layer stacks 7. The bottom surface 6a of the recesses forms the surface 5a of the exposed growth layer. The semiconductor layer stacks 7 are epitaxially deposited on the growth surface 9. The growth surface 9 has a surface 10 with a {111} orientation.

[0101] The growth surface 9 currently extends parallel to the main extension plane of the semiconductor wafer 2. That is to say, the growth layer 5 has a surface 10 with a {111} orientation or consists thereof, which surface is arranged parallel to the main extension plane of the semiconductor wafer 2.

[0102] Subsequently, it is possible to remove the growth layer 5 and a part of the semiconductor layer stacks 7 such that the first major surface 7a of the semiconductor layer stacks is exposed (not shown here).

[0103] In the method according to the embodiment of Figure 3 , first the method steps as already described according to Figure 1 are carried out. In a next method step, recesses 6 are produced which, however, have an inclined bottom surface differently from the method stage of Figure 3 . Accordingly, the growth surface 9 in accordance withFigure 4 extends obliquely to the main extension plane of the semiconductor wafer 2 in the method step. The growth layer 5 has a surface with a {100} orientation in this case, which is arranged parallel to the main extension plane of the semiconductor wafer 2.

[0104] The inclined growth surface 9 has a first region 9a and a second region 9b when observed in cross-section in the region of the recess 6. The inclined growth surface 9 extends from the side surface 11a of the barrier layer in the first region 9a to the central region 6c of the recess in the first region 9a. In addition, the inclined growth surface 9 extends from the opposite side surface 11a of the barrier layer in the second region 9b of the growth surface to the central region 6c of the recess in the second region 9b. The growth surface 9 has a wedge shape in cross-section.

[0105] In the method according to Figure 5 the embodiment of Figure 4 the embodiment of

[0106] chambers 17 are respectively produced in the growth layer 5 in the recess 6. The chambers 17 have a smaller cross-section in the transverse direction compared to the recess 6. The remaining bottom surface 6a of the recess and the side surface 17a of the chamber have a stepped shape. In other words, the remaining bottom surface 6a of the recess and the side surface 17b of the chamber formed in the bottom surface 6a of the recess are adjacent to each other, so as to form an edge.

[0107] The optoelectronic device 1 can be produced, for example, only after the semiconductor layer stack 7 is introduced. In addition, a plurality of optoelectronic devices 1 can be produced by a dicing process after the semiconductor layer stack is introduced.

[0108] According to Figure 6 the embodiment of

[0109] the optoelectronic device 1 has an epitaxial semiconductor layer stack 7, a functional semiconductor layer 3 and an insulating connection layer 8, the functional semiconductor layer having an electronic control element 4 for controlling the semiconductor layer stack 4. The functional semiconductor layer 3 and the insulating connection layer 8 are arranged beside the semiconductor layer stack 7, such that in a top view, the functional semiconductor layer 3 does not overlap with the first main surface 7a of the semiconductor layer stack.

[0110] Furthermore, the conductive connection portion 16 is applied to the second main surface 7b of the semiconductor layer stack. In this case, the conductive connection portion 16 electrically connects the second main surface 7b of the semiconductor layer stack to the functional semiconductor layer 3. At least one electronic control element 4 has, for example, an integrated circuit.

[0111] Furthermore, a reflective layer 12 is provided between the barrier layer 11 and the semiconductor layer stack 7. The reflective layer 12 and the barrier layer 11 are arranged around the first main surface 7a of the semiconductor layer stack and completely enclose the first main surface. The reflective layer 12 completely covers the bottom surface of the insulating connection layer.

[0112] In the method according to Figures 7 to 12 of the embodiment, similar to Figure 1 a semiconductor wafer 2 ( Figure 7 ) is provided. Subsequently, as shown in Figure 8 , a protective layer 14 is applied to the functional semiconductor layer 3. The protective layer 14 is applied on the covering surface of the functional semiconductor layer 3 facing away from the growth layer 5.

[0113] In the next method step, a recess 6 is produced, as shown in Figure 9 . The recess 6 completely penetrates the protective layer 14, the functional semiconductor layer 3, and the insulating connection layer 8 differently from Figure 4 .

[0114] According to Figure 10 , in the next method step, first a plurality of semiconductor layer stacks 7 are epitaxially grown on the exposed growth layer 5. The second main surface 7b is arranged in the region of the protective layer 14 in the vertical direction in this embodiment. Subsequently, the epitaxial semiconductor layer sequence 15 is deposited by growing laterally beyond the protective layer 14. Here, the second main surface 7b forms another growth surface for the semiconductor layer sequence 15.

[0115] In another method step, the device thus produced is arranged on an auxiliary carrier 13, as shown in Figure 11 . The device is arranged on the auxiliary carrier 13 with the second main surface 7b or facing forward with the semiconductor layer sequence 15.

[0116] Subsequently, according to Figure 12 , the growth layer 5, the insulating connection layer 8, and a part of the semiconductor layer stack 7 are removed. By removing, the first main surface 7a of the semiconductor layer stack is exposed. The first main surface 7a of the semiconductor layer stack is in a common plane with the bottom surface of the functional semiconductor layer 3.

[0117] According to Figure 13 of the embodiment, the optoelectronic device 1 is Figure 6Differently, a semiconductor layer sequence 15 (not shown here) is provided on the epitaxial semiconductor layer stack 7. In the present embodiment, the semiconductor layer sequence 15 has an active region that generates or detects electromagnetic radiation during operation.

[0118] Furthermore, a contact layer 18 is applied on top of the semiconductor layer sequence 15. Preferably, the contact layer 18 is a transparent conductive oxide (abbreviated as "TCO" in English "transparent conductive oxide").

[0119] Furthermore, a conductive connection 16 is applied on the semiconductor layer sequence 15 and the contact layer 18. In this case, the conductive connection 16 electrically connects the contact layer 18 and the semiconductor layer sequence 15 to the functional semiconductor layer 3.

[0120] In the present embodiment, the epitaxial semiconductor layer sequence 15 is structured and includes different elements R, G, B. The elements R, G, B of the semiconductor layer sequence 15 are configured to emit, for example, red light R, green light G, and blue light B.

[0121] This application claims the priority of German Patent Application 10 2019 100 521.3, the disclosure of which is incorporated herein by reference.

[0122] The present invention is not limited to the described embodiments by the description of the embodiments. Rather, this application may include any new features and any combination of features, which particularly includes any combination of features in the embodiments, even if such features or the combination itself is not exhaustively given in the embodiments.

[0123] List of Reference Numerals

[0124] 1 optoelectronic device

[0125] 2 semiconductor wafer

[0126] 3 functional semiconductor layer

[0127] 3a coverage area of the functional semiconductor layer

[0128] 4 control element

[0129] 5 growth layer

[0130] 5a surface of the exposed growth layer

[0131] 6 recess

[0132] 6a bottom surface of the recess

[0133] 6b side surface of the recess

[0134] 6c central region of the recess

[0135] 7 semiconductor layer stack

[0136] 7a first major surface of the semiconductor layer stack

[0137] 7b second major surface of the semiconductor layer stack

[0138] 8 insulating connection layer

[0139] 9 growth surface

[0140] 9a first region of the growth surface

[0141] 9b second region of the growth surface

[0142] 10 {111}-oriented surface

[0143] 11 barrier layer

[0144] 11a side surface of the barrier layer

[0145] 12 reflective layer

[0146] 13 auxiliary carrier

[0147] 14 protective layer

[0148] 15 semiconductor layer sequence

[0149] 16 conductive connection part

[0150] 17 chamber

[0151] 17a bottom surface of the chamber

[0152] 17b side surface of the chamber

[0153] 18 contact layer

[0154] R red

[0155] G green

[0156] B blue

Claims

1. A method for manufacturing an optoelectronic device (1), the method having the following steps: - Providing a semiconductor wafer (2) having a functional semiconductor layer (3) and a growth layer (5), the functional semiconductor layer having an electronic control element (4); - Generating a plurality of recesses (6) in the semiconductor wafer (2), the recesses locally exposing the growth layer (5); and - Epitaxially growing a plurality of semiconductor layer stacks (7) on the exposed growth layer (6), wherein - The surface (5a) of the exposed growth layer serves as a growth surface (9) for the semiconductor layer stack (7); - The growth surface (9) extends inclined to the main extension plane of the semiconductor wafer (2), - Removing the growth layer (5) such that a first main surface of the semiconductor layer stack (7a) is exposed, and - When removing the growth layer (5), removing a part of the semiconductor layer stack (7a) such that the first main surface of the semiconductor layer stack (7a) is flattened.

2. The method according to claim 1, wherein at least one electronic control element (4) has an integrated circuit.

3. The method according to claim 1, wherein an insulating connection layer (8) is provided between the functional semiconductor layer (3) and the growth layer (5).

4. The method according to claim 1, wherein the growth surface (9) has a surface (10) with a {111} orientation.

5. The method according to claim 4, wherein the growth surface (9) extends parallel to the main extension plane of the semiconductor wafer (2).

6. The method according to claim 1, wherein a barrier layer (11) is applied above the side surface (6b) of the recess.

7. The method according to claim 1, wherein a reflective layer (12) is applied above the side surface (6b) of the recess.

8. The method according to claim 1, wherein the semiconductor layer stack (7) is arranged on an auxiliary carrier (13) before removing the growth layer (5).

9. The method according to claim 1, wherein a protective layer (14) is applied to the functional semiconductor layer (3) before generating the recesses (6).

10. The method according to claim 9, wherein an epitaxial semiconductor layer sequence (15) is deposited by lateral growth beyond the protective layer (14).

11. The method according to claim 1, wherein a conductive connection (16) is applied to the semiconductor layer stack (7) and the functional semiconductor layer (3), the conductive connection electrically connecting the semiconductor layer stack (7) and the functional semiconductor layer (3) to each other.

12. An optoelectronic device (1), the optoelectronic device having: - An epitaxial semiconductor layer sequence (15) having an active region that generates or detects electromagnetic radiation during operation, - An epitaxial semiconductor layer stack (7), and - A functional semiconductor layer (3) having an electronic control element (4) for controlling the epitaxial semiconductor layer stack (7), wherein - The functional semiconductor layer (3) is arranged beside the epitaxial semiconductor layer stack (7), and - in a top view, the functional semiconductor layer (3) does not overlap with the first main surface (7a) of the epitaxial semiconductor layer stack, - the optoelectronic device (1) does not have a growth layer (6), - the epitaxial semiconductor layer sequence (15) is arranged above the epitaxial semiconductor layer stack (7) and the functional semiconductor layer (3).

13. The optoelectronic device (1) according to claim 12, wherein a protective layer (14) is arranged between the functional semiconductor layer (3) and the epitaxial semiconductor layer sequence (15).

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