LTPO type shift register circuit and its driving method, display panel

Abstract

The embodiments of the present application provide an LTPO-type shift register circuit and a driving method thereof, and a display panel. The second MOS tube is an N-type MOS tube, and the other MOS tubes, including the first MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, and the tenth MOS tube are all P-type MOS tubes. Through the CMOS process, a combination of N-type MOS tubes and P-type MOS tubes is adopted to reduce the number of MOS tubes while ensuring normal light emission of sub-pixels, reducing the loss of voltage signals passing through the MOS tubes, and reducing abnormal displays, thereby reducing the width of the LTPO-type shift register circuit and reducing the screen border.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to an LTPO-type shift register circuit and a driving method thereof, and a display panel. Background Art

[0002] AMOLED (Active-Matrix Organic Light Emitting Diode) flexible semiconductor screen is called the "crown" of the next generation of displays because of its many excellent characteristics such as low power consumption, high contrast, wide viewing angle, wide color gamut, thin panel, flexible display, wide operating temperature range, and low cost development potential.

[0003] OLED (Organic Light-Emitting Diode) can meet the requirements of most display devices in today's information age for higher performance and greater information capacity: it can be used for indoor and outdoor lighting; it can be used as wallpaper decoration; it can be made into foldable electronic newspapers; it can also be used in portable devices such as mobile phones, tablets, wearable electronic products, etc.

[0004] When AMOLED displays use the LTPS (Low Temperature Poly-silicon) process, the leakage current will be large, resulting in bright spots in the black screen. The prior art uses the LTPO (Low Temperature Poly-Silicon and Oxide) process to reduce the leakage current, but the LTPO process requires an LTPO-type shift register to provide a signal to control the gate switch. The LTPO-type shift register circuit in the related art is as follows: Figure 1a or Figure 1b As shown, it is composed of multiple MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistor) and capacitors.

[0005] However, in the related art, the number of MOS tubes in the LTPO-type shift register circuit is large, which will lead to the problem of a larger screen border. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide an LTPO type shift register circuit and a driving method thereof, and a display panel, so as to reduce the screen border. The specific technical solution is as follows:

[0007] In a first aspect, an embodiment of the present application provides an LTPO type shift register circuit, comprising:

[0008] A first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, a first capacitor, and a second capacitor;

[0009] Among them, the second MOS tube is an N-type MOS tube, and the first MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, and the tenth MOS tube are all P-type MOS tubes.

[0010] In a possible implementation manner, the first end of the first MOS transistor is connected to the STV line, the second end of the first MOS transistor is respectively connected to the gate of the second MOS transistor, the gate of the third MOS transistor, the second end of the fifth MOS transistor, the gate of the eighth MOS transistor, the gate of the tenth MOS transistor, and the first end of the first capacitor, and the gate of the first MOS transistor is connected to the CK2 line;

[0011] The first end of the second MOS tube is connected to the VGL line, and the second end of the second MOS tube is respectively connected to the first end of the third MOS tube, the gate of the fourth MOS tube, and the first end of the sixth MOS tube;

[0012] The second end of the third MOS tube is connected to the VGH circuit;

[0013] The first end of the fourth MOS tube is connected to the VGH line, and the second end of the fourth MOS tube is connected to the first end of the fifth MOS tube;

[0014] The gate of the fifth MOS tube is connected to the CK1 circuit;

[0015] The second end of the sixth MOS tube is respectively connected to the first end of the seventh MOS tube, the gate of the ninth MOS tube, and the first end of the second capacitor, and the gate of the sixth MOS tube is connected to the CK1 line;

[0016] The gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube;

[0017] The second end of the eighth MOS tube is connected to the VGH line;

[0018] The first end of the ninth MOS tube is connected to the CK3 line, and the second end of the ninth MOS tube is respectively connected to the second end of the second capacitor, the first end of the tenth MOS tube, and the output line;

[0019] The second end of the tenth MOS tube is connected to the VGL line;

[0020] The second end of the first capacitor is connected to the CK1 line.

[0021] In a possible implementation manner, the first end of the first MOS transistor is connected to the STV line, the second end of the first MOS transistor is respectively connected to the gate of the third MOS transistor, the second end of the fifth MOS transistor, the gate of the eighth MOS transistor, the gate of the tenth MOS transistor, and the first end of the first capacitor, and the gate of the first MOS transistor is connected to the CK2 line;

[0022] The first end of the second MOS tube is connected to the VGL line, the second end of the second MOS tube is respectively connected to the first end of the third MOS tube, the gate of the fourth MOS tube, and the first end of the sixth MOS tube, and the gate of the second MOS tube is connected to the STV line;

[0023] The second end of the third MOS tube is connected to the VGH circuit;

[0024] The first end of the fourth MOS tube is connected to the VGH line, and the second end of the fourth MOS tube is connected to the first end of the fifth MOS tube;

[0025] The gate of the fifth MOS tube is connected to the CK1 circuit;

[0026] The second end of the sixth MOS tube is respectively connected to the first end of the seventh MOS tube, the gate of the ninth MOS tube, and the first end of the second capacitor, and the gate of the sixth MOS tube is connected to the CK1 line;

[0027] The gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube;

[0028] The second end of the eighth MOS tube is connected to the VGH line;

[0029] The first end of the ninth MOS tube is connected to the CK3 line, and the second end of the ninth MOS tube is respectively connected to the second end of the second capacitor, the first end of the tenth MOS tube, and the output line;

[0030] The second end of the tenth MOS tube is connected to the VGL line;

[0031] The second end of the first capacitor is connected to the CK1 line.

[0032] In a possible implementation manner, the first end of the first MOS transistor is connected to the STV line, the second end of the first MOS transistor is respectively connected to the second end of the third MOS transistor, the gate of the eighth MOS transistor, the gate of the tenth MOS transistor, and the first end of the first capacitor, and the gate of the first MOS transistor is connected to the CK2 line;

[0033] The first end of the second MOS tube is connected to the VGL line, the second end of the second MOS tube is respectively connected to the gate of the fourth MOS tube, the first end of the fifth MOS tube, and the first end of the sixth MOS tube, and the gate of the second MOS tube is connected to the STV line;

[0034] The first end of the third MOS tube is connected to the second end of the fourth MOS tube and the gate of the fifth MOS tube respectively, and the gate of the third MOS tube is connected to the CK1 line;

[0035] The first end of the fourth MOS tube is connected to the VGH circuit;

[0036] The second end of the fifth MOS tube is connected to the VGH line;

[0037] The second end of the sixth MOS tube is respectively connected to the first end of the seventh MOS tube, the gate of the ninth MOS tube, and the first end of the second capacitor, and the gate of the sixth MOS tube is connected to the CK1 line;

[0038] The gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube;

[0039] The second end of the eighth MOS tube is connected to the VGH line;

[0040] The first end of the ninth MOS tube is connected to the CK3 line, and the second end of the ninth MOS tube is respectively connected to the second end of the second capacitor, the first end of the tenth MOS tube, and the output line;

[0041] The second end of the tenth MOS tube is connected to the VGL line;

[0042] The second end of the first capacitor is connected to the CK1 line.

[0043] In a possible implementation manner, the first end of the first MOS transistor is connected to the STV line, the second end of the first MOS transistor is respectively connected to the gate of the second MOS transistor, the second end of the third MOS transistor, the gate of the eighth MOS transistor, the gate of the tenth MOS transistor, and the first end of the first capacitor, and the gate of the first MOS transistor is connected to the CK2 line;

[0044] The first end of the second MOS tube is connected to the VGL line, and the second end of the second MOS tube is respectively connected to the gate of the fourth MOS tube, the first end of the fifth MOS tube, and the first end of the sixth MOS tube;

[0045] The first end of the third MOS tube is connected to the second end of the fourth MOS tube and the gate of the fifth MOS tube respectively, and the gate of the third MOS tube is connected to the CK1 line;

[0046] The first end of the fourth MOS tube is connected to the VGH circuit;

[0047] The second end of the fifth MOS tube is connected to the VGH line;

[0048] The second end of the sixth MOS tube is respectively connected to the first end of the seventh MOS tube, the gate of the ninth MOS tube, and the first end of the second capacitor, and the gate of the sixth MOS tube is connected to the CK1 line;

[0049] The gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube;

[0050] The second end of the eighth MOS tube is connected to the VGH line;

[0051] The first end of the ninth MOS tube is connected to the CK3 line, and the second end of the ninth MOS tube is respectively connected to the second end of the second capacitor, the first end of the tenth MOS tube, and the output line;

[0052] The second end of the tenth MOS tube is connected to the VGL line;

[0053] The second end of the first capacitor is connected to the CK1 line.

[0054] In a possible implementation manner, the circuit further includes: an eleventh MOS transistor, wherein the eleventh MOS transistor is arranged between the first MOS transistor and the tenth MOS transistor.

[0055] In a possible implementation, the eleventh MOS tube is an N-type MOS tube, the first end of the eleventh MOS tube is connected to the second end of the first MOS tube, the second end of the eleventh MOS tube is connected to the gate of the tenth MOS tube, and the gate of the eleventh MOS tube is connected to the VGH line.

[0056] In a possible implementation manner, the circuit further includes: a third capacitor, a first end of the third capacitor is connected to the VGH line or the VGL line, and a second end of the third capacitor is connected to the second end of the second MOS tube.

[0057] In a second aspect, an embodiment of the present application provides a driving method of an LTPO type shift register circuit, which is applied to any LTPO type shift register circuit described in the present application, and the method includes:

[0058] T1 cycle: STV line inputs low voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs high voltage, CK4 line inputs high voltage;

[0059] T2 period: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs low voltage;

[0060] T3 cycle: STV line inputs high voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs high voltage, CK4 line inputs high voltage;

[0061] T4 cycle: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs high voltage;

[0062] T5 cycle: STV line inputs low voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs low voltage, CK4 line inputs high voltage;

[0063] T6 cycle: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs low voltage;

[0064] T7 cycle: STV line inputs low voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs high voltage, and CK4 line inputs high voltage.

[0065] In a third aspect, an embodiment of the present application provides a display panel, comprising any LTPO type shift register circuit described in the present application.

[0066] Beneficial effects of the embodiments of the present application:

[0067] In the LTPO-type shift register circuit and its driving method and display panel provided in the embodiment of the present application, the second MOS tube is an N-type MOS tube, and the other MOS tubes, including the first MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, and the tenth MOS tube are all P-type MOS tubes. Through the CMOS process, the N-type MOS tube and the P-type MOS tube are combined to reduce the number of MOS tubes while ensuring the normal light emission of the sub-pixel, reducing the loss of the voltage signal through the MOS tube, and reducing abnormal display, thereby reducing the width of the LTPO-type shift register circuit and reducing the screen border. Of course, it is not necessary to achieve all the advantages described above at the same time for implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and a person skilled in the art can also obtain other drawings based on these drawings.

[0069] Figure 1a A schematic diagram of an LTPO type shift register circuit in the related art;

[0070] Figure 1b Another schematic diagram of an LTPO type shift register circuit in the related art;

[0071] Figure 2 A first schematic diagram of an LTPO-type shift register circuit according to an embodiment of the present application;

[0072] Figure 3 A second schematic diagram of the LTPO type shift register circuit according to an embodiment of the present application;

[0073] Figure 4 A third schematic diagram of the LTPO type shift register circuit according to an embodiment of the present application;

[0074] Figure 5 A fourth schematic diagram of the LTPO type shift register circuit according to an embodiment of the present application;

[0075] Figure 6 A fifth schematic diagram of the LTPO type shift register circuit according to an embodiment of the present application;

[0076] Figure 7 A sixth schematic diagram of the LTPO type shift register circuit according to an embodiment of the present application;

[0077] Figure 8A schematic diagram of the driving timing of the LTPO type shift register circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0078] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0079] Figure 1a It is an LTPO type shift register circuit used in the related art, through which the voltage signal of the sub-pixel in the first and second stages can be effectively provided. Figure 1b is another LTPO type shift register circuit used in the related art, wherein: Figure 1a The circuit shown includes 13 P-type MOS tubes. Figure 1b The circuit includes 12 P-type MOS tubes. The LTPO-type shift register circuit is generally arranged in the screen frame. The number of MOS tubes directly determines the size of the screen frame. When the number of MOS tubes is large, the screen frame will be larger.

[0080] In order to reduce the screen border, an embodiment of the present application provides an LTPO type shift register circuit, including:

[0081] A first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, a first capacitor, and a second capacitor;

[0082] Among them, the second MOS tube is an N-type MOS tube, and the first MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, and the tenth MOS tube are all P-type MOS tubes.

[0083] In the embodiment of the present application, the second MOS tube is an N-type MOS tube (N Metal Oxide Semiconductor Field-Effect Transistor), and the remaining MOS tubes, including the first MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, and the tenth MOS tube are all P-type MOS tubes (Positive Channel Metal Oxide Semiconductor Field-Effect Transistor). Through the CMOS (Complementary Metal Oxide Semiconductor) process, a combination of N-type MOS tubes and P-type MOS tubes is adopted to reduce the number of MOS tubes while ensuring normal light emission of sub-pixels, reducing the loss of voltage signals passing through MOS tubes, and reducing abnormal display, thereby reducing the width of the LTPO-type shift register circuit and reducing the screen border.

[0084] The following is a detailed description, see Figure 2 , Figure 2 A first schematic diagram of an LTPO type shift register circuit provided in an embodiment of the present application, wherein:

[0085] The first end of the first MOS transistor T1 is connected to the STV line, the second end of the first MOS transistor T1 is respectively connected to the gate of the second MOS transistor T2, the gate of the third MOS transistor T3, the second end of the fifth MOS transistor T5, the gate of the eighth MOS transistor T8, the gate of the tenth MOS transistor T10, and the first end of the first capacitor C1, and the gate of the first MOS transistor T1 is connected to the CK2 line;

[0086] The first end of the second MOS transistor T2 is connected to the VGL line, and the second end of the second MOS transistor T2 is respectively connected to the first end of the third MOS transistor T3, the gate of the fourth MOS transistor T4, and the first end of the sixth MOS transistor T6;

[0087] The second end of the third MOS transistor T3 is connected to the VGH circuit;

[0088] The first end of the fourth MOS transistor T4 is connected to the VGH line, and the second end of the fourth MOS transistor T4 is connected to the first end of the fifth MOS transistor T5;

[0089] The gate of the fifth MOS transistor T5 is connected to the CK1 circuit;

[0090] The second end of the sixth MOS transistor T6 is respectively connected to the first end of the seventh MOS transistor T7, the gate of the ninth MOS transistor T9, and the first end of the second capacitor C2, and the gate of the sixth MOS transistor T6 is connected to the CK1 line;

[0091] The gate of the seventh MOS transistor T7 is connected to the CK1 circuit, and the second end of the seventh MOS transistor T7 is connected to the first end of the eighth MOS transistor T8;

[0092] The second end of the eighth MOS transistor T8 is connected to the VGH circuit;

[0093] The first end of the ninth MOS transistor T9 is connected to the CK3 line, and the second end of the ninth MOS transistor T9 is respectively connected to the second end of the second capacitor C2, the first end of the tenth MOS transistor T10, and the output line;

[0094] The second end of the tenth MOS transistor T10 is connected to the VGL line;

[0095] The second end of the first capacitor C1 is connected to the CK1 line.

[0096] Among them, STV represents the row drive clock signal; VGL represents the gate low potential, that is, the voltage that closes the gate; VGH represents the gate high potential, that is, the voltage that opens the gate; CK1 represents the first clock line voltage; CK2 represents the second clock line voltage; CK3 represents the third clock line voltage; OUT represents the voltage of the output circuit.

[0097] In the embodiment of the present application, the second MOS tube is an N-type MOS tube, which is combined with the N-type MOS tube and the P-type MOS tube. While ensuring the normal light emission of the sub-pixel, reducing the loss of the voltage signal through the MOS tube, and reducing abnormal display, the number of MOS tubes and the number of capacitors are reduced, thereby reducing the width of the LTPO-type shift register circuit and reducing the screen border.

[0098] In a possible implementation manner, the circuit further includes: an eleventh MOS transistor T11 , which is arranged between the first MOS transistor and the tenth MOS transistor.

[0099] In order to enhance the voltage holding capability of point N4, a MOS tube, namely the eleventh MOS tube, can be added between tubes T1 and T10. Both P-type MOS tube and N-type MOS tube can be used. In an example, the eleventh MOS tube is an N-type MOS tube. The LTPO shift register circuit is as follows: Figure 3As shown, the first end of the eleventh MOS tube is connected to the second end of the first MOS tube, the second end of the eleventh MOS tube is connected to the gate of the tenth MOS tube, and the gate of the eleventh MOS tube is connected to the VGH line, wherein N1, N2, N3, and N4 are four points in the circuit, not devices.

[0100] In the embodiment of the present application, the number of MOS tubes and the number of capacitors are reduced, thereby reducing the width of the LTPO-type shift register circuit and reducing the screen border; and through the eleventh MOS tube, the ability to maintain voltage can be enhanced.

[0101] In a possible implementation manner, the circuit further includes: a third capacitor C3, a first end of the third capacitor is connected to the VGH line or the VGL line, and a second end of the third capacitor is connected to the second end of the second MOS tube.

[0102] In order to enhance the voltage holding capability of point N1, a capacitor can be added at point N1. One end of the capacitor is connected to point N1, and the other end is connected to a constant power supply signal, such as VGH or VGL. The circuit diagram for connecting the VGH line can be as follows: Figure 4 shown.

[0103] In the embodiment of the present application, the number of MOS tubes is reduced, thereby reducing the width of the LTPO-type shift register circuit, thereby reducing the screen border; and the ability to maintain voltage can be enhanced through the third capacitor.

[0104] The LTPO type shift register circuit provided in the embodiment of the present application can also be as follows Figure 5 As shown, where:

[0105] The first end of the first MOS tube is connected to the STV line, the second end of the first MOS tube is respectively connected to the gate of the third MOS tube, the second end of the fifth MOS tube, the gate of the eighth MOS tube, the gate of the tenth MOS tube, and the first end of the first capacitor, and the gate of the first MOS tube is connected to the CK2 line;

[0106] The first end of the second MOS tube is connected to the VGL line, the second end of the second MOS tube is respectively connected to the first end of the third MOS tube, the gate of the fourth MOS tube, and the first end of the sixth MOS tube, and the gate of the second MOS tube is connected to the STV line;

[0107] The second end of the third MOS tube is connected to the VGH circuit;

[0108] The first end of the fourth MOS tube is connected to the VGH line, and the second end of the fourth MOS tube is connected to the first end of the fifth MOS tube;

[0109] The gate of the fifth MOS tube is connected to the CK1 circuit;

[0110] The second end of the sixth MOS tube is respectively connected to the first end of the seventh MOS tube, the gate of the ninth MOS tube, and the first end of the second capacitor, and the gate of the sixth MOS tube is connected to the CK1 line;

[0111] The gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube;

[0112] The second end of the eighth MOS tube is connected to the VGH line;

[0113] The first end of the ninth MOS tube is connected to the CK3 line, and the second end of the ninth MOS tube is respectively connected to the second end of the second capacitor, the first end of the tenth MOS tube, and the output line;

[0114] The second end of the tenth MOS tube is connected to the VGL line;

[0115] The second end of the first capacitor is connected to the CK1 line.

[0116] The LTPO type shift register circuit provided in the embodiment of the present application can also be as follows Figure 6 As shown, where:

[0117] The first end of the first MOS transistor is connected to the STV line, the second end of the first MOS transistor is respectively connected to the second end of the third MOS transistor, the gate of the eighth MOS transistor, the gate of the tenth MOS transistor, and the first end of the first capacitor, and the gate of the first MOS transistor is connected to the CK2 line;

[0118] The first end of the second MOS tube is connected to the VGL line, the second end of the second MOS tube is respectively connected to the gate of the fourth MOS tube, the first end of the fifth MOS tube, and the first end of the sixth MOS tube, and the gate of the second MOS tube is connected to the STV line;

[0119] The first end of the third MOS tube is connected to the second end of the fourth MOS tube and the gate of the fifth MOS tube respectively, and the gate of the third MOS tube is connected to the CK1 line;

[0120] The first end of the fourth MOS tube is connected to the VGH circuit;

[0121] The second end of the fifth MOS tube is connected to the VGH line;

[0122] The second end of the sixth MOS tube is respectively connected to the first end of the seventh MOS tube, the gate of the ninth MOS tube, and the first end of the second capacitor, and the gate of the sixth MOS tube is connected to the CK1 line;

[0123] The gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube;

[0124] The second end of the eighth MOS tube is connected to the VGH line;

[0125] The first end of the ninth MOS tube is connected to the CK3 line, and the second end of the ninth MOS tube is respectively connected to the second end of the second capacitor, the first end of the tenth MOS tube, and the output line;

[0126] The second end of the tenth MOS tube is connected to the VGL line;

[0127] The second end of the first capacitor is connected to the CK1 line.

[0128] The LTPO type shift register circuit provided in the embodiment of the present application can also be as follows Figure 7 As shown, where:

[0129] The first end of the first MOS transistor is connected to the STV line, the second end of the first MOS transistor is respectively connected to the gate of the second MOS transistor, the second end of the third MOS transistor, the gate of the eighth MOS transistor, the gate of the tenth MOS transistor, and the first end of the first capacitor, and the gate of the first MOS transistor is connected to the CK2 line;

[0130] The first end of the second MOS tube is connected to the VGL line, and the second end of the second MOS tube is respectively connected to the gate of the fourth MOS tube, the first end of the fifth MOS tube, and the first end of the sixth MOS tube;

[0131] The first end of the third MOS tube is connected to the second end of the fourth MOS tube and the gate of the fifth MOS tube respectively, and the gate of the third MOS tube is connected to the CK1 line;

[0132] The first end of the fourth MOS tube is connected to the VGH circuit;

[0133] The second end of the fifth MOS tube is connected to the VGH line;

[0134] The second end of the sixth MOS tube is respectively connected to the first end of the seventh MOS tube, the gate of the ninth MOS tube, and the first end of the second capacitor, and the gate of the sixth MOS tube is connected to the CK1 line;

[0135] The gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube;

[0136] The second end of the eighth MOS tube is connected to the VGH line;

[0137] The first end of the ninth MOS tube is connected to the CK3 line, and the second end of the ninth MOS tube is respectively connected to the second end of the second capacitor, the first end of the tenth MOS tube, and the output line;

[0138] The second end of the tenth MOS tube is connected to the VGL line;

[0139] The second end of the first capacitor is connected to the CK1 line.

[0140] Among them, for any MOS tube in the LTPO type shift register circuit of the present application, the first end of the MOS tube is a source or a drain, and the second end of the MOS tube is a drain or a source corresponding to the first end.

[0141] With respect to any of the LTPO type shift register circuits described in the above embodiments, an embodiment of the present application further provides a driving method of the LTPO type shift register circuit, comprising:

[0142] T1 cycle: STV line inputs low voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs high voltage, CK4 line inputs high voltage;

[0143] T2 period: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs low voltage;

[0144] T3 cycle: STV line inputs high voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs high voltage, CK4 line inputs high voltage;

[0145] T4 cycle: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs high voltage;

[0146] T5 cycle: STV line inputs low voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs low voltage, CK4 line inputs high voltage;

[0147] T6 cycle: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs low voltage;

[0148] T7 cycle: STV line inputs low voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs high voltage, and CK4 line inputs high voltage.

[0149] In an example, the driving timing diagram of the LTPO type shift register circuit can be as follows: Figure 8 shown.

[0150] In the T1 timing cycle, STV and CK2 are low voltage signals, the T1 tube is turned on, the STV low voltage signal charges the capacitor C1, the N4 point is a low voltage signal, the T3 and T8 tubes are turned on, because the T10 tube has a threshold voltage Vth, the T10 tube is not fully turned on, the T2 tube is turned off, the N1 point is the VGH high voltage signal, the T4 tube is turned off, CK1 is a high voltage signal, the T5, T6 and T7 tubes are turned off, and because the capacitor C2 has the function of maintaining voltage stability, the N2 point maintains the VGH high voltage signal of the previous stage, the T9 tube is turned off, and the output result of the N3 point is L (indicating low voltage).

[0151] In the T2 timing cycle, STV is a low voltage signal, CK2 is a high voltage signal, and the T1 tube is turned off. Since the CK1 voltage signal jumps from a high voltage to a low voltage, the capacitor C1 produces a bootstrap effect, further pulling the N4 point down. The N4 point is a low voltage signal, the T10 tube is fully turned on, the T3 and T8 tubes are turned on, the T2 tube is turned off, the N1 point is a VGH high voltage signal, the T4 tube is turned off, the CK1 is a low voltage signal, the T5, T6 and T7 tubes are turned on, the VGH high voltage charges the capacitor C2, the N2 point is a VGH high voltage signal, the T9 tube is turned off, and the output result of the N3 point is L.

[0152] In the T3 timing cycle, STV is a high voltage signal, CK2 is a low voltage signal, T1 tube is turned on, STV high voltage signal charges capacitor C1, N4 point is a high voltage signal, T3, T8 and T10 tubes are turned off, T2 tube is turned on, N1 point is VGL low voltage signal, T4 tube is turned on, CK1 is a high voltage signal, T5, T6 and T7 tubes are turned off. Since capacitor C2 has the function of maintaining voltage stability, N2 point maintains the VGH high voltage signal of the previous stage, T9 tube is turned off, and N3 point repeats the output result of the previous stage as L.

[0153] In the T4 timing cycle, STV is a low voltage signal, CK2 is a high voltage signal, and the T1 tube is turned off. Since the capacitor C1 has the function of maintaining voltage stability, the N4 point maintains the high voltage signal of the previous stage, the T3, T8 and T10 tubes are turned off, the T2 tube is turned on, the N1 point is the VGL low voltage signal, the T4 tube is turned on, CK1 is a low voltage signal, the T5, T6 and T7 tubes are turned on, the VGH high voltage signal charges the capacitor C1, and the N4 point is a high voltage signal; the VGL low voltage signal charges the capacitor C2, the N2 point is a low voltage signal, the T9 tube is turned on, CK3 is a high voltage signal, and the output result of the N3 point is H (indicating high voltage).

[0154] In the T5 timing cycle, STV and CK2 are low voltage signals, the T1 tube is turned on, the STV low voltage signal charges the capacitor C1, the N4 point is a low voltage signal, the T3, T8 and T10 tubes are turned on, the T2 tube is turned off, the N1 point is the VGH high voltage signal, the T4 tube is turned off, CK1 is a high voltage signal, the T5, T6 and T7 tubes are turned off, and since the CK3 voltage signal jumps from a high voltage to a low voltage, the capacitor C2 produces a bootstrap effect, further pulling the N2 point down, the N2 point is a low voltage signal, the T9 tube is fully turned on, and the output result of the N3 point is L.

[0155] In the T6 timing cycle, STV is a low voltage signal, CK2 is a high voltage signal, and the T1 tube is turned off. Since the CK1 voltage signal jumps from a high voltage to a low voltage, the capacitor C1 produces a bootstrap effect, further pulling the N4 point down. The N4 point is a low voltage signal, the T10 tube is fully turned on, the T3 and T8 tubes are turned on, the T2 tube is turned off, the N1 point maintains the VGH high voltage signal, the T4 tube is turned off, CK1 is a low voltage signal, the T5, T6 and T7 tubes are turned on, the VGH high voltage charges the capacitor C2, the N2 point is a VGH high voltage signal, the T9 tube is turned off, and the output result of the N3 point is L.

[0156] In the T7 timing cycle, STV and CK2 are low voltage signals, the T1 tube is turned on, the STV low voltage signal charges the capacitor C1, the N4 point is a low voltage signal, the T3, T8 and T10 tubes are turned on, the T2 tube is turned off, the N1 point is the VGH high voltage signal, the T4 tube is turned off, CK1 is a high voltage signal, the T5, T6 and T7 tubes are turned off, and since the capacitor C2 has the function of maintaining voltage stability, the N2 point maintains the VGH high voltage signal of the previous stage, the T9 tube is turned off, and the output result of the N3 point is L.

[0157] In the embodiment of the present application, through the CMOS process, a combination of N-type MOS tubes and P-type MOS tubes is adopted to reduce the number of MOS tubes while ensuring normal light emission of sub-pixels, reducing the loss of voltage signals passing through the MOS tubes, and reducing abnormal displays, thereby reducing the width of the LTPO-type shift register circuit and reducing the screen border.

[0158] The embodiment of the present application also provides a display panel, including the LTPO type shift register circuit described in any of the above embodiments. Other parts of the display panel can refer to the display panel in the related art, and are not specifically limited in the present application.

[0159] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk SolidState Disk (SSD)), etc.

[0160] It should be noted that, in this article, the technical features in each optional solution can be combined to form a solution as long as there is no contradiction, and these solutions are all within the scope disclosed in this application. Relational terms such as first and second, etc. are only used to distinguish an entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements that are not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0161] Each embodiment in the specification is described in a related manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other.

[0162] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. An LTPO type shift register circuit, characterized in that: include: A first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a ninth MOS tube, and a tenth MOS tube; Wherein, the second MOS tube is an N-type MOS tube, and the first MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, and the ninth MOS tube are all P-type MOS tubes; the gates of the second MOS tube, the third MOS tube, and the tenth MOS tube are connected to the N4 point; The first end of the first MOS tube is connected to the STV line, the second end of the first MOS tube is respectively connected to the gate of the second MOS tube and the gate of the third MOS tube, and the gate of the first MOS tube is connected to the CK2 line; the first end of the second MOS tube is connected to the VGL line, the second end of the second MOS tube is respectively connected to the first end of the third MOS tube and the gate of the fourth MOS tube; the second end of the third MOS tube is connected to the VGH line; The first end of the fourth MOS tube is connected to the VGH line, the second end of the fourth MOS tube is connected to the first end of the fifth MOS tube; the gate of the fifth MOS tube is connected to the CK1 line; The ninth MOS tube is used to output a high level or low level signal, and the second end of the ninth MOS tube is connected to the output line; the tenth MOS tube is used to output a low level signal, and the second end of the tenth MOS tube is connected to the VGL line.

2. The circuit according to claim 1, characterized in that In the output signal of the LTPO type shift register circuit, the duration of the high potential signal is shorter than the duration of the low potential signal.

3. The circuit according to claim 1, characterized in that The circuit further comprises: An eleventh MOS tube, wherein the eleventh MOS tube is arranged at one end of the first MOS tube and the fifth MOS tube.

4. The circuit according to claim 3, characterized in that The eleventh MOS tube is an N-type MOS tube, and the gate of the eleventh MOS tube is connected to the VGH circuit; Or the eleventh MOS tube is a P-type MOS tube.

5. The circuit according to claim 4, characterized in that The circuit further includes a first capacitor, the eleventh MOS tube is connected to the first capacitor, and the first capacitor is configured to stabilize the potential of point N4.

6. The circuit according to claim 1, characterized in that The circuit also includes a sixth MOS tube, a seventh MOS tube, and an eighth MOS tube; The sixth MOS tube, the seventh MOS tube, and the eighth MOS tube are all P-type MOS tubes; The second end of the sixth MOS tube is connected to the first end of the seventh MOS tube and the gate of the ninth MOS tube respectively; The gate of the sixth MOS tube is connected to the CK1 circuit; The gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube; The second end of the eighth MOS tube is connected to the VGH line.

7. The circuit according to claim 1, characterized in that The circuit also includes a second capacitor; a first end of the second capacitor is connected to the gate of the ninth MOS tube, and a second end of the second capacitor is connected to the second end of the ninth MOS tube.

8. An LTPO type shift register circuit, characterized in that: include: A first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, and a tenth MOS tube; Wherein, the second MOS tube is an N-type MOS tube, and the first MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, and the tenth MOS tube are all P-type MOS tubes; the gates of the eighth MOS tube and the tenth MOS tube are connected to the N4 point; the gate of the fifth MOS tube is connected between the third MOS tube and the fourth MOS tube; The first end of the first MOS tube is connected to the STV line, the second end of the first MOS tube is connected to the gate of the eighth MOS tube, and the gate of the first MOS tube is connected to the CK2 line; the first end of the second MOS tube is connected to the VGL line, and the second end of the second MOS tube is connected to the gate of the fourth MOS tube; the first end of the third MOS tube is respectively connected to the second end of the fourth MOS tube and the gate of the fifth MOS tube, and the gate of the third MOS tube is connected to the CK1 line; the first end of the fourth MOS tube is connected to the VGH line; The second end of the fifth MOS tube is connected to the VGH line; the second end of the sixth MOS tube is connected to the first end of the seventh MOS tube; the gate of the seventh MOS tube is connected to the CK1 line, and the second end of the seventh MOS tube is connected to the first end of the eighth MOS tube; the second end of the eighth MOS tube is connected to the VGH line; the ninth MOS tube is used to output a high level or a low level signal, and the second end of the ninth MOS tube is connected to the output line; the second end of the tenth MOS tube is connected to the VGL line.

9. The circuit according to claim 8, characterized in that The gate of the second MOS tube is connected to the STV line or the N4 point.

10. A display panel, characterized in that: It comprises an LTPO type shift register circuit as described in any one of claims 1-9.

11. A driving method of an LTPO type shift register circuit, characterized in that: Applied to the LTPO type shift register circuit as claimed in any one of claims 1 to 9, the method comprising: T1 cycle: STV line inputs the start signal, CK1 line inputs a high voltage, CK2 line inputs a low voltage, CK3 line inputs a high voltage, and CK4 line inputs a high voltage; T2 period: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs low voltage; T3 cycle: STV line inputs high voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs high voltage, CK4 line inputs high voltage; T4 cycle: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs high voltage; T5 cycle: STV line inputs low voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs low voltage, CK4 line inputs high voltage; T6 cycle: STV line inputs low voltage, CK1 line inputs low voltage, CK2 line inputs high voltage, CK3 line inputs high voltage, CK4 line inputs low voltage; T7 cycle: STV line inputs low voltage, CK1 line inputs high voltage, CK2 line inputs low voltage, CK3 line inputs high voltage, and CK4 line inputs high voltage.

Images