Systems and methods for updating memory circuits

Abstract

This disclosure relates to systems and methods for updating memory circuitry. The invention discloses an electronic system, such as an imaging system, that may include processing circuitry and memory circuitry. The memory circuitry may include a one-time programmable memory with error correction code functionality (e.g., SECDED functionality). The one-time programmable memory may have a first set of previously programmed bits and a second set of unprogrammed and unused bits. The processing circuitry may process instructions to update bits in the second set of bits. To preserve ECC functionality (e.g., ECC check bits associated with the first and second sets of bits), the processing circuitry may also update additional bits in the second set of bits.

Description

Technical Field

[0001] The present invention relates generally to memory circuits in electronic systems such as imaging systems, and more specifically to systems and methods for updating data stored in memory circuits (sometimes referred to herein as memory). Background Technology

[0002] Modern electronic devices such as cell phones, cameras, computers, and other electronic system modules (e.g., those integrated into automotive systems) require various types of memory circuitry. To robustly store data in these memory circuits, these systems typically include memory with error correction codes (ECC) or ECC memory. For example, various types of memory circuitry may include one-time programmable memory (OTPM) storing ECC check bits, which are used to detect and / or correct bit errors in the stored data based on ECC values ​​generated from the ECC check bits.

[0003] However, because each bit location of a one-time programmable memory (OTC) is designed to be written once (e.g., during manufacturing), it can be difficult to modify the data on the OTC in the desired manner during the memory's lifetime (e.g., to store additional data). Furthermore, memories such as OTC may store ECC check bits (e.g., OTC with ECC functionality). The ECC value should not change during later data modifications to preserve error checking and / or error correction capabilities. This further limits the modification of these types of memory circuitry.

[0004] Therefore, it is desirable to provide systems and methods for overcoming these problems by updating data on memory circuits (such as one-time programmable memory and / or ECC memory) in a flexible manner. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of an exemplary system having memory circuitry in an imaging system and additional memory circuitry in a host subsystem, according to some embodiments.

[0006] Figure 2 This is a schematic diagram of an exemplary imaging circuit according to some embodiments, which includes memory circuitry and is configured to generate image signals in an image sensor.

[0007] Figure 3 This is a schematic diagram of an exemplary portion of a memory circuit that can be used in an imaging system, host subsystem, imaging circuit, and / or any other type of system or device, according to some embodiments.

[0008] Figure 4 According to some implementation plans Figure 3 The diagram shows an exemplary portion of a memory circuit having data modified in a manner that preserves the ECC value.

[0009] Figure 5 To identify a set of exemplary updatable bit positions according to some implementation schemes in Figure 1-4 An exemplary table for storing ECC values ​​in a memory circuit of the type shown.

[0010] Figure 6 This is an exemplary flowchart for updating memory while retaining ECC values, according to some implementation schemes.

[0011] Figure 7 This is a table showing the exemplary incremental states of stored data and parity bits, and their associated exemplary interpretations, according to some implementation schemes. Detailed Implementation

[0012] Embodiments of the present invention relate to memory circuitry and processing circuitry (e.g., memory controller (or interface) circuitry) for accessing and modifying data stored in memory circuitry. Those skilled in the art will understand that exemplary embodiments of the present invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

[0013] The memory and processing circuits described herein can typically be implemented in multiple hardware systems. For example, the memory and processing circuits described herein can be implemented as part of any electronic device such as a portable electronic device, camera, tablet computer, desktop computer, webcam, mobile phone, video camera, video surveillance system, automotive imaging system, video game system, or any other electronic device or system that may or may not have imaging capabilities. Exemplary configurations of memory circuits and corresponding processing circuits formed as part of an imaging system or an electronic system including imaging capabilities are described in detail herein as examples. However, this is merely illustrative. If desired, the memory circuits and corresponding processing circuits can be implemented in any of the aforementioned systems or in other suitable systems.

[0014] Figure 1 This is a schematic diagram of an exemplary imaging and response system, which includes an imaging system that captures images using an image sensor. Figure 1 System 100 may be an electronic device, such as a camera, cellular phone, video camera, or other electronic device that captures digital image data; it may be a vehicle safety system (e.g., an active braking system or other vehicle safety system) or other automotive system; it may be a surveillance system; or it may be any other system with imaging capabilities.

[0015] like Figure 1 As shown, system 100 may include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). Imaging system 10 may include camera module 12. Camera module 12 may include one or more image sensors 14 having one or more corresponding lenses.

[0016] Each image sensor in camera module 12 may be identical, or different types of image sensors may be present in a given image sensor array integrated circuit. During image capture operation, each corresponding lens can focus light onto the associated image sensor 14 (such as...). Figure 2 The image sensor 12 shown is used. The image sensor 14 may include photosensitive elements (i.e., pixels) that convert light into digital data. The image sensor may have any number (e.g., hundreds, thousands, millions or more) of pixels. A typical image sensor may, for example, have millions of pixels (e.g., several megapixels). For example, the image sensor 14 may include bias circuitry (e.g., source follower load circuitry), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter circuitry, data output circuitry, memory (e.g., buffer circuitry), addressing circuitry, etc.

[0017] In one arrangement (sometimes referred to as a system-on-a-chip (SoC) arrangement), the image sensor 14 and the image processing and data formatting circuitry 16 can be implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, the image sensor 14 and the image processing circuitry 16 can be formed on separate semiconductor substrates. For example, the image sensor 14 and the image processing circuitry 16 can be formed on separate, stacked substrates.

[0018] Still and / or video image data from image sensor 14 can be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 can be used to perform image processing functions (e.g., processing software instructions), such as data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, object detection, etc. Image processing and data formatting circuitry 16 can also be used to compress raw camera image files as needed (e.g., compressing to Joint Image Experts Group format, or JPEG for short). In some configurations, image processing and data formatting circuitry 16 may include memory circuitry 15 (e.g., for storing software instructions, processing parameters or variables, image data, etc.) used (or accessed) in the processing functions of processing circuitry 16. Memory circuitry 15 may include volatile and non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid-state drive, OTP memory, ECC memory, etc.) or any suitable non-transitory computer-readable medium. Processing circuitry 16 may also include a microprocessor, microcontroller, digital signal processor, application-specific integrated circuit, etc., and may include memory controller or memory interface circuitry for controlling and accessing memory 15. Although memory 15 is shown within processing circuitry 16, this is merely exemplary. Embodiments herein may refer to memory 15 and processing circuitry 16 as functionally distinct but used separately.

[0019] Imaging system 10 (e.g., image processing and data formatting circuitry 16 in imaging system 10) can transmit acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include processing circuitry (e.g., processing circuitry 24) for processing software instructions for detecting objects in images, software instructions for detecting motion of objects between image frames, software instructions for determining distances to objects in images, software instructions for filtering or otherwise processing images provided by imaging system 10, and / or other software instructions.

[0020] If needed, system 100 can provide users with a number of advanced functions. For example, in a computer, cellular phone, or automotive system, it can provide the user with the ability to run user applications. To achieve these functions, the host subsystem 20 of system 100 may have input-output devices 22 (such as keypads, input-output ports, joysticks, and displays) in addition to storage and processing circuitry 24. Storage and processing circuitry 24 may include memory circuitry 23 (e.g., for storing software instructions, processing parameters or variables, image data, etc.) used (or accessed) in the processing functions of processing circuitry 24. Memory circuitry 23 may include volatile and non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid-state drive, OTP memory, ECC memory, etc.) or any suitable non-transitory computer-readable medium. Storage and processing circuitry 24 may also include microprocessors, microcontrollers, digital signal processors, application-specific integrated circuits, etc., and may include memory controllers or memory interface circuitry for controlling and accessing memory 23. Although memory 23 is shown as being within processing circuitry 24, this is merely exemplary. The implementation described herein may refer to the memory 23 and the processing circuitry 24 as separate circuits that are functionally different but used together.

[0021] Figure 2 It shows Figure 1 An example of the arrangement structure of camera module 12. For example... Figure 2 As shown, the camera module 12 includes an image sensor 14 and control and processing circuitry 44. The control and processing circuitry 44 can be implemented as follows: Figure 1 Part of the image processing and data formatting circuitry 16, which can be used with Figure 1 The image processing and data formatting circuitry 16 in the image processing circuitry is the same as, or may include, the data processing and data formatting circuitry 16 in the image processing circuitry 16. Figure 1 The image processing and data formatting circuit 16 is included. If needed, the processing circuit 44 can be connected to... Figure 1 The image processing and data formatting circuitry 16 is separate from and distinct from this. Specifically, the control and processing circuitry 44 may include memory 43. Memory 43 may be used (or accessed) in the processing functions of the processing circuitry 44 (e.g., to store software instructions, processing parameters or variables, image data, etc.). Memory circuitry 43 may include volatile and non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid-state drive, OTP memory, ECC memory, etc.) or any suitable non-transitory computer-readable medium. Although memory 43 is shown as being within processing circuitry 44, this is merely exemplary. Embodiments herein may refer to memory 43 and processing circuitry 44 as functionally distinct but used separately.

[0022] Image sensor 14 may include a pixel array, such as an array 32 of pixels 34 (sometimes referred to herein as image sensor pixels, imaging pixels, or image pixels 34), and may also include row control circuitry 40 and column control and readout circuitry 42. Control and processing circuitry 44 may be coupled to row control circuitry 40 via path 46 and to column control and readout circuitry 42 via path 26. Row control circuitry 40 may receive row addresses from control and processing circuitry 44 and may supply corresponding row control signals (e.g., dual-conversion gain control signals, pixel reset control signals, charge transfer control signals, halo control signals, row selection control signals, or any other desired pixel control signals) to image pixels 34 via control path 36. Control path 36 may also be referred to as row line 36, control line 36, row control signal line, etc.

[0023] Column control and readout circuitry 42 may be coupled to columns of pixel array 32 via one or more wires (such as column lines 38). Column lines 38 may be coupled to each column of image pixels 34 in image pixel array 32 (e.g., each column of pixels may be coupled to a corresponding column line 38). Column lines 38 may be used to read image signals from image pixels 34 and to supply bias signals (e.g., bias current or bias voltage) to image pixels 34. During image pixel readout operation, row control circuitry 40 may be used to select a pixel row in image pixel array 32, and image data associated with the image pixels 34 of that pixel row may be read out by column control and readout circuitry 42 on column lines 38.

[0024] The column control and readout circuit 42 may include column circuitry, such as a column amplifier for amplifying the signal read from array 32, a sample-and-hold circuit for sampling and storing the signal read from array 32, an analog-to-digital converter circuit for converting the read analog signal into a corresponding digital signal, and a column memory for storing the read signal and any other desired data. The column control and readout circuit 42 can output digital pixel values ​​to the control and processing circuit 44 via line 26.

[0025] Array 32 may have any number of rows and columns. Generally speaking, the size of array 32 and the number of rows and columns in array 32 will depend on the specific implementation of image sensor 14. Although rows and columns are generally described herein as horizontal and vertical respectively, rows and columns may refer to any grid-like structure (e.g., features described herein as rows may be arranged vertically, and features described herein as columns may be arranged horizontally).

[0026] Pixel array 32 may be configured with a color filter array having multiple color filter elements, allowing a single image sensor to sample different colors of light. For example, image sensor pixels such as the image pixels in array 32 may be configured with a color filter array that allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels arranged in a Bayer mosaic pattern. The Bayer mosaic pattern consists of repeating cells of 2×2 image pixels, where two green image pixels are diagonally opposite each other and adjacent to a red image pixel diagonally opposite a blue image pixel. In another suitable example, the green pixels in the Bayer pattern are replaced with broadband image pixels having broadband color filter elements (e.g., transparent color filter elements, yellow color filter elements, etc.). These examples are merely exemplary, and in general, color filter elements of any desired color and any desired pattern can be formed over any desired number of image pixels 34.

[0027] Such as combination Figure 1 and Figure 2 As shown, the system is such as Figure 1 System 100 may include one or more sets of memory circuits (e.g., Figure 1 The memory circuits 15 and 23 in the memory circuit and Figure 2 The memory circuits 43 in the document may include one or more memory circuits that can be one-time programmable (OTP) circuits and / or ECC memory circuits. For example, one of the memory circuits 15, 23, and 43 may include an OTP memory with ECC functionality (e.g., ECC protected). Specifically, an ECC protected OTP memory may include separate and distinct stored data bits and ECC parity bits (sometimes referred to herein as parity bits). The stored data bits may be one-time programmable (e.g., each data bit may be programmable or toggled from a default bit value once during the lifetime of the memory). The ECC parity bits may be used to detect and correct single errors in the stored data bits, and may be used to detect but not correct two-bit errors in the stored data bits (i.e., with single error correction, double error detection, or SECDED functionality). These types of ECC protected OTP memories are described herein as examples. However, the embodiments described herein may be implemented with ECC memory, OTP memory, or other types of memory if desired.

[0028] In some types of memory (e.g., memory with OTP and / or ECC functionality), updating and modifying data stored in memory (e.g., non-ECC data) can be difficult. For example, in some applications, it may be desirable to update data bits in memory after their initial programming. However, the one-time programmable nature of memory can limit the bits that can be updated, and more importantly, the ECC value generated based on the ECC check bit may change during such updates. A changed ECC value can lead to the loss of satisfactory ECC functionality, which may be critical in some applications.

[0029] To maintain the effectiveness of the ECC function, the memory circuit and the corresponding processing circuit (e.g., the memory controller circuit in the processing circuit) can be implemented according to the implementation scheme described herein. Figure 3 This is a schematic diagram of an exemplary portion of memory 60 (e.g., implemented as...). Figure 1 Part of the memory 15 is implemented as Figure 1 Part of the memory 23 is implemented as Figure 2 (or may be part of the memory 43 in the system, or implemented as part of any other suitable system).

[0030] The memory 60 may include data stored at a first set of bit positions 62 (such as bit positions 0 to 15), and may include corresponding ECC check bits (sometimes referred to herein as parity bits) stored at a second set of bit positions 64 (such as bit positions p0, p1, p2, p3, p4, and p5). In other words, in Figure 3 In an exemplary example, this portion of memory 60 may include 16 bits of data and 6 bits of ECC check bits, each bit storing a binary 1 or 0. Memory 60 may include bit portions of additional groups (e.g., it may include 16-bit words of additional groups, each group associated with an additional 6 bits of ECC check bits). For example, memory 60 may include an OTPM having a size of approximately several kilobytes (e.g., one or two kilobytes), a size of less than one kilobyte, a size of less than one megabyte, or any other suitable size. As an example described herein, memory 60 may be a one-time programmable memory with ECC functionality (i.e., memory including ECC check bits). This is merely illustrative. If desired, memory 60 may be or include one or more suitable types of memory.

[0031] like Figure 3As shown, the data stored at bit positions 62 in the first group can be associated with different field names (sometimes referred to herein as different fields). For example, the data stored at bit positions 0 through 6 can store data associated with the field name VAR (e.g., a 7-bit word, or one or more binary values). Similarly, the data stored at bit position 7 can store data associated with the field name A (e.g., a binary bit value). Again, the data stored at bit positions 8 through 14 can store data associated with reserved field names. And again, the data stored at bit position 15 can store data associated with the field name B. If needed, one or more bits in this group of bit positions 62 can be unused or unprogrammed spare bits (e.g., at default bit values).

[0032] Processing circuitry (e.g., memory controller (or interface) circuitry) can access one or more of these values ​​associated with each field (e.g., bits associated with a given field name) to perform processing functions (e.g., using...). Figure 1 Processing circuit 16 or processing circuit 24 in the middle, using Figure 2 (e.g., processing circuit 44 in the memory). For example, one or more memory bits in the memory can be used to perform arithmetic calculations, perform comparison operations, provide control signals to the circuit, perform cryptographic functions, etc.

[0033] Additionally, memory 60 may include ECC check bits corresponding to the data bits in bit position 62. Specifically, a change in one or more bits stored at bit positions 0 to 15 can result in a change in one or more bits stored at bit positions p0, p1, p2, p3, p4, and p5. The ECC check bits can be used to generate an ECC value (i.e., Figure 3 The ECC check bit and ECC value can be used to determine whether one or more errors have occurred in the data bits stored at position 62 of the first set of bit positions (e.g., whether one bit in position 62 of the first set of bit positions has changed, whether two bits in position 62 of the first set of bit positions have changed, etc.) and whether one or more errors have occurred in the bits stored at position 64 of the second set of bit positions (e.g., whether one bit in position 64 of the second set of bit positions has changed, whether two bits in position 64 of the second set of bit positions have changed). For example, the ECC circuit can receive the corresponding bits at bit positions p0 to p5 (or ECC value X) as input. Based on the ECC bit or value, the ECC circuit can determine that a unit error has occurred and can correct the unit error (e.g., by toggling the error bit, i.e., a binary value from 0 to 1 or a binary value from 1 to 0). The corresponding bits stored at bit positions p0 to p5 are not in Figure 3 This is explicitly shown to avoid unnecessarily obscuring the implementation scheme described herein. Instead, the collective ECC value X is shown.

[0034] During the lifetime of memory 60, it may be desirable to use memory controllers and / or processing circuitry to change... Figure 3 The stored value at one or more bit locations in a portion of the memory 60 shown. Figure 3 In an exemplary example, it might be desirable to use a memory controller and / or processing circuitry to update bit 68-1 (i.e., for field B) stored at bit location 15 from its default value and unused value of 0 to a new value of 1. However, even if no error occurs and the update of bit 68-1 is intentional, doing so would unintentionally change the ECC value X.

[0035] To overcome these problems, the memory controller and / or processing circuitry can update (e.g., process software instructions to update) bit 68-1 and the additional bits at the additional bit locations. By updating the target bit 68-1 along with these specific additional bits, the ECC value can be preserved, and the desired update of the memory can be achieved. Figure 3 In the example, memory 60 includes one or more bits 66 that can be pre-programmed with a set of desired binary values ​​(each labeled "?"). Although each bit is labeled "?", this indicates that these bits were previously programmed to remain available. The value of each bit in bit 66 can be different from each other (e.g., "?" can represent 0 or 1). Bits 68-1 and 68-2 can be kept as spare or additional (unused) bits that can be used for reprogramming at a time different from the initial programming of bit 66.

[0036] Although the processing software instruction updates bit 68-1 from value 0 to value 1, the processing circuitry and / or memory controller can also process software instructions that also update all three bits 68-2 from value 0 to value 1. Figure 3 These updates to the memory 60 shown can lead to Figure 4 The state of memory 60 is shown. Although a total of four bits can be updated in this process, the bit value stored only at bit position 15 (e.g., the value associated with field name B) can subsequently be accessed and / or used by processing circuitry for subsequent processing functions (e.g., performing arithmetic calculations, performing comparison operations, providing control signals to circuitry, performing cryptographic functions, etc.). Only the other three bit values ​​stored at bit positions 12 through 14 can be changed to resolve ECC value consistency issues (e.g., maintaining the same ECC value before and after updating bit 68-1).

[0037] like Figure 4 As shown, although the state of this portion of memory 60 has changed, the ECC value associated with this portion of memory 60 remains the same. Figure 3The state of that portion of the memory 60 shown remains the same (e.g., remains at value X). Thus, one or more portions of the memory 60 can be updated without changing the corresponding ECC value associated with the corresponding portion of the memory 60 (e.g., implemented as OTPM).

[0038] Update bits at positions 12 to 15 and access bit at position 15 for use in Figure 3 and Figure 4 The examples of subsequent use are merely illustrative. Any of the four update bits can be accessed for subsequent use if needed. Other (unused and / or spare) bits at other bit locations can be updated to reprogram previously unprogrammed or unused portions of the memory if required. For example, if bits at bit locations 9, 10, 14, and 15 are... Figure 3 If the same type of memory shown is unused (e.g., previously unprogrammed, storing default values ​​of 0 or 1), then the bits at bit positions 9, 10, 14, and 15 can be simultaneously flipped to preserve the ECC value while updating memory 60. At least one (e.g., only one) of the bits stored at bit positions 9, 10, 14, and 15 is used for subsequent processing, while the remaining bits may be used solely for ECC value consistency reasons. Similarly, additional four-bit groups at various corresponding bit positions can be updated (e.g., simultaneously flipped) to preserve the ECC value. Specifically, in the example of a 16-bit word, there may be 64 such 4-bit combinations that preserve the ECC value when simultaneously flipped (e.g., from all 0s to all 1s or from all 1s to all 0s).

[0039] Figure 5 An exemplary table (e.g., Table 70) is shown that identifies exemplary 4-bit combinations and corresponding characteristics associated with the identified 4-bit combinations (and other 4-bit combinations). When flipped, the table retains the ECC value (e.g., to combine...). Figure 3 and Figure 4 (As shown). Specifically, Table 70 shows the encoded data bits, including parity bits p1', p2', p4', p8', and p16' (corresponding to...). Figure 3 and Figure 4 Five of the six ECC check bits at positions p0, p1, p2, p3, p4, and p5 (e.g., the ECC check bits at positions p1, p2, p3, p4, and p5) are scattered between data bits d1 and d16 (corresponding to...). Figure 3 and Figure 4 The data bits shown are the sixteen data bits located at positions 0 to 15.

[0040] The rows covered by the parity bits show how each parity bit changes based on variations in the encoded data bits. For example, if d1 is flipped (e.g., by a soft error), then both p1' and p2' bits can be flipped (as indicated by the "X" in the rows covered by the parity bits corresponding to p1' and p2'). In other words, an error in d1 can be detected when both p1' and p2' bits are flipped. Similarly, if d14 is flipped, then p1', p2', and p16' bits can all be flipped. Naturally, when only p1' bit is flipped, this identifies that an error has occurred in p1' bit itself. In a similar manner, individual errors in every bit of the entire encoded data bit set, including both parity bits and data bits, can be identified. Because specific error bits can be located, individual errors can also be corrected (e.g., by flipping the identified error bit).

[0041] Based on how the parity bit changes as identified in Table 70, a quadruplet (e.g., four consecutive or non-consecutive bits) can be identified that does not change any parity bit when flipped simultaneously. Section 72 of Table 70 identifies such a quadruplet (e.g., data bits d8, d9, d10, and d11). Since parity bit p1' is flipped twice (because changes to bits d9 and d11 both cause parity bit p1' to be flipped), the value of parity bit p1' remains unchanged when bits d8, d9, d10, and d11 are flipped simultaneously. By similar reasoning, parity bit p2' can be similarly preserved when bits d8, d9, d10, and d11 are flipped simultaneously. Since parity bit p4' is flipped four times (because changes to bits d8, d9, d10, and d11 all cause parity bit p1' to be flipped), the value of parity bit p4' remains unchanged when bits d8, d9, d10, and d11 are flipped simultaneously. By similar reasoning, parity bit p8' can be similarly preserved when bits d8, d9, d10, and d11 are flipped simultaneously. Since parity bit p16' is never flipped when bits d8, d9, d10, and d11 are flipped simultaneously, parity bit p16' can also be preserved.

[0042] In other words, 4-bit combinations can be identified based on the following criteria: when the 4-bit combination is flipped, bits p1', p2', p4', p8', and p16' are never flipped or are flipped an even number of times. These 4-bit combinations do not need to be consecutive bits. For example, an exemplary non-consecutive 4-bit combination could be bits d1, d3, d5, and d8.

[0043] Table 70 shows the five parity bits, which correspond to... Figure 3 and Figure 4 The bits at positions p1 to p5 in the table (as an example) are not shown in Table 70. The final parity bit is not shown (e.g., ...). Figure 3 and Figure 4The median bit is located at p0. The final parity bit can be a parity bit used for all bits (e.g., for all 16 data bits and all 5 parity bits). The final parity bit can be used to identify double-bit errors.

[0044] Figure 3-5 The exemplary examples in the document all show 16-bit memory and 5 or 6-bit ECC values. However, these examples are merely illustrative. If desired, memory 60 can be implemented as 8-bit memory, 32-bit memory, 64-bit memory, etc., having any suitable number of bits for ECC functionality. Figure 5 Table 70 in the table can be expanded to show how the parity bit coverage expands when more than 16 bits of data are used.

[0045] Figure 6 This is an exemplary flowchart for updating data while preserving ECC values ​​(e.g., parity bits at each location). Figure 6 One or more portions of the steps in the flowchart may be stored in memory as software instructions (e.g., stored separately from and / or with the OTPM). Figure 3 and Figure 4 The memory is divided into 60 separate memory locations. These software instructions can be processed using processing circuitry (sometimes referred to herein as control circuitry) to execute. Figure 6 One or more of the steps in the flowchart. As an example, the memory and processing circuitry used to store and / or process these instructions may be included. Figure 1 Implemented in the system (e.g., using a portion of memory 15 and processing circuitry 16, or using a portion of memory 23 and processing circuitry 24), or in Figure 2 Implemented in the circuit (e.g., using a portion of memory 43 and processing circuitry 44).

[0046] At step 80, the manufacturer may physically manufacture the memory circuitry (e.g., memory circuitry 60, an OTPM with ECC functionality, etc.). The memory may have a default bit value for each data bit location in the memory (e.g., all data bit locations may store a default bit value of 0, all data bit locations may store a default bit value of 1, etc.). If necessary, during step 80, the processing circuitry may process software instructions (stored on a non-transitory computer-readable medium) that virtually allocate memory (e.g., implement the memory in software using programmable circuitry) rather than physically manufacture the memory.

[0047] At step 82, the processing circuitry may process software instructions (stored in a non-transitory computer-readable medium) to store data in memory at the first set of data bit locations (e.g., bit values ​​of 0 and 1 may be stored at the data bit locations in the first set of data bit locations, the stored bit values ​​corresponding to the stored data). For example, the processing circuitry may process software instructions to store data at bit 66 in... Figure 3 In the memory 60.

[0048] At step 84, the processing circuitry may process software instructions (stored in a non-transitory computer-readable medium) to retain unused portions of the memory at the second set of data bit locations (e.g., to retain bit values ​​at default bit values ​​at data bit locations within the second set of data bit locations). For example, the processing circuitry may process software instructions to... Figure 3 Bits 68-1 and 68-2 in memory 60 remain at their default value of 0.

[0049] At step 86, the processing circuitry may process software instructions (stored in a non-transitory computer-readable medium) to store ECC bits that can be used to generate an ECC value that identifies and / or corrects one or more errors at data bit positions at a set of ECC bit positions (e.g., assigning SECDED functionality). For example, the processing circuitry may process software instructions to store ECC check bits. Figure 3 The bits of memory 60 are located at p0, p1, p2, p3, p4 and p5.

[0050] At step 88, the processing circuitry may process software instructions (stored in a non-transitory computer-readable medium) to store additional data in memory at the second set of data bit locations (e.g., storing bit values ​​of 0 and 1 at the data bit locations in the second set of data bit locations, the stored bit values ​​corresponding to the stored additional data). This storage of the additional data can be done without changing the ECC value (e.g., while retaining the ECC value).

[0051] To perform step 88, the processing circuitry may process software instructions (stored in a non-transitory computer-readable medium) associated with steps 90, 92, and 94. Specifically, at step 90, the processing circuitry may process software instructions (stored in a non-transitory computer-readable medium) to identify a first data bit position in a second set of data bit positions for storing additional data. For example, the processing circuitry may process software instructions to identify... Figure 3 Bit 68-1 of memory 60 is used to store additional data (e.g., flipping bit 68-1 from the default value 0 to the value 1).

[0052] At step 92, the processing circuitry can process software instructions (stored in a non-transitory computer-readable medium) to identify the second, third, and fourth data bit positions in the second set of data bit positions that can be used to reserve the ECC value. For example, the processing circuitry can process software instructions to identify... Figure 3 Bits 68-2 in memory 60 are used to preserve the ECC value (e.g., at least in part by referencing parity bit data, such as...). Figure 5 (Parity check bit coverage table 70).

[0053] At step 94, the processing circuitry may process software instructions (stored in a non-transitory computer-readable medium) to store additional data at the first data bit location, the second data bit location, the third data bit location, and the fourth data bit location to preserve the ECC value. For example, the processing circuitry may process software instructions to toggle... Figure 3 All bits 68-1 and 68-2 in memory 60 are used to store additional data while retaining the ECC value.

[0054] Figure 7 An exemplary table (e.g., Table 110) is shown that identifies the exemplary meanings of data bits, parity bits, and data bits in memory (e.g., OTPM). Specifically, column 112 shows data bits (e.g., 16-bit words) in memory that can be used to provide version data (e.g., in column 116). Column 112 shows the parity bit associated with the data bits for checking for errors in the parity bit.

[0055] Specifically, line 118 can identify the data word and parity bit associated with the version data indicating the initial version. To represent different versions of data using a finite number of data bits, while maintaining the parity bit value at least between some version numbers, a combination of... Figure 1-6 The methods and systems described. For example, line 120 shows data indicating version 1. By toggling four different bits to update the data bits, memory can store data indicating version 2. Similarly, version data such as version 4 (in line 126) and version 5 (in line 128) can be represented by data bits indicating version 3 (in line 124) by updating four bits while retaining the parity bit value.

[0056] According to one embodiment, the system may include memory circuitry storing a first set of data bits and a second set of parity bits for the first set of data bits. The system may also include control circuitry coupled to the memory circuitry and configured to update the first bit by updating the first bit, the second bit, the third bit, and the fourth bit of the second set of data bits. The updated first, second, third, and fourth bits may be configured to retain the second set of parity bits in the memory circuitry during the update process.

[0057] According to another embodiment, the memory circuit may include a one-time programmable memory that stores a first set of data bits and a second set of parity bits.

[0058] According to another implementation, the second set of parity bits can be configured to provide single error correction for the first set of data bits.

[0059] According to another implementation, the second set of parity bits can be configured to provide double error detection for the first set of data bits.

[0060] According to another implementation, each bit of the one-time programmable memory can be programmable only once.

[0061] According to another implementation, the first set of data bits may include a first plurality of programmed bits and a second plurality of programmable bits.

[0062] According to another implementation, each bit in the second plurality of programmable bits may have the same default bit value.

[0063] According to another embodiment, the second plurality of programmable bits may include a first data bit, a second data bit, a third data bit, and a fourth data bit.

[0064] According to another implementation, the control circuit can be configured to update the first bit by simultaneously updating the first, second, third, and fourth bits.

[0065] According to another implementation, the control circuit can be configured to identify the corresponding bit positions of the second, third, and fourth bits based on the bit position of the first bit.

[0066] According to one embodiment, a method for updating a one-time programmable memory with error correction code functionality may include: storing data at a first set of data bit locations in the one-time programmable memory, retaining unused portions of the one-time programmable memory at a second set of data bit locations in the one-time programmable memory, storing error correction code bits at the first set of data bit locations and the second set of data bit locations, and storing additional data at the second set of data bit locations while retaining the error correction code bits.

[0067] According to another embodiment, storing additional data may include storing the additional data at a first data bit position in a second set of data bit positions, and identifying additional data bit positions in the second set of data bit positions to preserve error correction bits.

[0068] According to another embodiment, storing additional data may include storing the additional data at an additional data bit location in a second set of data bit locations.

[0069] According to another embodiment, storing additional data may include storing the additional data simultaneously at a first data bit location and an additional data bit location.

[0070] According to another embodiment, storing additional data simultaneously at the first data bit position and the additional data bit position may include flipping the default bit value at each bit position in the first data bit position and the additional data bit position.

[0071] According to another implementation, each bit in the unused portion of the one-time programmable memory can store the same default bit value.

[0072] According to another implementation, each bit of the one-time programmable memory can be programmable only once.

[0073] According to one embodiment, the imaging system may include an image sensor and a one-time programmable memory with error correction code functionality. The one-time programmable memory can store data at a first set of data bit locations, maintain the same default bit value at each bit location in a second set of data bit locations in the one-time programmable memory, and store parity bits corresponding to the error correction code values ​​at the first and second sets of data bit locations. The imaging system may also include processing circuitry coupled to the image sensor and the one-time programmable memory. The processing circuitry can be configured to store additional data at the second set of data bit locations while retaining the error correction code values.

[0074] According to another implementation, the processing circuitry can be configured to store additional data by updating exactly four bit values ​​at corresponding bit positions in the second set of data bit positions.

[0075] According to another embodiment, the processing circuit can be configured to store additional data at a target bit position in a second set of data bit positions, and can be configured to identify additional spare bit positions configured to retain error correction code values.

[0076] The foregoing description is merely an illustrative illustration of the principles of the present invention, and those skilled in the art can make various modifications. The above embodiments can be implemented individually or in any combination.

Claims

1. A system comprising: a memory circuit storing a first set of data bits and a second set of parity bits for the first set of data bits; and a control circuit coupled to the memory circuit and configured to update a first bit in the first set of data bits by updating a second bit in the first set of data bits, a third bit in the first set of data bits, and a fourth bit in the first set of data bits, wherein the first bit, the second bit, the third bit, and the fourth bit, when updated, are configured to preserve the second set of parity bits in the memory circuit.

2. The system of claim 1, wherein the memory circuit comprises a one-time programmable memory storing the first set of data bits and the second set of parity bits.

3. The system of claim 2, wherein the second set of parity bits is configured to provide a single error correction function and a double error detection function to the first set of data bits.

4. The system of claim 2, wherein each bit of the one-time programmable memory is one-time programmable, wherein the first set of data bits comprises a first plurality of programmed bits and a second plurality of programmable bits, wherein each bit of the second plurality of programmable bits has a same default bit value, and wherein the second plurality of programmable bits comprises the first bit, the second bit, the third bit, and the fourth bit.

5. The system of claim 1, wherein the control circuit is configured to update the first bit by simultaneously updating the first bit, the second bit, the third bit, and the fourth bit, and is configured to identify respective bit positions of the second bit, the third bit, and the fourth bit based on a bit position of the first bit.

6. A method of updating a one-time programmable memory having error correction code functionality, the method comprising: storing data at a first set of data bit locations in the one-time programmable memory; maintaining an unused portion of the one-time programmable memory at a second set of data bit locations in the one-time programmable memory; storing error correction code bits for the first set of data bit locations and the second set of data bit locations; and storing additional data at the second set of data bit locations while preserving the error correction code bits.

7. The method of claim 6, wherein storing the additional data comprises: storing the additional data at a first data bit location in the second set of data bit locations; and identifying an additional data bit location in the second set of data bit locations to preserve the error correction code bits.

8. The method of claim 7, wherein storing the additional data comprises: storing the additional data at the additional data bit location in the second set of data bit locations; and storing the additional data at the first data bit location and the additional data bit location simultaneously, wherein storing the additional data at the first data bit location and the additional data bit location simultaneously comprises: ​ ​ ​ ​ inverting a default bit value at each of the first data bit locations and the additional data bit locations.

9. The method of claim 6, wherein each bit in the unused portion of the one-time programmable memory stores a same default bit value, and wherein each bit of the one-time programmable memory is one-time programmable.

10. An imaging system comprising: an image sensor; a one-time programmable memory having error correction code functionality, the one-time programmable memory storing data at a first set of data bit locations, maintaining a same default bit value at each of a second set of data bit locations in the one-time programmable memory, and storing parity bits corresponding to error correction code values for the first set of data bit locations and the second set of data bit locations; and processing circuitry coupled to the image sensor and the one-time programmable memory, wherein the processing circuitry is configured to store additional data at the second set of data bit locations while preserving the error correction code values.

11. The imaging system of claim 10, wherein the processing circuitry is configured to store the additional data at target bit locations in the second set of data bit locations, and is configured to identify additional spare bit locations configured to preserve the error correction code values.

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