Preparation Method and Structure of Rewiring Layer

Abstract

The present invention provides a method for preparing a redistribution layer and its structure. The method includes: providing a support substrate and forming a diffusion barrier layer thereon; forming a patterned photoresist layer on the diffusion barrier layer through processes of coating, exposure, and development; forming a metal wire layer with a trumpet-like morphology that is smaller at the upper end and larger at the lower end on the diffusion barrier layer; removing the patterned photoresist layer; removing the diffusion barrier layer by wet etching; and etching the metal wire layer by plasma etching to shape the morphology of the metal wire layer. By using the plasma etching process to shape the lower end of the metal wire layer, removing the sharp corner protrusions at the lower end of the metal wire layer or rounding the sharp corner protrusions, the line pitch between adjacent metal wire layers can be effectively increased, and the integration degree of the WLP can be improved; in addition, by eliminating the sharp corner protrusions at the lower end of the metal wire layer, the risk of tip discharge of the redistribution layer and bridging between adjacent metal wire layers can be avoided, and the electrical performance of the redistribution layer can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and particularly to a method for preparing a redistribution layer and its structure. Background Art

[0002] With the trend of multi-functionalization and miniaturization of electronic products, high-density microelectronic packaging technology has gradually become the mainstream in the new generation of electronic products. To meet the development of the new generation of electronic products, especially the development of products such as smart phones, tablet computers, and ultrabooks, the size of chips is developing in the directions of higher density, faster speed, smaller size, and lower cost, and at the same time, higher density development requirements are also put forward for packaging technology.

[0003] Due to the advantages of miniaturization, low cost, high integration, better performance, and higher energy efficiency, wafer-level packaging (WLP) technology has become an important packaging method for high-demand electronic devices such as mobile / wireless networks, and is one of the most promising packaging technologies at present.

[0004] WLP technology is based on BGA technology and is an improved and enhanced CSP. Taking the wafer as the processing object, multiple chips are simultaneously packaged, aged, and tested on the wafer, and finally cut into individual devices, which can be directly mounted on a substrate or a printed circuit board. It reduces the packaging size to the size of the IC chip and greatly reduces the production cost.

[0005] The redistribution layer (RDL) can re-layout the solder pad areas of the chip so that the new solder pad areas meet the requirements for the minimum pitch of solder balls and are arranged in an array. For high I / O chip packaging structures, multiple layers of RDL metal lines are required. However, within the limited form factor and packaging size, the smaller the line width and line pitch of the RDL metal lines, the more power supply tracks can be obtained.

[0006] In the existing process, the manufacturing part of the RDL metal lines is the most expensive part of the entire WLP process. In the process, lithography and etching processes are generally used to form the RDL metal lines, and the higher requirements for small RDL metal line widths and small line pitches have basically reached the physical limit of the resolution of traditional optical projection lithography technology. Therefore, the shape of the patterned photoresist layer formed by lithography and etching is large at the upper end and small at the lower end, and this shape directly results in the shape of the subsequently formed RDL metal lines being small at the upper end and large at the lower end, similar to a trumpet shape, and a sharp foot is formed at the lower end (as shown by the dashed box D in Figure 1 ). The trumpet-shaped RDL metal lines will reduce the line pitch between adjacent RDL metal lines, even bridge adjacent RDL metal lines, reducing the electrical performance of the RDL structure and at the same time reducing the integration of the WLP structure. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the object of the present invention is to provide a method for preparing a redistribution layer and its structure, which is used to solve the problems in the prior art that when forming a redistribution layer with a small line width and a small pitch in the WLP packaging technology, the redistribution layer has a trumpet-like morphology with a small upper end and a large lower end, and a bottom foot is formed at the lower end. The redistribution layer with this trumpet-like morphology will reduce the line pitch between adjacent redistribution layers, even bridge adjacent redistribution layers, reduce the electrical performance of the redistribution layer, and at the same time reduce the integration of the WLP structure, etc.

[0008] To achieve the above object and other related objects, the present invention provides a method for preparing a redistribution layer, and the preparation method at least includes the following steps:

[0009] Provide a support substrate, and form a diffusion barrier layer on the support substrate;

[0010] Coat a photoresist layer on the diffusion barrier layer, and form a filling window on the photoresist layer through exposure and development processes, and the filling window has a morphology with a small upper end and a large lower end;

[0011] Form a metal wire layer on the diffusion barrier layer of the filling window, the metal wire layer has a morphology with a small upper end and a large lower end, and the lower end of the metal wire layer has a sharp corner convex part;

[0012] Remove the photoresist layer;

[0013] Adopt wet etching to remove the diffusion barrier layer not covered by the metal wire layer;

[0014] Adopt plasma etching to etch the metal wire layer to remove the sharp corner convex part at the lower end of the metal wire layer, or make the sharp corner convex part at the lower end of the metal wire layer rounded.

[0015] Optionally, the diffusion barrier layer is formed on the support substrate by sputtering, and the metal wire layer is formed on the diffusion barrier layer of the filling window by electroplating.

[0016] Optionally, after forming the diffusion barrier layer on the support substrate, it further includes the step of forming a metal seed layer on the diffusion barrier layer, the photoresist layer is formed on the metal seed layer, the metal wire layer is formed on the metal seed layer of the filling window, and the diffusion barrier layer is removed by wet etching, and at the same time the metal seed layer is removed.

[0017] Optionally, the material of the metal seed layer includes Cu.

[0018] Optionally, the material of the diffusion barrier layer includes one or more of Ti, TiN, Ta, TaN, TiW, and Cr, and the material of the metal wire layer includes aluminum, aluminum alloy, copper, or copper alloy.

[0019] Optionally, the thickness of the photoresist layer is between 13 μm and 17 μm, and the thickness of the metal wire layer is between 8 μm and 12 μm.

[0020] Optionally, the metal wire layer is etched by sputter etching or reactive ion etching.

[0021] Optionally, the etching gas used for sputter etching the metal wire layer includes at least one of Ar and N2, and the etching gas used for reactive ion etching the metal wire layer includes BCl3 and Cl2.

[0022] Optionally, the line width of the metal wire layer is between 1.3 μm and 1.7 μm, and the line pitch between adjacent metal wire layers is between 1.3 μm and 1.7 μm.

[0023] The present invention also provides a redistribution layer, which at least includes:

[0024] A diffusion barrier layer;

[0025] A metal wire layer located on the diffusion barrier layer, wherein the lower edge of the metal wire layer does not exceed the diffusion barrier layer, and the lower end of the metal wire layer is arc-shaped.

[0026] Optionally, the redistribution layer further includes a metal seed layer formed between the diffusion barrier layer and the metal wire layer, wherein the lower edge of the metal wire layer does not exceed the metal seed layer.

[0027] Optionally, the material of the metal seed layer includes Cu.

[0028] Optionally, the material of the diffusion barrier layer includes one or more of Ti, TiN, Ta, TaN, TiW, and Cr, and the material of the metal wire layer includes aluminum, aluminum alloy, copper, or copper alloy.

[0029] Optionally, the line width of the metal wire layer is between 1.3 μm and 1.7 μm, and the line pitch between adjacent metal wire layers is between 1.3 μm and 1.7 μm.

[0030] As described above, in the method for preparing a rewiring layer and its structure according to the present invention, the lower end of the metal wire layer is shaped by using a plasma etching process to remove the sharp corner protrusions at the lower end of the metal wire layer or to round the sharp corner protrusions at the lower end of the metal wire layer. Through this morphology shaping step, the wire pitch between adjacent metal wire layers can be effectively increased, improving the integration of the WLP; in addition, the sharp corner protrusions at the lower end of the metal wire layer are eliminated, avoiding the risks of tip discharge of the rewiring layer and bridging between adjacent metal wire layers, and improving the electrical performance of the rewiring layer. Brief Description of the Drawings

[0031] Figure 1 An SEM image showing a rewiring layer in the prior art.

[0032] Figure 2 A schematic flow diagram showing the method for preparing a rewiring layer according to the present invention.

[0033] Figures 3 to 18 A schematic structural diagram showing the structure presented in each step of the method for preparing a rewiring layer according to the present invention, where Figure 7 Shown as Figure 6 A partial enlarged view of area A in Figure 14 Shown as Figure 13 A partial enlarged view of area B in Figure 17 Shown as Figure 16 A partial enlarged view of area C in Figure 16 And Figure 18 Also shown is a schematic structural diagram of the rewiring layer according to the present invention.

[0034] Element Number Description

[0035] 10 Support substrate

[0036] 100 Support layer

[0037] 101 Separation layer

[0038] 11 Diffusion barrier layer

[0039] 12 Photoresist layer

[0040] 120 Upper end of the photoresist layer

[0041] 121 Lower end of the photoresist layer

[0042] 122 Filling window

[0043] 13 Metal wire layer

[0044] 130 Upper end of the metal wire layer

[0045] 131 Lower end of the metal wire layer

[0046] The pointed convex part at the lower end of the 132 metal wire layer

[0047] 14 Metal seed layer

[0048] Steps S1 to S6 Specific implementation manners

[0049] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] Please refer to Figures 2 to 18 Note that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0051] Example 1

[0052] As Figures 2 to 18 shown, this embodiment provides a method for preparing a rewiring layer. Specifically, as Figures 3 to 18 shows the structural schematic diagrams presented by the steps of the method for preparing the rewiring layer in this embodiment.

[0053] As Figures 2 to 5 shown, first, step S1 is performed to provide a support substrate 10, and a diffusion barrier layer 11 is formed on the support substrate 10.

[0054] As Figure 3 shown, as an example, the support substrate 10 includes a support layer 100 and a separation layer 101 thereon.

[0055] The support layer 100 includes one of a glass layer, a metal layer, a semiconductor layer, a polymer layer, and a ceramic layer. In this embodiment, the support layer 100 is selected as a glass layer. The glass layer has a low cost, is easy to form a separation layer 101 on its surface, and can reduce the difficulty of subsequent peeling processes.

[0056] The separation layer 101 includes a polymer layer or an adhesive layer. The polymer layer or the adhesive layer is first coated on the surface of the support layer 100 by a spin coating process, and then cured and formed by an ultraviolet curing or thermal curing process.

[0057] In this embodiment, the polymer layer includes an LTHC photothermal conversion layer. Subsequently, when the support layer 100 is peeled off, the LTHC photothermal conversion layer can be heated based on a laser so that the rewiring layer and the support layer 1000 are separated from each other at the LTHC photothermal conversion layer.

[0058] As Figure 4 shown, as an example, the material of the diffusion barrier layer 11 can be one or more of Ti, TiN, Ta, TaN, TiW, and Cr. Since the metal wire layer in the general rewiring layer has a very high diffusion coefficient, when the rewiring layer is bonded to the wafer, due to the high diffusion coefficient of the metal wire layer, metal ions will diffuse into the device structure of the wafer, affecting the performance of the wafer. Therefore, in order to avoid the ion diffusion of the metal wire layer, when preparing the rewiring layer, a layer of the diffusion barrier layer 11 needs to be prepared on the support substrate first to prevent metal ions from diffusing into the wafer; in addition, it is also to improve the adhesion between the metal wire layer and the support substrate 10 during the subsequent preparation of the rewiring layer.

[0059] The preparation method of the diffusion barrier layer 11 can be physical or chemical methods such as sputtering, electroplating, physical vapor deposition, and chemical vapor deposition. In this embodiment, Ti is selected as the diffusion barrier layer, and the conventional sputtering method is used to deposit the diffusion barrier layer 11. The Ti layer is deposited by the sputtering method, and the process is easy to implement and the adhesion between the Ti layer and the support substrate is strong.

[0060] As Figure 5 shown, as an example, the electroplating method is generally used to form the metal wire layer, and the key to electroplating is to generate current through the metal layer on the surface to deposit the metal. For the diffusion barrier layer 11, which needs to achieve the functions of blocking diffusion and improving adhesion, the selected material has a small conductivity, so a metal layer with a large conductivity needs to be formed as the metal seed layer 14 for electroplating the metal wire layer. As Figure 5 shown, the metal seed layer 14 is formed on the diffusion barrier layer 11. The material of the metal seed layer 14 can be selected as Cu, and the metal seed layer 14 can be formed by the sputtering method.

[0061] As Figure 2 、 Figures 6 to 8 shown, then step S2 is carried out. A photoresist layer 12 is coated on the diffusion barrier layer 11, and through the processes of exposure and development, a filling window 122 is formed in the photoresist layer 12, and the filling window 122 has a morphology with a small upper end and a large lower end.

[0062] As Figure 7As shown, since the requirements for the line width and line spacing of the finally formed metal wire layer are very small, basically in the micrometer range, which has basically reached the physical limit of the resolution of the lithographic projection technology, the upper end 120 of the photoresist layer of the formed photoresist layer 12 has a larger line width, and the lower end 121 of the photoresist layer has a smaller line width, that is, the upper end of the filling window 122 is smaller and the lower end is larger.

[0063] As an example, the method for forming the patterned photoresist layer 12 is as follows: The photoresist is uniformly coated on the surface of the diffusion barrier layer 11 (as Figure 6 shown) or the metal seed layer 14 (as Figure 8 shown). Then, the support substrate covered with the photoresist is transferred from the coater to an oven for post-application baking to evaporate the moisture in the photoresist and fix the photoresist. Ultraviolet light is passed through the pattern on the mask plate and irradiated onto the surface of the support substrate coated with the photoresist. After being irradiated by the ultraviolet light, the photoresist deforms, and the photoresist is etched by the developer. After cleaning, a pattern consistent with or complementary to the mask plate is left, thereby forming the patterned photoresist layer 12.

[0064] As Figure 2 , Figures 9 to 10 shown, then step S3 is carried out. A metal wire layer 13 is formed on the diffusion barrier layer 11 of the filling window 122. The metal wire layer 13 has a morphology with a smaller upper end and a larger lower end, and the lower end 131 of the metal wire layer has a sharp-corner convex part 132.

[0065] As Figure 10 shown, as described above, if the metal wire layer 13 is formed by an electroplating process, generally a metal seed layer 14 is formed on the diffusion barrier layer 11. Then, in this step, the metal wire layer 13 is formed on the metal seed layer 14 of the filling window 122. As Figure 14 shown, based on the morphology of the patterned photoresist 12, that is, the morphology of the filling window 122, the upper end 130 of the metal wire layer has a smaller line width, the lower end 131 of the metal wire has a larger line width, and a sharp-corner convex part 132 is formed at the lower end 131 of the metal wire.

[0066] As an example, the thickness of the metal wire layer 13 is less than or equal to the thickness of the patterned photoresist layer 12. In this way, the line width of the metal wire layer 13 can be precisely controlled. Preferably, the thickness of the patterned photoresist layer 12 is between 13 μm and 17 μm, and the thickness of the metal wire layer 13 is between 8 μm and 12 μm.

[0067] As an example, the material of the metal wire layer 13 includes aluminum, aluminum alloy, copper or copper alloy. In this embodiment, the metal wire layer 13 is formed by electroplating, and the material of the metal wire layer 13 is selected as Cu.

[0068] As Figure 2 , Figures 11 to 12 shown, then step S4 is performed to remove the photoresist layer 12.

[0069] In actual production, a process temperature higher than 200°C is generally used for ashing treatment with an oxygen and fluorine mixed process gas to remove the patterned photoresist layer 12.

[0070] As Figure 2 , Figures 13 to 15 shown, then step S5 is performed to remove the diffusion barrier layer 11 not covered by the metal wire layer 13 by wet etching.

[0071] Since wet etching has a fast etching rate and low cost, it has become a commonly used etching method. As Figure 15 shown, as described above, if the metal seed layer 14 is formed on the diffusion barrier layer 11, then when removing the diffusion barrier layer 11 in this step, the metal seed layer 14 is also removed simultaneously. Since the materials used for the diffusion barrier layer 11 and the metal seed layer 14 are different, i.e., the etching ratios are different, different etching solutions need to be selected. For example, when the material of the diffusion barrier layer 11 is selected as Ti, hydrogen peroxide and phosphoric acid are selected as the etching solution, and when the material of the metal seed layer 14 is selected as Cu, potassium hydroxide and hydrogen peroxide are selected as the etching solution. Those skilled in the art can make selections according to actual needs.

[0072] As Figure 2 , Figures 16 to 18 shown, finally step S6 is performed to etch the metal wire layer 13 by plasma etching to remove the sharp corner protrusion 132 at the lower end 131 of the metal wire layer 13, or to round off the sharp corner protrusion 132 at the lower end 131 of the metal wire layer. To achieve shaping of the morphology of the metal wire layer 13.

[0073] As Figure 14 and Figure 17 shown, the plasma etching process of this step can be used to Figure 14 shape the lower end 131 of the metal wire layer shown, remove the sharp corner protrusion 132 at the lower end 131 of the metal wire layer, or round off the sharp corner protrusion 132 at the lower end 131 of the metal wire layer. By shaping the morphology of the metal wire layer 13 in this step, the line pitch between adjacent metal wire layers 13 can be effectively increased, improving the integration of the WLP; in addition, the sharp corner protrusion 132 is eliminated, avoiding the risk of tip discharge in the redistribution layer and bridging between adjacent metal wire layers, and improving the electrical performance of the redistribution layer.

[0074] As an example, the line width of the metal line layer 13 is between 1.3 μm and 1.7 μm, and the line pitch between adjacent metal line layers 13 is between 1.3 μm and 1.7 μm.

[0075] As an example, the metal line layer 13 can be etched by a sputter etching process or a reactive ion etching process. The etching gas used in the sputter etching process for etching the metal line layer 13 includes at least one of Ar and N2, and the etching gas used in the reactive ion etching process for etching the metal line layer 13 includes BCl3 and Cl2.

[0076] As a preferred example, the metal line layer 13 is etched by a sputter etching process, and the etching gas is selected as Ar. The above structure is placed in an etching chamber, the chamber pressure is selected as 0.3 T, the flow rate of Ar is 500 sccm, the microwave power is 1500 W, and the RF power is 280 W. The etching time is specifically controlled according to the thicknesses of the diffusion barrier layer 11 and the metal intermediate layer 14. Through physical bombardment etching by Ar ions, the diffusion barrier layer 11 and the metal intermediate layer 14 are removed to form the metal line layer 13 with the above morphology.

[0077] As an example, after forming the above structure, it may further include forming a dielectric layer covering the metal line layer 13, the metal seed layer 14, and the diffusion barrier layer 11, and then separating the rewiring layer from the support layer 100 through the separation layer 101.

[0078] Embodiment 2

[0079] As Figures 16 to 18 shown, this embodiment provides a rewiring layer. The structure of this rewiring layer can be obtained by the preparation method of Embodiment 1 above, but it can also be prepared by other methods, which are not limited herein. The beneficial effects brought by the rewiring layer of this embodiment can be referred to those described in Embodiment 1 and will not be elaborated herein.

[0080] As Figure 16 and Figure 17 shown, the rewiring layer at least includes:

[0081] Diffusion barrier layer 11;

[0082] Metal line layer 13, located on the diffusion barrier layer 11, wherein the edge of the lower end 131 of the metal line layer does not exceed the diffusion barrier layer 11, and the lower end 131 of the metal line layer is arc-shaped.

[0083] As Figure 17 shown, as an example, the rewiring layer further includes a metal seed layer 14 formed between the diffusion barrier layer 11 and the metal line layer 13, wherein the edge of the lower end 131 of the metal line layer does not exceed the metal seed layer 14.

[0084] As an example, the material of the metal seed layer 14 includes Cu.

[0085] As an example, the material of the diffusion barrier layer 11 includes one or more of Ti, TiN, Ta, TaN, TiW, and Cr, and the material of the metal wire layer 13 includes aluminum, aluminum alloy, copper, or copper alloy.

[0086] As an example, the line width of the metal wire layer 13 is between 1.3 μm and 1.7 μm, and the line pitch between adjacent metal wire layers 13 is between 1.3 μm and 1.7 μm.

[0087] In summary, the present invention provides a method for preparing a redistribution layer and its structure. By using a plasma etching process to shape the lower end of the metal wire layer, the sharp convex part at the lower end of the metal wire layer is removed, or the sharp convex part at the lower end of the metal wire layer is rounded. Through this morphology shaping step, the line pitch between adjacent metal wire layers can be effectively increased, and the integration degree of the WLP can be improved; in addition, the sharp convex part at the lower end of the metal wire layer is eliminated, which can avoid the risk of tip discharge of the redistribution layer and bridging between adjacent metal wire layers, and improve the electrical performance of the redistribution layer. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0088] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a rewiring layer, characterized in that The preparation method at least includes the following steps: Provide a support substrate and form a diffusion barrier layer on the support substrate; Coat a photoresist layer on the diffusion barrier layer, and form a filling window on the photoresist layer through exposure and development processes. The filling window has a morphology with a smaller upper end and a larger lower end; Form a metal wire layer on the diffusion barrier layer of the filling window. The metal wire layer has a morphology with a smaller upper end and a larger lower end, and the lower end of the metal wire layer has a sharp-corner protrusion; Remove the photoresist layer; Use wet etching to remove the diffusion barrier layer not covered by the metal wire layer; Use plasma etching to etch the metal wire layer to remove the sharp-corner protrusion at the lower end of the metal wire layer, or to round the sharp-corner protrusion at the lower end of the metal wire layer.

2. The method for preparing a rewiring layer according to claim 1, wherein: Use sputtering to form the diffusion barrier layer on the support substrate, and use electroplating to form the metal wire layer on the diffusion barrier layer of the filling window.

3. The method for preparing the rewiring layer according to claim 2, wherein: After forming the diffusion barrier layer on the support substrate, it further includes the step of forming a metal seed layer on the diffusion barrier layer. The photoresist layer is formed on the metal seed layer, the metal wire layer is formed on the metal seed layer of the filling window, and the diffusion barrier layer is removed by wet etching while removing the metal seed layer.

4. The method for preparing a rewiring layer according to claim 3, wherein: The material of the metal seed layer includes Cu.

5. The method for preparing a rewiring layer according to claim 1, characterized in that: The material of the diffusion barrier layer includes one or more of Ti, TiN, Ta, TaN, TiW, Cr, and the material of the metal wire layer includes aluminum, aluminum alloy, copper or copper alloy.

6. The method for preparing a rewiring layer according to claim 1, wherein: The thickness of the photoresist layer is between 13μm and 17μm, and the thickness of the metal wire layer is between 8μm and 12μm.

7. The method for preparing a rewiring layer according to claim 1, characterized in that: Use sputter etching or reactive ion etching to etch the metal wire layer.

8. The method for preparing a rewiring layer according to claim 7, wherein: The etching gas used for sputter etching the metal wire layer includes at least one of Ar and N2, and the etching gas used for reactive ion etching the metal wire layer includes BCl3 and Cl2.

9. The method for preparing a rewiring layer according to claim 1, wherein: The line width of the metal wire layer is between 1.3μm and 1.7μm, and the line pitch between adjacent metal wire layers is between 1.3μm and 1.7μm.

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