Method of manufacturing a semiconductor device

Abstract

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged region is formed on sidewalls of the fin structure, and the annealing operation eliminates the damaged region.

Description

Technical Field

[0001] Embodiments of the present application relate to a method of manufacturing a semiconductor device. Background Art

[0002] As the semiconductor industry enters the nanotechnology process node in the pursuit of higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs such as multi-gate field-effect transistors (FETs), including fin field-effect transistors (FinFETs) and gate-all-around (GAA) FETs. As the transistor size continues to shrink to technology nodes below 10 - 15 nm, FinFETs require further improvement, for example, precise critical dimension (CD) control and defect-free or damage-free fin formation processes. Summary of the Invention

[0003] Embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: forming a fin structure by patterning a semiconductor layer; and performing an annealing operation on the fin structure, wherein: the patterning includes forming a damaged region on a sidewall of the fin structure, and the annealing operation eliminates the damaged region.

[0004] Embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: forming a fin structure by patterning a semiconductor layer; performing a cleaning operation on the fin structure; after the cleaning operation, performing an annealing operation on the fin structure; and after the annealing operation, performing a patterning operation on the fin structure to divide the fin structure into multiple parts, wherein: forming the fin structure includes plasma dry etching with a pulsed bias voltage, and the annealing operation includes a process temperature of the annealing operation in the range of 900 °C to 1100 °C and a process duration of the annealing operation in the range of 1 second to 20 seconds.

[0005] Embodiments of the present application further provide a method for manufacturing a semiconductor device, the method comprising: forming a fin structure by performing a first etching operation on a semiconductor layer; performing a first cleaning operation on the fin structure; after the first cleaning operation, performing a first annealing operation on the fin structure; after the first annealing operation, performing a second etching operation on the fin structure to divide the fin structure into multiple parts; after the second etching operation, performing a second annealing operation on the fin structure; and after the second annealing operation, forming an isolation insulating layer such that an upper portion of the fin structure protrudes from the isolation insulating layer; at least one of the first etching operation or the second etching operation includes forming a damaged region including an amorphous or polycrystalline region on a sidewall of the fin structure, and at least one of the first annealing operation or the second annealing operation eliminates the damaged region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, the present invention can be better understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1A 、 Figure 1B 、 Figure 1C and Figure 1D show cross-sectional views of the various stages of a sequential process for manufacturing a FinFET device in accordance with an embodiment of the present disclosure.

[0008] Figure 2A 、 Figure 2B 、 Figure 2C and Figure 2D show cross-sectional views of the various stages of a sequential process for manufacturing a FinFET device in accordance with an embodiment of the present disclosure.

[0009] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D show cross-sectional views of the various stages of a sequential process for manufacturing a FinFET device in accordance with an embodiment of the present disclosure.

[0010] Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D show cross-sectional views of the various stages of a sequential process for manufacturing a FinFET device in accordance with an embodiment of the present disclosure.

[0011] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D 、 Figure 5E and Figure 5F show cross-sectional views of the various stages of a sequential process for manufacturing a FinFET device in accordance with an embodiment of the present disclosure.

[0012] Figure 6 shows a flowchart of the sequential manufacturing operations of a FinFET device in accordance with an embodiment of the present disclosure.

[0013] Figure 7A shows a pulsed bias etching operation in accordance with an embodiment of the present disclosure, Figure 7B shows a pulsed bias etching in accordance with an embodiment of the present disclosure. Figure 7C and Figure 7D also show a pulsed bias etching operation in accordance with an embodiment of the present disclosure.

[0014] Figure 8A shows the damage produced in the sidewalls of the fin structure, Figure 8B The damage (recrystallized regions) recovered by the annealing operation are shown. Figure 8C Defects generated in the channel region of the fin structure are shown.

[0015] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E Cross-sectional views illustrating various stages of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure.

[0016] Figure 10A , Figure 10B , Figure 10C and Figure 10D Cross-sectional views illustrating various stages of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure.

[0017] Figure 11A , Figure 11B , Figure 11C and Figure 11D Cross-sectional views illustrating various stages of a sequential process for fabricating a FinFET device according to an embodiment of the present disclosure.

[0018] Figure 12 The beneficial effects of this embodiment are shown. DETAILED DESCRIPTION

[0019] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, the size of the component is not limited to the disclosed range or value, but may depend on the process conditions and / or the performance required for the device. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which additional components may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. For simplicity and clarity, each component may be arbitrarily drawn with different sizes.

[0020] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. Except for the orientation shown in the figures, the spatial relationship terms are intended to include different orientations during the use or operation of the device. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly. Additionally, the term "made of" may mean "including" or "composed of". In the present disclosure, the phrase "one of A, B, and C" refers to "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and / or C), and does not denote one element from A, one element from B, and one element from C unless otherwise specified. Throughout the disclosure, the source and drain may be used interchangeably, and source / drain refers to one or both of the source and drain. In the following embodiments, the materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (e.g., one or more of the figures) may be adopted in other embodiments, and their detailed descriptions may be omitted.

[0021] In the manufacturing operation of a semiconductor device including a FinFET, the fin etching process is one of the key processes. In particular, during the plasma etching process for patterning the fin structure, it is required that the fin structure after fin patterning has no defects or damage caused by ion bombardment. In the present disclosure, a new process is provided that is used to reduce or suppress damage to the fin structure during plasma dry etching and to eliminate residual damage after the fin patterning process.

[0022] Figures 1A - 5F Views showing the stages of the sequential manufacturing operation of a FinFET device according to an embodiment of the present disclosure, Figure 6 showing its flowchart. It should be understood that additional operations may be provided before, during, and after the processes shown in Figures 1A - 5F and Figure 6 and for additional embodiments of the method, some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchanged.

[0023] In some embodiments, as Figure 1AAs shown, a hard mask layer 15 is formed above the substrate 10. In one embodiment, the substrate 10 includes a single crystal semiconductor layer at least on its surface portion. The substrate 10 may include single crystal semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In one embodiment, the substrate 10 is made of Si. The substrate 10 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity). For example, for an n-type FinFET, the dopant is boron (BF2), and for a p-type FinFET, the dopants are phosphorus and arsenic.

[0024] In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. In some embodiments, the first mask layer 15A includes a silicon nitride layer, and the second mask layer 15B includes a silicon oxide layer. The first mask layer 15A and the second mask layer 15B are formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable film forming processes. In some embodiments, a liner oxide layer 12 made of silicon oxide that can be formed by thermal oxidation is formed before the first mask layer 15A is formed.

[0025] In some embodiments, fin structures are formed by using one or more lithography processes, including double patterning processes or multi-patterning processes. Generally, double patterning or multi-patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, pitches smaller than those achievable using a single, direct lithography process. For example, as Figure 1B shown, a sacrificial layer is formed above the substrate and patterned using one or more lithography and etching processes to form a mandrel pattern (sacrificial pattern) 16. Then, as Figure 1C shown, a blanket layer 18 is formed, and anisotropic etching is performed to form sidewall spacers 18 next to the mandrel pattern using a self-alignment process, as Figure 1D shown. Then, the mandrel pattern 16 is removed, and the remaining spacers 18 are used as a mask pattern 18, as Figure 2A shown. In some embodiments, one or more additional sidewall formation processes are performed to form a mask pattern with a further reduced pitch.

[0026] As Figure 2A shown, the mask pattern 18 includes a plurality of line patterns corresponding to one or more fin structures in the p-type region and one or more fin structures in the n-type region. In some embodiments, the pitch of the mask pattern 18 in the p-type region is greater than the pitch of the mask pattern 18 in the n-type region.

[0027] Furthermore, as Figure 2BAs shown, in some embodiments, a capping layer 19 is further formed over the mask pattern 18. In some embodiments, the capping layer 19 is made of one or more of the following: silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorinated silicate glass (FSG), or a low-k dielectric material. In some embodiments, the capping layer 19 is formed by ALD. In some embodiments, the thickness of the capping layer 19 ranges from about 0.5 nm to about 5 nm.

[0028] Then, the mask layer 15 and the pad oxide layer 12 are patterned by using one or more etching operations, as Figure 2C shown. Additionally, at S101 of Figure 6 , the substrate 10 is patterned by using the patterned mask layer as an etch mask, thereby forming fin structures 20N and 20P (collectively referred to as fin structures 20) that extend in the Y direction. Details of the fin etching are described below. In some embodiments, the fin structure 20N is for an n-type FET, and the fin structure 20P is for a p-type FET. In Figure 2D , two fin structures 20P are arranged in the X direction in the p-type region, and four fin structures 20N are arranged in the X direction in the n-type region. However, the number of fin structures is not limited to two or four, and can be as small as one or three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures 20 to improve pattern fidelity during the patterning operation.

[0029] In some embodiments, the fin etching process includes using pulsed bias etching of the plasma etching apparatus 1000 as Figure 7B shown. Figure 7A FIG. shows a pulsed bias etching operation according to an embodiment of the present disclosure. In some embodiments, the substrate 10 is placed on the wafer stage 1100 of the etching chamber, and the substrate 10 and / or the wafer stage 1100 are biased, for example, by a DC voltage. In some embodiments, RF power (transformer-coupled plasma (TCP) power) is applied to the counter electrode 1200, which is a coil arranged above or around the etching chamber.

[0030] During the plasma etching operation, a DC bias voltage is applied to the wafer stage 1100, and RF power is applied to the TCP electrode. In the TCP plasma, the coil electrode 1200 is placed above or around the plasma etching chamber, and RF power is applied to the coil electrode 1200. In the pulsed bias method, as Figure 7A shown, the bias voltage is applied as a pulse while the power of the RF voltage is constant.

[0031] In some embodiments, the high (or on) value of the DC pulse bias voltage (V1) is in the range of about 100V to about 900V, and in other embodiments, in the range of about 200V to about 400V. In some embodiments, the low value of the DC pulse bias is zero (off). In some embodiments, the power of the RF voltage is in the range of about 400W to about 1200W, and in other embodiments, in the range of about 600W to 1000W.

[0032] In some embodiments, the frequency of the pulse bias voltage (1 / (one cycle)) is in the range of about 200Hz to about 8000Hz, and in other embodiments, in the range of about 1000Hz to about 4000Hz.

[0033] In some embodiments, the duty cycle of the pulse (on / off cycle ratio) is in the range of about 10% to about 80%, and in other embodiments, in the range of about 20% to 60%. The duty cycle can be any range of two values among 10%, 20%, 30%, 40%, 50%, 60%, 70%, and 80%.

[0034] In some embodiments, the source gas for the fin etching operation includes one or more selected from the group consisting of: HBr, O2, SF6, Cl2, CHF3, CO2, CH3F, C4F8, C4F6, CF4, NF3, Ar, H2, and He. The source gas includes at least one hydrogen source gas (e.g., HBr, CHF3, CH3F, and / or H2), at least one fluorine source gas (SF6, CHF3, CH3F, and / or NF3), and at least one carrier gas (Ar, H2, and / or He). In some embodiments, the pressure during the asymmetric pulse bias etching is in the range of about 1mTorr to about 100mTorr, and in other embodiments, in the range of about 10mTorr to about 50mTorr. It should be noted that the plasma source gas includes passivation gases (such as C4F8, C4F6, O2, etc.) and etchant gases (SF6, NF3, CF4, etc.) as a mixture or in an alternating cycle. During the passivation gas cycle, a passivation layer is formed (similar to during the bias-off phase), while during the etchant gas cycle, the bottom passivation layer is removed and etching proceeds towards the trench bottom (similar to during the bias-on phase).

[0035] In some embodiments, as Figure 7CAs shown, during etching, the bias voltage or bias power changes. In some embodiments, during etching, the bias voltage or bias power monotonically (e.g., linearly) increases. In other embodiments, the bias voltage or bias power is constant until the etching reaches a certain depth (e.g., about 30 - 50% of the total target depth), at which point the bias voltage or bias power increases. In the case of constant bias power, neutral species accumulate on the sidewalls of the upper portion of the fin structure, thereby forming a tapered shape, and the ratio of reactive ions to neutral species at the bottom of the trench (fin) begins to decrease with process time. In contrast, by using pulsed bias, the ratio of reactive ions to neutral species can be kept constant even at the bottom of the trench by increasing the bias power or voltage with process time, which can avoid an undesired tapered shape.

[0036] In addition, in some embodiments, as Figure 7D shown, one or more purge operations are performed during etching. By using, for example, an inert gas (Ar, He, etc.) for cyclic purging or by pumping out during the etching process, excessive neutral species deposited on the sidewalls of the fin structure can be removed or reduced. In some embodiments, the purge operation is performed at about 55 - 65% (e.g., 60%) of the total target depth and / or every 15 - 25% (e.g., 20%) of the total target depth. In a particular embodiment, the purge operation is performed at about 55 - 65% (e.g., 60%) and about 75 - 85% (e.g., 80%) of the total target depth.

[0037] In addition, in some embodiments, the reactive ions that prevent further etching at the bottom of the trench are neutralized by applying a charge to the substrate (wafer or substrate holder). In some embodiments, the substrate bias voltage is greater than zero and within + / - 5V. In some embodiments, the substrate bias is applied periodically.

[0038] As Figure 8AAs shown, plasma etching involving a hydrogen source and a fluorine source gas can cause damage to the sidewalls of the etched fin structure by hydrogen and fluorine ion bombardment and diffusion into the fin structure. In some embodiments, the damaged region is amorphous silicon or polycrystalline silicon. For example, when silicon contains about 8 - 20% hydrogen, this region can become amorphous, while when silicon contains about 3 - 8% hydrogen, this region can become polycrystalline. The damage on the sidewalls of the fin structure turns into triangular defects of silicon oxide in subsequent processes. It should be noted that the amorphous silicon portion containing hydrogen is different from the hydrogenated amorphous film (a-Si:H). Although both contain hydrogen, the a-Si:H film has more Si-H bonds, which act as dangling bonds and maintain the strain in the film. The presence of hydrogen in the amorphous silicon network leads to an increase in the material's resistance to plastic deformation. Additionally, the hardness of a-Si:H is the same as that of c-Si material. In contrast, the hydrogen content in the damaged region of the fin structure generates amorphous silicon, thus forming dangling bonds. Therefore, the initial hydrogen content in the damaged region is in the range of about 8 - 20%, and then decreases to about 1 - 3% after annealing.

[0039] However, in the present disclosure, plasma dry etching using a pulsed bias voltage can suppress damage to the sidewalls of the etched fin structure by generating more vertical ion bombardment than horizontal ion bombardment. As described above, one or more conditions of the pulsed bias etching and the type and / or ratio of the source gas are adjusted to suppress damage to the sidewalls of the fin structure. When the bias voltage (or power) is less than the above range, the ratio of neutral species to ions in the plasma increases, which results in more deposition, less etching and does not produce the desired higher etching depth. When the bias voltage is greater than the above range, the electron temperature in the plasma becomes too high, which causes damage to the underlying layer. When the duty cycle is less than the above range, more neutral species are generated, and the etched profile (space) becomes tapered without achieving a high etching depth. When the duty cycle is greater than the above range, more ion flux is generated, which leads to damage to the underlying layer.

[0040] After forming the fin structure 20, at Figure 6 S102, one or more cleaning operations are performed. In some embodiments, meniscus reconstruction cleaning using heated isopropyl alcohol is used as the cleaning operation.

[0041] After the wet cleaning operation, at Figure 6At S103, a first annealing operation is performed. Even if damage occurs on the sidewalls of the fin structure, this damage can be eliminated through the first annealing operation. In some embodiments, the annealing operation includes performing rapid thermal annealing at a temperature in the range of about 900 °C to about 1100 °C for about 1 second to 20 seconds. In other embodiments, the temperature is in the range of about 950 °C to 1050 °C. In other embodiments, the duration is in the range of about 5 seconds to 15 seconds. In some embodiments, the annealing operation is performed in an inert gas (Ar, He, and / or N2) environment. In other embodiments, the annealing operation is performed at a pressure of 1×10 -7 Torr to 5×10 -6 Torr. The annealing operation causes hydrogen and fluorine atoms to diffuse out of the fin structure and recrystallizes the damaged region, as shown in Figure 8B . When the temperature is below the above range, hydrogen and fluorine may not be effectively removed from the damaged region of the fin structure, and when the temperature is above the above range, the fin structure may bend and be damaged. When the process time is shorter than the above range, hydrogen and fluorine may not be effectively removed from the damaged region of the fin structure, and when the process time is longer than the above range, the previously formed diffusion region may be damaged.

[0042] Figure 3A shows the structure after the annealing operation is performed. In some embodiments, the mask layer 15 and the pad oxide layer 12 are removed before or after the annealing operation.

[0043] In some embodiments, after the annealing operation is performed, at Figure 6 S104, a liner semiconductor layer 100 is formed over the fin structure 20, as shown in Figure 3B . In some embodiments, the liner semiconductor layer 100 includes silicon, SiGe, or Ge. In a particular embodiment, silicon is used. The liner semiconductor layer 100 is formed over the fin structure to prevent the fins from bending. In some embodiments, depending on the device and / or process requirements, the thickness of the liner semiconductor layer 100 is in the range of about 0.2 nm to about 4 nm, and in the range of about 0.5 nm to about 2 nm. In some embodiments, the silicon liner layer 100 is epitaxially grown by LPCVD process, molecular beam epitaxy, atomic layer deposition, or any other suitable method. The LPCVD process is performed at a temperature of about 400 °C to 850 °C below the annealing temperature and at a pressure of about 1 Torr to 200 Torr using a silicon source gas (such as SiH4, Si2H6, or Si3H8). If SiGe or Ge is formed, the source gas includes one or more of GeH4 or G2H6. In some embodiments, the liner semiconductor layer 100 is undoped, and in other embodiments, for the n-type fin structure 20N and the p-type fin structure 20P, the liner semiconductor layer 100 is appropriately doped.

[0044] After forming the liner semiconductor layer 100, at Figure 6 at S105, in some embodiments, one or more wet cleaning operations are performed. In some embodiments, the wet cleaning solution includes an aqueous solution of ammonia (NH3) and hydrogen peroxide (H2O2) and / or an aqueous solution of hydrochloric acid (HCl) and hydrogen peroxide (H2O2). During the wet cleaning operation, the liner semiconductor layer 100 (and in some embodiments, the fin structure 20) is slightly etched, as Figure 3C shown.

[0045] Then, in some embodiments, at Figure 6 at S106, a cap semiconductor layer 110 is formed over the fin structure 20, as Figure 3D shown. In some embodiments, the cap semiconductor layer 110 includes silicon, SiGe, or Ge. In a particular embodiment, silicon is used. The cap semiconductor layer 110 is formed over the fin structure to adjust the size (width) of the fin structure. In some embodiments, depending on the device and / or process requirements, the thickness of the cap semiconductor layer 110 ranges from about 0.2 nm to about 4 nm, and from about 0.5 nm to about 2 nm. In some embodiments, similar to the liner semiconductor layer 100, the cap semiconductor layer 110 is epitaxially grown. In some embodiments, the cap semiconductor layer 110 is undoped, and in other embodiments, for n-type fin structures 20N and p-type fin structures 20P, the cap semiconductor layer 110 is appropriately doped.

[0046] Figure 4A is a plan view (projection view) of the fin structure 20 after forming the cap semiconductor layer 110. Next, as Figure 4B shown, at Figure 6 at S107, the fin structure 20 is cut into short segments to form individual fin structures by using one or more lithography and etching operations as a second fin etch. In some embodiments, plasma dry etching similar to the fin etch described above is used. In some embodiments, one or more unnecessary fin structures (e.g., dummy fin structures) are also removed by etching. After the plasma dry etching, the photoresist layer used in the lithography process is removed by, for example, an oxygen plasma ashing process.

[0047] After the second fin etch, at Figure 6 at S108, one or more cleaning operations are performed. In some embodiments, a meniscus reconstruction cleaning using heated isopropyl alcohol at room temperature to about 200 °C is used as the cleaning operation.

[0048] After the wet cleaning operation, at Figure 6At S109, a second annealing operation is performed. In some embodiments, damage is generated to the sidewalls of the fin structure during the second fin etching operation, and if damage is generated, the damage is eliminated by the second annealing operation. The second annealing operation causes hydrogen and fluorine atoms to diffuse out of the fin structure and recrystallizes the damaged region. The conditions of the second annealing operation are the same as or similar to those of the first annealing operation. In some embodiments, the annealing temperature in the second annealing operation is different (lower or higher) from the annealing temperature in the first annealing operation. In some embodiments, the second annealing operation is not performed.

[0049] Subsequently, at Figure 6 S110, an isolation insulating layer 30 is formed, as Figure 4C shown. In some embodiments, an insulating material layer including one or more layers of insulating material is formed over the substrate such that the fin structures 20 are completely embedded in the insulating layer. The insulating material for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material formed by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. An annealing operation may be performed after the insulating layer is formed. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed such that the upper surface of the fin structures 20 is exposed from the insulating material layer. Then, as Figure 4C shown, the insulating material layer is grooved to form the isolation insulating layer 30 such that the upper portions (channel regions) of the fin structures 20 are exposed. By this operation, the fin structures 20 are electrically separated from each other by the isolation insulating layer 30, which is also referred to as a shallow trench isolation (STI).

[0050] In some embodiments, one or more insulating liner layers are formed over the fin structures 20 before the isolation insulating layer 30 is formed. The insulating liner layer includes silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, or any other suitable material. When the isolation insulating layer 30 is grooved, the insulating liner layer formed on the channel region of the fin structure is removed, and the lower portion of the fin structure is covered by the insulating liner layer in the isolation insulating layer 30.

[0051] After the isolation insulating layer 30 is formed, at Figure 6 S111, one or more wet cleaning operations are performed in some embodiments. In some embodiments, a thin oxide layer formed on the channel region of the fin structures 20 is removed. In some embodiments, the channel regions of the fin structures exposed from the isolation insulating layer are also slightly etched.

[0052] Then, in some embodiments, at Figure 6 S112, the channel regions of the fin structures 20 are trimmed (etched), as Figure 4DAs shown. In some embodiments, one or more dry etchings and / or wet etchings are performed. In some embodiments, wet etching using an aqueous solution of tetramethylammonium hydroxide (TMAH) and / or an aqueous solution of KOH is used as the wet etchant. In other embodiments, chemical dry etching using HCl gas is used to trim the channel region. In some embodiments, the amount of trimming (etching) is in the range of about 0.2 nm to about 2.0 nm, and in other embodiments, in the range of about 0.5 nm to about 1.0 nm.

[0053] If plasma etch damage remains on the sidewalls of the channel region of the fin structure, the trim etching operation can etch the damaged region, resulting in triangular cavities or pits exposing the (111) plane. However, in the present embodiment, since the first and / or second annealing operations for removing damage are performed before the fin trimming operation, defective etching of the channel region does not occur.

[0054] After the trim etching, in some embodiments, at Figure 6 S113, a capping semiconductor layer 120 is formed over the channel region of the fin structure 20, as Figure 5A shown. In some embodiments, the capping semiconductor layer 120 includes silicon, SiGe, or Ge. In a particular embodiment, silicon is used. The capping semiconductor layer 120 is formed over the fin structure to adjust the size (width) of the fin structure and also control the outward diffusion of Ge from the SiGe or Ge layer (if used). In some embodiments, depending on device and / or process requirements, the thickness of the capping semiconductor layer 120 is in the range of about 0.2 nm to about 4 nm, and in other embodiments, in the range of about 0.5 nm to about 2 nm. In some embodiments, similar to the liner semiconductor layer 100 and / or the capping semiconductor layer 110, the capping semiconductor layer 120 is epitaxially grown. In some embodiments, the capping semiconductor layer 120 is undoped, and in other embodiments, for the n-type fin structure 20N and the p-type fin structure 20P, the capping semiconductor layer 120 is appropriately doped.

[0055] After forming the capping semiconductor layer 120, at Figure 6 S114, a third annealing operation is performed. In some embodiments, the annealing operation includes performing rapid thermal annealing at a temperature in the range of about 900 °C to about 1100 °C for about 0.1 second to 10 seconds. In other embodiments, the temperature is in the range of about 950 °C to 1050 °C. In other embodiments, the duration is in the range of about 0.5 second to 5 seconds. In some embodiments, the annealing operation is performed in a mixed gas of N2 and O2, where the oxygen concentration is in the range of about 0.1% to 0.5%.

[0056] After the third annealing operation, a sacrificial gate structure 40 is formed over the fin structure, as Figure 5BAs shown. In some embodiments, the sacrificial gate structure 40 includes a sacrificial dielectric layer, a sacrificial gate electrode layer, and a hard mask layer. The sacrificial gate dielectric layer includes one or more layers of insulating material, such as silicon oxide-based materials. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer ranges from about 1 nm to about 5 nm. The sacrificial gate electrode layer includes silicon such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nm to about 200 nm. In some embodiments, a planarization operation is performed on the sacrificial gate electrode layer. CVD including LPCVD and PECVD, PVD, ALD, or other suitable processes are used to deposit the sacrificial gate dielectric layer and the sacrificial gate electrode layer. The hard mask layer is used to form the sacrificial gate electrode layer and includes one or more layers of silicon nitride and silicon. In some embodiments, the sacrificial gate dielectric layer also covers the source / drain regions of the fin structure 20.

[0057] After forming the sacrificial gate structure 40, a blanket layer of insulating material for sidewall spacers is conformally formed by using CVD or other suitable methods. The blanket layer is deposited conformally such that it is formed with a substantially equal thickness on the vertical surfaces (such as sidewalls), horizontal surfaces, and top of the sacrificial gate structure. In some embodiments, the blanket layer is deposited to a thickness in the range of about 2 nm to about 10 nm. In one embodiment, the insulating material of the blanket layer is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN and combinations thereof. Sidewall spacers are formed on opposite sidewalls of the sacrificial gate structure 40.

[0058] In Figure 5B the embodiments, one sacrificial gate structure 40 is disposed above two fin structures 20P in the p-type region, and one sacrificial gate structure 40 is disposed above four fin structures 20N in the n-type region. However, the number of fin structures for each sacrificial gate structure is not limited and can be one, two, three, or more than four. In other embodiments, one sacrificial gate structure is formed above one or more n-type fin structures 20N and one or more p-type fin structures 20P.

[0059] Subsequently, source / drain epitaxial layers 62 and 64 are formed (see Figure 5F)。In some embodiments, the fin structures of the source / drain regions are grooved downwardly below the upper surface of the isolation insulating layer 30 by using dry etching and / or wet etching, and then one or more semiconductor layers are epitaxially formed over the grooved fin structures. In other embodiments, one or more semiconductor layers are epitaxially formed over the source / drain regions of the non-grooved fin structures. The source / drain epitaxial layer 62 for the n-type FET includes one or more layers of SiC, SiP, and SiCP, and the source / drain epitaxial layer 64 for the p-type FET includes one or more layers of SiGe, SiGeSn, which may be doped with B. In at least one embodiment, the epitaxial layer is epitaxially grown by an LPCVD process, molecular beam epitaxy, atomic layer deposition, or any other suitable method. The LPCVD process is performed under the following conditions: at a temperature of about 400 °C to about 850 °C, at a pressure of about 1 Torr to about 200 Torr, using a silicon source gas such as SiH4, Si2H6, or Si3H8, a germanium source gas such as GeH4 or G2H6, a carbon source gas such as CH4 or SiH3CH3, a phosphorus source gas such as PH3, and / or a boron source gas such as B2H6. In some embodiments, two or more layers having different compositions (e.g., different P, C, Ge, and / or B concentrations) are formed as the source / drain epitaxial layer.

[0060] Subsequently, as Figure 5C shown, a first interlayer dielectric (ILD) layer 50 is formed over the source / drain epitaxial layer and the sacrificial gate structure 40. Then, a planarization operation such as CMP is performed such that the top of the sacrificial gate electrode layer is exposed. The material of the first ILD layer 50 includes compounds containing Si, O, C, and / or H such as silicon oxide, SiCOH, and SiOC. An organic material such as a polymer can be used for the first ILD layer 50.

[0061] Next, the sacrificial structure 40 including the sacrificial gate electrode layer and the sacrificial gate dielectric layer is removed, thereby exposing the upper portion (channel region) of the fin structure 20, as Figure 5D shown. The sacrificial gate structure 40 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer is polysilicon and the first ILD layer 50 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer. Thereafter, the sacrificial gate dielectric layer is removed using plasma dry etching and / or wet etching.

[0062] After removing the sacrificial gate structure, a gate dielectric layer 82 is formed over the channel region (the upper portion of the fin structure 20 over the isolation insulating layer 30), and a gate electrode layer 84 is formed over the gate dielectric layer 82, as Figure 5E shown.

[0063] In certain embodiments, the gate dielectric layer 82 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interface layer formed between the channel layer and the dielectric material.

[0064] The gate dielectric layer 82 can be formed by CVD, ALD, or any suitable method. In one embodiment, a highly conformal deposition process such as ALD is used to form the gate dielectric layer 82 to ensure that a gate dielectric layer with a uniform thickness is formed over each channel layer. In one embodiment, the thickness of the gate dielectric layer 82 is in the range of about 1 nm to about 6 nm.

[0065] A gate electrode layer 84 is formed over the gate dielectric layer 82. The gate electrode 84 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0066] The gate electrode layer 84 can be formed by CVD, ALD, electroplating, or other suitable methods. The gate electrode layer is also deposited over the upper surface of the first ILD layer 50. Then, the gate dielectric layer and the gate electrode layer formed over the first ILD layer 50 are planarized by using, for example, CMP until the top surface of the first ILD layer 50 is exposed. In some embodiments, after the planarization operation, the gate electrode layer 84 is grooved and a capping insulating layer is formed over the grooved gate electrode 84. The capping insulating layer includes one or more layers of silicon nitride-based materials, such as SiN. The capping insulating layer can be formed by depositing an insulating material and then performing a planarization operation.

[0067] In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) are inserted between the gate dielectric layer 82 and the gate electrode 84. The work function adjustment layer is made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or a multi-layer of two or more of these materials. For n-channel FETs, one or more of TaN, TiAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, while for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layer can be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Additionally, different metal layers can be used to separately form the work function adjustment layers for n-channel FETs and p-channel FETs.

[0068] In the FETs formed in the foregoing embodiments, in some embodiments, the fin sidewalls exhibit a low surface roughness Ra of less than about 1.8 nm (greater than 0 nm). In some embodiments, the hydrogen content in the fin structure is in the range of about 1×10 18 atoms / cm 3 to about 3×10 18 atoms / cm 3 . In some embodiments, the crystallinity of the entire fin structure is greater than about 90% and less than 100%. When the fin structure is formed by a method other than this embodiment, the crystallinity is less than about 30%. In some embodiments, the depth (height) variation of the fin structure is very small, for example, less than about 3% (greater than 0%) of the average fin depth (measured for 50 fin structures). When the fin structure is formed by a method other than this embodiment, the depth variation is about 10 - 20% of the average depth.

[0069] In the foregoing embodiments, a pulsed bias voltage etching operation is employed to reduce damage to the fin structure, particularly for deep trench regions (e.g., the level below the upper surface of the isolation insulating layer). Even if damage occurs, the post-annealing treatment reconstructs the damaged region into a crystal, and the damaged region becomes oxide-free. Therefore, it is impossible to damage the gate dielectric layer and the metal gate layer in subsequent processes. In some embodiments, there are damaged regions in the channel region above the upper surface of the isolation insulating layer, and these damaged regions may not be completely removed by the annealing operation. However, as Figure 8C shown, the damaged regions only have (100) and / or (110) planes and no (111) planes. When the damaged regions are reconstructed, the remaining damaged regions (defects) become smaller, which does not affect subsequent processes. In some embodiments, the depth of the remaining defects is in the range of about 0.1 nm to about 0.5 nm.

[0070] It should be understood that Figure 5E and Figure 5F the semiconductor device shown also undergoes a CMOS process to form various components such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0071] Figures 9A - 9E A sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. It should be understood that additional operations may be provided before, during, and after the Figures 9A - 9E shown process, and for additional embodiments of the method, some of the operations described below may be replaced or deleted. The order of operations / processes may be interchanged. The materials, configurations, dimensions, processes, and / or operations described with respect to the foregoing embodiments may be employed in the following embodiments, and their detailed descriptions may be omitted. In this embodiment, the channel region of the p-type FET includes SiGe.

[0072] In some embodiments, a portion of the substrate 10 corresponding to the p-type region is etched through one or more lithography and etching operations to form a groove. Then, an epitaxial layer 11 is formed in the groove. In some embodiments, the epitaxial layer 11 is made of SiGe. In some embodiments, the germanium concentration of the SiGe layer 11 is in the range of about 5 atomic % to about 30 atomic %. In some embodiments, one or more buffer layers having a Ge concentration lower than that of the epitaxial layer 11 are formed between the epitaxial layer 11 and the substrate 10. The SiGe layer 11 can be formed by CVD such as low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), or any other suitable process. In some embodiments, a CMP operation is performed after the epitaxial layer 11 is formed. In some embodiments, the thickness of the epitaxially grown SiGe layer 11 (the depth of the groove) is in the range of about 30 nm to about 100 nm, and in other embodiments, in the range of 40 nm to 80 nm.

[0073] Then, as Figure 9A -Convex 9D shows, operations the same as or similar to those described with respect to Figures 1A - 2D are performed to form a p-type fin structure 20P and an n-type fin structure 20N each having a SiGe layer for the channel region. Subsequently, operations the same as or similar to those described with respect to Figures 3A - 5F are performed, and a p-type FinFET and an n-type FinFET are formed as Figure 9E shown.

[0074] Figures 10A - 11D A sequential process for manufacturing a FinFET device according to an embodiment of the present disclosure is shown. It should be understood that it may be possible toFigures 10A - 11D Additional operations are provided before, during, and after the process shown, and for additional embodiments of the method, some of the operations described below may be replaced or removed. The order of operations / processes may be interchanged. The materials, configurations, dimensions, processes, and / or operations described with respect to the foregoing embodiments may be employed in the following embodiments, and their detailed descriptions may be omitted. In this embodiment, the channel region of the p-type FET includes SiGe, and etching for forming the p-type fin structure and the n-type fin structure is performed separately.

[0075] Figures 10A - 10C Same as Figures 9A - 9C As shown, the p-type region is covered by a covering layer 27 (e.g., a photoresist pattern). Then, as Figure 10D shown, the n-type fin structure 20N is formed by one or more plasma dry etching operations. Thereafter, as Figure 11A shown, the covering layer 27 is removed. As Figure 11B shown, the n-type region is covered by a covering layer 28 (e.g., a photoresist pattern). Then, as Figure 11C shown, the p-type fin structure 20P is formed by one or more plasma dry etching operations. Thereafter, the covering layer 28 is removed to obtain the same or a similar structure as Figure 11D shown. Subsequently, operations the same as or similar to those described with respect to Figure 9D are performed, and p-type FinFETs and n-type FinFETs are formed as Figures 3A - 5F shown. In other embodiments, the n-type fin structure 20N is formed first, and then the p-type fin structure 20P is formed. Figure 5F shown.

[0076] Figure 12 Shows the beneficial effects of this embodiment. In the comparative example, pulse bias etching and annealing operations are not performed after fin etching. As Figure 12 shown, the FinFETs fabricated by this embodiment exhibit an almost zero leakage current (Id, off) (e.g., about 0.01 nA). The results show that in this embodiment, defects or damages in the channel region of the fin structure are effectively suppressed or eliminated.

[0077] Each of the embodiments or examples described herein provides several advantages over the prior art. In the embodiments of the present disclosure, in the fin etching process, pulse bias voltage plasma etching is employed, followed by an annealing operation, to suppress or reduce the damage on the sidewalls of the etched fin structure and eliminate the damage, thereby improving device performance and yield.

[0078] It should be understood that not all advantages need to be discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0079] According to one aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged region is formed on the sidewalls of the fin structure, and the annealing operation eliminates the damaged region. In one or more of the foregoing and following embodiments, the semiconductor layer is a single-crystalline semiconductor, and the damaged region includes an amorphous region or a polycrystalline region. In one or more of the foregoing and following embodiments, the damaged region includes hydrogen and fluorine having a concentration higher than that of the rest of the fin structure. In one or more of the foregoing and following embodiments, hydrogen and fluorine are removed by the annealing operation. In one or more of the foregoing and following embodiments, the annealing operation recrystallizes the damaged region. In one or more of the foregoing and following embodiments, the process temperature of the annealing operation is in the range of 950 °C to 1050 °C. In one or more of the foregoing and following embodiments, the process duration of the annealing operation is in the range of 5 seconds to 15 seconds.

[0080] According to another aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, a cleaning operation is performed on the fin structure, after the cleaning operation, an annealing operation is performed on the fin structure, and after the annealing operation, a patterning operation is performed on the fin structure to divide the fin structure into multiple ones. In the formation of the fin structure, plasma dry etching with a pulsed bias voltage is employed, and in the annealing operation, the process temperature is in the range of 900 °C to 1100 °C, and the process duration of the annealing operation is in the range of 1 second to 20 seconds. In one or more of the foregoing and following embodiments, the pulsed bias voltage includes a frequency in the range of 200 Hz to 8000 Hz. In one or more of the foregoing and following embodiments, the duty cycle of the pulsed bias voltage is in the range of 0.2 to 0.6. In one or more of the foregoing and following embodiments, the voltage of the pulsed bias voltage is in the range of 100 V to 900 V. In one or more of the foregoing and following embodiments, the plasma dry etching includes a mixed gas of at least one hydrogen source, at least one fluorine source, and at least one carrier gas. In one or more of the foregoing and following embodiments, the plasma dry etching includes forming a damaged region including an amorphous region or a polycrystalline region on the sidewalls of the fin structure, and the annealing operation eliminates the damaged region. In one or more of the foregoing and following embodiments, the annealing operation is performed in an inert gas environment.

[0081] According to another aspect of the present disclosure, in a method for manufacturing a semiconductor device, a fin structure is formed by performing a first etching operation on a semiconductor layer, a first cleaning operation is performed on the fin structure, after the first cleaning operation, a first annealing operation is performed on the fin structure, after the first annealing operation, a second etching operation is performed on the fin structure to divide the fin structure into a plurality of parts, after the second etching operation, a second annealing operation is performed on the fin structure, and after the second annealing operation, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer. In at least one of the first etching operation or the second etching operation, a damaged region including an amorphous region or a polycrystalline region is formed on a sidewall of the fin structure, and in at least one of the first annealing operation or the second annealing operation, the damaged region is eliminated. In one or more of the foregoing and following embodiments, the first cleaning operation uses a heated isopropyl alcohol treatment. In one or more of the foregoing and following embodiments, a second cleaning operation using a heated isopropyl alcohol treatment is further performed between the second patterning operation and the second annealing operation. In one or more of the foregoing and following embodiments, between the first annealing operation and the second patterning operation, a liner semiconductor layer is formed over the fin structure, a first wet etching operation is performed on the fin structure, and a first capping semiconductor layer is formed over the fin structure. In one or more of the foregoing and following embodiments, after forming the isolation insulating layer, a second wet etching operation is performed, a trimming etching operation is performed on the fin structure, and a second capping semiconductor layer is formed over the fin structure. In one or more of the foregoing and following embodiments, after forming the second capping semiconductor layer, a third annealing operation is performed in an environment including oxygen.

[0082] According to another aspect of the present disclosure, a semiconductor device includes: a fin structure; an isolation insulating layer from which a channel region of the fin structure protrudes; a gate structure located above the channel region; and a source / drain epitaxial layer located above a source / drain region of the fin structure. A surface roughness Ra of a sidewall of the fin structure is greater than 0 nm and less than 1.8 nm. In one or more of the foregoing and following embodiments, a crystallinity of the fin structure is greater than 90% and less than 100%.

[0083] According to another aspect of the present disclosure, a semiconductor device includes: a plurality of fin structures disposed above a substrate; an isolation insulating layer from which channel regions of the plurality of fin structures protrude; a gate structure located above one or more of the channel regions; and a source / drain epitaxial layer located above source / drain regions of one or more of the fin structures. A variation in height of the plurality of fin structures is greater than 0% and less than 3% of an average height of the plurality of fin structures. In one or more of the foregoing and following embodiments, a surface roughness Ra of sidewalls of the plurality of fin structures is greater than 0 nm and less than 1.8 nm. In one or more of the foregoing and following embodiments, a crystallinity of the plurality of fin structures is greater than 90% and less than 100%.

[0084] Embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: forming a fin structure by patterning a semiconductor layer; and performing an annealing operation on the fin structure, wherein: the patterning includes forming a damaged region on the sidewalls of the fin structure, and the annealing operation eliminates the damaged region. In some embodiments, the semiconductor layer is a single-crystalline semiconductor, and the damaged region includes an amorphous or polycrystalline region. In some embodiments, the damaged region includes hydrogen and fluorine with a concentration higher than that of the rest of the fin structure. In some embodiments, hydrogen and fluorine are removed by the annealing operation. In some embodiments, the annealing operation recrystallizes the damaged region. In some embodiments, the process temperature of the annealing operation is in the range of 950 °C to 1050 °C. In some embodiments, the process duration of the annealing operation is in the range of 5 seconds to 15 seconds.

[0085] Embodiments of the present application provide a method for manufacturing a semiconductor device, the method comprising: forming a fin structure by patterning a semiconductor layer; performing a cleaning operation on the fin structure; after the cleaning operation, performing an annealing operation on the fin structure; and after the annealing operation, performing a patterning operation on the fin structure to divide the fin structure into multiple ones, wherein: forming the fin structure includes plasma dry etching with a pulsed bias voltage, and the annealing operation includes a process temperature of the annealing operation in the range of 900 °C to 1100 °C and a process duration of the annealing operation in the range of 1 second to 20 seconds. In some embodiments, the pulsed bias voltage includes a frequency in the range of 200 Hz to 8000 Hz. In some embodiments, the duty cycle of the pulsed bias voltage is in the range of 0.2 to 0.6. In some embodiments, the voltage of the pulsed bias voltage is in the range of 100 V to 900 V. In some embodiments, the plasma dry etching includes a mixed gas of at least one hydrogen source, at least one fluorine source, and at least one carrier gas. In some embodiments, the plasma dry etching includes forming a damaged region including an amorphous or polycrystalline region on the sidewalls of the fin structure, and the annealing operation eliminates the damaged region. In some embodiments, the annealing operation is performed in an inert gas environment.

[0086] Embodiments of the present application also provide a method for manufacturing a semiconductor device, the method comprising: forming a fin structure by performing a first etching operation on a semiconductor layer; performing a first cleaning operation on the fin structure; after the first cleaning operation, performing a first annealing operation on the fin structure; after the first annealing operation, performing a second etching operation on the fin structure to divide the fin structure into a plurality of parts; after the second etching operation, performing a second annealing operation on the fin structure; and after the second annealing operation, forming an isolation insulating layer such that an upper portion of the fin structure protrudes from the isolation insulating layer; at least one of the first etching operation or the second etching operation includes forming a damaged region including an amorphous or polycrystalline region on a sidewall of the fin structure, and at least one of the first annealing operation or the second annealing operation eliminates the damaged region. In some embodiments, the first cleaning operation uses a heated isopropyl alcohol treatment. In some embodiments, a second cleaning operation using a heated isopropyl alcohol treatment is further included between the second patterning operation and the second annealing operation. In some embodiments, it further includes, between the first annealing operation and the second patterning operation: forming a liner semiconductor layer above the fin structure; performing a first wet etching operation on the fin structure; and forming a first capping semiconductor layer above the fin structure. In some embodiments, after forming the isolation insulating layer: performing a second wet etching operation; performing a trimming etching operation on the fin structure; and forming a second capping semiconductor layer above the fin structure. In some embodiments, it further includes performing a third annealing operation in an environment including oxygen after forming the second capping semiconductor layer.

[0087] The components of several embodiments have been described above so that those skilled in the art can better understand various aspects of the present invention. Those of ordinary skill in the art should understand that it is possible to easily use the present invention as a basis to design or change other processes and structures for achieving the same purposes and / or realizing the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a fin structure by patterning a semiconductor layer; and performing an annealing operation on the fin structure, after which a patterning operation is performed on the fin structure to divide the fin structure into a plurality of parts, wherein: the patterning includes forming a damaged region on the sidewalls of the fin structure, and the annealing operation eliminates the damaged region; wherein, between the annealing operation and the patterning operation for dividing the fin structure into a plurality of parts: forming a liner semiconductor layer over the fin structure; performing a first wet etching operation on the fin structure; and forming a first capping semiconductor layer over the fin structure.

2. The method according to claim 1, wherein, The semiconductor layer is a single-crystalline semiconductor, and the damaged region includes an amorphous or polycrystalline region.

3. The method according to claim 2, wherein The damaged region includes hydrogen and fluorine at a concentration higher than the rest of the fin structure.

4. The method according to claim 3, wherein, Hydrogen and fluorine are removed by the annealing operation.

5. The method according to claim 2, wherein The annealing operation recrystallizes the damaged region.

6. The method according to claim 1, wherein The process temperature of the annealing operation is in the range of 950 °C to 1050 °C.

7. The method according to claim 6, wherein The process duration of the annealing operation is in the range of 5 seconds to 15 seconds.

8. A method for manufacturing a semiconductor device, the method comprising: forming a fin structure by patterning a semiconductor layer; performing a cleaning operation on the fin structure; after the cleaning operation, performing an annealing operation on the fin structure; and after the annealing operation, performing a patterning operation on the fin structure to divide the fin structure into a plurality of parts, wherein: forming the fin structure includes plasma dry etching with a pulsed bias voltage, and the annealing operation includes a process temperature of the annealing operation in the range of 900 °C to 1100 °C and a process duration of the annealing operation in the range of 1 second to 20 seconds; wherein, between the annealing operation and the patterning operation for dividing the fin structure into a plurality of parts: forming a liner semiconductor layer over the fin structure; performing a first wet etching operation on the fin structure; and forming a first capping semiconductor layer over the fin structure.

9. The method according to claim 8, wherein The pulsed bias voltage includes a frequency in the range of 200 Hz to 8000 Hz.

10. The method according to claim 9, wherein The duty cycle of the pulsed bias voltage is in the range of 0.2 to 0.

6.

11. The method according to claim 8, wherein, The voltage of the pulsed bias voltage is in the range of 100 V to 900 V.

12. The method according to claim 8, wherein The plasma dry etching includes a mixed gas of at least one hydrogen source, at least one fluorine source, and at least one carrier gas.

13. The method according to claim 8, wherein: the plasma dry etching includes forming a damaged region including an amorphous or polycrystalline region on the sidewalls of the fin structure, and the annealing operation eliminates the damaged region.

14. The method according to claim 8, wherein, The annealing operation is performed in an inert gas environment.

15. A method for manufacturing a semiconductor device, the method comprising: forming a fin structure by performing a first etching operation on a semiconductor layer; performing a first cleaning operation on the fin structure; after the first cleaning operation, performing a first annealing operation on the fin structure; after the first annealing operation, performing a second etching operation on the fin structure to divide the fin structure into a plurality of parts; After the second etching operation, a second annealing operation is performed on the fin structure; and After the second annealing operation, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer; At least one of the first etching operation or the second etching operation includes forming a damaged region including an amorphous or polycrystalline region on sidewalls of the fin structure, and At least one of the first annealing operation or the second annealing operation eliminates the damaged region, wherein, between the first annealing operation and the second etching operation: A liner semiconductor layer is formed over the fin structure; A first wet etching operation is performed on the fin structure; and A first capping semiconductor layer is formed over the fin structure.

16. The method according to claim 15, wherein, The first cleaning operation uses a heated isopropyl alcohol treatment.

17. The method according to claim 16, further comprising a second cleaning operation using a heated isopropyl alcohol treatment between the second etching operation and the second annealing operation.

18. The method according to claim 15, wherein The first annealing operation is carried out at a pressure of 1×10 -7 Torr to 5×10 -6 Torr.

19. The method according to claim 15, further comprising, after forming the isolation insulating layer: Performing a second wet etching operation; Performing a trimming etching operation on the fin structure; and Forming a second capping semiconductor layer over the fin structure.

20. The method according to claim 19, further comprising performing a third annealing operation in an environment including oxygen after forming the second capping semiconductor layer.

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