Semiconductor device and method for forming the same

Abstract

The present invention provides a semiconductor device and a method for forming the same. The semiconductor device according to an embodiment of the present invention includes: a first fin structure extending longitudinally along a first direction above a substrate; a first epitaxial component located above a source / drain region of the first fin structure; a gate structure arranged above a channel region of the first fin structure and extending along a second direction perpendicular to the first direction; and a source / drain contact located above the first epitaxial component. The bottommost surface of the gate structure is closer to the substrate than the bottommost surface of the source / drain contact.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that simultaneously support increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved to a large extent by scaling down the size (e.g., minimum component size) of semiconductor ICs and thereby increasing production efficiency and reducing associated costs. However, such scaling down also increases the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] For example, as integrated circuit (IC) technology develops to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current and reducing short channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or part thereof arranged above more than one side of the channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps the top and sidewalls of the semiconductor material "fin" extending from the substrate). The gate structure of the MBC transistor can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of the MBC transistor can be formed by nanowires, nanosheets, other nanostructures and / or other suitable structures.

[0004] When the dielectric layer between the gate structure and the source / drain contacts of a multi-gate device becomes thinner, the parasitic capacitance between the gate structure and the source / drain contacts may affect device performance. For example, in some conventional techniques, an overetch is performed to form a source / drain contact opening that extends well into the isolation features between the active areas, and the source / drain contacts are formed into the source / drain contact opening. Such lateral overlap between the source / drain contacts and the adjacent gate structure may have undesirable parasitic capacitance. Therefore, although conventional source / drain contacts and formation processes are generally sufficient to achieve their intended purpose, they are not satisfactory in all aspects. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor device, including: a first fin structure, extending longitudinally along a first direction above a substrate; a first epitaxial component, located above a source / drain region of the first fin structure; a gate structure, arranged above a channel region of the first fin structure and extending along a second direction perpendicular to the first direction; and a source / drain contact, located above the first epitaxial component, wherein the bottommost surface of the gate structure is closer to the substrate than the bottommost surface of the source / drain contact.

[0006] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: receiving a workpiece, the workpiece comprising: a fin structure, a gate structure arranged above a channel region of the fin structure, an epitaxial component arranged above a source / drain region of the fin structure, an etch stop layer arranged above the epitaxial component, and a first dielectric layer located above the etch stop layer; depositing a capping layer above the workpiece; depositing a second dielectric layer above the capping layer; forming an etching mask on the second dielectric layer, the etching mask having an opening; performing a plurality of main etching processes through the opening of the etching mask to etch through the first dielectric layer, the capping layer, and the second dielectric layer; and performing a plurality of over-etching processes through the opening of the etching mask to etch through the etch stop layer.

[0007] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: receiving a workpiece, the workpiece comprising: a fin structure, a gate structure, arranged above a channel region of the fin structure, an epitaxial component, arranged above a source / drain region of the fin structure, an etch stop layer, arranged above the epitaxial component, and a first dielectric layer, located above the etch stop layer; depositing a capping layer above the workpiece; depositing a second dielectric layer above the capping layer; forming an etching mask on the second dielectric layer, the etching mask having an opening; performing a first main etching process through the opening of the etching mask to etch through at least a portion of the second dielectric layer; performing a second main etching process through the opening of the etching mask to etch through at least a portion of the capping layer and the first dielectric layer; performing a first over-etching process to expose a first surface of the epitaxial component; and performing a second over-etching process to recess the epitaxial component and the etch stop layer to expose a second surface of the epitaxial component, wherein the second surface is larger than the first surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1When read together, various aspects of the present invention are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0009] Figure 1 is a flow chart of a method of manufacturing a semiconductor device according to various aspects of the present invention.

[0010] Figure 2 is a partial top view of a workpiece at a stage of manufacture according to various aspects of the present invention, such as with Figure 1 The artifacts associated with the methods in .

[0011] Figures 3 to 12 are partial cross-sectional views of a workpiece at various stages of manufacture according to various aspects of the present invention, such as Figure 1 The stages associated with the methods in . DETAILED DESCRIPTION

[0012] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted to form, and may also include an embodiment in which additional components can be formed between the first component and the second component. In addition, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, for simplicity and clarity, the various components may be arbitrarily drawn in different proportions.

[0013] Further, for ease of description, as shown in the figures, spatially relative terms such as "under", "beneath", "lower", "above", "upper", etc. may be used to describe the relationship of one element or component to another (or other) elements or components. In addition to the orientation shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, what is described as "under the elements of other elements or components" or "under the elements of other elements or components" will be oriented as "above the other elements or components". Therefore, the exemplary term "under" can include orientations above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0014] Furthermore, when "about," "approximately," etc. are used to describe a number or a range of numbers, the term is intended to encompass values ​​within a reasonable range that includes the described value, such as within + / -10% of the described value or other values ​​as understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0015] As IC device sizes shrink, short channel effects (SCEs) prevent further scaling down of planar field effect transistors (FETs). In recent years, various multi-gate devices with improved short channel effect control have emerged, facilitating the continuous scaling down of semiconductor devices to even smaller device nodes and higher device densities. Examples of multi-gate devices include fin field effect transistors (FinFETs) and multi-bridge channel (MBC) FETs. Although scaling down can be achieved through multi-gate devices, the conductive structures in multi-gate devices may be separated by thin dielectric layers, resulting in increased parasitic resistance and parasitic capacitance. The parasitic capacitance between conductive structures increases as their size increases, and decreases as the distance between them increases. For example, when forming a FinFET, the source / drain components in the source / drain region of the fin structure are recessed to form a source / drain opening, which will be filled with a conductive material for forming a source / drain contact. In some conventional techniques, the recesses of the source / drain regions may be etched too much below the source / drain features and unnecessarily increase the depth of the source / drain openings. The increased depth may result in increased parasitic capacitance. The present invention provides a method of forming a source / drain contact that does not extend below the bottommost level of the gate structure. By reducing the depth of the source / drain contact, the parasitic capacitance between the source / drain contact and the adjacent gate structure is reduced.

[0016] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart of a method 100 for manufacturing a semiconductor device according to various aspects of the present invention. The method 100 is merely an example and is not intended to limit the present invention to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 100. For simplicity, not all steps are described in detail herein. Figure 2 The top view of workpiece 200 and Figures 3 to 12 Method 100 is described with reference to a partial cross-sectional view of a workpiece 200 in FIG.

[0017] refer to Figure 1 , Figure 2 , Figure 3 and Figure 4, method 100 includes a box 102 in which a workpiece 200 is provided. Workpiece 200 may be an intermediate device manufactured during the process of an IC or a portion thereof, which may include static random access memory (SRAM) and / or other logic circuits, passive components (such as resistors, capacitors, and inductors), and active components (such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and / or other memory cells). The present invention is not limited to any particular number of devices or device regions, nor to any particular device configuration. Additional components may be added to the semiconductor device manufactured on workpiece 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device to be manufactured on workpiece 200. Because a semiconductor device is to be formed from workpiece 200 at the end of the process described in the present invention, workpiece 200 may be referred to as semiconductor device 100 as the context requires.

[0018] First reference Figure 2 , Figure 2 is a partial top view of the workpiece 200. To simplify the description, Figure 2 The orientation, regions, and relative positions of the substrate 202 , the fin structure 204 , the gate structure 208 , and the isolation gate structure 208 ′ are shown. Figure 3 as well as Fig.12 A partial cross-sectional view of the II′ cross section along the length direction of the fin structure 204 extending along the Y direction is shown. Figure 4 as well as Figure 5 and Fig.11A partial cross-sectional view of a II-II' section along the length direction of the gate structure 208 extending along the X direction is shown. In the depicted embodiment, the workpiece 200 includes a substrate 202. The substrate 202 may be a bulk substrate including silicon. Optionally, in some embodiments, the substrate 202 includes a bulk substrate (including, for example, silicon) and one or more material layers arranged above the bulk substrate. For example, the one or more material layers may include a semiconductor layer stack having individual semiconductor layers (such as a heterostructure) arranged above the bulk substrate, wherein the semiconductor layer stack is subsequently patterned to form a fin structure. The semiconductor layer may include any suitable semiconductor material, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. Depending on the design requirements of the semiconductor device 200, the semiconductor layers may include the same or different materials, etching rates, composition atomic percentages, composition weight percentages, thicknesses, and / or configurations. In some embodiments, the semiconductor layer stack includes alternating semiconductor layers, such as semiconductor layers composed of a first material and semiconductor layers composed of a second material. For example, the semiconductor layer stack alternates silicon layers and silicon germanium layers (e.g., Si / SiGe / Si from bottom to top). In some embodiments, the semiconductor layer stack includes semiconductor layers of the same material but with alternating composition atomic percentages, such as a semiconductor layer with a composition of a first atomic percentage and a semiconductor layer with a composition of a second atomic percentage. For example, the semiconductor layer stack includes silicon germanium layers with alternating silicon and / or germanium atomic percentages (e.g., Si / SiGe / Si from bottom to top). a Ge b / Si c Ge d / Si a Ge b , where a, c are different atomic percentages of silicon, and b, d are different atomic percentages of germanium). Optionally or additionally, the bulk substrate 202 and / or one or more material layers include another basic semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide and / or cadmium telluride; an alloy semiconductor, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; other III-V group materials; other II-V group materials; or a combination thereof. Optionally, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using isolation by implanted oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0019] The fin structure 204 may be formed from the substrate 202 or a semiconductor layer deposited over the substrate 202 using a process such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric patterning (SIDP) process, other double patterning processes, or combinations thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or combinations thereof. Typically, multiple patterning processes combine lithography processes and self-alignment processes, thereby allowing the creation of patterns with smaller pitches than those obtained using a single direct lithography process. For example, in some embodiments, a patterned sacrificial layer is formed over the substrate using a lithography process, and spacers are formed next to the patterned sacrificial layer using, for example, a self-alignment process. The patterned sacrificial layer is then removed and the spacers may be used to pattern the underlying layers. In some embodiments, a directed self-assembly (DSA) technique is implemented during the multiple patterning processes. In the depicted embodiment, there may be multiple fin structures 204 on the substrate 202. As described above, when the semiconductor device 200 includes a FinFET, the fin structure 204 may be formed of a uniform semiconductor composition, or when the semiconductor device 200 includes an MBCFET, the fin structure 204 may include a stack of alternating semiconductor layers. As shown in the figure, reference Figure 3 and Figure 4 The fin structures 204 are isolated from each other by isolation features 206 , which may be shallow trench isolation (STI) features.

[0020] like Figure 2 As shown, the fin structure 204 extends longitudinally along the Y direction, and the gate structure 208 extends longitudinally over the channel region 10 of the fin structure 204 along the X direction. Each channel region 10 is sandwiched between two source / drain regions 20 along the Y direction. Figure 1 In some embodiments shown in other figures of the present invention, the workpiece 200 includes isolation regions 30. Each isolation region 30 divides the fin structure 204 into different segments and represents a form of a fin cutting component. Figure 3 , an isolation structure 217 may be present in the isolation region 30 to separate one fin structure 204 from another fin structure aligned with the fin structure 204 along the Y direction. Figure 2 and Figure 3, the isolation structure 217 can be two isolation gate structures 208', each isolation gate structure 208' is arranged above the edge of the fin structure 204. The two isolation gate structures 208' can sandwich a dielectric layer arranged between the two isolation gate structures 208'. The isolation gate structure 208' can have a similar structure to the gate structure 208. The difference lies mainly in the position and function. Although the gate structure 208 in the channel region 10 is functional, the isolation gate structure 208' in the isolation region 30 provides fin structure isolation, but does not perform circuit functions.

[0021] A variety of different processes may be used to form the isolation structure 217. The resulting structure may be Figure 3 . In the example process, fin-cut grooves are formed along the X direction to divide one or more fin structures 204 into segments. Isolation dielectric material (such as silicon oxide, silicon nitride, silicon oxide) is deposited over the workpiece 200, including in recesses and trenches in the fin structures 204. The deposited isolation dielectric material is then planarized, such as by chemical mechanical polishing (CMP), and then etched back to form isolation features 206. In some instances, the isolation features 206 may be shallow trench isolation (STI) features, and may be referred to as STI features. Figure 3 As shown, isolation features 206 may be present between fin structure segments of fin structure 204 . Figure 4The isolation component 206 is shown to also be arranged between two parallel fin structures 204. After forming the isolation component 206, a dummy gate stack (not shown) is formed above the channel region 10 of the fin structure 204 as a placeholder for the gate structure 208 and the isolation gate structure 208'. In some instances, the dummy gate stack may include a dummy gate dielectric layer formed of silicon oxide and a dummy gate electrode formed of polysilicon. For patterning purposes, the dummy gate stack may also include one or more gate top hard mask layers formed of silicon nitride, silicon oxide, or both. Then a gate spacer layer 210 is deposited above the workpiece 200, including above the sidewalls of the dummy gate stack. When there is a gate top hard mask layer, the gate spacer layer 210 may be deposited above the top surface of the gate top hard mask layer. The gate spacer layer 210 may be a single layer or multiple layers. In some embodiments, the gate spacer layer may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, or silicon carbide. Using the gate top hard mask layer and the gate spacer layer 210 as an etching mask, the source / drain region 20 of the fin structure 204 is recessed to form a source / drain groove. Then, a source / drain component 212 is formed in the source / drain groove using an epitaxial deposition process. The source / drain component 212 may include a semiconductor material doped with a dopant. In some examples, the source / drain component 212 may include boron-doped silicon germanium (SiGeB) for p-type devices or phosphorus-doped silicon (SiP) for n-type devices. After forming the source / drain component 212, the ESL 214 and the first dielectric layer 216 are sequentially deposited over the workpiece 200, including over the source / drain component 212 and the dummy gate stack. The workpiece 200 is flattened or recessed to expose the top surface of the dummy gate stack on the flat top surface. At this point, the process replaces the dummy gate stack with a gate structure 208 or an isolation gate structure 208'. After the workpiece 200 is planarized again to remove excess material, a capping layer 218 is deposited over the exposed top surfaces of the gate structure 208 and the isolation gate structure 208 ′. A second dielectric layer 220 is then deposited over the capping layer 218 .

[0022] In some embodiments where the first dielectric layer 216 is deposited using CVD or spin coating, one or more air gaps or voids may be formed in the first dielectric layer 216 as the width of the fin-cut trench or the fin-to-fin spacing continues to decrease along the Y direction. Figure 3 In the illustrated embodiment, first air gap 221, second air gap 222, and third air gap 223 may be formed in first dielectric layer 216. First air gap 221 represents a single air gap in the first dielectric layer, while second air gap 222 and third air gap 223 represent vertically spaced apart air gaps.

[0023] refer to Figure 4The ESL 214 is conformally deposited on the surface of the source / drain feature 212 to control the etching process to form a source / drain contact opening exposing the source / drain feature 212. In this regard, the ESL 214 may also be referred to as a contact etch stop layer (CESL) 214. Figure 4 As shown, the ESL 214 is deposited not only on the source / drain features 212, but also on the top surface of the isolation features 206 within the fin structure 204 (or a segment of the fin structure 204). The first dielectric layer 216 may be referred to as a first interlayer dielectric (ILD) layer 216, and the second dielectric layer 220 may be referred to as a second interlayer dielectric (ILD) layer 220. The first dielectric layer 216 and the second dielectric layer 220 may be formed of the same dielectric material. In some embodiments, the first dielectric layer 216 and the second dielectric layer 220 may include a dielectric material including, for example, silicon oxide, an oxide formed from TEOS, PSG, BPSG, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. The capping layer 218 may also be referred to as a gate top capping layer 218. In some embodiments, the capping layer 218 is formed of an oxygen-free (or oxygen-free) dielectric material such as silicon nitride. The capping layer 218 is used to prevent the gate structure 208 from being oxidized due to the diffusion of oxygen atoms from an upper dielectric layer such as the second dielectric layer 220.

[0024] refer to Figure 1 , Figure 5 , Figure 6 and Figure 7 , the method 100 includes block 104, where a first main etching process 300 is performed to etch through a portion of the second dielectric layer 220. Figure 5In order to form an etching mask for the first main etching process 300 and subsequent etching processes, a mask layer 224 is deposited over the workpiece 200. In some embodiments, the mask layer 224 is formed of a material that can withstand the various etching processes of the present invention. In some implementations, the mask layer 224 is formed of tungsten carbide, titanium carbide, zirconium oxide, or aluminum oxide. In one example, the mask layer 224 is formed of tungsten carbide. The mask layer 224 is then patterned using a photolithography and etching process. In the example process, a photoresist layer is deposited over the mask layer 224. The photoresist layer is then exposed to patterned radiation transmitted through or reflected from the photomask, baked in a post-exposure bake process, developed in a developer solution, and then rinsed to form a patterned photoresist layer. The patterned photoresist layer is then used as an etching mask to etch the underlying mask layer 224, such as Figure 6 It is patterned as shown in . Figure 6 In the embodiment shown in , the patterned mask layer 224 includes mask openings 225 , each of which is disposed directly above a plurality of source / drain features 212 .

[0025] Reference now Figure 7, using the patterned mask layer 224 as an etching mask, a first main etching process 300 is performed. In the depicted embodiment, the first main etching process 300 etches only through the second dielectric layer 220 and is timed to stop before etching the capping layer 218. In some embodiments, the second dielectric layer 220 may have a first thickness D1 along the Z direction, wherein the first thickness D1 is between about 55 nm and about 75 nm. The first main etching process 300 may etch a first depth E1 into the second dielectric layer 220. The first depth E1 is less than the thickness D1. In embodiments where the second dielectric layer 220 is substantially formed of silicon oxide, one or more etchants for the first main etching process 300 are selected so that the first main etching process 300 is selective to silicon oxide. In some embodiments, the first main etching process 300 may include a dry etching process using a halogen-containing or oxygen-containing etchant. For example, the first main etching process 300 may include a fluorine-containing etchant (e.g., CF4, SF6, NF3, CH2F2, CHF3 and / or C2F6), an oxygen-containing etchant, a chlorine-containing etchant (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing etchant (e.g., HBr and / or CHBR3), an iodine-containing etchant, other suitable etchants (which may be used to generate an etchant gas and / or an etching plasma) or a combination thereof. In one example, the first main etching process 300 includes a fluorine-containing etchant (e.g., CF4, SF6, NF3, CH2F2, CHF3 and / or C2F6). In an optional embodiment, the first main etching process 300 may include a wet etching process using a dilute hydrofluoric acid (DHF) solution. At the end of the operation at frame 104, a first opening 226 is formed in the second dielectric layer 220. Because the first main etching process 300 stops before it reaches the capping layer 218, the capping layer 218 is not exposed to the first opening 226.

[0026] refer to Figure 1 and Figure 8 , the method 100 includes block 106, wherein a second main etching process 310 is performed to etch through the capping layer 218 and at least a portion of the first dielectric layer 216. The second main etching process 310 is performed while the patterned mask layer 224 continues to be used as an etching mask to form the first opening 226 ( Figure 7 ) extends through the cover layer 218 to form a second opening 228. Figure 8 As shown, the second main etching process 310 etches through the remaining portion of the first thickness D1 of the second dielectric layer 220 exposed in the mask opening 225 (i.e., the difference between D1 and E1), the entire second thickness D2 of the capping layer 218, and partially etches into the first dielectric layer 216. Figure 8In the embodiment, each of the second openings 228 has a second depth E2. When the second depth E2 is greater than the sum of the first thickness D1 and the second thickness D2, the second depth E2 is also greater than the first depth E1. In some embodiments, the second thickness D2 can be between about 3 nm and 10 nm, and the second depth E2 can be between 80 nm and about 120 nm. Figure 8 In some embodiments shown, the second main etching process 310 may form a bottom recess 229 at the bottom surface of the second opening 228. Figure 8 As shown, the bottom recess 229 may extend downward between two adjacent source / drain features 212 .

[0027] From top to bottom, the second main etch process 310 etches through the remaining portion of the second dielectric layer 220, the capping layer 218, and a portion of the first dielectric layer 216. In some embodiments, the second main etch process 310 stops before or at the ESL 214. Figure 8 An embodiment is shown in which the second main etching process 310 stops before etching the ESL 214. Since the first dielectric layer 216 and the second dielectric layer 220 may be substantially formed of silicon oxide and the capping layer 218 may be formed of an oxygen-free dielectric material such as silicon nitride, the etchant of the second main etching process 310 is selected to etch both. The second main etching process 310 may include a suitable dry etching process or a suitable wet etching process. In embodiments where the second main etching process 310 includes a dry etching process, the second main etching process 310 may include using a fluorine-containing etchant (e.g., CF4, SF6, NF3, CH2F2, CHF3, and / or C2F6) and a nitrogen-containing agent (such as nitrogen (N2) or ammonia (NH3). It has been observed that the presence of a nitrogen-containing agent may increase the etching rate of silicon nitride while slowing down the etching rate of silicon oxide. In embodiments where the second main etching process 310 includes a wet etching process, the second main etching process 310 may include using a dilute hydrofluoric acid (DHF) solution and a buffer (such as ammonium fluoride (NH4F)). A mixture of DHF and a buffer may be referred to as a buffered hydrofluoric acid (BHF) solution. The BHF solution may etch both silicon oxide and silicon nitride simultaneously, although at a slower rate than DHF.

[0028] In some embodiments, the second main etching process 310 may be a single-stage process. In these embodiments, the second main etching process 310 may be a single-stage dry etching process using a fluorine-containing etchant and a nitrogen-containing reagent or a single-stage wet etching process using a BHF solution. In some optional embodiments, the second main etching process 310 may be a multi-stage process, such as a dual-stage process. In an exemplary dual-stage process, the second main etching process 310 includes a first stage of etching through the capping layer 218 and a subsequent second stage that is selective to the first dielectric layer 216. In this example, the first stage is less selective to silicon oxide than the second stage of the second main etching process 310. In other words, the first stage is not selective, so that it etches both the second dielectric layer 220 formed of silicon oxide and the capping layer 218 formed of silicon nitride. The second stage is selective to silicon oxide, so that the second stage etches the first dielectric layer 216 and substantially stops or slows down when reaching the ESL 214. When the two-stage second main etching process 310 includes a dry etching process, the first stage includes more nitrogen-containing reagents (larger partial pressure in the gas phase) than the second stage, or the first stage includes nitrogen-containing reagents and the second stage does not contain nitrogen-containing reagents. When the two-stage second main etching process 310 includes a wet etching process, the first stage includes more buffering agents (higher concentration in the etchant solution) than the second stage, or the first stage uses BHF as an etchant and the second stage uses DHF as an etchant.

[0029] refer to Figure 1 and Fig. 9 , the method 100 includes block 108, where a first over-etching process 320 is performed to etch through the etch stop layer 214 on the source / drain features 212. While retaining the patterned mask layer 224 as an etch mask, the first over-etching process 320 selectively etches the etch stop layer 214 without substantially extending the bottom recess 229 further into the first dielectric layer 216. At the end of the operation at block 108, the exposed Figure 8The ESL 214 in the second opening 228 in the first overetching process 320 is removed to form the third opening 230. The first overetching process 320 may be a dry etching process or a wet etching process. In an embodiment where the first overetching process 320 is a dry etching process, the first overetching process 320 may include using a fluorine-containing etchant (e.g., CF4, SF6, NF3, CH2F2, CHF3 and / or C2F6) and a nitrogen-containing reagent (such as nitrogen (N2) or ammonia (NH3). As described above, the presence of the nitrogen-containing reagent may increase the etching selectivity relative to the ESL 214 that may be formed of silicon nitride. In an embodiment where the first overetching process 320 is a wet etching process, the first overetching process 320 may include using a phosphoric acid (H3PO4) solution. Such a wet etching process is isotropic, but is highly selective relative to the ESL 214 that may be formed of silicon nitride.

[0030] refer to Figure 1 and Fig.10, the method 100 includes a block 110, wherein a second over-etching process 330 is performed to recess the etch stop layer 214 and the source / drain features 212 to form a source / drain contact opening 232. For the operation at block 110, the patterned mask layer 224 remains as an etching mask. The second over-etching process 330 further etches back the ESL 214, the first dielectric layer 216, and the source / drain features 212. Therefore, the second over-etching process 330 can be regarded as a shearing or cleaning process that further extends the third opening 230 to the source / drain contact opening 232. The source / drain contact opening 232 exposes additional surfaces of the source / drain features 212 compared to the third opening 230. Because the second over-etching process 330 etches a layer formed of a different dielectric material, there is no selectivity for the ESL 214. Therefore, the first over-etching process 320 has a first etch selectivity with respect to the ESL 214 or silicon nitride, and the second over-etching process 330 has a second etch selectivity with respect to the ESL 214 or silicon nitride. The first etch selectivity is greater than the second etch selectivity. The second over-etching process 330 may be a dry etch process or a wet etch process. In embodiments where the second overetch process 330 includes a dry etching process, the second overetch process 330 may include using a fluorine-containing etchant (e.g., CF4, SF6, NF3, CH2F2, CHF3, and / or C2F6) and a nitrogen-containing reagent (e.g., nitrogen (N2) or ammonia (NH3). The second overetch process 330 may include less or a lower partial pressure of the nitrogen-containing reagent than the first overetch process. In embodiments where the second overetch process 330 is a wet etching process, the second overetch process 330 may include using BHF. BHF etches both silicon oxide and silicon nitride at a slower rate than DHF. The slower etching rate of BHF prevents the second overetch process 330 from etching too much in the space between adjacent source / drain features 212. At the end of the operations of block 110, the source / drain contact openings 232 are substantially formed.

[0031] refer to Figure 1 , Fig.11 and Fig.12, the method 100 includes a frame 112, wherein a source / drain contact 236 is formed in the source / drain contact opening 232. In some embodiments, before forming the source / drain contact 236, a silicide component 234 is formed over the exposed surface of the source / drain component 212 by depositing a metal material over the source / drain component 212 and annealing the workpiece 200 to induce a silicidation reaction between the metal material and the source / drain component 212. In some examples, the metal material may include titanium (Ti), nickel (Ni), cobalt (Co), tantalum (Ta), or tungsten (W), and the silicide component 234 may include titanium silicide, nickel silicide, cobalt silicide, tantalum silicide, tungsten silicide. The silicide component 234 is used to reduce the contact resistance. After forming the silicide component 234, the source / drain contact 236 is deposited in the source / drain contact opening 232. Each of the source / drain contacts 236 may be formed of a metal selected from copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), nickel (Ni), other suitable materials or combinations thereof, and deposited using PVD, CVD, ALD or other suitable processes. Although not explicitly shown, the source / drain contact openings 232 may be lined with a barrier layer to isolate the source / drain contacts 236 from the first dielectric layer 216 and the second dielectric layer 220. The barrier layer may be formed of titanium nitride, tantalum nitride or tungsten nitride. In some embodiments, a planarization process such as a CMP process may be performed to remove excess metal and mask layer 224 from the top surface of the workpiece 200.

[0032] Embodiments of the present invention provide benefits. For example, by using the first main etching process 300, the second main etching process 310, the first over-etching process 320, and the second over-etching process 330, the method of the present invention forms a source / drain contact opening that does not extend below the bottommost surface of the source / drain feature 212, thereby reducing the size of the source / drain contact 236 on the XZ plane. The reduction in the size of the source / drain contact 236 can reduce the parasitic capacitance between the gate structure 208 and the source / drain contact 236. Referring again to Fig.11 and Fig.12 Each of the gate structures 208 has a topmost surface 208T ( Fig.11 ) and the bottommost surface 208B ( Fig.12). Each of the source / drain contacts 236 includes a bottommost surface 236B. Each of the source / drain features 212 includes a bottommost surface 212B. For ease of reference, the topmost surface 208T of the gate structure 208 may be referred to as the gate top surface 208T; the bottommost surface 208B of the gate structure 208 may be referred to as the gate bottom surface 208B; the bottommost surface 236B of the source / drain contact 236 may be referred to as the contact bottom surface 236B; and the bottommost surface 212B of the source / drain feature 212 may be referred to as the S / D bottom surface 212B. Fig.11 As shown, the gate top surface 208T is spaced apart from the S / D bottom surface 212B by a first distance d1, and the gate top surface 208T is spaced apart from the contact bottom surface 236B by a second distance d2. The second distance d2 is also spaced apart from the S / D bottom surface 212B by a first distance d1. Fig.12 As shown in Fig.12 As shown, the gate top surface 208T is separated from the gate bottom surface 208B by a third distance d3. In some embodiments, the contact bottom surface 236B is near the S / D bottom surface 212B but not lower than the S / D bottom surface 212B. In this regard, the ratio of the first distance d1 to the second distance d2 is between about 1.0 and about 1.1. In some embodiments, the contact bottom surface 236B is above the gate bottom surface 208B. In this regard, the ratio of the second distance d2 to the third distance d3 is between about 0.7 and about 0.8. Because the contact bottom surface 236B does not extend as deeply into the first dielectric layer 216 as the gate bottom surface 208B, the parasitic capacitance between the source / drain contact 236 and the gate structure 208 can be reduced. In addition, Fig.11 and Fig.12 Gate bottom surface 208B is shown to be closer to substrate 202 than contact bottom surface 236B.

[0033] As above combined Figure 3 As described, the workpiece 200 may include a first air gap 221, a second air gap 222, and a third air gap 223 arranged in the first dielectric layer 216. In some embodiments, the source / drain contact 236 may be elongated along the X direction to contact more than one source / drain component 212 arranged in the X direction. In those embodiments, the source / drain contact 236 is shared by more than one source / drain component 212 or more than one transistor. Therefore, the source / drain contact 236 may span more than one source / drain component above different fin structures 204, or extend above the isolation structure 217. When conventional source / drain contact opening formation techniques are used, the source / drain contact opening may extend through the first dielectric layer 216 and merge with the air gap present in the first dielectric layer 216. In an embodiment of the present invention, the source / drain contact opening 232 may merge with the third air gap 223, but without reaching the first air gap 221 and the second air gap 222. As Fig.12As shown, while the first air gap 221 and the second air gap 222 remain close to the source / drain contact 236, the resulting source / drain contact 236 can fill the source / drain contact opening 232 and the third air gap 223. The source / drain contact 236 of the present invention does not extend downward into the ESL 214 disposed on the isolation feature 206. Fig.11 Here, the contact bottom surface 236B terminates within the first dielectric layer 216 between the two fin structures 204 and does not extend into the portion of the ESL 214 on the isolation feature 206. Fig.12 As shown, in the isolation region 30 , the contact bottom surface 236B terminates within the first dielectric layer 216 and does not extend into the portion of the ESL 214 over the isolation feature 206 . Fig.11 and Fig.12 Both show that the source / drain contacts 236 of the present invention do not extend into the isolation features 206 .

[0034] In one exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes: a first fin structure extending longitudinally along a first direction above a substrate; a first epitaxial component located above a source / drain region of the first fin structure; a gate structure arranged above a channel region of the first fin structure and extending along a second direction perpendicular to the first direction; and a source / drain contact located above the first epitaxial component. The bottommost surface of the gate structure is closer to the substrate than the bottommost surface of the source / drain contact.

[0035] In some embodiments, the gate structure further includes a topmost surface away from the substrate. The gate structure includes a first depth toward the substrate measured from the topmost surface of the gate structure, the source / drain contact includes a second depth toward the substrate measured from the topmost surface of the gate structure, and the ratio of the second depth to the first depth is between 0.7 and about 0.8. In some embodiments, the gate structure further includes a topmost surface away from the substrate, the source / drain contact includes a first bottommost surface toward the substrate, the first epitaxial component includes a second bottommost surface toward the substrate, and the ratio of the first distance between the topmost surface and the first bottommost surface to the second distance between the topmost surface and the second bottommost surface is between about 1.0 and about 1.1. In some embodiments, the semiconductor device may further include a second fin structure longitudinally aligned with the first fin structure along the first direction, an isolation component arranged between the first fin structure and the second fin structure along the first direction, a dielectric layer located above the isolation component, a second source / drain contact arranged in the dielectric layer, and a first air gap arranged in the dielectric layer. The first air gap is vertically arranged between the isolation component and the second source / drain contact. In some instances, the semiconductor device may further include an etch stop layer disposed between the isolation component and the dielectric layer. In some instances, the semiconductor device may further include a second air gap disposed in the dielectric layer and directly above the first air gap. The second source / drain contact is exposed in the second air gap. In some embodiments, the semiconductor device may further include a first isolation gate structure partially disposed above an end of the first fin structure, and a second isolation gate structure partially disposed above an end of the second fin structure. The dielectric layer and the second source / drain contact are disposed between the first isolation gate structure and the second isolation gate structure.

[0036] In another exemplary aspect, the present invention is directed to a method. The method includes receiving a workpiece, the workpiece including a fin structure, a gate structure disposed above a channel region of the fin structure, an epitaxial component disposed above a source / drain region of the fin structure, an etch stop layer disposed above the epitaxial component, and a first dielectric layer located above the etch stop layer. The method also includes depositing a capping layer above the workpiece; depositing a second dielectric layer above the capping layer; forming an etch mask above the second dielectric layer, the etch mask having an opening; performing a plurality of main etching processes through the opening of the etch mask to etch through the first dielectric layer, the capping layer, and the second dielectric layer; and performing a plurality of over-etch processes through the opening of the etch mask to etch through the etch stop layer.

[0037] In some embodiments, the capping layer is free of oxygen and the etching mask comprises tungsten carbide. In some embodiments, the plurality of main etching processes comprises a first main etching process and a second main etching process. In some embodiments, the first main etching process substantially etches through the second dielectric layer, and the second main etching process etches through the capping layer and the first dielectric layer and stops before reaching the etch stop layer. In some embodiments, the plurality of over-etching processes comprises a first over-etching process and a second over-etching process. In some embodiments, the first over-etching process etches through the etch stop layer to expose the epitaxial component, and the second over-etching process further etches back the stop layer to further expose the epitaxial component.

[0038] In yet another exemplary aspect, the present invention is directed to a method. The method includes receiving a workpiece, the workpiece including a fin structure, a gate structure disposed above a channel region of the fin structure, an epitaxial component disposed above a source / drain region of the fin structure, an etch stop layer disposed above the epitaxial component, and a first dielectric layer located above the etch stop layer. The method also includes depositing a capping layer above the workpiece, depositing a second dielectric layer above the capping layer; forming an etch mask above the second dielectric layer, the etch mask having an opening; performing a first main etch process through the opening of the etch mask to etch through at least a portion of the second dielectric layer; performing a second main etch process through the opening of the etch mask to etch through at least a portion of the capping layer and the first dielectric layer; performing a first over-etch process to expose a first surface of the epitaxial component; and performing a second over-etch process to recess the epitaxial component and the etch stop layer to expose a second surface of the epitaxial component. The second surface is larger than the first surface.

[0039] In some embodiments, each of the first main etching process and the second main etching process is a dry etching process, the first main etching process includes the use of a fluorine-containing etchant, and the second main etching process includes the use of a fluorine-containing etchant and a nitrogen-containing reagent. In some embodiments, the fluorine-containing etchant includes CF4, SF6, NF3, CH2F2, CHF3 or C2F6, and the nitrogen-containing reagent includes nitrogen or ammonia. In some embodiments, each of the first main etching process and the second main etching process is a wet etching process, the first main etching process includes the use of a dilute hydrofluoric acid (DHF) solution, and the second main etching process includes the use of DHF and ammonium fluoride. In some embodiments, the first over-etching process has a first etching selectivity to the etching stop layer, the second over-etching process has a second etching selectivity to the etching stop layer, and the first etching selectivity is greater than the second etching selectivity. In some instances, each of the first over-etching process and the second over-etching process is a dry etching process, the first over-etching process includes the use of a fluorine-containing etchant and a nitrogen-containing reagent, and the second over-etching process includes the use of a fluorine-containing etchant and a non-nitrogen-containing reagent. In some embodiments, the first over-etching process includes using a phosphoric acid solution, and the second over-etching process includes using CF4, SF6, NF3, CH2F2, CHF3, or C2F6.

[0040] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. It should be understood by those skilled in the art that the present invention can be easily used as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages as the embodiments described herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A first fin structure extending longitudinally along a first direction above the substrate; a first epitaxial component located above the source / drain region of the first fin structure; a gate structure, arranged above the channel region of the first fin structure and extending along a second direction perpendicular to the first direction; a first source / drain contact located above the first epitaxial component, wherein a bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the first source / drain contact; a dielectric layer over the substrate and adjacent to the first fin structure; and A second source / drain contact, wherein a bottommost surface of the second source / drain contact contacts the dielectric layer.

2. The semiconductor device according to claim 1, in, The gate structure further includes a topmost surface away from the substrate, wherein the gate structure comprises a first depth measured from the topmost surface of the gate structure toward the substrate, wherein the first source / drain contact comprises a second depth measured from the topmost surface of the gate structure toward the substrate, Wherein, a ratio of the second depth to the first depth is between 0.7 and 0.

8.

3. The semiconductor device according to claim 1, in, The gate structure further includes a topmost surface away from the substrate, wherein the first source / drain contact comprises a first bottommost surface facing the substrate, wherein the first epitaxial component comprises a second bottommost surface facing the substrate, Wherein, a ratio of a first distance between the topmost surface and the first bottommost surface to a second distance between the topmost surface and the second bottommost surface is between 1.0 and 1.

1.

4. The semiconductor device according to claim 1, further comprising: a second fin structure longitudinally aligned with the first fin structure along the first direction; an isolation component, arranged between the first fin structure and the second fin structure along the first direction; and a first air gap disposed in the dielectric layer, The dielectric layer is located above the isolation component, the second source / drain contact is arranged in the dielectric layer, and the first air gap is vertically arranged between the isolation component and the second source / drain contact.

5. The semiconductor device according to claim 4, further comprising: An etch stop layer is disposed between the isolation feature and the dielectric layer.

6. The semiconductor device according to claim 4, further comprising: a second air gap disposed in the dielectric layer and directly above the first air gap, Wherein, the second source / drain contact is exposed in the second air gap.

7. The semiconductor device according to claim 4, further comprising: a first isolation gate structure, partially disposed above an end of the first fin structure; as well as a second isolation gate structure, partially disposed above an end of the second fin structure, The dielectric layer and the second source / drain contact are arranged between the first isolation gate structure and the second isolation gate structure.

8. A method of forming a semiconductor device, comprising: A workpiece is received, the workpiece comprising: Fin structure, A gate structure is arranged above the channel region of the fin structure, an epitaxial component arranged above the source / drain region of the fin structure, an etch stop layer disposed above the epitaxial feature, and a first dielectric layer located above the etch stop layer; depositing a capping layer over the workpiece; depositing a second dielectric layer over the capping layer; forming an etching mask on the second dielectric layer, the etching mask having an opening; performing a plurality of main etching processes through the openings of the etching mask to etch through the first dielectric layer, the capping layer, and the second dielectric layer; and A plurality of over-etching processes are performed through the openings of the etch mask to etch through the etch stop layer.

9. The method according to claim 8, in, The covering layer does not contain oxygen, Wherein, the etching mask comprises tungsten carbide.

10. The method according to claim 8, wherein: The plurality of main etching processes include a first main etching process and a second main etching process.

11. The method according to claim 10, in, The first main etching process etches through the second dielectric layer, The second main etching process etches through the capping layer and the first dielectric layer and stops before reaching the etching stop layer.

12. The method according to claim 8, wherein: The plurality of over-etching processes include a first over-etching process and a second over-etching process.

13. The method according to claim 12, in, The first over-etching process etches through the etch stop layer to expose the epitaxial feature, Wherein, the second over-etching process further etches back the etching stop layer to further expose the epitaxial component.

14. A method of forming a semiconductor device, comprising: A workpiece is received, the workpiece comprising: Fin structure, A gate structure is arranged above the channel region of the fin structure, an epitaxial component arranged above the source / drain region of the fin structure, an etch stop layer disposed above the epitaxial feature, and a first dielectric layer located above the etch stop layer; depositing a capping layer over the workpiece; depositing a second dielectric layer over the capping layer; forming an etching mask on the second dielectric layer, the etching mask having an opening; performing a first main etching process through the opening of the etching mask to etch through at least a portion of the second dielectric layer; performing a second main etching process through the opening of the etching mask to etch through at least a portion of the capping layer and the first dielectric layer; performing a first over-etching process to expose a first surface of the epitaxial feature; and performing a second over-etching process to recess the epitaxial component and the etch stop layer to expose a second surface of the epitaxial component, The second surface is larger than the first surface.

15. The method according to claim 14, in, Each of the first main etching process and the second main etching process is a dry etching process, Wherein, the first main etching process includes using a fluorine-containing etchant, Wherein, the second main etching process includes using a fluorine-containing etchant and a nitrogen-containing reagent.

16. The method according to claim 15, in, The fluorine-containing etchant includes CF4, SF6, NF3, CH2F2, CHF3 or C2F6, Wherein, the nitrogen-containing reagent includes nitrogen or ammonia.

17. The method according to claim 14, in, Each of the first main etching process and the second main etching process is a wet etching process, Wherein, the first main etching process includes using a dilute hydrofluoric acid (DHF) solution, Wherein, the second main etching process includes using dilute hydrofluoric acid and ammonium fluoride.

18. The method according to claim 14, in, The first over-etching process has a first etch selectivity to the etch stop layer, wherein the second over-etching process has a second etching selectivity to the etching stop layer, Wherein, the first etching selectivity is greater than the second etching selectivity.

19. The method according to claim 14, in, Each of the first over-etching process and the second over-etching process is a dry etching process, Wherein, the first main etching process includes using a fluorine-containing etchant and a nitrogen-containing reagent, Wherein, the second main etching process includes using a fluorine-containing etchant and does not contain a nitrogen-containing agent.

20. The method according to claim 14, in, The first over-etching process includes using a phosphoric acid solution, Wherein, the second over-etching process includes using CF4, SF6, NF3, CH2F2, CHF3 or C2F6.

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