Semiconductor Device and Method of Forming the Same

Abstract

A semiconductor device includes a plurality of fin structures, each fin structure protruding vertically upward from a substrate and extending in a first direction in a top view. A gate structure is disposed above the fin structures. In the top view, the gate structure extends in a second direction. The second direction is different from the first direction. The fin structures have a fin pitch equal to the sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of fin structures in the second direction. End segments of the gate structure extend beyond an edge of the nearest fin structure in the second direction. The end segments have a tapered profile in the top view or are at least four times as long as the fin pitch in the second direction. According to other embodiments of the present application, a method of forming a semiconductor device is also provided.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced multiple generations of ICs, each of which has smaller and more complex circuits than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases while the geometric size (i.e., the smallest element (or line) that can be made using a manufacturing process) decreases. This scaling process generally provides many benefits by increasing production efficiency and reducing related costs. This scaling process also increases the complexity of processing and manufacturing ICs.

[0003] For example, the manufacturing process for performing the gate structure that defines a transistor may generate residues or unwanted by-products. As device sizes continue to shrink, the risk of electrical short circuits caused by such residues or by-products may also increase, which may lead to a decrease in yield or poor device performance.

[0004] Therefore, although conventional methods of forming gate structures have generally been sufficient, they are not satisfactory in all respects. Summary of the Invention

[0005] According to an embodiment of the present application, a semiconductor device is provided, including: a plurality of fin structures, each fin structure protruding vertically upward from a substrate and extending in a first direction in a top view; and a gate structure disposed above the fin structures, wherein the gate structure extends in a second direction in the top view, and the second direction is different from the first direction; wherein: the fin structures have a fin pitch equal to the sum of: the dimension of one of the fin structures in the second direction and the distance between an adjacent pair of fin structures in the second direction; an end segment of the gate structure extends beyond the edge of the nearest fin structure in the second direction; and the end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

[0006] According to another embodiment of the present application, a method of forming a semiconductor device is provided, including: forming a plurality of first active regions on a wafer, each extending horizontally along a first direction, wherein the first active regions include first fin structures each protruding vertically upward above a substrate; depositing a dummy gate layer above the first fin structures; patterning the dummy gate layer into at least first dummy gate structures through an etching process using an etchant, wherein the etching process generates etching by-products containing elements of the dummy gate layer and the etchant, and wherein the first dummy gate structures extend horizontally along a second direction different from the first direction; performing a cleaning process to remove the etching by-products, wherein after performing the cleaning process, there are no etching by-products between the first fin structures; and replacing the first dummy gate structures with metal-containing gate structures, wherein in a top view, the metal-containing gate structures substantially inherit the shape of the first dummy gate structures.

[0007] According to yet another embodiment of the present application, a method of forming a semiconductor device is provided, including: receiving an integrated circuit (IC) layout plan that includes a plurality of fin structures each extending along a first direction and a gate structure extending along a second direction different from the first direction, wherein in a top view, the gate structure overlaps the fin structures; and modifying the IC layout plan at least in part by: elongating an end segment of the gate structure that extends beyond the fin structures in the second direction; or contracting an end segment of the gate structure in the first direction.

[0008] Embodiments of the present application relate to optimizing the transistor gate profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When read in conjunction with the accompanying drawings, the present invention can be better understood from the following detailed description. It should be emphasized that, according to standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0010] Figure 1A is a perspective view of an IC device in the form of a FinFET according to various aspects of the present disclosure.

[0011] Figure 1B is a top plan view of an IC device in the form of a FinFET according to various aspects of the present disclosure.

[0012] Figure 1C is a perspective view of an IC device in the form of a GAA device according to various aspects of the present disclosure.

[0013] Figures 2 - 18 is a top view of various embodiments of an IC device at various stages of manufacture according to various aspects of the present disclosure.

[0014] Figures 19 - 20 is a flowchart showing a method of manufacturing a semiconductor device in accordance with various aspects of the present disclosure.

[0015] Figure 21A and Figure 21B shows a top - view profile of different patterns on a photolithography mask and their corresponding patterns on a wafer.

[0016] Figure 22 is a flowchart of a method of manufacturing a multi - gate device or portion provided in accordance with one or more aspects disclosed in U.S. Patent No. 9,887,269 and including an isolation region under a gate. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity, but in and of itself does not indicate a relationship between the various embodiments and / or configurations being discussed.

[0018] In addition, the present invention may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity, but in and of itself does not indicate a relationship between the various embodiments and / or configurations being discussed. Further, in the present invention below, a component being formed on, connected and / or coupled to another component may include embodiments where the components are formed in direct contact, and may also include embodiments where additional components are formed inserted between the components such that the components may not be in direct contact. Moreover, for ease of understanding, spatially relative terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "under", "below", "on", "off", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to describe the relationship of a component of the present invention to another component. The spatially relative terms are intended to cover different orientations of a device including the components. Further still, when a numerical value or range of numerical values is described using "about", "approximate", etc., the term is intended to cover values within a reasonable range including the described numerical value, such as + / - 10% of the described numerical value or other values as understood by a person skilled in the art. For example, the phrase "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0019] The present disclosure generally relates to semiconductor devices, and more particularly to field effect transistors (FETs) such as planar FETs, three-dimensional finFETs, or gate-all-around (GAA) devices. One aspect of the present disclosure relates to forming a dipole layer directly on an interface layer in a gate structure and then using multiple interface layer patterning processes to achieve different threshold voltages for different devices. This improves the flexibility in adjusting the threshold voltage and reduces the gate resistance as compared to conventional devices, which will be discussed in more detail below.

[0020] Figure 1A and Figure 1B respectively show a three-dimensional perspective view and a top view of a portion of an integrated circuit (IC) device 90. The IC device 90 can be an intermediate device fabricated during the processing of an IC or a portion thereof, and can include static random access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. Unless otherwise required, the present disclosure is not limited to any particular number of devices or device regions or any particular device configuration. For example, although the illustrated IC device 90 is a three-dimensional FinFET device, the concepts of the present disclosure can also be applied to planar FET devices or GAA devices.

[0021] Reference Figure 1A, the IC device 90 includes a substrate 110. The substrate 110 may include: elemental (single-element) semiconductors, such as silicon, germanium, and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 may be a single-layer material with a uniform composition. Alternatively, the substrate 110 may include multiple material layers with similar or different compositions suitable for IC device manufacturing. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions, such as source / drain regions, may be formed in or on the substrate 110. The doped regions may be doped with an n-type dopant such as phosphorus or arsenic and / or a p-type dopant such as boron, depending on the design requirements. The doped regions may be directly formed on the substrate 110 in the form of a p-well structure, an n-well structure, a dual-well structure, or using a raised structure. The doped regions may be formed by implanting dopant atoms, in-situ doping epitaxial growth, and / or other suitable techniques.

[0022] A three-dimensional active region 120 is formed on the substrate 110. The active region 120 is an elongated fin-like structure that protrudes upward from the substrate 110. Thus, hereinafter, the active region 120 may be interchangeably referred to as the fin 120 or the fin structure 120. The fin structure 120 may be fabricated using suitable processes including photolithography and etching processes. The photolithography process may include: forming a photoresist layer on the substrate 110; exposing the photoresist to a pattern; performing a post-exposure bake process; and developing the photoresist to form a masking element (not shown) including the resist. Then, the masking element is used to etch a groove in the substrate 110, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed by a double-patterning or multi-patterning process. Generally, the double-patterning or multi-patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch smaller than that obtainable using a single, direct photolithography process. As an example, a layer may be formed above the substrate and patterned using a photolithography process. A spacer is formed adjacent to the patterned layer using a self-alignment process. Then, the layer is removed, and the remaining spacer or mandrel may then be used to pattern the fin structure 120.

[0023] The IC device 90 further includes source / drain components 122 formed above the fin 120. The source / drain components 122 may include an epitaxial layer grown epitaxially on the fin structure 120.

[0024] IC device 90 further includes an isolation structure 130 formed over a substrate 110. The isolation structure 130 electrically isolates the various components of the IC device 90. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable materials. In some embodiments, the isolation structure 130 may include a shallow trench isolation (STI) component. In one embodiment, the isolation structure 130 is formed by etching trenches in the substrate 110 during the formation of the fin structures 120. The trenches can then be filled with the above-described isolation materials and then a chemical mechanical planarization (CMP) process is performed. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures may also be implemented as the isolation structure 130. Alternatively, the isolation structure 130 may include a multi-layer structure, e.g., having one or more thermal oxide liner layers.

[0025] IC device 90 further includes a gate structure 140 that is formed over and engages with each fin 120 on three sides in the channel region of each fin 120. The gate structure 140 can be a dummy gate structure (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or they can be a HKMG structure including a high-k gate dielectric and a metal gate electrode, where the HKMG structure is formed by replacing the dummy gate structure. Although not shown herein, the gate structure 140 may include additional material layers such as an interface layer, a capping layer, other suitable layers, or a combination thereof over the fin 120.

[0026] Reference Figure 1B , a plurality of fins 120 are longitudinally oriented in the X direction, and a plurality of gate structures 140 are longitudinally oriented in the Y direction (i.e., generally perpendicular to the direction of the fins 120). In many embodiments, the IC device 90 includes additional components such as gate spacers disposed along the sidewalls of the gate structure 140, a hard mask layer disposed over the gate structure 140, and many other components.

[0027] It should also be understood that the various aspects of the present disclosure discussed below can be applied to multi-channel devices such as gate-all-around (GAA) devices. Figure 1C A three-dimensional perspective view of an exemplary GAA device 150 is shown. For reasons of consistency and clarity, Figure 1C and Figures 1A - 1BSimilar components in [the figure] will be labeled the same. For example, the fin structure 120 rises vertically upward from the substrate 110 in the Z direction. The isolation structure 130 provides electrical isolation between the fin structures 120. The gate structure 140 is located above the fin structures 120 and above the isolation structure 130. The mask 155 is located above the gate structure 140, and the gate spacer 160 is located on the sidewalls of the gate structure 140. The capping layer 165 is formed above the fin structures 120 to protect the fin structures 120 from oxidation during the formation of the isolation structure 130. A plurality of nanostructures 170 are disposed above each fin structure 120. The nanostructures 170 may include nanosheets, nanotubes, or nanowires or some other type of nanostructure that extends horizontally in the X direction. The portion of the nanostructure 170 below the gate structure 140 may be used as the channel of the GAA device 150. The dielectric inner spacer 175 may be disposed between the nanostructures 170. Additionally, although not shown for simplicity, each nanostructure 170 may be circumferentially surrounded by a gate dielectric layer. In the illustrated embodiment, the portions of the nanostructures 170 outside the gate structure 140 may be used as the source / drain components of the GAA device 150. However, in some embodiments, a continuous source / drain component may be epitaxially grown above the portions of the fin structures 120 that are outside the gate structure 140. In any case, a conductive source / drain contact 180 may be formed above the source / drain component to provide electrical connectivity thereto. The interlayer dielectric (ILD) 185 is formed above the isolation structure 130 and around the gate structure 140 and the source / drain contact 180.

[0028] Additional details related to the fabrication of GAA devices are disclosed in U.S. Patent No. 10,164,012, entitled "Semiconductor Device and Manufacturing Method Thereof," issued on December 25, 2018, U.S. Patent No. 10,361,278, entitled "Method of Manufacturing a Semiconductor Device and a Semiconductor Device," issued on July 23, 2019, and U.S. Patent No. 9,887,269, entitled "Multi-Gate Device and Method of Fabrication Thereof," issued on February 6, 2018, the disclosures of each of which are incorporated herein by reference in their entirety. To the extent that the present disclosure relates to fin structures or FinFET devices, such discussions may equivalently apply to GAA devices.

[0029] In one embodiment, the fabrication of a GAA device will be described below (see U.S. Patent No. 10,164,012). On a substrate, a first semiconductor layer is formed along a first direction and sandwiched between second semiconductor layers. The first semiconductor layer and the second semiconductor layers are patterned to form a fin structure such that the fin structure includes a sacrificial layer formed of the second semiconductor layer and a channel layer formed of the first semiconductor layer. A sacrificial gate structure is formed on the fin structure such that the sacrificial gate structure covers a portion of the fin structure and the remaining portion of the fin structure is kept exposed. The remaining portion of the fin structure not covered by the sacrificial gate structure is removed. The sacrificial layer is recessed horizontally such that the edges of the sacrificial layer are located below the sides of the sacrificial gate structure. A liner epitaxial layer is formed at least on the recessed surface of the sacrificial layer. Source / drain regions are formed. The sacrificial gate structure is removed. After removing the sacrificial gate structure, the sacrificial layer in the fin structure is removed such that the channel layer is exposed. A gate dielectric layer and a gate electrode layer are formed around the exposed channel layer.

[0030] In one embodiment, the fabrication of a GAA device will be described below (see U.S. Patent No. 10,361,278). A fin structure is formed, wherein the fin structure includes alternately stacked first semiconductor layers and second semiconductor layers. A sacrificial gate structure is formed above the fin structure. The source / drain regions of the fin structure not covered by the sacrificial gate structure are etched, thereby forming source / drain spacers. The first semiconductor layer is etched laterally through the source / drain spacers. A first insulating layer is formed in the source / drain spacers, at least on the etched first semiconductor layer. A source / drain epitaxial layer is formed in the source / drain spacers such that an air gap is formed between the source / drain epitaxial layer and the first insulating layer. In another embodiment, a fin structure of alternately stacked first semiconductor layers and second semiconductor layers is formed. A sacrificial gate structure is formed above the fin structure. The first semiconductor layer is removed from the source / drain regions of the fin structure not covered by the sacrificial gate structure. A first insulating layer is formed around the second semiconductor layer in the source / drain regions and on the lateral ends of the first semiconductor layer. The first insulating layer is partially removed from the second semiconductor layer in the source / drain regions. A source / drain epitaxial layer is formed on the source / drain regions such that an air gap is formed between the source / drain epitaxial layer and the lateral ends of the first semiconductor layer.

[0031] In one embodiment, the following will be referred to Figure 22The fabrication of a GAA device is described (see U.S. Patent No. 9,887,269). Fabrication method 2200 begins at step 2202 by implanting an anti-punch through (APT) implant into the substrate. Fabrication method 2200 then proceeds to step 2204, where an epitaxial stack is formed on the APT-implanted substrate. The epitaxial stack includes a first epitaxial layer of a first composition interposed by a second epitaxial layer of a second composition. Fabrication method 2200 proceeds to step 2206, where a plurality of fins extending from the substrate are formed. Fabrication method 2200 proceeds to step 2208, where an oxidation process is performed to form isolation regions within the fin components. Fabrication method 2200 proceeds to step 2210, where shallow trench isolation (STI) features are formed between the fins. Fabrication method 2200 proceeds to step 2212, where the STI features are recessed to form STI features, and fins are inserted to provide fins extending over the recessed STI features. Fabrication method 2200 proceeds to step 2214, where a dummy dielectric layer is formed on the fins. Fabrication method 2200 proceeds to step 2216, where a dummy gate stack is formed. The dummy gate stack may also define source / drain (S / D) regions of the fins. Fabrication method 2200 proceeds to step 2218, where a spacer layer is formed on the substrate. Fabrication method 2200 proceeds to step 2220, where the spacer layer is etched back. Fabrication method 2200 proceeds to step 2222, where the first epitaxial layer is removed from the S / D regions. Fabrication method 2200 proceeds to step 2224, where an internal spacer layer is formed on the substrate, including on each of the second epitaxial layers surrounding the S / D regions. Fabrication method 2200 proceeds to step 2226, where this internal spacer layer is etched back. Fabrication method 2200 proceeds to step 2228, where S / D features are formed in the S / D regions. Fabrication method 2200 proceeds to step 2230, where a contact etch stop layer (CESL) is formed on the substrate. Fabrication method 2200 proceeds to step 2232, where an inter-layer dielectric (ILD) layer is formed on the substrate. Fabrication method 100 proceeds to step 2234, where the previously formed remaining dummy gate stack is removed to form a gate trench in the channel region. Fabrication method 2200 proceeds to step 2236, which removes the dummy dielectric layer and the first epitaxial layer from the fins within the gate trench. Fabrication method 2200 proceeds to step 2238, where a final gate stack is formed within the gate trench, including surrounding nanowires. Fabrication method 2200 proceeds to step 2240, where a patterned hard mask is formed on the substrate. Fabrication method 2200 proceeds to step 2242, where the ILD layer is removed via openings and portions of the S / D features to form source / drain (S / D) contact trenches.The manufacturing method 2200 proceeds to step 2244, where a conductive layer is deposited in the shared S / D contact trench to form a source / drain (S / D) conductive metal.

[0032] Figures 2 - 13 Schematic partial top views showing different portions of an IC device at various stages of manufacture. For example, Figures 2 - 13 Schematic partial top views showing IC devices 200A, 200B, 200C, 200D, and 200E. In some embodiments, IC devices 200A, 200B, 200C, 200D, and 200E may be fabricated on the same wafer (or the same IC chip), but they may be fabricated using different processes. For reasons of consistency and clarity, similar components that appear in Figures 2 - 13 as well as Figures 1A - 1B will be labeled the same.

[0033] Referring to Figure 2 , IC device 200A includes a plurality of active regions, such as the fin structures 120 discussed above with reference to Figures 1A - 1B . The fin structures 120 each extend in the X direction, and they are separated from each other in the Y direction. The fin structures 120 have a pitch 210 measured in the Y direction, which can be the sum of the spacing 220 between two adjacent fin structures 120 and the width 230 of one of the fin structures 120 in the Y direction. In other words, pitch 210 = spacing 220 + width 230.

[0034] In the Figure 2 top view, IC device 200A includes a gate structure 240 covering the fin structures 120. It can be understood that in a cross-sectional view or a three-dimensional view, the gate structure 240 will be formed above and partially surrounding the fin structures 120 in a manner similar to the way the gate structure 140 in Figure 1A is formed above and around the fin structures. In some embodiments, the gate structure 240 includes a dummy gate structure, and may be referred to interchangeably hereinafter. For example, in some embodiments, the dummy gate structures 240 may each include a dummy polysilicon gate electrode and may include a dummy silicon oxide gate dielectric. As the dummy gate structure 240, the dummy polysilicon gate electrode (and the dummy silicon oxide gate dielectric, if included) will be removed in a gate replacement process and replaced with a high-k metal gate (HKMG) structure including a metal gate electrode and a high-k gate dielectric. The HKMG structure may substantially adopt or inherit the top view shape or profile of the dummy gate structure 240.

[0035] It should be understood that in Figure 2In the figure, only a part of each pseudo-gate structure 240 is shown for space considerations. For example, each pseudo-gate structure 240 may include an elongated body segment connected by two opposite end segments 240A. In some embodiments, the end segment 240A may refer to the part of the pseudo-gate structure 240 that extends beyond the edge of the outermost fin structure 120. For example, the end segment 240A may have an outermost end 250 in the Y direction, spaced apart from the nearest fin structure 120 by a distance 255. In some embodiments, the distance 255 is less than about 3 times the pitch 210 associated with the fin structure 120. In some embodiments, the distance 255 is between about 0.5 times and about 3 times the pitch 210.

[0036] Note that only one such end segment 240A and a part of the body segment are shown. For space considerations, the other end segment (e.g., opposite the end segment 240A in the Y direction) and the rest of the body segment are omitted in the Figure 2 illustration.

[0037] As Figure 2 shown, the end segment 240A may have an outwardly protruding profile (e.g., protruding in both the X and Y directions). This may be an accidental result of the lithography effect. More specifically, the pseudo-gate structure 240 can be formed by depositing a pseudo-gate layer (e.g., a polysilicon layer) over the substrate (including over the fin structure 120), defining a mask structure (e.g., a photoresist structure and / or a hard mask structure) over the pseudo-gate layer, and etching the pseudo-gate layer while using the mask structure as an etch mask. The shape or profile of the mask structure is defined by the mask pattern of the lithography mask. The part of the pseudo-gate layer under the mask structure is protected from etching, while the exposed part of the pseudo-gate layer is etched away. The remaining part of the pseudo-gate layer forms the pseudo-gate structure 240.

[0038] In many cases, the mask pattern on the lithography mask may have a rectangular or polygonal profile. In older technology generations with much larger device sizes, the pseudo-gate structure could mainly inherit the top-view shape and / or profile of the mask pattern on the lithography mask and thus could have a profile similar to a rectangle or polygon. However, as device sizes continue to shrink, the optical effects of the lithography process may distort the profile of the pattern formed on the wafer. For example, the mask structure (formed over the pseudo-gate layer) according to the mask pattern on the lithography mask may not maintain a rectangular / polygonal profile but may be formed to have an outwardly protruding profile at the end segments. Thus, the end segment 240A of the pseudo-gate structure 240 may also have an outwardly protruding profile, as Figure 2 shown.

[0039] Note that the end segments 240A do not need to have an outwardly protruding profile. In some cases, the end segments 240A may each have a top view profile that is more similar to a rectangle, but with slightly curved edges (e.g., at the corners), such as Figure 3 as shown in

[0040] Referring back to Figure 2 , due to defects in the lithography process, residues or by-products 260 may be formed around the end segments 240A of the dummy gate structure 240 and even a portion of the body segment. More specifically, the etching process used to etch the dummy gate layer (while the mask structure serves as an etch mask) as discussed above may use a gas containing fluorine (F), chlorine (Cl), and / or bromine (Br). These gases may react with the polysilicon material of the dummy gate layer to produce residues or by-products 260, which may contain elements of polysilicon and / or the gas. For example, in some cases, the residues or by-products 260 may contain SiF4 or Si2OCH6.

[0041] Portions of the residues or by-products 260 may be dispersed as particles 270 around the dummy gate structure 240. Generally, the manufacturing tools used to fabricate the IC device 200A may employ a suction or fan mechanism to remove the residues or by-products 260 and the particles 270. Removing the residues or by-products 260 is not too difficult because, at this stage of manufacturing, the residues or by-products 260 are not typically surrounded by a densely packed structure. However, removing the particles 270 may be more difficult, especially if the particles 270 are trapped between adjacent fin structures 120 (which may resemble two adjacent vertically protruding walls surrounding the particles 270). For example, the vertically protruding fin structures 120 may interfere with the suction used to remove the particles 270, which may result in incomplete removal of the particles 270.

[0042] Incomplete removal of the particles 270 may cause an electrical shorting problem. For example, in a gate replacement process to be performed later, the dummy gate structure 240 is replaced with an HKMG structure. Since any remaining particles 270 and the dummy gate structure 240 have a similar material composition (e.g., both contain polysilicon), the remaining particles 270 can be replaced by the HKMG structure even if not intentionally. Effectively, an undesired "extra" HKMG structure will be formed at the location corresponding to the remaining particles 270. These "extra" HKMG structures may short-circuit the components of the IC device 200A. For example, if the remaining particle 270 is located between the fin structures 120 and / or overlaps with the location of the source / drain contact to be formed (which is typically between adjacent dummy gate structures 240), the "extra" HKMG structure corresponding to the remaining particle 270 may cause an undesired electrical short between the HKMG structure and the source / drain contact. Such an electrical short may degrade the device performance, such as the voltage breakdown (also known as breakdown voltage) VBD, and may result in a lower yield.

[0043] It should be understood that for some structures, such an electrical short may not be that important. For example, for a device with a relatively large spacing between adjacent gate structures, the particles 270 may be easier to remove, and even the unremoved particles 270 can still be positioned far enough away from sensitive structures such as the fin structures 120 and / or the source / drain contacts. Thus, even if there are "extra" HKMG structures, an undesired electrical short may not occur. As another example, if a planar structure instead of a fin structure is used to implement the IC device 200A, since there may be no vertically standing walls (e.g., corresponding to the vertically protruding fin structures 120) around the particles 270, the particles 270 will be easier to remove. Thus, when performing the gate replacement process, the planar device may not have particles 270. In this way, no "extra" HKMG gate structures will be formed for the planar device, and thus no undesired electrical short will occur.

[0044] However, since the electrical short discussed above may be a problem for IC devices and / or FinFET devices (including multi-channel gate-all-around (GAA) devices) with closer spacing (e.g., higher pattern density), the present disclosure attempts to optimize the shape and / or profile of the gate structure to minimize the risk of electrical short. For example, Figure 4 is a schematic partial top view of an IC device 200B according to an embodiment, which shows an optimized dummy gate shape profile. For reasons of consistency and clarity, similar components that appear in Figures 2 - 4 will be labeled the same.

[0045] Referring to Figure 4 , the IC device 200B includes fin structures 120 and in a manner similar to Figure 1AA plurality of dummy gate structures 300 are formed above and partially surrounding the fin structure 120 in a similar manner as shown. The dummy gate structure 300 has an end segment 300A that extends beyond the edge of the outermost fin structure 120 in the Y direction. Different from Figure 2 the end segment 240A of the dummy gate structure 240 in Figure 4 the end segment 300A has a top view profile that tapers inward. For example, the end segment 300A may have a tip 310, which is the farthest point of the end segment 300A from the fin structure 120. The end segment 300A may also have a dimension 320 (measured in the X direction), which varies according to the position in the end segment 300A or according to the distance from the nearest fin structure 120. At the same time, the dimension (measured in the X direction) of the main body 300B of the dummy gate structure 300 remains relatively constant, regardless of the position within the main body.

[0046] In Figure 4 the embodiment shown, the dimension 320 gradually shrinks as the distance from the fin structure 120 increases (i.e., as the end segment 300A extends beyond the fin structure 120). For example, at a first position closer to the fin structure 120, the dimension 320 may have a first value. At a second point farther from the fin structure 120 than the first position, the dimension 320 may have a second value that is less than the first value. In some embodiments, the tapered profile of the end segment 300A is curved and substantially smooth, that is, the dimension 320 may continuously and gradually decrease as the distance from the fin structure 120 increases. In other embodiments, the tapered profile of the end segment 300A may not be completely smooth, so that it may have some flat or serrated edges (e.g., if the contraction of the dimension 320 is discontinuous). For example, in a top view, the shape of the end segment 300A may be similar to a triangle or similar to a polygon, as long as the part farther from the fin structure 120 is narrower in the X direction than the part closer to the fin structure 120.

[0047] In some embodiments, the tapered profile of the end segment 300A can also manifest itself, since the end segment 300A is on average narrower than the body 300B of the pseudo-gate structure 300. For example, the end segment 300A can have a first average width (measured along the X direction), which can be the average of all the different dimensions 320 taken at different positions of the end segment 300A. At the same time, the body 300B can have a second average width (measured along the X direction), which can be the average of all the different dimensions 330 taken at different positions of the body 300B. Since the end segment 300A is tapered, the first average width of the end segment 300A is substantially less than the second average width of the body 300B. In some embodiments, the ratio between the first average width and the second average width is in the range of about 0.5 and about 0.78. The above ratio range is not randomly selected, but is specifically configured to ensure that the curvature or taper of the end segment 300A is sufficient to allow substantially complete removal of the particles 270, while also ensuring that the end segment 300A is not too narrow to adversely affect the function of the gate.

[0048] The inwardly tapered profile of the end segment 300A helps to alleviate the problems caused by the particles 270. For example, even if the particles 270 are formed, it is easier to remove them from the IC device 200B during the cleaning process performed after the patterning of the pseudo-gate structure 300. This is because the inwardly tapered profile of the end segment 300A effectively creates a larger and more void area for the particles 270. In this way, the particles 270 are less likely to be trapped (e.g., stuck between adjacent pseudo-gate structures 300 or between fin structures 120). Therefore, the particles 270 generated during the manufacture of the IC device 200B can be more easily sucked away or otherwise removed, thus avoiding the potential problems caused by the presence of the remaining particles 270 discussed above in connection with Figure 2 In some embodiments, the tapered profile of the end segment 300A allows all of the particles 270 (and by-products 260) to be removed during the cleaning process.

[0049] Figure 5 is a schematic partial top view of an IC device 200C according to another embodiment, which shows an optimized pseudo-gate shape profile. For reasons of consistency and clarity, similar components that appear in Figures 2 - 5 will be labeled the same. Referring to Figure 5 , the IC device 200C includes fin structures 120 and a plurality of pseudo-gate structures 350 formed above the fin structures 120 and partially surrounding the fin structures 120 in a manner similar to that shown in Figure 1A .

[0050] The pseudo-gate structure 350 has an end segment 350A that extends beyond the outermost fin structure 120 in the Y direction. Although the end segment 350A is shown having an outwardly protruding shape or profile (e.g., as compared toFigure 2 The end segment 240A is somewhat similar), but it should be understood that in other embodiments, they may have a rectangular profile (e.g., similar to Figure 3 the end segment 240A in Figure 4 ), or a tapered profile (e.g., similar to Figure 2 ). However, different from the end segments 240A and / or 300A, the end segment 350A extends further beyond the nearest fin structure 120. In other words, the end segment 350A extends or stretches longer in the Y direction than the end segment 240A. For example, the outermost tip 310 of the end segment 350A is spaced apart from the edge of the nearest fin structure 120 by a distance 360. In some embodiments, the distance 360 is at least 4 times the pitch 210 associated with the fin structure 120. In some embodiments, the distance 360 ranges between about 4 times and about 8 times the pitch 210. In contrast, the distance 255 associated with the dummy gate structure 240 (see

[0051] ) is less than about 3 times the pitch 210. The above ranges are not randomly selected, but are specifically configured such that the distance 360 is long enough to ensure that the particles 270 (if any are generated) are located far enough from the fin structure 120 so that, in accordance with various aspects of the present disclosure, they can be easily removed. At the same time, the above ranges also ensure that the distance 360 is not so long as to waste an excessive amount of chip space / area. In other words, the above ranges are optimized such that the removal of unwanted particles 270 is facilitated without sacrificing too much valuable chip space. Figure 2 The fact that the end segment 350A extends or stretches longer also helps to alleviate the above problems caused by the particles 270. For example, even if particles 270 are formed, due to the now greater distance from the fin structure 120, it is less likely that particles 270 will form near the fin structure 120. This makes it easier to remove the particles 270 because, compared to the particles in the case of

[0052] It should be understood that in some embodiments, Figure 4 the features of the embodiments of Figure 5 (e.g., the tapered profile of the end segment of the gate) and Figure 6 the features of the embodiments of Figure 4 andFigure 5 Schematic partial top view of an IC device 200D of an embodiment of an element of an embodiment, showing an optimized dummy gate shape profile. For reasons of consistency and clarity, similar components appearing in Figures 2 - 6 will be labeled the same.

[0053] Referring to Figure 6 , the IC device 200D includes a fin structure 120 and a plurality of dummy gate structures 400 formed over and partially surrounding the fin structure 120 in a manner similar to that shown in Figure 1A . The dummy gate structures 400 have end segments 400A, each of which has an inwardly tapering profile, similar to the embodiment shown in Figure 4 . For example, the dimension 420 of the end segment 400A shrinks more as it gets closer to the tip 410 of the end segment 400A (e.g., as the end segment 400A extends further beyond the nearest fin structure 120). At the same time, the end segment 400A also extends or spreads in a manner similar to the embodiment shown in Figure 5 . For example, the distance 430 between the tip 410 and the edge of the nearest fin structure 120 is at least 4 times the pitch 210 associated with the fin structure 120. Due to these unique physical properties, it is easier to remove particles 270 during cleaning, and any remaining particles 270 (and the HKMG-containing structures they create) are less likely to cause electrical shorting problems later.

[0054] Figure 7 Schematic partial top view of an IC device 200E according to another embodiment, showing an optimized dummy gate shape profile. For reasons of consistency and clarity, similar components appearing in Figures 2 - 7 will be labeled the same. In Figure 7 , the IC device 200E includes a fin structure 120 and a plurality of dummy gate structures 450 formed over and partially surrounding the fin structure 120 in a manner similar to that shown in Figure 1A . However, the dummy gate structures 450 lack the end segments of the dummy gate structures 240, 300, 350, and 400. In other words, the dummy gate structures 450 are each formed as a continuous dummy gate structure extending along the length of the die (e.g., the die of a wafer) in the Y direction, rather than as separate gate structures such as the dummy gate structures 240, 300, 350, and 400. However, for space considerations, Figure 7 only a portion of each of the continuous dummy gate structures 450 that are continuous in the Y direction may be shown, but it should be understood that each of the continuous dummy gate structures 450 may extend beyond the range shown in Figure 7 .

[0055] Subsequently, after forming the HKMG structure to replace the dummy gate structure 450, a dielectric structure 470 (also referred to as a metal cut gate or CMG component) can be formed to divide the HKMG structure into individual HKMG gate structures. In this way, the dummy gate structure does not have end segments similar to the end segments 240A, 300A, 350A, or 400A, which reduces the likelihood of forming particles 270. Even if particles 270 are formed, they are still located farther from the fin structure 120 and are easier to remove, thus alleviating the electrical short circuit problem discussed above. It should be understood that the dielectric structure 470 has not been formed at the manufacturing stage shown in Figure 7 and it is included in Figure 7 merely to indicate the location where the continuous gate structure can be "cut". Thus, the edges / boundaries of the dielectric structure 470 are shown as dashed lines herein.

[0056] Figures 8 - 13 Schematic partial top views of IC devices 200A, 200B, 200C, 200D, and 200E are shown at a later stage of manufacturing, for example, after a gate replacement process has been performed to replace the dummy gate structure discussed above with an HKMG structure. For example, an interlayer dielectric (ILD) can be formed around the above dummy gate structure. The dummy gate structure can be removed using an etching process that leaves openings (trenches) in the ILD. These openings or trenches are then filled with the metal gate electrodes of the HKMG structure. In some embodiments, if the dummy gate structure includes a dummy gate dielectric layer (e.g., a silicon oxide gate dielectric), the dummy gate dielectric layer will also be replaced by a high-k gate dielectric layer as part of the HKMG structure.

[0057] Referring to Figures 8 - 9 , an HKMG structure 540 is formed to replace the dummy gate structure 240. The HKMG structure 540 substantially inherits the top view shape or profile of the dummy gate structure 240. For example, the HKMG structure 540 can have end segments 540A that protrude outward in the X direction and / or Y direction, and the distance 555 between the tips 550 of the end segments 540A can be less than approximately three times the pitch 210 of the fin structure 120. In other words, the end segments 540A of the HKMG structure 540 do not taper inward, and they do not elongate in the Y direction.

[0058] Source / drain contact members 500 can be formed between the HKMG structures 540. The source / drain contact members 500 provide electrical connections to the underlying source / drain components. If the particles 270 discussed above are not removed and are subsequently incorporated into a structure containing HKMG (such as structure 570), they may cause an electrical short circuit with the source / drain contact members 500, which may lead to insufficient device performance or device defects, such as with respect to the breakdown voltage (VBD).

[0059] Now refer to Figure 10 , an HKMG structure 600 is formed to replace the dummy gate structure 300. The HKMG structure 600 substantially inherits the top-down shape or profile of the dummy gate structure 300. In this way, the HKMG structure 600 can have an end segment 600A that tapers inwardly similar to the end segment 300A. For example, the end segment 600A can have a dimension 620 (measured in the X direction) that contracts more as it approaches the tip 610 of the end segment 600A (e.g., the farther the end segment 600A extends beyond the edge of the nearest fin structure 120), while the dimension 630 of the body segment 600B remains relatively the same throughout the body. As described above, the contraction of the end segment 600A helps remove particles 270 during the cleaning performed after defining the dummy gate structure 300, and reduces the likelihood of an electrical short caused by an HKMG-containing structure corresponding to any particles 270 remaining after cleaning. In this way, the likelihood of an electrical short with the conductive source / drain contact 500 is smaller. In some embodiments, when performing the gate replacement process, there are no remaining particles 270 between the fin structures 120, which means that no undesired HKMG-containing structures are formed between the fin structures 120 that could be electrically shorted to the conductive source / drain contact 500.

[0060] Now refer to Figure 11 , an HKMG structure 650 is formed to replace the dummy gate structure 350. The HKMG structure 650 substantially inherits the top-down shape or profile of the dummy gate structure 350. In this way, the HKMG structure 650 can have an end segment 650A that extends or stretches in the Y direction. For example, the tip 610 of the end segment 650A is spaced apart from the edge of the nearest fin structure 120 by a distance 660. The value of the distance 660 is similar to the distance 360. In some embodiments, the distance 660 is at least 4 times the pitch 210 of the fin structures 120. For example, the distance 660 can be between about 4 times and about 8 times the pitch 210. As described above, the elongation of the end segment 650A helps remove particles 270 during the cleaning performed after defining the dummy gate structure 350, and reduces the likelihood of an electrical short caused by an HKMG-containing structure corresponding to any particles 270 remaining after cleaning. In this way, the likelihood of an electrical short with the conductive source / drain contact 500 is smaller.

[0061] Now refer to Figure 12, an HKMG structure 700 is formed to replace the dummy gate structure 400. The HKMG structure 700 substantially inherits the top-down shape or profile of the dummy gate structure 400. In this way, the HKMG structure 700 can have end segments 700A, each having a tapered-inward profile and extending or stretching in the Y direction. For example, the dimension 720 (measured in the X direction) of the end segment 700A shrinks the closer it gets to the tip 710 of the end segment 700A. At the same time, the distance 730 between the tip 610 and the nearest fin structure 120 is at least 4 times the pitch 210 of the fin structure 120. For example, the distance 730 can be between about 4 times and about 8 times the pitch 210. As described above, the tapered-inward profile and elongation of the end segment 700A help remove particles 270 during the cleaning performed after the dummy gate structure 400 is defined, and reduce the likelihood of an electrical short caused by the HKMG-containing structure corresponding to any particles 270 remaining after cleaning. In this way, the likelihood of an electrical short with the conductive source / drain contact 500 is smaller.

[0062] Now refer to Figure 13 , an HKMG structure 750 is formed to replace the dummy gate structure 450. The HKMG structure 750 substantially inherits the top-down shape or profile of the dummy gate structure 450. In this way, since the HKMG structure 750 can be formed as a continuous structure extending through the length of the die in the Y direction, the HKMG structure 750 can have no end segments similar to the end segments 540A, 600A, 650A, or 700A. For space considerations, Figure 13 only a portion of the HKMG structure 750 may be shown, and it should be understood that the HKMG structures 750 can each extend beyond Figure 13 the range shown. The dielectric structure 470 (e.g., the CMG component) discussed above is formed to divide each continuous HKMG structure 750 into separate gate structures 750A and 750B. As described above, such a process produces fewer particles 270, makes any potentially generated particles 270 easier to remove, and / or also reduces the likelihood of an electrical short between the conductive source / drain contact 500 and any HKMG-containing structure formed corresponding to the particles 270.

[0063] Figure 14is a schematic partial top view of HKMG structures 540 and 600A, showing the difference in their curvatures. For example, the end segment 540A of the HKMG structure 540 has an outwardly protruding profile that can be measured at least in part by an angle 800. The angle 800 can be defined by a substantially straight (e.g., substantially extending in the Y direction) edge 810 of the HKMG structure 540 and a tangent 820 (a tangent along the outwardly curved portion of the end segment 540A). The angle 800 is greater than 0. In some embodiments, the angle 800 is in the range of about 1 degree and about 30 degrees.

[0064] In contrast, the end segment 600A of the HKMG structure 600 has an inwardly tapering profile, which can be measured at least in part by an angle 850. The angle 850 can be defined by a substantially straight (e.g., substantially extending in the Y direction) edge 860 of the HKMG structure 600 and a tangent 870 (a tangent along the inwardly tapering portion of the end segment 600A). The angle 850 is less than 0. In some embodiments, the angle 850 is in the range of about -1 degree and about -30 degrees. The above ranges are not randomly selected, but are specifically configured to ensure that the end segment 600A is tapered enough to facilitate the easy removal of unwanted particles 270, while also ensuring that the end segment 600A is not too thin or too tapered such that the function of the gate is adversely affected. It should be understood that the end segment 700A of the HKMG structure 700 can also have an angle 850 including a similar range of values.

[0065] Figure 15 is a schematic partial top view of the HKMG structure 540 and another HKMG structure 900 formed according to an embodiment of the present disclosure. For the HKMG structure 540, a distance 880 separates the edge 810 from the outermost protruding point of its end segment 540A. The distance 880 is greater than 0. In some embodiments, the distance 880 is in the range of about 1 nanometer (nm) and about 20 nm. In contrast, the HKMG structure 900 can have an end segment 900A that is generally thinner in the X direction than the body of the HKMG structure 900. The end segment 900A also has an inwardly curved recessed portion 910. For example, the end segment 900A curves inwardly the most at a point 920. Due to this inward curvature, a distance 930 separates the point 920 from an edge 940 of the HKMG structure 900, where the edge 940 extends substantially straight in the Y direction. The distance 930 is in the range of about 1 nm and about 30 nm.

[0066] It should be understood that although Figures 14 - 15Shows a top - view outline of various HKMG structures that have been actually formed on a wafer, but they can also correspond to (e.g., be similar to) the top - view outline of a mask pattern on a photolithography mask. For example, the mask pattern on the photolithography mask used to define the HKMG structure 600 can also have a shape / profile similar to that of Figure 14 the shape / profile shown. Some minor differences between the shape / profile of the HKMG structure and the mask pattern on the photolithography mask can be that the mask pattern can be thinner (e.g., in the X - direction) and / or longer (e.g., in the Y - direction) than its corresponding HKMG structure. Additionally, the end portions of the pattern on the photolithography mask can be modified (e.g., by adding OPC assist features) to achieve the desired shape / profile of the pattern formed on the actual wafer. In this regard, Figure 21A and Figure 21B show several examples of the relationship between different patterns on a photolithography mask and their corresponding patterns on a wafer. For example, Figure 21A shows how a rectangular pattern on a photolithography mask can form a pattern with rounded end portions on a wafer. Figure 21B shows how a rectangular main pattern with smaller assist features attached to its end portions can form a pattern with more - constricted end portions (e.g., tapered according to aspects of the present disclosure) on a wafer. Thus, according to embodiments of the present disclosure, it can be seen how the pattern on a photolithography mask can be configured, manipulated, or otherwise adjusted to achieve a gate structure with a specific profile (e.g., tapered and / or elongated end portions).

[0067] According to some aspects of the present disclosure, gate structures with different shapes or profiles can be fabricated on the same wafer. For example, referring to Figure 16 , a schematic partial top - view of different portions of a wafer 1000 is shown. The wafer 1000 can include multiple regions, such as regions 1000A and 1000B. Active regions such as fin structures can be formed in both regions 1000A and 1000B. For example, multiple fin structures 1010 can be formed in the wafer region 1000A, while multiple fin structures 1110 can be formed in the wafer region 1000B. The fin structures 1010 and 1110 can be similar to the fin structure 120 discussed above. For example, they can be formed as structures containing semiconductor that project vertically upward from a substrate. The fin structures 1010 and 1110 each extend in the X - direction and have widths 1020 and 1120 measured along the Y - direction, respectively. In some embodiments, the widths 1020 and 1120 can be substantially equal to each other. In other embodiments, the widths 1020 and 1120 can have different values. It should be understood that, for space considerations, only a subset of the fin structures 1010 and 1110 is shown in Figure 16 .

[0068] Wafer regions 1000A and 1000B have different pattern densities. For example, pairs of adjacent fin structures 1010 are separated by a distance 1030, while pairs of adjacent fin structures 1110 are separated by a distance 1130. As Figure 16 shown, the distance 1030 is substantially longer than the distance 1130. In some embodiments, the ratio between the distance 1030 and the distance 1130 is in the range of about 1.6 and about 2.0. At least in part due to the difference in distances 1030 and 1130, wafer regions 1000A and 1000B can also have substantially different fin pitches 1040 and 1140, respectively. In some embodiments, the ratio between the fin pitch 1040 and the fin pitch 1140 is in the range of about 1.8 and about 2.3.

[0069] The difference in pattern density between wafer regions 1000A and 1000B may be due to design or manufacturing requirements. For example, certain types of IC devices may require a greater pattern density (e.g., more closely packed fin structures), while other types of IC devices may require a lower pattern density (e.g., more widely spaced fin structures).

[0070] Due to the difference in pattern density, wafer regions 1000A and wafer region 1000B can implement gate structures with different end segment profiles. More specifically, a gate structure 1200 can be implemented in wafer region 1000A, while a gate structure 1300 can be implemented in wafer region 1000B. Gate structures 1200 and 1300 can each extend in the Y direction and can respectively surround fin structures 1010 and 1110. In some embodiments, gate structures 1200 and 1300 can be HKMG structures.

[0071] The lower fin pattern density of wafer region 1000A means that unwanted particles 270 are more likely to be generated. More specifically, during the etching of the dummy gate layer to define the dummy gate structure, when reaching the underlying fin structure 1010, the etching can stop. The lower fin pattern density of wafer region 1000A means that a larger amount of dummy gate layer material needs to be etched away, thus providing a greater opportunity for the generation of particles 270. Therefore, the gate structure 1200 can be implemented similar to Figure 10 the HKMG structure 600 or Figure 11 the HKMG structure 650 or Figure 12 the HKMG structure 700 (e.g., as a combination of HKMG structures 600 and 650). In other words, the gate structure 1200 can be implemented to have an inwardly tapered end segment 1200A, or an end segment 1200A that extends beyond the outermost fin structure 1010 by a distance 1060 that is at least 4 times the fin pitch 1040 (note that Figure 16Not drawn to scale). Again, the fact that the end segment 1200A has an inwardly tapering profile and / or extends along the Y direction causes the generation of unwanted particles 270 to occur further away from the fin structure 1010, making them easier to remove (e.g., by suction) during the cleaning process.

[0072] On the other hand, the greater pattern density in the wafer region 1000B means that there is a lower likelihood of generating unwanted particles 270 because the greater presence of the fin structures 1110 under the dummy gate layer means that not as much dummy gate layer material needs to be etched away. Therefore, there is no need to optimize the gate structure 1300 in a manner similar to the gate structure 1200. In the illustrated embodiment, the shape of the gate structure 1300 can be similar to Figure 8 the HKMG structure 540. For example, the gate structure 1300 can include an end segment 1300A having a shape similar to Figure 8 or Figure 9 the end segment 540A shown, which can have an outwardly protruding profile or a rectangular profile with rounded corners. The end segment 1300A also does not have to extend as much as the end segment 1200A. For example, the end segment 1300A can protrude in the Y direction beyond the outermost fin structure 1110 by a distance 1160, where the ratio between the distance 1160 and the fin pitch 1140 can be less than about 3. In some embodiments, the distance 1060 is also substantially greater than the distance 1160. For example, the ratio between the distance 1060 and the distance 1160 can be in the range of about 2.0 to about 4.0. Again, the difference in the values between the distances 1060 and 1160 is not the result of randomness, but rather due to specifically configuring the profile of the gate structure 1200 in accordance with aspects of the present disclosure.

[0073] Figure 17 A schematic partial top view showing different portions of the wafer 1000 in accordance with some other aspects of the present disclosure. For reasons of clarity and consistency, similar components that appear in Figures 16 - 17 will be labeled the same. For example, Figure 17 also shows the wafer region 1000A in which the gate structure 1200 is formed in accordance with the present disclosure. As described above, the gate structure 1200 has an optimized profile because its end segment 1200A tapers and elongates in the Y direction.

[0074] Figure 17Wafer region 1000C is also shown, which includes a plurality of active regions 1410. Note that wafer region 100C may or may not be on the same wafer or die as wafer region 100A. In some embodiments, the active regions 1410 are non-fin structures. For example, the active regions 1410 may be active regions for planar devices. In other words, the active regions 1410 may include semiconductor regions (a portion of which may be doped) embedded in the substrate and not protruding vertically from the substrate. As described above, planar devices may not have problems associated with particles 270 because there are no vertically protruding fin structures to trap the particles 270. Therefore, the gate structure 1500 formed above the active regions 1410 does not need to optimize its profile. For example, the gate structure 1500 may include an end segment 1500A having a shape similar to Figure 16 the end segment 1300A (or similar to Figure 8 or Figure 9 the end segment 540A shown), which may have an outwardly protruding profile or a rectangular profile with rounded corners.

[0075] The end segment 1500A also does not have to extend as much as the end segment 1200A. For example, the end segment 1500A may extend beyond the edge of the outermost active region 1410 by a distance 1460 that is less than 3 times the pitch 1440 of the active regions 1410, where the pitch 1440 is equal to the sum of the size 1420 of the active regions 1410 and the distance 1430 between an adjacent pair of active regions 1410. In other words, for planar devices (e.g., devices without vertically protruding fin structures), unwanted particles 270 are less likely to be trapped, which means that it will not be a problem even at the gate ends. The problem related to unwanted particles 270 only occurs in the case of FinFETs (including all-around-gate devices). Therefore, for planar devices, it is not obvious to implement a gate structure having a tapered or elongated end portion as in the present disclosure because it is unnecessary for planar devices.

[0076] Another aspect of the present disclosure relates to modifying an IC layout plan to optimize the shape or profile of a gate structure. In this regard, modern semiconductor manufacturing may involve a foundry that receives an original IC layout plan from a fabless IC design house, where the fabless IC design house generates the original IC layout plan. The original IC layout plan typically contains patterns shaped as rectangles, squares, or other polygons having substantially straight edges and 90-degree angles. The foundry may modify these patterns to facilitate manufacturing. For example, optical proximity correction (OPC) patterns may be added to the original IC layout plan to achieve a desired device pattern shape and / or size. According to various aspects of the present disclosure, the gate pattern in the original IC layout may be optimized to have a tapered end segment and be stretched or elongated.

[0077] As an example of such a modification to the original IC layout plan is shown in Figure 18 which shows a top view of a portion of the original IC layout plan 1600A and the corresponding modified IC layout plan 1600B. The original IC layout plan 1600A includes a plurality of active regions, such as fin structure patterns 1610 each extending in the X direction. The fin structure patterns 1610 each have a dimension 1620 measured in the Y direction, and a distance 1630 separates adjacent fin structure patterns 1610. The fin pitch 1640 of the fin structure patterns 1610 is equal to the sum of the dimension 1620 and the distance 1630.

[0078] In the top view, the gate structure pattern 1700 overlaps the fin structure pattern 1610 and extends in the Y direction. The gate structure pattern 1700 has end segments 1700A, each extending in the Y direction a distance 1660 beyond the boundary of the outermost fin structure pattern 1610. As Figure 18 shown, the fin structure pattern 1610 and the gate structure pattern 1700 can each be shaped as rectangles. As described above, if such an IC layout plan is transferred to a photolithography mask, the gate pattern obtained on the actually manufactured wafer can have end segments, for example, protruding outward in a manner similar to the end segment 540A (see Figure 15 ). As described above, this may be undesirable because it can generate particles 270 that may be too close to the fin structures corresponding to the fin structure patterns 1610, which may subsequently cause electrical short circuits.

[0079] The present disclosure solves this problem by generating a modified IC layout plan 1600B based on the original IC layout plan 1600A. The modified IC layout plan 1600B may or may not modify the fin structure patterns 1610, but modifies the gate structure pattern 1700 to a gate structure pattern 1800. In some embodiments, the gate structure pattern 1800 can be generated to have end segments 1800A that taper inwardly (e.g., similar to the gate structure 1200 discussed above (see Figures 16 - 17 ).

[0080] In some embodiments, in addition to (or alternatively to) tapering the end segment 1800A, the gate structure pattern 1800 is also stretched or elongated in the Y direction. For example, while the gate structure pattern 1700 extends beyond the outermost fin structure 1610 by a distance 1660 according to the original IC layout plan, the gate structure pattern 1800 extends beyond the outermost fin structure 1610 by a distance 1860 according to the modified IC layout plan, where the distance 1860 is substantially greater than the distance 1660. In some embodiments, the distance 1860 is stretched to be at least 4 times the fin pitch 1640. In some embodiments, the ratio between the distance 1860 and the distance 1660 is in the range between about 2.0 and about 4.0. The above range is not randomly selected, but is specifically configured such that the gate structure fabricated according to the modified IC layout plan is long enough to ensure that any undesired particles 270 (if any are generated) are far enough away from the fabricated fin structures so that they can be easily removed, while not overly sacrificing chip space / area due to the elongation of the gate structure.

[0081] Figure 19 is a flowchart showing a method 2000 of manufacturing a semiconductor device according to an embodiment of the present disclosure. Method 2000 includes step 2010 of forming a plurality of first active regions on a wafer, each extending horizontally in a first direction. The first active regions include first fin structures, each protruding vertically upward above a substrate.

[0082] Method 2000 includes step 2020 of depositing a dummy gate layer above the first fin structures.

[0083] Method 2000 includes step 2030 of patterning the dummy gate layer into at least first dummy gate structures by an etching process using an etchant. The etching process produces etching by-products that contain elements of the dummy gate layer and the etchant. The first dummy gate structures extend horizontally in a second direction different from the first direction.

[0084] Method 2000 includes step 2040 of performing a cleaning process to remove the etching by-products. After performing the cleaning process, no etching by-products remain between the first fin structures.

[0085] Method 2000 includes step 2050 of replacing the first dummy gate structures with metal-containing gate structures. In a top view, the metal-containing gate structures substantially inherit the shape of the first dummy gate structures.

[0086] In some embodiments, the patterning of the dummy gate layer includes forming a first end segment of the first dummy gate structure that extends beyond the first fin structure by a first distance that is at least 4 times the pitch associated with the first fin structure.

[0087] It should be understood that method 2000 may include other steps performed before, during, or after steps 2010 - 2050. For example, method 2000 may include the step of forming a plurality of second active regions each extending along a first direction on a wafer. Method 2000 may also include the step of forming a second dummy gate structure over the second active regions. In a top view, the second dummy gate structure extends in a second direction and includes a second end segment that extends beyond the second active regions. In a top view, the shape of the second end segment is different from the shape of the first end segment. In some embodiments, patterning of the dummy gate layer includes tapering the end segment of the first dummy gate structure. In some embodiments, the second end segment is shorter than the first end segment in the second direction. In some embodiments, in a top view, the degree of tapering of the second end segment is less than that of the first end segment. In some embodiments, forming the second active regions includes forming a plurality of second fin structures having a lower pattern density than the first fin structures. In some embodiments, forming the second active regions includes forming a non - fin structure as the second active regions. Other steps may include forming vias, contacts, or metal layers, etc.

[0088] Figure 20 is a flowchart showing a method 2100 for facilitating the manufacture of a semiconductor device according to an embodiment of the present disclosure. Method 2100 includes step 2110 of receiving an integrated circuit (IC) layout plan. The IC layout plan includes a plurality of fin structures each extending in a first direction and a gate structure extending in a second direction different from the first direction. In a top view, the gate structure overlaps the fin structures. Method 2100 includes step 2120 of modifying the IC layout plan at least in part by: elongating an end segment of the gate structure that extends beyond the fin structures in the second direction; or contracting the end segment of the gate structure in the first direction. Method 2100 includes step 2130 of facilitating the manufacture of a semiconductor device using the modified IC layout plan. For example, a photolithography mask may be manufactured according to the modified IC layout plan, and the semiconductor device may be manufactured using the photolithography mask.

[0089] In some embodiments, the elongation is performed such that the distance between the outermost tip of the gate structure and the nearest fin structure is at least 4 times the pitch of the fin structures.

[0090] In some embodiments, the contraction includes making the degree of contraction of a first portion of the end segment greater than that of a second portion. The first portion is farther from the fin structure than the second portion.

[0091] In some embodiments, modifying the IC layout plan includes elongating and contracting the end segments of the gate structure.

[0092] It should be understood that method 2100 may include other steps performed before, during, or after steps 2110 - 2130. For example, method 2100 may include the following steps: performing a design rule check on the IC layout plan; adding optical proximity correction (OPC) features to the IC layout plan; and / or performing other modifications to the IC layout plan, etc.

[0093] The advanced lithography processes, methods, and materials described above can be used in many applications, including fin field - effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacings between components, for which the foregoing disclosure is well - suited. Additionally, spacers, also known as mandrels, for fins used to form FinFETs can be processed in accordance with the foregoing disclosure.

[0094] It should also be understood that the various aspects of the present disclosure discussed above can be applicable to multi - channel devices, such as gate - all - around (GAA) devices. Additional details related to the fabrication of GAA devices are disclosed in U.S. Patent No. 10,164,012, entitled "Semiconductor Device and Manufacturing Method Thereof", issued on December 25, 2018, and U.S. Patent No. 10,361,278, entitled "Method of Manufacturing a Semiconductor Device and a Semiconductor Device", issued on July 23, 2019, the disclosures of each of which are incorporated herein by reference in their entirety. To the extent that the present disclosure relates to fin structures or FinFET devices, such discussion can be equivalently applied to GAA devices.

[0095] In summary, the present disclosure optimizes the profile of a transistor's gate by tapering the end segments of the gate inwardly, by elongating the gate, or both. Optimizing the gate profile can provide advantages over conventional devices. However, it should be understood that not all advantages are discussed herein, different embodiments can provide different advantages, and any embodiment is not required to have a particular advantage. One advantage is that the present disclosure improves device performance and / or yield. For example, during patterning of a dummy gate structure, etch residues or by-products may be generated. Some etch residues or by-products (e.g., particles) may be trapped by the vertically protruding fin structures and may be difficult to remove during cleaning. If such residues or by-products remain when replacing the dummy gate with a high-k metal gate (HKMG), the residues or by-products can also become structures containing HKMG. These HKMG-containing structures may come into contact with IC device elements such as source / drain contacts, which may result in an electrical short. Here, by tapering the end segments of the gate or by elongating the gate, any etch residues or by-products generated can be positioned away from the fin structures, which makes them easier to remove during cleaning. Even if some residues or by-products remain after cleaning, the fact that they are farther away from the fin structures (and from the source / drain contacts to be formed) will reduce the risk of electrical shorts. In this way, device performance (e.g., voltage breakdown or VBD) and yield can be improved. Another advantage is a larger etch window. For example, the definition of a dummy gate structure involves etching, and since it is more certain that etch residues or by-products are more likely to be removed and any remaining etch residues or by-products are less likely to cause an electrical short, the etch window is now larger (e.g., can be performed for a longer duration or have greater flexibility with respect to the etchant). Other advantages can include compatibility with existing manufacturing processes and ease and low cost of implementation.

[0096] One aspect of the present disclosure relates to a device. The device includes a plurality of fin structures, each fin structure protruding vertically upward from a substrate and extending in a first direction in a top view. A gate structure is disposed above the fin structures. In the top view, the gate structure extends in a second direction. The second direction is different from the first direction. The fin structures have a fin pitch equal to the sum of: the dimension of one of the fin structures in the second direction and the distance between an adjacent pair of fin structures in the second direction. An end segment of the gate structure extends beyond the edge of the nearest fin structure in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

[0097] Another aspect of the present disclosure relates to a method. The method includes forming a plurality of first active regions on a wafer that horizontally extend along a first direction respectively. The first active regions include first fin structures, each vertically protruding upward above a substrate. The method includes depositing a dummy gate layer above the first fin structures. The method includes patterning the dummy gate layer into at least first dummy gate structures by an etching process using an etchant. The etching process generates etch by-products that contain elements of the dummy gate layer and the etchant. The first dummy gate structures horizontally extend in a second direction different from the first direction. The method includes performing a cleaning process to remove the etch by-products. After performing the cleaning process, no etch by-products remain between the first fin structures. The method includes replacing the first dummy gate structures with metal-containing gate structures. In a top view, the metal-containing gate structures substantially inherit the shape of the first dummy gate structures.

[0098] Yet another aspect of the present disclosure relates to a method. The method includes receiving an integrated circuit (IC) layout plan. The IC layout plan includes a plurality of fin structures each extending in a first direction and a gate structure extending in a second direction different from the first direction. In a top view, the gate structure overlaps the fin structures. The IC layout plan is modified at least in part by: elongating an end segment of the gate structure that extends beyond the fin structures in the second direction; or contracting an end segment of the gate structure in the first direction.

[0099] According to one embodiment of the present application, a semiconductor device is provided, including: a plurality of fin structures, each fin structure protruding vertically upward from a substrate and extending in a first direction in a top view; and a gate structure disposed above the fin structures, wherein the gate structure extends in a second direction in the top view, and the second direction is different from the first direction; wherein: the fin structures have a fin pitch equal to the sum of: the dimension of one of the fin structures in the second direction and the distance between an adjacent pair of fin structures in the second direction; an end segment of the gate structure extends beyond the edge of the nearest fin structure in the second direction; and the end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction. In some embodiments, as the end segment extends away from the fin structures in the second direction, the dimension of the end segment gradually decreases. In some embodiments, wherein the end segment has a tapered profile in the top view and is at least 4 times as long as the fin pitch in the second direction. In some embodiments, wherein: the plurality of fin structures are first fin structures having a first pattern density; the gate structure is a first gate structure; the semiconductor device further includes a plurality of second fin structures, the second pattern density of the second fin structures being lower than the first pattern density, and a second gate structure disposed above the second fin structures; and the end segment of the second gate structure has a different top view profile from the end segment of the first gate structure. In some embodiments, wherein the degree of tapering of the end segment of the second gate structure is less than or shorter than that of the end segment of the first gate structure. In some embodiments, wherein the gate structure is a first gate structure, and wherein the semiconductor device further includes a plurality of non-fin active regions disposed in the substrate and a second gate structure disposed above the non-fin active regions; and the end segment of the second gate structure has a different top view profile from the end segment of the first gate structure. In some embodiments, wherein the degree of tapering of the end segment of the second gate structure is less than or shorter than that of the end segment of the first gate structure.

[0100] According to another embodiment of the present application, a method of forming a semiconductor device is provided, including: forming a plurality of first active regions on a wafer, each extending horizontally along a first direction, wherein the first active regions each include a first fin structure protruding vertically upward above a substrate; depositing a dummy gate layer above the first fin structure; patterning the dummy gate layer into at least a first dummy gate structure by an etching process using an etchant, wherein the etching process generates an etching by-product containing elements of the dummy gate layer and the etchant, and wherein the first dummy gate structure extends horizontally along a second direction different from the first direction; performing a cleaning process to remove the etching by-product, wherein after performing the cleaning process, there is no etching by-product between the first fin structures; and replacing the first dummy gate structure with a metal-containing gate structure, wherein in a top view, the metal-containing gate structure substantially inherits the shape of the first dummy gate structure. In some embodiments, wherein patterning the dummy gate layer includes forming a first end segment of the first dummy gate structure extending a first distance beyond the first fin structure, the first distance being at least 4 times a pitch associated with the first fin structure. In some embodiments, the method of forming a semiconductor device further includes: forming a plurality of second active regions on the wafer, each extending along the first direction; and forming a second dummy gate structure above the second active regions, wherein the second dummy gate structure extends along the second direction and includes a second end segment extending beyond the second active regions in a top view, and wherein in a top view, the shape of the second end segment is different from the shape of the first end segment. In some embodiments, wherein patterning the dummy gate layer includes tapering an end segment of the first dummy gate structure. In some embodiments, wherein the second end segment is shorter than the first end segment in the second direction. In some embodiments, wherein in a top view, the degree of tapering of the second end segment is less than that of the first end segment. In some embodiments, wherein forming the second active regions includes forming a plurality of second fin structures, the pattern density of the plurality of second fin structures being lower than the pattern density of the first fin structures. In some embodiments, wherein forming the second active regions includes forming a non-fin structure as the second active regions.

[0101] According to another embodiment of the present application, a method of forming a semiconductor device is provided, including: receiving an integrated circuit (IC) layout plan, the IC layout plan including a plurality of fin structures each extending along a first direction and gate structures extending along a second direction different from the first direction, wherein, in a top view, the gate structures overlap the fin structures; and modifying the IC layout plan at least in part by: elongating an end segment of the gate structure that extends beyond the fin structure in the second direction; or contracting an end segment of the gate structure in the first direction. In some embodiments, the method of forming a semiconductor device further includes: using the modified IC layout plan to facilitate the manufacture of the semiconductor device. In some embodiments, wherein the elongation is performed such that the distance between the outermost tip of the gate structure and the nearest fin structure is at least 4 times the pitch of the fin structures. In some embodiments, wherein the contraction includes contracting a first portion of the end segment to a greater extent than a second portion of the end segment, wherein the first portion is farther from the fin structure than the second portion. In some embodiments, wherein modifying the IC layout plan includes elongating and contracting an end segment of the gate structure.

[0102] The components of several embodiments have been described above so that those skilled in the art can better understand the various embodiments of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or change other processes and structures for achieving the same purposes and / or realizing the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A plurality of fin structures, each of which protrudes vertically upward from the substrate and extends along a first direction in a top view; and a gate structure disposed above the fin structure, wherein the gate structure extends along a second direction in the top view, and the second direction is different from the first direction; in: The fin structures have a fin pitch that is equal to the sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of fin structures in the second direction; The end segment of the gate structure extends beyond the edge of the nearest fin structure along the second direction; and The end segment is at least 4 times longer than the fin pitch in the second direction, In which, in the second direction away from the fin structure, the first part of the end segment shrinks inwardly, while the second part of the end segment protrudes outwardly, the first part of the end segment is closer to the fin structure in the second direction than the second part of the end segment, and the first part and the second part of the end segment jointly define a groove in a top view, and the maximum size of the first part of the end segment and the maximum size of the second part of the end segment are smaller than the maximum size of the rest of the gate structure.

2. The semiconductor device according to claim 1, wherein, The gate structure is part of a FinFET device or part of a gate-all-around device.

3. The semiconductor device according to claim 1, wherein, A distance between a lowest point of the groove and an outer edge of the gate structure in the second direction is between 1 nm and 30 nm.

4. The semiconductor device according to claim 1, wherein: The plurality of fin structures are first fin structures having a first pattern density; The gate structure is a first gate structure; The semiconductor device further includes a plurality of second fin structures, a second pattern density of the second fin structures being lower than the first pattern density, and a second gate structure being disposed above the second fin structures; and An end segment of the second gate structure has a top-view profile different from that of an end segment of the first gate structure.

5. The semiconductor device according to claim 4, wherein, The end section of the second gate structure is less tapered than the end section of the first gate structure.

6. The semiconductor device according to claim 1, wherein, The gate structure is a first gate structure, and wherein the semiconductor device further comprises a plurality of non-fin active regions disposed within the substrate and a second gate structure disposed above the non-fin active regions; and An end segment of the second gate structure has a top-view profile different from that of an end segment of the first gate structure.

7. The semiconductor device according to claim 6, wherein, The end section of the second gate structure is less tapered than the end section of the first gate structure.

8. A method of forming a semiconductor device, comprising: forming a plurality of first active regions each extending horizontally along a first direction on the wafer, wherein the first active regions include first fin structures each protruding vertically upward above the substrate; depositing a dummy gate layer over the first fin structure; patterning the dummy gate layer into at least a first dummy gate structure by an etching process using an etchant, wherein the etching process produces an etching byproduct comprising elements of the dummy gate layer and the etchant, and wherein the first dummy gate structure extends horizontally along a second direction different from the first direction; performing a cleaning process to remove the etching byproducts, wherein after performing the cleaning process, no etching byproducts exist between the first fin structures; and replacing the first dummy gate structure with a metal-containing gate structure, wherein, in a top view, the metal-containing gate structure substantially inherits the shape of the first dummy gate structure, wherein patterning the dummy gate layer includes forming a first end segment of the first dummy gate structure extending beyond the first fin structure by a first distance, the first distance being at least 4 times a pitch associated with the first fin structure, Among them, in the second direction, the first part of the first end segment of the first pseudo gate structure shrinks inward, while the second part of the first end segment of the first pseudo gate structure protrudes outward, the first part of the first end segment is closer to the first fin structure in the second direction than the second part of the first end segment, and the first part and the second part of the first end segment jointly define a groove in the top view, and the maximum size of the first part of the first end segment and the maximum size of the second part of the first end segment are smaller than the maximum size of the rest of the first pseudo gate structure.

9. The method according to claim 8, wherein The first dummy gate structure is part of a FinFET device or part of a gate-all-around device.

10. The method according to claim 9, further comprising: forming a plurality of second active regions on the wafer, each of which extends along the first direction; and A second dummy gate structure is formed above the second active region, wherein the second dummy gate structure extends along the second direction and includes a second end segment extending beyond the second active region in the top view, and wherein, in the top view, a shape of the second end segment is different from a shape of the first end segment.

11. The method according to claim 8, wherein, A distance between a lowest point of the groove and an outer edge of the first dummy gate structure in the second direction is between 1 nm and 30 nm.

12. The method according to claim 10, wherein The second end segment is shorter than the first end segment in the second direction.

13. The method according to claim 10, wherein, In the top view, the second end section tapers less than the first end section.

14. The method according to claim 10, wherein, Forming the second active region includes forming a plurality of second fin structures, wherein a pattern density of the plurality of second fin structures is lower than a pattern density of the first fin structures.

15. The method according to claim 10, wherein Forming the second active region includes forming a non-fin structure.

16. A method of forming a semiconductor device, comprising: receiving an integrated circuit layout plan, the integrated circuit layout plan comprising a plurality of fin structures each extending along a first direction and a gate structure extending along a second direction different from the first direction, wherein in a top view, the gate structure overlaps the fin structure; and Modifying the integrated circuit floorplan at least in part by: elongating an end section of the gate structure extending beyond the fin structure in the second direction; or The end section of the gate structure is contracted in the first direction, wherein the contraction causes the first portion of the end section to contract inwardly and the second portion of the end section to protrude outwardly in the second direction away from the fin structure, the first portion of the end section is closer to the fin structure in the second direction than the second portion of the end section, and the first portion and the second portion of the end section jointly define a groove in a top view, and the maximum size of the first portion of the end section and the maximum size of the second portion of the end section are smaller than the maximum size of the rest of the gate structure.

17. The method according to claim 16, further comprising: The modified integrated circuit floorplan is used to facilitate fabrication of semiconductor devices.

18. The method according to claim 16, wherein, The elongating is performed such that a distance between an outermost tip of the gate structure and a nearest fin structure is at least 4 times a pitch of the fin structures.

19. The method according to claim 16, wherein The gate structure is part of a FinFET device or part of a gate-all-around device.

20. The method according to claim 16, wherein Modifying the integrated circuit floorplan includes lengthening and shrinking end segments of the gate structure.

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