Semiconductor structure and method for forming the same

Abstract

The semiconductor structure includes: a SiGe fin protruding from a substrate, wherein the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and wherein each of a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall has a tapered profile extending away from the first sidewall and the second sidewall, respectively; and a Si-containing layer disposed on the top portion of the SiGe fin, wherein a portion of the Si-containing layer located on the first transition region extends away from the first sidewall by a first lateral distance, and a portion of the Si-containing layer located on the second transition region extends away from the second sidewall by a second lateral distance different from the first lateral distance. Embodiments of the present application also relate to semiconductor structures and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased.

[0003] Such scaling down processes generally provide benefits by increasing production efficiency and reducing associated costs. Such scaling down also increases the complexity of processing and manufacturing ICs. For example, challenges such as short channel effects (SCE) and threshold voltage (Vt) tuning become more pronounced at reduced length scales, thereby compromising device performance. While existing approaches to addressing these challenges (e.g., introducing silicon germanium based channels) are generally adequate, they are not completely satisfactory in all respects. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate; a silicon germanium (SiGe) fin protruding from the semiconductor substrate, wherein the silicon germanium fin includes a top having a first sidewall and a second sidewall, the top being disposed above a bottom having a third sidewall and a fourth sidewall, and wherein each of a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall has a tapered profile extending away from the first sidewall and the second sidewall, respectively; an isolation component disposed above the semiconductor substrate and surrounding the bottom of the silicon germanium fin; a silicon-containing layer disposed on the top of the silicon germanium fin, wherein a first portion of the silicon-containing layer disposed on the first transition region extends a first lateral distance away from the first sidewall, and a second portion of the silicon-containing layer disposed on the second transition region extends a second lateral distance away from the second sidewall that is different from the first lateral distance, and wherein a spacing between external vertical surfaces of the silicon-containing layer is defined by a third lateral distance; and a metal gate stack disposed above the silicon-containing layer in a channel region of the silicon germanium fin.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: a semiconductor substrate including a first region and a second region; an isolation structure disposed above the first region and the second region; a first fin protruding from the semiconductor substrate in the first region, wherein the first fin includes silicon (Si) and substantially no germanium (Ge), and wherein a portion of the first fin in contact with a top surface of the isolation structure extends laterally away from a sidewall of the first fin to form a first fin shoulder; a second fin protruding from the semiconductor substrate in the second region, wherein the second fin includes silicon and germanium, wherein a portion of the second fin in contact with a top surface of the isolation structure extends laterally away from a sidewall of the second fin to form a second fin shoulder, and wherein the second fin shoulder has a width greater than the first fin shoulder; a silicon layer disposed above the first fin and the second fin, wherein a portion of the silicon layer disposed above the first fin has a first thickness, and a portion of the silicon layer disposed above the second fin has a second thickness greater than the first thickness; and a metal gate stack disposed above the silicon layer in a channel region of the first fin and a channel region of the second fin.

[0006] Still other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a semiconductor substrate having a first region and a second region; forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin comprises silicon germanium (SiGe) and the second fin comprises silicon (Si) but no germanium (Ge); determining a thickness of a silicon-containing layer to be deposited over the first fin; trimming the first fin based on the thickness of the silicon-containing layer, wherein trimming the first fin forms a fin shoulder protruding from a sidewall of the trimmed first fin; depositing the silicon-containing layer over the trimmed first fin to the determined thickness, wherein a portion of the silicon-containing layer extends laterally beyond the fin shoulder; forming a dummy gate stack over a portion of the silicon-containing layer; forming a source / drain (S / D) component adjacent to the dummy gate stack in the first fin and the second fin; and replacing the dummy gate stack with a metal gate stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A and Figure 1B Together, flow charts are shown of methods for forming a semiconductor structure or portion thereof according to aspects of the present invention.

[0009] Figure 2 The use of the invention according to aspects of the invention is shown Figure 1A and Figure 1B A three-dimensional perspective view of a semiconductor structure implemented in accordance with an embodiment of a method.

[0010] Figure 3 , Figure 4A , Figure 4B , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 8 , Fig.9A and Fig. 9B It is shown that according to the present invention, in the embodiment Figure 1A and Figure 1B The method of the embodiment of the intermediate step during the method of the embodiment of the intermediate step taken along the line A-A' or line B-B' Figure 2 Cross-sectional view of a semiconductor structure.

[0011] Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A It is shown that in the implementation according to aspects of the present invention Figure 1A and Figure 1B A method of an embodiment of the invention taken along line A-A' during an intermediate step Figure 2 Cross-sectional view of a semiconductor structure.

[0012] Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B It is shown that in the implementation according to aspects of the present invention Figure 1A and Figure 1B A view taken along line BB' during an intermediate step of an embodiment of the method Figure 2 Cross-sectional view of a semiconductor structure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the present invention. The specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples, and are not intended to limit the present invention. For example, in the following present invention, the formation of a component on another component, connected to and / or coupled to another component can include an embodiment in which the component is formed in the form of direct contact, and can also include an embodiment in which additional components can be inserted between components so that the components can not be directly contacted. In addition, use, for example, "bottom", "upper", "horizontal", "vertical", "above", "above", "below", "below", "under", "upward", "downward", "top", "bottom" and other spatial relative terms and their derivatives (for example, "horizontally", "downwardly", "upwardly", etc.) to easily understand the relationship between a component of the present invention and another component. Spatially relative terms are intended to include different orientations of the device of the component.

[0014] In addition, when "about", "approximately", etc. are used to describe a value or a range of values, the term is intended to encompass values ​​within a reasonable range including the value, such as within + / -10% of the described value or other values ​​understood by those skilled in the art. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm. Further, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] The present invention relates generally to semiconductor devices and fabrication methods, and more particularly to three-dimensional field effect transistors (FETs), such as fin FETs (FinFETs), gate-all-around FETs (GAA FETs), and / or other FETs.

[0016] Various approaches have been developed to improve the performance of three-dimensional FETs. One exemplary approach is directed to introducing silicon germanium (SiGe) based channels in FETs to address challenges such as tuning the threshold voltage (V t Although this approach is often adequate, it is not completely satisfactory in all respects. For example, SiGe is more susceptible to oxidation during the device manufacturing process than silicon (Si), thus producing germanium oxide (GeO x ) can adversely affect the performance of the device. Therefore, for at least this reason, it is desirable to improve the processing of SiGe-based channels in FETs.

[0017] Figure 1A and Figure 1B1 and 1 , together, illustrate a process flow of a method 100 for forming a device 10 according to an embodiment of the present invention. The method 100 is merely an example and is not intended to limit the present invention, other than as expressly set forth in the claims. Additional operations may be performed before, during, and after the method 100, and some operations described herein may be replaced, eliminated, or moved to provide additional embodiments of the method 100. Figures 2 to 15B Method 100 is described.

[0018] Device 10 may be an intermediate device fabricated during processing of an IC or a portion thereof, which may include static random access memory (SRAM) and / or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, multi-gate FETs (e.g., gate-all-around FETs or GAA FETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and / or other memory cells. The present invention is not limited to any particular number of devices or device regions, nor to any particular device configuration. Additional components may be added to device 10, and some of the components described below may be replaced, modified, or eliminated in other embodiments of device 10.

[0019] In operation 102, referring to Figure 1A and Figure 2 , method 100 provides or is provided with a device 10, the device 10 includes a substrate 20, the substrate 20 has a device region 10A and a device region 10B disposed thereon and configured to provide FETs of different conductivity types. For example, the device region 10A can be configured to provide at least one NFET, and the device region 10B can be configured to provide at least one PFET. However, it should be noted that as shown in the present embodiment, the device region 10A and the device region 10B may not be disposed in close proximity to each other. The device 10 may include many other components, such as, for example, a hard mask layer, an etch stop layer, a barrier layer, other suitable layers, or combinations thereof. For the purpose of simplicity, the following reference is made to Figures 3 to 15B Describe the intermediate steps of method 100; wherein, Figures 3 to 9B is a cross-sectional view taken through the source / drain (S / D) region or channel region of the device 10, i.e., along Figure 2 The line A-A' or the line B-B' shown, Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A is a cross-sectional view taken through the S / D region of device 10, and Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B is a cross-sectional view taken through the channel region of device 10 .

[0020] The substrate 20 may include: an element (single element) semiconductor, such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 20 may be a single layer of material having a uniform composition. Alternatively, the substrate 20 may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate 20 may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer.

[0021] In the present embodiment, substrate 20 comprises silicon, such as elemental silicon. Figure 2 As shown, device region 10A and device region 10B are formed over substrate 20, wherein device region 10A is provided in and / or over layer 22A, and device region 10B is provided in and / or over layer 22B, and both of them are formed over substrate 20. In this embodiment, reference is made to Figure 4A , layers 22A and 22B have different compositions, for example, layer 22A includes silicon, such as elemental silicon, and layer 22B includes silicon germanium (SiGe). Layers 22A and 22B may be epitaxially grown over substrate 20 by one or more selective epitaxial growth (SEG) processes including chemical vapor deposition (CVD) processes (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure CVD (LP-CVD), plasma enhanced (PE-CVD), other suitable CVD processes, or combinations thereof), molecular beam epitaxy (MBE), other suitable SEG processes, or combinations thereof. Layers 22A and 22B may be epitaxially grown using gaseous and / or liquid precursors that interact with the composition of the underlying substrate (i.e., substrate 20).

[0022] refer to Figure 3 , Figure 4A and Figure 4B, the method 100 forms a first fin 30A and a second fin 30B from the layers 22A and 22B, respectively, in operation 104. In the present embodiment, the first fin 30A and the second fin 30B are configured to form a FET having different conductivity types. In the present invention, due to the different composition between the layers 22A and 22B, the first fin 30A may be optionally referred to as a Si-based fin 30A, and the second fin 30B may be optionally referred to as a SiGe-based fin 30B. Figure 3 , which is a side view of the device 10 shown in the YZ plane, hard mask layers 24 and 26 are deposited over layers 22A and 22B before forming the first fin 30A and the second fin 30B. The hard mask layers 24 and 26 can each include any suitable dielectric material, such as silicon oxide, silicon nitride, carbon and / or oxygen-doped silicon nitride, silicon carbide, oxygen-doped silicon carbide, other suitable dielectric materials, or combinations thereof. In the present embodiment, the hard mask layer 24 includes an oxide-containing material, such as silicon oxide, and the hard mask layer 26 includes a nitride-containing material, such as silicon nitride. The hard mask layers 24 and 26 are configured to protect the underlying components of the device 10 from being accidentally etched during a subsequent fin formation process.

[0023] refer to Figure 4A , the first fin 30A and the second fin 30B can be manufactured from layers 22A and 22B, respectively, by using a suitable process including photolithography and etching processes. The photolithography process may include: forming a photoresist layer (resist) located above layers 22A and 22B; exposing the resist to a pattern; implementing a post-exposure baking process; and developing the resist to form a masking element (not shown) including the resist. The masking element is then used to etch grooves in layers 22A and 22B, so that the first fin 30A and the second fin 30B protrude from the substrate 20. The etching process may include dry etching, wet etching, reactive ion etching (RIE), other suitable processes, or combinations thereof. After the etching process is implemented, portions of the hard mask layers 24 and 26 remain above the first fin 30A and the second fin 30B, thereby protecting the fins from subsequent manufacturing processes.

[0024] Many other embodiments of the method for forming the first fin 30A and the second fin 30B may be suitable. For example, the first fin 30A and the second fin 30B may be patterned using a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the generation of patterns with, for example, a pitch smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate 20 and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the first fin 30A and the second fin 30B.

[0025] In the present embodiment, two fins are formed in each of the device region 10A and the device region 10B. However, it should be noted that the present embodiment is not limited to this configuration. For example, each of the device region 10A and the device region 10B may include only one fin or more than two fins to suit the desired design requirements. In some embodiments, as Figure 4B As shown, patterned layers 22A and 22B remove portions of substrate 20 to form recesses 23A and 23B. Recesses 23A and 23B may be defined by depths R1 and R2, respectively, where R1 may be different from R2. For example, in the embodiment shown, R1 is less than R2. Of course, the present embodiment is not limited to this configuration.

[0026] Then, still refer to Figure 4A , a dielectric liner 32 is formed on the sidewalls of the first fin 30A and the second fin 30B and over the substrate 20. The dielectric liner 32 may include silicon oxide, silicon nitride, other suitable materials, or combinations thereof. In the present embodiment, the dielectric liner 32 is formed by conformally depositing one or more dielectric materials discussed above over the device 10 by a method including chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or combinations thereof. In some embodiments, the dielectric liner 32 is omitted from the device 10. For Figure 4B In the illustrated embodiment, portions of dielectric liner 32 are deposited in recesses 23A and 23B. However, for purposes of illustration, reference is made to Figure 4A The illustrated embodiment discusses subsequent operations of method 100 .

[0027] refer to Figure 5 and Figure 6 In operation 106, the method 100 forms an isolation structure 40 above the substrate 20 to separate the components of the device 10 (eg, the first fin 30A, the second fin 30B, etc.). Figure 5, method 100 first forms an isolation structure 40 above device 10, thereby filling the trench separating the first fin 30A and the second fin 30B. The isolation structure 40 may include silicon dioxide, a low-k dielectric material, other suitable materials, or a combination thereof. The isolation structure 40 may be deposited by any suitable method, such as CVD, flowable CVD (FCVD), spin-on glass (SOG), other suitable methods, or a combination thereof. In some embodiments, the composition of the dielectric liner 32 is substantially the same as the composition of the isolation structure 40. For example, both the dielectric liner 32 and the isolation structure 40 may include silicon oxide. In some embodiments, the composition of the dielectric liner 32 is different from the composition of the isolation structure 40. For example, the dielectric liner 32 may include silicon nitride, and the isolation structure 40 may include silicon oxide. The isolation structure 40 may include a shallow trench isolation (STI) component. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), other suitable structures, or a combination thereof may also be implemented as the isolation structure 40. Isolation structure 40 may include a single layer structure, or alternatively a multi-layer structure having, for example, one or more thermal oxide layers.

[0028] Then, the method 100 performs one or more chemical mechanical planarization (CMP) processes to remove the top of the isolation structure 40. In some embodiments, the CMP process removes the hard mask layers 24 and 26 from the top surfaces of the first fin 30A and the second fin 30B. Figure 6 The method 100 performs an etching process 402 to recess the isolation structure 40 so that a top surface of the isolation structure 40 is located below top surfaces of the first fin 30A and the second fin 30B.

[0029] In the present embodiment, the etching process 402 removes portions of the dielectric liner 32 while recessing the isolation structure 40. For embodiments where the isolation structure 40 and the dielectric liner 32 have the same composition (e.g., both include silicon oxide), the resulting height of the dielectric liner 32 is substantially similar to the thickness of the isolation structure 40. For embodiments where the isolation structure 40 and the dielectric liner 32 have different compositions (e.g., the isolation structure 40 includes silicon oxide and the dielectric liner 32 includes silicon nitride), the resulting height of the dielectric liner 32 is different from the thickness of the isolation structure 40, and this difference may be due to the difference in etch rates between the two compositions when subjected to a common etchant.

[0030] In this embodiment, device 10 includes regions of varying fin density, i.e., the separation distance between adjacent fins varies depending on the number of fins present in a given device region. Figure 6As shown, adjacent first fins 30A formed in the device region 10A may be separated by a spacing P1, adjacent second fins 30B formed in the device region 10B may be separated by a spacing P2, and the first fin 30A may be separated from the adjacent second fin 30B by a spacing P3, wherein P3 is greater than P1 and P2. In other words, the region of the device 10 disposed between the two first fins 30A and the region of the device 10 disposed between the two second fins 30B are considered to be a higher fin density or HFD region, while the region of the device 10 disposed between the first fin 30A and its adjacent second fin 30B is considered to be a lower fin density or LFD region. In some embodiments, the difference in fin density results in a difference in the amount of the isolation structure 40 removed in operation 106. For example, due to loading more etchant between sparsely disposed fins, the isolation structure 40 may be recessed more in the LFD region than in the HFD region. Because removing a portion of the isolation structure 40 also removes a portion of the dielectric liner 32, the dielectric liner 32 on the opposite sidewalls of each of the first fin 30A and the second fin 30B may have different heights. For example, the dielectric liner 32A disposed in the HFD region is defined by a height H1 , and the dielectric liner 32B disposed in the LFD region has a height H2 , wherein H1 is greater than H2 .

[0031] Typically, SiGe-based fins, such as the second fin 30B provided herein, can be susceptible to oxidation at various stages of FinFET fabrication, thereby producing germanium oxide (GeO) that degrades device performance. x ). To address this issue, a silicon capping layer (hereinafter referred to as a Si cap, such as Si cap 34 discussed in detail below) can be deposited over the SiGe-based fins to prevent accidental oxidation. Although this approach is generally sufficient, it is not completely satisfactory in all aspects. For example, depositing a Si cap can cause the critical dimension (CD) or width of the SiGe-based fins (as well as fins of other materials or conductivity types disposed on the same substrate) to increase, which may cause drain-to-barrier lowering (DIBL) to occur. The present invention provides a method for trimming SiGe-based fins (for forming PMOS devices) and Si-based fins (for forming NMOS devices) before forming a Si cap thereon to meet the desired CD of the fins to improve the resulting device performance.

[0032] Reference now Fig. 7A and Figure 7B , the method 100 trims the width of each of the first fin 30A and the second fin 30B before depositing the Si cap 34 in operation 108. In this embodiment, the trimming process includes the following steps: Figure 1BOperations 202 to 220 of method 200 are shown. In some embodiments, method 200 is implemented by a control unit 201 configured to electrically and signal control and / or communicate with various tools. In some embodiments, control unit 201 includes a computer-readable medium with an integrated hard drive, flash drive, CD-ROM, RAM memory, display device (e.g., monitor), input / output device (e.g., mouse and keyboard), etc. Control unit 201 can implement a series of software instructions written in any suitable programming language and designed to implement various operations of method 200, including, for example: measuring fin width (or fin CD); determining the thickness of Si cap 34 to be deposited; calculating various parameters based on the measured fin width; determining whether fin trimming is required; trimming fins; actions necessary based on trimming feedback and / or other suitable operations. In some embodiments, each of operations 202 to 220 includes a processor operable to implement instructions read from the computer-readable medium of control unit 201 using software instructions encoded thereon. In some embodiments, the control unit 201 and the various tools together form an advanced process control (APC) system to automatically process the first fin 30A and the second fin 30B before depositing the Si cap 34 .

[0033] The method 200 measures the fin width FW1 of each first fin 30A and the fin width FW2 of each second fin 30B in operation 202, such as Figure 6 , Fig. 7A and Figure 7B As shown. The fin width FW1 and the fin width FW2 may be different in size or substantially the same, depending on the specific design requirements. In some embodiments, the fin width FW1 and the fin width FW2 vary vertically along the height of each fin, that is, the sidewalls of each fin may be inclined. Therefore, the fin widths FW1 and FW2 may each be determined at a portion away from the top and bottom surfaces of each fin, for example, at approximately half the step height of the fin, which corresponds to the height of each fin protruding from the isolation structure 40. Optionally, the fin widths FW1 and FW2 may be determined by taking the average of the fin widths at various locations along the height of each fin. In some instances, such as Figure 6 As shown in the enlarged view of the portion 36 of the second fin 30B in FIG. 4 , the etching process 402 may slightly remove the portion of the second fin 30B so that the top of the second fin 30B has an approximately hemispherical shape with a radius R, where R may be less than or equal to half of the fin width FW2. Although not shown, similar geometries may also apply to one or more of the first fins 30A. In some embodiments, the fin widths FW1 and FW2 are determined using an optical measurement method, such as a critical dimension scanning electron microscope (CDSEM), an optical critical dimension (OCD) spectroscopy, other suitable measurement methods, or a combination thereof.

[0034] In operation 204, the method 200 determines a thickness T2 of the Si cap 34 to be deposited over the second fin 30B. In the present embodiment, the thickness T2 is determined based on the desired level of protection of the second fin 30B against oxidation reactions without excessively increasing the resulting fin width (or fin CD) of the second fin 30B. In other words, the Si cap 34 is formed to a minimum thickness while providing adequate protection for the second fin 30B below. In some examples, the thickness T2 may be about 0.7 nm to about 0.8 nm.

[0035] Subsequently, the method 200 determines the thickness T1 of the Si cap 34 to be formed above the first fin 30A in operation 206. In the present embodiment, although the Si cap 34 is formed as a whole above the device 10, that is, above the device region 10A and the device region 10B, the Si growth rate on Si (that is, the first fin 30A) is different from the Si growth rate on SiGe (that is, the second fin 30B) due to the different incubation periods of the Si growth process. Generally, the incubation period of Si growth is shorter on SiGe than on Si. Therefore, the Si growth rate on SiGe is greater than the Si growth rate on Si, so that given the same deposition time, the thickness T2 is greater than T1. In some instances, the ratio of thickness T2 to thickness T1 can be about 1.1 to about 1.8. In the present embodiment, the control unit 201 includes a suitable computing device configured to estimate the thickness T1 based on the desired thickness T2 and the known difference in the Si growth rate between the first fin 30A and the second fin 30B.

[0036] In operation 208, the method 200 determines the protruding fin size (or protruding fin CD) based on the measured fin width and the thickness of the Si cap 34 to be deposited. In the present embodiment, the protruding fin size CD1 of each first fin 30A is determined based on the measured fin width FW1 and thickness T1, i.e., CD1=2*T1+FW1, and the protruding fin size CD2 of each second fin 30B is determined based on the measured fin width FW2 and thickness T2, i.e., CD2=2*T2+FW2. Subsequently, the method 200 compares the protruding fin sizes CD1 and CD2 with the desired or target fin size CD1 of the first fin 30A, respectively, in operation 210. T and a target fin size CD2 of the second fin 30B T In this embodiment, CD1 T Considering the trimmed fin width FW1′ of the first fin 30A and the thickness T1 of the Si cap 34 deposited thereon, and CD2 T The trimmed fin width FW2′ of the second fin 30B and the thickness T2 of the Si cap 34 deposited thereon are taken into account. Although the present embodiment does not limit the target fin size to a specific value, it should be noted that the protruding fin size is generally larger than the target fin size due to the increased thickness of the Si cap 34. Therefore, the method 200 obtains CD1 and CD1 in operation 210.T The numerical difference between CD2 and CD2 T In this embodiment, the subsequent trimming process of method 200 is performed to ensure that the target fin size CD1 T and CD2 T are substantially the same as FW1 and FW2 measured in operation 202 , respectively.

[0037] Still reference Fig. 7A and Figure 7B , the method 200 continues in operation 212 to trim the first fin 30A and the second fin 30B based on the comparison result obtained in operation 210. As discussed above, because the composition of the first fin 30A is different from the composition of the second fin 30B, subjecting the first fin 30A and the second fin 30B to a common etchant may not be suitable for achieving the desired trimming results. Although existing methods for trimming fins are generally sufficient, they are not completely satisfactory in all aspects. For example, some methods may involve trimming the first fin 30A and the second fin 30B separately using a photolithography mask to protect the fins from being trimmed, which may unexpectedly increase the complexity and cost of production. However, in the present embodiment, the method 200 implements the etching process 404 ( Fig. 7A ) to selectively etch the first fin 30A, and perform an etching process 406 ( Figure 7B ) to selectively etch the second fin 30B. In some examples, the ratio of the etch selectivity (i.e., the ratio of the etch rates) of the first fin 30A relative to the second fin 30B during the etch process 404 and the etch selectivity of the second fin 30B relative to the first fin 30A during the etch process 406 can be at least about 5:1. In some embodiments, a dry ash process is performed after the etch processes 404 and 406 to remove any etching byproducts from the device 10.

[0038] Because each of the trimming processes is selective for etching fins of different compositions, method 200 does not require a specific order in which etching processes 404 and 406 are performed and the fins are exposed to each etching process together. Fig. 7A and Figure 7B The etching process 404 is shown to be performed before the etching process 406 ; alternatively, the method 200 may perform the etching process 406 before performing the etching process 404 .

[0039] In this embodiment, the etching process 404 is performed using a metal hydroxide (M n+ (OH - ) n), amine derivatives, other suitable reagents or combinations thereof. The metal hydroxide may include NaOH, KOH, LiOH, RbOH, CsOH, other suitable metal hydroxides or mixtures thereof. The amine derivative may include ammonia, tetramethylammonium hydroxide (TMAH), tetraethylammonium hydroxide (TEAH), tetradecyltrimethylammonium hydroxide (TTAH), tetrabutylammonium hydroxide (TBAH), other suitable amine derivatives or combinations thereof. Quaternary ammonium salts (-R4N + ), sulfate (-OSO3 - ), sulfonate (-SO3 - ), phosphate, carboxylate (-COO - ) derivatives or nonionic surfactants such as alcohol ethoxylates, alkylphenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, ethylene glycol esters, glycerol esters, or combinations thereof to reduce the surface tension of the etchant.

[0040] In the present embodiment, the etching process 406 is a wet etching process using an etchant including a metal hydroxide, an amine derivative, a combination thereof, one or more ionic surfactants, and an oxidant. The metal hydroxide, the amine derivative, and the ionic surfactant may be similar to those provided above with respect to the etching process 404. In the present embodiment, the oxidant not present in the etchant used for the etching process 404 includes ozone, hydrogen peroxide (H2O2), or a combination thereof dissolved in deionized water.

[0041] During the etching process 406, the oxidant is configured to oxidize the SiGe in the second fin 30B, and the resulting oxidized SiGe and / or germanium oxide is subsequently etched by a metal hydroxide and / or amine derivative that does not substantially attack the unoxidized second fin 30B. Although the oxidant may also oxidize the Si in the first fin 30A, this reaction is much slower than the oxidation of SiGe and / or Ge, and any silicon oxide formed by the oxidant is generally not etched by the metal hydroxide and / or amine derivative provided herein. Therefore, in the present embodiment, the addition of the oxidant enhances the selective etching of the second fin 30B relative to the first fin 30A. In some embodiments, during the etching process 406, the oxidant is mixed with the metal hydroxide and / or amine derivative. In some embodiments, the oxidant is applied to the device 10 before the metal hydroxide and / or amine derivative is applied, so that the oxidant first oxidizes the second fin 30B to form oxidized SiGe and / or germanium oxide, and the metal oxide and / or amine derivative then removes such oxidation products as well as portions of the first fin 30A. For embodiments in which any silicon oxide is formed during the etching process 406 , a wet etching process may be performed after trimming the first and second fins 30A, 30B, wherein the wet etching process utilizes an etchant that selectively removes silicon oxide from the first fin 30A but does not remove SiGe from the second fin 30B or does not remove unoxidized Si from the first fin 30A.

[0042] Various etching parameters may be adjusted to fine tune etching process 404 and / or etching process 406. For example, increasing the concentration of the etchant for a given etching process may increase the rate at which the fins are removed. Thus, the concentration of each etchant used to remove the first fin 30A and the second fin 30B is respectively equal to the numerical difference (CD1-CD1 T ) and (CD2-CD2 T ). In some embodiments, due to the effect of etchant loading as described above Figure 6 The LFD region and the HFD region discussed are different, so the amount of material removed by the etching processes 404 and 406 is different between the opposite sidewalls of the fin (e.g., the first fin 30A or the second fin 30B), thereby producing an asymmetric structure at the bottom of the fin in contact with the isolation structure 40 (described below with respect to FIG. Fig.9A and Fig. 9B (discussed in detail).

[0043] Subsequently, the method 200 measures the trimmed fin width FW1′ of the first fin 30A and the trimmed fin width FW2′ of the second fin 30B in operation 214 in a manner similar to those discussed with respect to operation 202. Based on the trimmed fin widths FW1′ and FW2′, and the protruding thicknesses T1 and T2 of the Si cap 34 obtained in operations 204 and 206, respectively, the method 200 determines the trimmed fin size CD1′ for the first fin 30A and the trimmed fin size CD2′ for the second fin 30B in operation 216, where CD1′=2*T1+FW1′, and CD2′=2*T2+FW2′. In some examples, CD1′ and CD2′ may each be about 5 nm to about 10 nm, and T1 and T2 may each be about 0.5 nm to about 3 nm (e.g., as discussed above, T2 may be about 0.7 nm to about 0.8 nm). Thus, the ratio of T1 to CD1′ and the ratio of T2 to CD2′ may each be about 0.05 to about 0.6. Similar to operation 210 discussed above, method 200 compares the trimmed fin dimensions to their corresponding target fin dimensions in operation 218, i.e., comparing CD1′ to CD1′. T Compare and compare CD2' with CD2 T In this embodiment, the control unit 201 determines in operation 220 whether the method 200 repeats operations 212 to 218, and in the case Figure 1A In the operation 110 shown, the first fin 30A and / or the second fin 30B are trimmed, or the Si cap 34 is deposited on the trimmed first fin 30A and the trimmed second fin 30B. T and / or if CD2' is greater than CD2 T , the trimming process is repeated, and the trimmed fin dimensions are measured and compared as discussed above, until the trimmed fin dimensions CD1′ and CD2′ are respectively less than or equal to the target fin dimension CD1 T and CD2 T Thus, the present invention provides a method suitable for fine-tuning the dimensions of Si-based fins and SiGe-based fins through a series of measurement, trimming and adjustment processes to account for the thickness (e.g., T1 and T2) of the Si cap 34 to be deposited over the Si-based fins and SiGe-based fins.

[0044] refer to Figure 8 , Fig.9A and Fig. 9B, the method 100 deposits the Si cap 34 to a thickness T1 over the trimmed first fin 30A having the trimmed fin width FW1′, and deposits the Si cap 34 to a thickness T2 over the trimmed second fin 30B having the trimmed fin width FW2′, as discussed above, in operation 110. Thus, the trimmed first fin 30A having the Si cap 34 is defined by the trimmed fin dimension CD1′, and the trimmed second fin 30B having the Si cap 34 is defined by the trimmed fin dimension CD2′. Furthermore, as will be discussed in detail below, portions of the Si cap 34 extend laterally beyond the bottom of the trimmed first fin 30A and the trimmed second fin 30B to contact the dielectric liner 32, thereby forming wing-like structures 37A and 38A over the first fin 30A, and wing-like structures 37B and 38B over the second fin 30B, wherein each of the wing-like structures is defined by a lateral dimension or wing width (WW). In some embodiments, the trimmed fin dimensions CD1' and CD2' are adjusted to substantially the same value to achieve uniformity in the component size. Therefore, due to the differences in T1 and T2 discussed in detail above, the first fin 30A and the second fin 30B can be trimmed to different fin widths FW1' and FW2', respectively. Specifically, some embodiments provide that FW1' is greater than FW2', that is, the second fin 30B is trimmed more than the first fin 30A.

[0045] The Si cap 34 may be epitaxially formed over the trimmed first fin 30A and the trimmed second fin 30B. For example, the method 200 may implement one or more selective epitaxial growth (SEG) processes discussed above with respect to forming layers 22A and 22B. The Si cap 34 may be epitaxially grown using a gaseous and / or liquid precursor that interacts with the composition of the underlying substrate (i.e., the first fin 30A comprising Si and the second fin 30B comprising SiGe). In the present embodiment, the Si cap 34 selectively nucleates from or epitaxially grows on the semiconductor surface (e.g., the first fin 30A and the second fin 30B) but not or substantially not on the dielectric surface (e.g., the isolation structure 40 and the dielectric liner 32 (if included)). In some embodiments, as will be discussed in detail below, a small portion of the Si cap 34 is deposited over a portion of the dielectric liner 32 due to epitaxial growth in the lateral direction (along the Y direction as shown herein).

[0046] refer to Fig.9A, various embodiments of the structure of the device 10 after forming the Si cap 34 are discussed in detail with respect to the second fin 30B. As provided herein, the second fin 30B is trimmed so that the top of the second fin 30B above the isolation structure 40 has a narrower fin width (i.e., a trimmed fin width FW2') than the bottom of the fin embedded in the isolation structure 40, which is defined by the fin width FW2 (i.e., the width of the untrimmed second fin 30B). This may be due to less etchant being loaded at the bottom of the second fin 30B than at the top of the second fin 30B during the etching process 406. The fin width FW2 of the unetched portion of the second fin 30B can be defined as the lateral spacing (along the Y direction) between the sidewalls S1 and S2, and the trimmed fin width FW2' can be defined as the lateral spacing between the sidewalls S1' and S2'. In the present embodiment, the first transition region between the sidewalls S1 and S1' and the second transition region between the sidewalls S2 and S2' each have a tapered profile, i.e., each transition region is defined by a curved surface. The lateral (in the Y direction) offset or displacement between S1 and S1' and between S2 and S2' is defined as fin shoulder FS1 and fin shoulder FS2, respectively. In other words, the first transition region extends laterally from S1' by a distance FS1, and the second transition region extends laterally from S2' by a distance FS2. In other words, the fin width FW2 is the numerical sum of the trimmed fin width FW2', the fin shoulder FS1, and the fin shoulder FS2, or FW2 = FW2' + FS1 + FS2. In some embodiments, as described herein, FS1 and FS2 are different in size. In this embodiment, regardless of the composition of the fin, the fin shoulder is generally in the range of about 0.5 nm to about 3 nm; of course, this embodiment does not limit the fin shoulder to a specific value. On the one hand, if the fin shoulder is less than about 0.5 nm, indicating a smaller degree of trimming, the subsequently deposited Si cap 34 may not be thick enough to effectively prevent oxidation of the SiGe-based fin (i.e., the second fin 30B). On the other hand, if the shoulder of the fin is greater than about 3 nm, indicating a greater degree of trimming, the structural integrity of the trimmed fin may be compromised.

[0047] Still reference Fig.9ADue to the presence of the fin shoulders, the formation of the Si cap 34 also tapers at the transition region extending from each sidewall S1' and S2'. As discussed above, although the Si cap 34 is not typically epitaxially grown on a dielectric surface (such as a dielectric liner 32 or an isolation structure 40), each fin shoulder provides a surface over which the Si cap 34 is laterally epitaxially overgrown, resulting in the small wing-like structures 37B and 38B each extending above the top surface of the dielectric liner 32, so that the outer edge of the Si cap 34 terminates at the tip of each wing-like structure. The wing-like structure 37B can be defined by a wing width WW1, and the wing-like structure 38B can be defined by a wing width WW2, where WW1 is the lateral offset between the sidewall S1 and the tip of the wing-like structure 37B, and WW2 is the lateral offset between the sidewall S2 and the tip of the wing-like structure 38B. In some embodiments, the size of the wing width depends on the epitaxial growth conditions of the Si cap 34. For example, if the epitaxial growth rate increases due to a higher precursor concentration, the wing width also increases in size. In this regard, because the Si cap 34 grows faster on SiGe than on Si as discussed above, the wing widths WW1 and WW2 of the second fin 30B are generally larger than those of the Si cap 34. Fig. 9B The wing widths WW3 and WW4 of the first fin 30A are shown. In some examples, each of the wing widths WW1, WW2, WW3, and WW4 may be less than about 3 nm. In some examples, the wing structures 37B and / or 38B may not be present in the device 10, i.e., the Si cap 34 does not extend above the top surface of the dielectric liner 32, so that WW1 and / or WW2 are approximately 0. In addition, in the present embodiment, each of WW1 and WW2 is less than or equal to each of FS1 and FS2.

[0048] In addition, in the present embodiment, the fin protrusion dimension or FPCD takes into account the fin shoulder and the wing width of the trimmed fin with the Si cap 34 formed thereon, that is, FPCD1=FS1+WW1, and FPCD2=FS2+WW2. Therefore, in some examples, FPCD1 and FPCD2 can each be about 0.5nm to about 6nm, and the ratio of FPCD (e.g., FPCD1 or FPCD2) to the trimmed fin dimension CD2' can be about 0.05 to about 1.2 (see the examples of CD1' and CD2' discussed above). In some cases, excessive expansion of FPCD due to the formation of fin shoulders and / or wing-like structures can cause leakage problems, resulting in reduced device performance. Therefore, the present embodiment provides FS1 and FS2 from about 0.5nm to about 3nm, and WW1 and WW2 are less than about 3nm.

[0049] Furthermore, as mentioned above, Fig. 7A and Figure 7BDue to the differences in etchant loading discussed above, the wing structures extending from the opposite sidewalls of the second fin 30B can be vertically displaced. For example, the wing structure 37B is disposed above the wing structure 38B by a vertical distance D1. As shown herein, this vertical offset is consistent with the above description of Figure 6 The difference between the height H1 and the height H2 discussed is consistent. In other words, the vertical position of the wing-like structure is inversely proportional to the step height of the fin measured from the top surface of the isolation structure 40 to the top surface of the fin of a given sidewall. Because more of the portion of the etched isolation structure 40 located in the LFD region is than the portion in the HFD region discussed above, the second fin 30B has a fin step height H3 in the HFD region that is less than the fin step height H4 in the LFD region. Therefore, the wing-like structure 37B disposed in the HFD region is located above the wing-like structure 38B disposed in the LFD region.

[0050] Fig. 9B depicts a display similar to reference Fig.9A Embodiments of trimmed first fins 30A of various components of the structural relationships of those of the trimmed second fins 30B depicted and discussed. For example, the third transition region between sidewalls S3 and S3' and the fourth transition region between sidewalls S4 and S4' each have a tapered profile, and the lateral (in the Y direction) displacement between S3 and S3' and between S4 and S4' is defined as fin shoulder FS3 and fin shoulder FS4, respectively. In other words, fin width FW1 is the numerical sum of the trimmed fin width FW1', fin shoulder FS3, and fin shoulder FS4, or FW1 = FW1' + FS3 + FS4. In this embodiment, each of FS3 and FS4 is smaller than FS1 and FS2 because the first fin 30A is typically trimmed to a lesser degree than the second fin 30B discussed in detail above. Depositing Si cap 34 over each trimmed first fin 30A forms wing structures 37A and 38A defined by wing widths WW3 and WW4, respectively, which contribute to the size of FPCD3 and FPCD4 similar to that defined by FPCD1 and FPCD2 above. In the present embodiment, each of WW3 and WW4 is generally smaller than each of WW1 and WW2 because the epitaxial growth rate of Si cap 34 is generally lower on the first fin 30A than on the second fin 30B. Therefore, in the present embodiment, each of FPCD3 and FPCD4 is generally smaller than each of FPCD1 and FPCD2. Furthermore, in the present embodiment, each of WW3 and WW4 is generally smaller than each of FS3 and FS4. Still similar to Fig.9A In the illustrated embodiment of the second fin 30B, the wing structures 37A and 38A may be vertically displaced by a distance D2, and such displacement is inversely proportional to the difference in fin step height between the HFD region and the LFD region.

[0051] Reference now Fig. 10A and Fig. 10BIn operation 112, method 100 performs the following steps: Fig. 10B A dummy (or reserved position) gate stack 52 is formed above the channel regions of the first fin 30A and the second fin 30B as shown. Fig. 10A As shown, during operation 112, the S / D regions of the first fin 30A and the second fin 30B remain the same as Figure 8 , Fig.9A and Fig. 9B The S / D regions shown are substantially the same. In the present embodiment, the method 100 first forms an interfacial layer (IL) 50 over the Si cap 34 in the device region 10A and the device region 10B before forming the dummy gate stack 52. The IL 50 may include a suitable material, such as silicon oxide (e.g., SiO2), and may be formed over the Si cap 34 by a deposition process (e.g., CVD), thermal oxidation, chemical oxidation, other suitable processes, or combinations thereof. Typically, the process of forming the IL 50 may accidentally oxidize the SiGe-based second fin 30B, thereby degrading device performance. However, in the present embodiment, the Si cap 34 formed in operation 110 is configured to protect the underlying second fin 30B during operation 112 and / or any subsequent oxidation process.

[0052] The dummy gate stack 52 is configured to be partially or completely replaced by a metal gate stack during subsequent processing steps. The dummy gate stack 52 includes at least a gate electrode layer including polysilicon, which can be formed by first depositing a blanket layer of polysilicon over the device 10 and then applying an anisotropic etching process over the IL 50 to form the dummy gate stack 52. The dummy gate stack 52 may include additional material layers, such as a gate dielectric layer, a hard mask layer, other suitable layers, or combinations thereof. The various layers of the dummy gate stack 52 may be formed by suitable processes such as CVD, ALD, PVD (physical vapor deposition), other suitable methods, or combinations thereof.

[0053] Although not shown herein, the method 100 forms gate spacers on the sidewalls of the dummy gate stack 52 in operation 112. In some embodiments, the gate spacers include a dielectric material such as silicon dioxide, silicon nitride, carbon and / or oxygen doped silicon nitride, silicon carbide, oxygen doped silicon carbide, low-k dielectric materials, high-k dielectric materials, other suitable dielectric materials, or combinations thereof. The gate spacers can be formed by first depositing a blanket layer of spacer material over the device 10 and then performing an anisotropic etching process to remove portions of the spacer material to form gate spacers on the sidewalls of the dummy gate stack 52.

[0054] Reference now FIG. 11A to FIG. 12B , the method 100 performs operation 114 on the S / D regions ( Fig.11A and Fig. 12A ) are formed in the S / D components 62A and 62B, and the channel regions ( Fig. 11B and Fig. 12B ) Keep with Fig. 10B The channel regions shown are substantially the same. In the present embodiment, S / D components 62A and 62B include dopants (or impurities) suitable for forming the desired device. In the present embodiment, S / D component 62A is doped with n-type dopants to provide an NMOS device, and S / D component 62B is doped with p-type dopants to provide a PMOS device. S / D components 62A and 62B can be formed by any suitable technique, such as an etching process followed by one or more epitaxial processes. In one example, reference Fig.11A , one or more etching processes are performed to remove portions of the first fin 30A and the second fin 30B to form recesses 60A and 60B, respectively. A cleaning process may then be performed to clean the recesses 60A and 60B with a hydrofluoric acid (HF) solution and / or other suitable solutions. Thereafter, one or more epitaxial growth processes similar to those discussed above with respect to forming the Si cap 34 are performed on the S / D components 62A and 62B in the recesses 60A and 60B, respectively. The S / D component 62A may include one or more epitaxial layers of silicon (epitaxial Si) or silicon carbon (epitaxial SiC) doped with n-type dopants such as arsenic, phosphorus, other n-type dopants, or combinations thereof, and the S / D component 62B may include one or more epitaxial layers of silicon germanium (epitaxial SiGe) doped with p-type dopants such as boron, germanium, indium, other p-type dopants, or combinations thereof. The method 100 may then perform an annealing process on the S / D components 62A and 62B in operation 114 to activate the dopants.

[0055] Then, refer to FIG. 13A to FIG. 15B , the method 100 replaces the dummy gate stack 52 with the metal gate stack 80 in operation 116. Fig.13A, before removing the dummy gate stack 52 to form the gate trench 74, the method 100 first forms an etch stop layer (ESL) 70 over the S / D features 62A and 62B. In the present embodiment, the ESL 70 includes a dielectric material such as silicon nitride, carbon-doped silicon nitride, aluminum oxide, aluminum nitride, other suitable materials, or combinations thereof. The ESL 70 may be conformally deposited over the device 10 by CVD, ALD, other suitable deposition methods, or combinations thereof. Thereafter, the method 100 forms an interlayer dielectric (ILD) layer 72 over the device 10 and then performs a CMP process to expose the top surface of the dummy gate stack 52. In the present embodiment, the ILD layer 72 includes a dielectric material such as silicon dioxide (SiO2), a low-k dielectric material, tetraethyl orthosilicate (TEOS), doped silicon dioxide (such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), other suitable dielectric materials, or combinations thereof. The ILD layer 72 may include a multi-layer structure or a single-layer structure, and may be formed by a deposition process such as CVD, FCVD, SOG, other suitable methods, or combinations thereof. Reference Fig.14A and Fig. 14B , the method 100 then removes the dummy gate stack 52 to form the gate trench 74 adjacent to the S / D features 62A and 62B. The method 100 selectively removes the dummy gate stack 52 without removing or substantially removing other portions of the device 10. In some embodiments, as shown herein, after removing the dummy gate stack 52, the IL 50 remains over the Si cap 34 and becomes part of the metal gate stack 80 formed thereafter.

[0056] Afterwards, refer to Fig.15A and Fig. 15B, the method 100 forms a metal gate stack 80 in the gate trench 74. In the present embodiment, the metal gate stack 80 includes at least a gate dielectric layer 82 disposed above the IL 50 and a metal gate electrode 84 disposed above the gate dielectric layer 82. The gate dielectric layer 82 may include silicon oxide, silicon oxynitride, aluminum silicon oxide, a high-k dielectric material (i.e., having a dielectric constant greater than the dielectric constant of silicon oxide, the dielectric constant of silicon oxide being approximately 3.9) (such as hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate), other suitable dielectric materials, or combinations thereof. In the present embodiment, the metal gate electrode 84 includes at least a work function metal layer (not shown separately) disposed above the gate dielectric layer 82 and a bulk conductive layer (not shown separately) disposed above the work function metal layer. The work function metal layer may be a p-type or n-type work function metal layer, and may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The metal gate electrode 84 may include additional work function metal layers having similar or different conductivity types. The bulk conductive layer may include Cu, W, Al, Co, Ru, other suitable metals, or combinations thereof. The metal gate stack 80 may further include other layers (not shown), such as a capping layer, a barrier layer, other suitable layers, or combinations thereof. The various layers of the metal gate stack 80 may be deposited by any suitable method such as ALD, CVD, PVD, plating, other suitable methods, or combinations thereof.

[0057] Subsequently, the method 100 may perform additional processing steps on the device 10 including multiple dielectric layers and conductive features disposed in the dielectric layers in operation 118. For example, the method 100 may form S / D contacts (not shown) in the ILD layer 72 to contact the S / D features 62A and / or 62B and one or more gate contacts (not shown) to contact the metal gate stack 80. In addition, the method 100 may form a multi-layer interconnect (MLI) structure over the S / D contacts and the gate contacts. The MLI may include horizontal interconnect features (e.g., metal lines) and vertical interconnect features (e.g., vias) disposed in various ILD layers and ESLs, wherein the vertical interconnect features are configured to connect horizontal interconnect features of different layers.

[0058] Although not intended to be limiting, one or more embodiments of the present invention provide numerous benefits to semiconductor devices and their formation. The present invention provides a method for selectively trimming Si-based fins and SiGe-based fins without the need to perform a photolithography process and form a Si cap (optionally referred to as a Si-containing layer) over the trimmed Si-based fins and SiGe-based fins to protect the SiGe-based fins from accidental oxidation during subsequent manufacturing processes. Embodiments of the present invention provide an adjustable trimming process based on the desired thickness of the Si cap over the SiGe-based fins, so that the resulting fin size (including the thickness of the Si cap) is consistent with the desired feature size (e.g., CD). In this embodiment, the resulting trimmed fins show various structural features, such as fin shoulders and wing-like structures, which reflect the extent of the trimming process and the subsequent Si cap formation process. Advantageously, as feature sizes (such as fin sizes) continue to decrease, the device structure of the present invention provides a SiGe-based channel to address issues related to adjusting V t Related challenges.

[0059] In one aspect, the present embodiment provides a semiconductor structure including a silicon germanium (SiGe) fin protruding from a substrate and an isolation feature disposed above the substrate and surrounding a bottom of the SiGe fin, wherein the SiGe fin includes a top portion having a first sidewall and a second sidewall, the top portion being disposed above a bottom portion having a third sidewall and a fourth sidewall, and wherein a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively. The semiconductor structure also includes a Si-containing layer disposed on the top of the SiGe fin, wherein a first portion of the Si-containing layer disposed on the first transition region extends a first lateral distance away from the first sidewall, and a second portion of the Si-containing layer disposed on the second transition region extends a second lateral distance away from the second sidewall that is different from the first lateral distance, and wherein a spacing between external vertical surfaces of the Si-containing layer is defined by a third lateral distance. In addition, the semiconductor structure includes: a metal gate stack disposed above the Si-containing layer in a channel region of the SiGe fin.

[0060] In some embodiments, the spacing between the first sidewall and the second sidewall defines a first width of the silicon germanium fin, and the spacing between the third sidewall and the fourth sidewall defines a second width of the silicon germanium fin that is greater than the first width. In some embodiments, the ratio of the first lateral distance to the third lateral distance and the ratio of the second lateral distance to the third lateral distance are each about 0.05 to about 1.2. In some embodiments, the first transition region and the second transition region extend from the first sidewall and the second sidewall, respectively, by about 0.5 nm to about 3 nm. In some embodiments, the first portion of the silicon-containing layer extends a fourth lateral distance away from the third sidewall, and the second portion of the silicon-containing layer extends a fifth lateral distance away from the fourth sidewall, and wherein the fourth lateral distance and the fifth lateral distance are less than or equal to a width of the first transition region and a width of the second transition region, respectively. In some embodiments, the fourth lateral distance or the fifth lateral distance is about 0. In some embodiments, the first transition region and the second transition region are vertically offset along the height of the silicon germanium fin. In some embodiments, the semiconductor structure further comprises: a dielectric liner disposed between the isolation feature and the bottom of the silicon germanium fin, wherein the first portion, the second portion, or both portions of the silicon-containing layer extend over the dielectric liner. In some embodiments, a portion of the dielectric liner disposed on the third sidewall has a first height, and a portion of the dielectric liner disposed on the fourth sidewall has a second height different from the first height.

[0061] On the other hand, the present embodiment provides a semiconductor structure, including: a semiconductor substrate having a first region and a second region; an isolation structure disposed above the first region and the second region; a first fin protruding from the semiconductor substrate in the first region; a second fin protruding from the semiconductor substrate in the second region; a Si layer disposed above the first fin and the second fin; and a metal gate stack disposed above the Si layer in the channel region of the first fin and the channel region of the second fin. In the present embodiment, the first fin includes silicon (Si) and substantially no germanium (Ge), wherein a portion of the first fin in contact with the top surface of the isolation structure extends laterally away from the sidewall of the first fin to form a first fin shoulder. In addition, the second fin includes Si and Ge, wherein a portion of the second fin in contact with the top surface of the isolation structure extends laterally away from the sidewall of the second fin to form a second fin shoulder, and wherein the second fin shoulder has a width greater than the first fin shoulder. Further, a portion of the Si layer disposed above the first fin has a first thickness, and a portion of the Si layer disposed above the second fin has a second thickness greater than the first thickness.

[0062] In some embodiments, an outermost edge of the silicon layer extends laterally a first distance from the sidewall of the first fin, and an outermost edge of the silicon layer extends laterally a second distance greater than the first distance from the sidewall of the second fin. In some embodiments, a ratio of the first distance or the second distance to the spacing distance between the vertical sidewalls of the silicon layer is about 0.05 to about 1.2. In some embodiments, the bottom of the first fin and the bottom of the second fin are embedded in the isolation structure, and the semiconductor structure further includes: a dielectric layer disposed between the isolation structure and the bottom of the first fin and between the isolation structure and the bottom of the second fin. In some embodiments, the silicon layer extends laterally to contact a top surface of the dielectric layer.

[0063] In another aspect, the present embodiment provides a method, comprising: forming a semiconductor substrate having a first region and a second region; forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin comprises silicon germanium (SiGe) and the second fin comprises silicon (Si) but no germanium (Ge); determining a thickness of a Si-containing layer to be deposited over the first fin; and trimming the first fin based on the thickness of the Si-containing layer, wherein the trimming of the first fin forms a fin shoulder protruding from a sidewall of the trimmed first fin. Subsequently, the method continues by depositing a Si-containing layer over the trimmed first fin to a determined thickness, wherein a portion of the Si-containing layer extends laterally beyond the fin shoulder; forming a dummy gate stack over the portion of the Si-containing layer; forming a source / drain (S / D) feature adjacent to the dummy gate stack in the first fin and the second fin; and replacing the dummy gate stack with a metal gate stack.

[0064] In some embodiments, the method further comprises: before depositing the silicon-containing layer: measuring a first width of the first fin; determining a first size based on the first width and the thickness of the silicon-containing layer; comparing the first size to a first target size of the first fin; and trimming the first fin based on the result of the comparison, wherein trimming the first fin is configured to remove a portion of the first fin without substantially removing a portion of the second fin. In some embodiments, trimming the first fin comprises: oxidizing silicon germanium in the first fin with an etchant; and removing the oxidized silicon germanium with the etchant, wherein the etchant comprises an oxidant and a metal hydroxide, an amine derivative, or a combination thereof. In some embodiments, the thickness of the silicon-containing layer is a first thickness, and wherein depositing the silicon-containing layer forms the silicon-containing layer over the second fin to a second thickness, and wherein the second thickness is less than the first thickness. In some embodiments, the method further comprises: before depositing the silicon-containing layer: measuring a second width of the second fin; determining a second size based on the second width and the second thickness of the silicon-containing layer; comparing the second size to a second target size of the second fin; and trimming the second fin based on the result of the comparison, wherein trimming the second fin is configured to remove a portion of the second fin without substantially removing a portion of the first fin. In some embodiments, trimming the second fin includes applying an etchant including a metal hydroxide, an amine derivative, or a combination thereof, and wherein the etchant is free of an oxidizing agent.

[0065] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand aspects of the present invention. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: Semiconductor substrate; a silicon germanium fin protruding from the semiconductor substrate, wherein the silicon germanium fin includes a top portion having a first sidewall and a second sidewall, the top portion being disposed above a bottom portion having a third sidewall and a fourth sidewall, and wherein each of a first transition edge connecting the first sidewall to the third sidewall and a second transition edge connecting the second sidewall to the fourth sidewall has a tapered profile extending away from the first sidewall and the second sidewall, respectively, wherein the first transition edge extends to a greater height above the semiconductor substrate than the second transition edge; an isolation component disposed above the semiconductor substrate and surrounding the bottom of the silicon germanium fin; a silicon-containing layer disposed on the top portion of the silicon-germanium fin, wherein a first portion of the silicon-containing layer disposed on the first transition edge extends a first lateral distance away from the first sidewall, and a second portion of the silicon-containing layer disposed on the second transition edge extends a second lateral distance away from the second sidewall that is different than the first lateral distance, and wherein a spacing between outer vertical surfaces of the silicon-containing layer is defined by a third lateral distance; and A metal gate stack is disposed over the silicon-containing layer in the channel region of the silicon germanium fin.

2. The semiconductor structure according to claim 1, wherein: A space between the first sidewall and the second sidewall defines a first width of the silicon germanium fin, and a space between the third sidewall and the fourth sidewall defines a second width of the silicon germanium fin that is greater than the first width.

3. The semiconductor structure according to claim 1, wherein: A ratio of the first lateral distance to the third lateral distance and a ratio of the second lateral distance to the third lateral distance are each 0.05±10% to 1.2±10%.

4. The semiconductor structure according to claim 1, wherein: The first transition edge and the second transition edge extend from the first sidewall and the second sidewall by 0.5 nm±10% to 3 nm±10%, respectively.

5. The semiconductor structure according to claim 4, wherein: The first portion of the silicon-containing layer extends a fourth lateral distance away from the third sidewall, and the second portion of the silicon-containing layer extends a fifth lateral distance away from the fourth sidewall, and wherein the fourth lateral distance and the fifth lateral distance are less than or equal to a width of the first transition edge and a width of the second transition edge, respectively.

6. The semiconductor structure according to claim 5, wherein: The fourth lateral distance or the fifth lateral distance is 0±10%.

7. The semiconductor structure according to claim 1, wherein: The first transition edge and the second transition edge are vertically offset along a height of the silicon germanium fin.

8. The semiconductor structure according to claim 1, further comprising: A dielectric liner is disposed between the isolation feature and the bottom of the silicon germanium fin, wherein the first portion, the second portion, or both portions of the silicon-containing layer extend over the dielectric liner.

9. The semiconductor structure according to claim 8, wherein: A portion of the dielectric liner disposed on the third sidewall has a first height, and a portion of the dielectric liner disposed on the fourth sidewall has a second height different from the first height.

10. A semiconductor structure comprising: A semiconductor substrate including a first region and a second region; An isolation structure, disposed above the first region and the second region; a first fin protruding from the semiconductor substrate in the first region, wherein the first fin includes silicon and is free of germanium, wherein the first fin includes a first upper portion and a first lower portion, wherein the first upper portion has a first edge and a second edge opposite the first edge, and the first lower portion has a third edge and a fourth edge opposite the third edge, wherein the first fin further includes a first transition edge that tapers from the third edge toward the first edge, and the first edge and the third edge are on a same side of the first fin; a second fin protruding from the semiconductor substrate in the second region, wherein the second fin comprises silicon and germanium, wherein the second fin comprises a second upper portion and a second lower portion, wherein the second upper portion has a fifth edge and a sixth edge opposite to the fifth edge, and the second lower portion has a seventh edge and an eighth edge opposite to the seventh edge, wherein the second fin further comprises a second transition edge tapering from the seventh edge to the fifth edge, the fifth edge and the seventh edge being on a same side of the second fin, and wherein the first transition edge extends to a different height above the semiconductor substrate than the second transition edge; a silicon layer disposed over the first fin and the second fin, wherein a portion of the silicon layer disposed over the first fin has a first thickness, and a portion of the silicon layer disposed over the second fin has a second thickness greater than the first thickness; and A metal gate stack is disposed over the silicon layer in the channel region of the first fin and the channel region of the second fin.

11. The semiconductor structure according to claim 10, wherein: An outermost edge of the silicon layer extends laterally a first distance from a sidewall of the first fin, and an outermost edge of the silicon layer extends laterally a second distance from a sidewall of the second fin that is greater than the first distance.

12. The semiconductor structure according to claim 11, wherein: A ratio of the first distance or the second distance to a spacing distance between vertical sidewalls of the silicon layer is 0.05±10% to 1.2±10%.

13. The semiconductor structure according to claim 10, wherein: The bottom of the first fin and the bottom of the second fin are embedded in the isolation structure. The semiconductor structure further includes a dielectric layer disposed between the isolation structure and the bottom of the first fin and between the isolation structure and the bottom of the second fin.

14. The semiconductor structure according to claim 13, wherein: The silicon layer extends laterally to contact a top surface of the dielectric layer.

15. A method of forming a semiconductor structure, comprising: forming a semiconductor substrate having a first region and a second region; forming a first fin protruding from the first region and a second fin protruding from the second region, wherein the first fin comprises silicon germanium and the second fin comprises silicon but no germanium; determining a thickness of a silicon-containing layer to be deposited over the first fin; trimming the first fin based on the thickness of the silicon-containing layer, wherein trimming the first fin forms a fin shoulder protruding from a sidewall of the trimmed first fin; depositing the silicon-containing layer to a determined thickness over the trimmed first fin, wherein a portion of the silicon-containing layer extends laterally beyond the fin shoulder; forming a dummy gate stack over a portion of the silicon-containing layer; forming source / drain features in the first fin and the second fin adjacent to the dummy gate stack; and The dummy gate stack is replaced with a metal gate stack.

16. The method according to claim 15, further comprising: Prior to depositing the silicon-containing layer: measuring a first width of the first fin; determining a first dimension based on the first width and the thickness of the silicon-containing layer; comparing the first size to a first target size of the first fin; as well as The first fin is trimmed based on a result of the comparing, wherein trimming the first fin is configured to remove a portion of the first fin without removing a portion of the second fin.

17. The method according to claim 16, wherein: Trimming the first fin includes: oxidizing the silicon germanium in the first fin with an etchant; and The oxidized silicon germanium is removed by using the etchant, wherein the etchant includes an oxidant and a metal hydroxide, an amine derivative, or a combination thereof.

18. The method according to claim 15, wherein: The silicon-containing layer has a first thickness, and wherein depositing the silicon-containing layer forms the silicon-containing layer over the second fin to a second thickness, and wherein the second thickness is less than the first thickness.

19. The method according to claim 18, further comprising: Prior to depositing the silicon-containing layer: measuring a second width of the second fin; determining a second dimension based on the second width and the second thickness of the silicon-containing layer; comparing the second size to a second target size of the second fin; as well as The second fin is trimmed based on a result of the comparing, wherein trimming the second fin is configured to remove a portion of the second fin without removing a portion of the first fin.

20. The method according to claim 19, wherein: Trimming the second fin includes applying an etchant including a metal hydroxide, an amine derivative, or a combination thereof, and wherein the etchant is free of an oxidizing agent.

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