Display device

Abstract

A display device is provided that includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate includes a gate line, a data line, a storage electrode, and a switching element. The switching element is connected to the data line and the gate line. The first substrate further includes a pixel electrode, a shield electrode, and a first capacitor electrode and a second capacitor electrode. The pixel electrode is connected to an output electrode of the switching element, and the shield electrode includes a line portion disposed along the data line and an extension portion extending from the line portion. The first capacitor electrode extends from the output electrode and overlaps the pixel electrode and the storage electrode. The second capacitor electrode is disposed spaced apart from the first capacitor electrode and overlaps the extension portion of the shield electrode and the storage electrode.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a display device. More particularly, the present disclosure relates to a display device operating in a vertical alignment mode to improve transmittance and display quality. BACKGROUND

[0002] A liquid crystal display apparatus includes a liquid crystal display panel including two substrates facing each other and a liquid crystal layer disposed between the substrates. The liquid crystal display apparatus supplies a voltage to an electrode generating an electric field to apply an electric field to the liquid crystal layer. Accordingly, an alignment direction of liquid crystal molecules of the liquid crystal layer is determined, and an image is displayed by controlling polarization of incident light.

[0003] In a liquid crystal display apparatus, a liquid crystal display apparatus in which long axes of liquid crystal molecules are arranged in a vertical alignment mode perpendicular to two substrates in a state in which an electric field is not applied has a large contrast ratio, and a wide reference viewing angle can be easily implemented.

[0004] To improve a viewing angle characteristic of a liquid crystal display apparatus, a technology for dividing a pixel area into a plurality of domains and controlling has been developed, and examples of such a technology include a Charge Share (CS) method and a Resistivity Division (RD) method.

[0005] However, when the CS method or the RD method is employed, a large number of transistors and a large number of capacitors are required, thereby having a problem of reducing transmittance of a liquid crystal display panel. SUMMARY

[0006] The present disclosure provides a display device having improved transmittance and display quality.

[0007] An embodiment of the present disclosure provides a display device including a first substrate, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate.

[0008] The first substrate includes a gate line, a data line insulated from the gate line, a storage electrode insulated from the gate line and the data line, respectively, a switching element electrically connected to the data line and the gate line, a pixel electrode electrically connected to an output electrode of the switching element, and a shield electrode insulated from the pixel electrode and having a line portion disposed in alignment with the data line and an extension portion extending from the line portion. The first substrate further includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode extends from the output electrode and overlaps the pixel electrode and the storage electrode. The second capacitor electrode is disposed spaced apart from the first capacitor electrode and overlaps the extension portion of the shield electrode and the storage electrode.

[0009] In an embodiment, the second capacitor electrode can be in direct contact with the extension portion of the shield electrode.

[0010] In an embodiment, the first capacitor electrode can be in direct contact with the pixel electrode.

[0011] In an embodiment, an area of the second capacitor electrode can be greater than an area of the first capacitor electrode.

[0012] In an embodiment, the first substrate can further include a first insulating layer disposed on the gate line and the storage electrode and making the output electrode, the data line, and the first and second capacitor electrodes disposed on the gate line and the storage electrode, and a second insulating layer disposed on the output electrode, the data line, and the first and second capacitor electrodes and making the pixel electrode and the shield electrode disposed on the output electrode, the data line, and the first and second capacitor electrodes.

[0013] In an embodiment, the second insulating layer can include a first contact hole configured to expose the first capacitor electrode and a second contact hole configured to expose the second capacitor electrode, the pixel electrode can be in direct contact with the first capacitor electrode through the first contact hole, and the extension of the shield electrode can be in direct contact with the second capacitor electrode through the second contact hole.

[0014] In an embodiment, the second substrate can include a reference electrode to which a first reference voltage is applied, and a second reference voltage can be applied to the shield electrode.

[0015] In an embodiment, a storage voltage can be applied to the storage electrode, and the first and second reference voltages can each have a voltage level different from the storage voltage.

[0016] In an embodiment, the first and second reference voltages can have the same voltage level.

[0017] In an embodiment, the first substrate can further include a storage line insulated from the gate line and the data line, and the storage line can be connected to the storage electrode.

[0018] In an embodiment of the disclosure, a display device includes a gate line, a data line insulated from the gate line, a storage line insulated from the gate line and the data line, and a pixel connected to the gate line, the data line, and the storage line.

[0019] In an embodiment, the pixel can include a switching element electrically connected to the gate line and the data line, a liquid crystal capacitor electrically connected to the output electrode of the switching element, a first storage capacitor electrically connected to the liquid crystal capacitor and the storage line, and a second storage capacitor electrically connected to the storage line and the shield electrode.

[0020] In an embodiment, the liquid crystal capacitor may include: a pixel electrode that is electrically connected to the output electrode of the switching element as a first electrode, and a reference electrode that faces the pixel electrode as a second electrode.

[0021] In an embodiment, the first storage capacitor may include: a storage electrode that is electrically connected to the storage line as a first electrode, and a first capacitor electrode that overlaps with the storage electrode and extends from the output electrode as a second electrode.

[0022] In an embodiment, the second storage capacitor may include: a storage electrode serving as a first electrode and a second capacitor electrode serving as a second electrode, which overlaps with the storage electrode and is in direct contact with the shielding electrode.

[0023] In an embodiment, the storage electrode can receive the storage voltage via a storage line, the reference electrode can receive a first reference voltage having a voltage level different from the storage voltage, and the shielding electrode can receive a second reference voltage having a voltage level different from the storage voltage.

[0024] In an embodiment, the first reference voltage and the second reference voltage may have the same voltage level.

[0025] In one embodiment, the capacitance of the second storage capacitor may be greater than that of the first storage capacitor. Attached Figure Description

[0026] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0027] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure;

[0028] Figure 2 This is a plan view of a display device according to an embodiment of the present disclosure;

[0029] Figure 3 This is a plan view illustrating the layout of pixels according to an embodiment of the present disclosure;

[0030] Figure 4 yes Figure 3 A magnified view of area AA shown;

[0031] Figure 5A It is along Figure 3 The sectional view shown is taken by line I-I'.

[0032] Figure 5B It is along Figure 3 The sectional view shown is taken by line II-II'.

[0033] Figure 6A is an enlarged view partially showing a layout of a pixel according to an embodiment of the disclosure;

[0034] Figure 6B is a plan view of a first capacitor electrode and a second capacitor electrode according to an embodiment of the disclosure;

[0035] Figure 6C is a plan view of a first capacitor electrode and a second capacitor electrode according to an embodiment of the disclosure;

[0036] Figure 6D is a cross-sectional view taken along line III-III' shown in FIG. 3B; Figure 6A

[0037] Figure 7 is an enlarged view partially showing a layout of a pixel according to an embodiment of the disclosure;

[0038] Figure 8 is an equivalent circuit diagram of a pixel shown in FIG. 4A; Figure 7

[0039] Figure 9 is an equivalent circuit diagram of a pixel shown in FIG. 4B; Figure 6A

[0040] Figure 10A is a waveform diagram showing a storage voltage shown in FIG. 5A; Figure 9

[0041] Figure 10B is a waveform diagram showing a pixel voltage of FIG. 5B charged to a liquid crystal capacitor; and Figure 9

[0042] Figure 10C is an enlarged waveform diagram showing a BB region of FIG. 6. Figure 10B DETAILED DESCRIPTION

[0043] In the disclosure, when an element (or a region, a layer, a part, and the like) is referred to as being "on" or "connected to" or "coupled to" another element, it means that the element can be directly on, connected to, or coupled to the other element or a third element can be present in between.

[0044] Like reference numerals refer to like elements throughout the specification. Also, in the drawings, the thickness, proportions, and dimensions of elements can be exaggerated for effective description of the technical content.

[0045] The term "and / or" includes all combinations of one or more of the associated configurations.

[0046] ​​​​​​It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the example embodiments of this disclosure. The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0047] In addition, terms such as "below", "under", "above", "on", and similar terms are used to describe relationships of configuration shown in the drawings. These terms are used as relative concepts and are described with reference to the directions indicated in the drawings.

[0048] It should be understood that the terms "comprise" or "have" are intended to denote that there are features, integers, steps, operations, elements, components or combinations thereof described in the disclosure, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.

[0049] Hereinafter, example embodiments of the disclosure will be described with reference to the accompanying drawings.

[0050] Figure 1 is a block diagram of a display apparatus 1000 according to an embodiment of the disclosure, and Figure 2 is a plan view of a display apparatus 1000 according to an example of the disclosure.

[0051] Referring to Figure 1 , a display apparatus 1000 according to an embodiment of the disclosure includes a display panel 100 for displaying an image, a plurality of panel drivers 200, 300, and 400 for driving the display panel 100, a backlight unit 500 for providing light to the display panel 100, and a backlight driver 600 for driving the backlight unit 500. In an embodiment of the disclosure, the plurality of panel drivers 200, 300, and 400 can include a gate driver 200, a data driver 300, and a signal controller 400.

[0052] The display panel 100 includes a plurality of gate lines from GL1 to GLn, a plurality of data lines from DL1 to DLm, and a plurality of pixels PX. The plurality of gate lines from GL1 to GLn are arranged in parallel to each other in a first direction DR1. The plurality of gate lines from GL1 to GLn can extend in a second direction DR2 crossing the first direction DR1. In an embodiment of the disclosure, the second direction DR2 can be perpendicular to the first direction DR1. The plurality of data lines from DL1 to DLm are arranged in parallel in the second direction DR2 and can extend in the first direction DR1. The plurality of pixels PX are arranged in a matrix form, and each of the plurality of pixels PX can be electrically connected to one of the plurality of gate lines from GL1 to GLn and one of the plurality of data lines from DL1 to DLm.

[0053] The signal controller 400 receives an input image signal I-RGB and a plurality of control signals I-CS from an external source (not shown) outside the display device 1000. The signal controller 400 renders the input image signal I-RGB to satisfy an interface specification with the data driver 300 in order to convert the input image signal I-RGB into an output image signal D-RGB. The signal controller 400 provides the output image signal D-RGB to the data driver 300. In addition, the signal controller 400 generates a data control signal D-CS (e.g., an output start signal and the like) and a gate control signal G-CS (e.g., a scan start signal, a clock signal, and a clock inhibit signal) based on the plurality of control signals I-CS. The signal controller 400 provides the data control signal D-CS to the data driver 300 and provides the gate control signal G-CS to the gate driver 200.

[0054] The gate driver 200 sequentially outputs a gate signal in response to the gate control signal G-CS provided from the signal controller 400. Accordingly, the plurality of pixels PX can be sequentially scanned row by row by the gate signal.

[0055] The data driver 300 converts the output image signal D-RGB into a data voltage in response to the data control signal D-CS provided from the signal controller 400. The data driver 300 applies the data voltage to the plurality of data lines from DL1 to DLm of the display panel 100.

[0056] Accordingly, each of the plurality of pixels PX is turned on by the gate signal, and the turned-on pixel PX receives a corresponding data voltage from the data driver 300 and displays an image of a desired gray scale.

[0057] As Figure 1As illustrated in FIG. 1, the backlight unit 500 is located on the rear surface of the display panel 100 and provides light from the rear of the display panel 100. The backlight driver 600 receives the light source control signal B-CS from the signal controller 400 and drives the backlight unit 500 in synchronization with the display panel 100.

[0058] Reference Figure 2 In the display apparatus 1000 according to an embodiment of the disclosure, the gate driver 200 (refer to Figure 1 ) includes a first gate driving circuit 210 and a second gate driving circuit 220. The first gate driving circuit 210 is connected to a first end of the plurality of gate lines from GL1 to GLn, and the second gate driving circuit 220 is connected to a second end of the plurality of gate lines from GL1 to GLn.

[0059] Each of the first gate driving circuit 210 and the second gate driving circuit 220 can include a shift register sequentially outputting a gate signal. The first gate driving circuit 210 and the second gate driving circuit 220 can operate simultaneously to output a gate signal to the same gate line at the same time. Accordingly, each of the gate lines from GL1 to GLn can receive a gate signal from the first gate driving circuit 210 and the second gate driving circuit 220 through the first end and the second end.

[0060] The data driver 300 (refer to Figure 1 ) can include a plurality of data integrated circuits 310, 320, 330, and 340. Although Figure 2 a structure in which the data driver 300 includes four data integrated circuits 310, 320, 330, and 340 is illustrated, embodiments of the disclosure are not limited thereto. That is, the number of data integrated circuits included in the data driver 300 is not particularly limited.

[0061] According to an embodiment, the display apparatus 1000 can include a plurality of flexible circuit boards 360, 370, 380, and 390 on which each of the plurality of data integrated circuits 310, 320, 330, and 340 is mounted, and a printed circuit board 350 electrically connected with the plurality of flexible circuit boards 360, 370, 380, and 390.

[0062] The plurality of flexible circuit boards 360, 370, 380, and 390 electrically connect the display panel 100 to the printed circuit board 350. Specifically, one end of each of the plurality of flexible circuit boards 360, 370, 380, and 390 can be coupled to the printed circuit board 350, and the other end of each of the flexible circuit boards 360, 370, 380, and 390 can be coupled to the display panel 100.

[0063] As Figure 2As depicted in FIG. 1, the display panel 100 includes a display area DA for displaying an image and a non-display area NDA adjacent to the display area DA. The display area DA is an area in which an image is substantially displayed, and the non-display area NDA is a bezel area in which an image is not displayed. Figure 2 The non-display area NDA is shown to be disposed to surround the display area DA, but embodiments of the present disclosure are not limited thereto. The non-display area NDA can be disposed on at least one side of the display area DA. In embodiments of the present disclosure, the plurality of flexible circuit boards 360, 370, 380, and 390 can be connected to the non-display area NDA of the display panel 100 adjacent to the printed circuit board 350.

[0064] Figure 2 The plurality of data integrated circuits 310, 320, 330, and 340 are shown to be disposed on the plurality of flexible circuit boards 360, 370, 380, and 390, respectively, but embodiments of the present disclosure are not limited thereto. That is, the plurality of data integrated circuits 310, 320, 330, and 340 can be mounted directly on the non-display area NDA of the display panel 100 in a Chip On Glass (COG) manner.

[0065] Figure 3 is a plan view showing a layout of a pixel PXij according to an embodiment of the present disclosure, and Figure 4 is a plan view showing a layout of a pixel PXij according to an embodiment of the present disclosure, and Figure 3 is a magnified view of the AA area shown in Figure 5A is a cross-sectional view taken along Figure 3 is a cross-sectional view taken along Figure 5B is a cross-sectional view taken along Figure 3 is a cross-sectional view taken along

[0066] Since each of the plurality of pixels PX shown in Figure 1 in order to facilitate description, Figure 3 Only one pixel PXij of the plurality of pixels PX is shown. Hereinafter, the pixel PXij will be described with reference to the accompanying drawings, and the description of the remaining pixels will be omitted.

[0067] Referring to Figure 3 and Figure 4 , the pixel PXij is connected to an i-th data line DLi among a plurality of data lines (shown in Figure 1 ) from DL1 to DLm, and connected to a j-th gate line GLj among a plurality of gate lines (shown in Figure 1 ) from GL1 to GLn. An i+1-th data line DLi+1 is disposed adjacent to the i-th data line DLi in a second direction DR2, and a j-1-th gate line GLj-1 is disposed adjacent to the j-th gate line GLj in a first direction DR1. As shown inFigure 3 As shown in FIG. 1, the i-th data line DLi, the (i+1)-th data line DLi+1, the j-th gate line GLj, and the (j-1)-th gate line GLj-1 intersect each other to define a pixel region having a quadrangular shape. A pixel PXij can be provided in correspondence with the pixel region. The shape of the pixel region is not limited, and the pixel region can have various shapes such as a rhombic shape, a hexagonal shape, and a circular shape in addition to the quadrangular shape.

[0068] The pixel PXij includes a switching element TR, a pixel electrode PE, a storage electrode SSE, a shield electrode LSE, and a first capacitor electrode CE1 and a second capacitor electrode CE2.

[0069] The switching element TR is electrically connected to the i-th data line DLi and the j-th gate line GLj. In an embodiment of the disclosure, the switching element TR can include a thin film transistor. The switching element TR can include a control electrode GE, an input electrode SE, and an output electrode DE. The control electrode GE is branched from the j-th gate line GLj in a first direction DR1, and the input electrode SE is branched from the i-th data line DLi in a second direction DR2. The output electrode DE can be disposed to be spaced apart from the input electrode SE on an upper portion of the control electrode GE.

[0070] The storage electrode SSE can be spaced apart from the data lines DLi and DLi+1 and the gate lines GLj and GLj-1 and disposed in the pixel region. In an embodiment of the disclosure, the storage electrode SSE can include an electrode portion SSE-EP and two line portions SSE-LP1 and SSE-LP2. The two line portions SSE-LP1 and SSE-LP2 extend from one side of the electrode portion SSE-EP along the data lines DLi and DLi+1. The two line portions SSE-LP1 and SSE-LP2 can be disposed to be spaced apart with respect to the pixel electrode PE.

[0071] However, the shape of the storage electrode SSE is not limited. For example, the two line portions SSE-LP1 and SSE-LP2 in the storage electrode SSE can be omitted.

[0072] The storage electrode SSE can be connected to an adjacent storage electrode in the second direction DR2 through a storage line SL. The storage line SL can have an overall shape with the storage electrode SSE. However, embodiments of the disclosure are not limited. That is, the storage line SL and the storage electrode SSE can be disposed on different layers and contact each other through a contact hole. The storage line SL can be disposed in parallel with the gate lines GLj and GLj-1, and can cross the data lines DLi and DLi+1 while the storage line SL is insulated from the data lines DLi and DLi+1. The storage line SL can receive a storage voltage Vst Figure 8The storage line SL crosses the data lines DLi and DLi+1 but does not cross the gate lines GLj and GLj-1.

[0073] The pixel electrode PE is electrically connected to the output electrode DE of the switching element TR. Thus, when the switching element TR is turned on in response to the gate signal applied from the jth gate line GLj, the switching element TR can output the data voltage applied from the ith data line DLi to the output electrode DE. The voltage output through the output electrode DE is applied to the pixel electrode PE. Here, the voltage applied to the pixel electrode PE can be defined as a pixel voltage Vp Figure 10B The storage line SL crosses the data lines DLi and DLi+1 but does not cross the gate lines GLj and GLj-1.

[0074] The pixel electrode PE includes a trunk portion TP for dividing the pixel region into a plurality of domains and a plurality of branch portions BP extending radially from the trunk portion TP. The trunk portion TP can include a vertical trunk portion VTP extending in the first direction DR1 and a horizontal trunk portion HTP extending in the second direction DR2. The trunk portion TP is provided in a cross shape formed by the vertical trunk portion VTP and the horizontal trunk portion HTP, and in this case, the pixel region can be divided into 4 domains.

[0075] The plurality of branch portions BP extend in parallel to each other in each domain divided by the trunk portion TP and are arranged to be spaced apart from each other. In an embodiment of the disclosure, the branch portions BP can extend in a direction of about 45° with respect to the trunk portion TP. For the branch portions BP, two branch portions BP adjacent to each other are spaced apart at a distance of about one micron to form a plurality of fine slits US. Liquid crystal molecules of the liquid crystal layer LCL Figure 5A The liquid crystal molecules of the liquid crystal layer LCL

[0076] The shield electrode LSE includes a vertical line portion LSE-LP1 disposed along the data lines DLi and DLi+1 and an extension portion LSE-EP extending from the vertical line portion LSE-LP1. The vertical line portion LSE-LP1 of the shield electrode LSE can overlap the data lines DLi and DLi+1 when viewed on a plane. The shield electrode LSE can further include a horizontal line portion LSE-LP2 disposed along the gate lines GLj and GLj-1. The horizontal line portion LSE-LP2 of the shield electrode LSE can overlap the gate lines GLj and GLj-1 when viewed on a plane. The shield electrode LSE can be electrically insulated from the gate lines GLj and GLj-1 and the data lines DLi and DLi+1. In addition, the shield electrode LSE is disposed spaced apart from the pixel electrode PE viewed on a plane to be electrically insulated from the pixel electrode PE. That is, the shield electrode LSE does not overlap the pixel electrode PE when viewed on a plane.

[0077] The first capacitor electrode CE1 extends from the output electrode DE of the switching element TR in the first direction DR1 and overlaps the storage electrode SSE and the pixel electrode PE. The first capacitor electrode CE1 can be formed in an integral shape with the output electrode DE of the switching element TR. The first capacitor electrode CE1 can be in direct contact with the extension PE-EP of the pixel electrode PE through the first contact hole CNT1. The extension PE-EP of the pixel electrode PE can overlap the electrode portion SSE-EP of the first capacitor electrode CE1 and the storage electrode SSE. In addition, the first capacitor electrode CE1 can face the electrode portion SSE-EP of the storage electrode SSE through the insulating layer provided between the first capacitor electrode CE1 and the electrode portion SSE-EP of the storage electrode SSE. Thus, the first storage capacitor Cst1 (shown in FIG. 10) can be defined between the first capacitor electrode CE1 and the electrode portion SSE-EP of the storage electrode SSE. Figure 5B

[0078] The second capacitor electrode CE2 can be provided spaced apart from the first capacitor electrode CE1 and can overlap the shield electrode LSE and the storage electrode SSE. The second capacitor electrode CE2 can overlap the extension LSE-EP of the shield electrode LSE and can be in direct contact with the extension LSE-EP of the shield electrode LSE through the second contact hole CNT2. In addition, the second capacitor electrode CE2 can face the electrode portion SSE-EP of the storage electrode SSE through the insulating layer provided between the second capacitor electrode CE2 and the electrode portion SSE-EP of the storage electrode SSE. Thus, the second storage capacitor Cst2 (shown in FIG. 10) can be defined between the second capacitor electrode CE2 and the electrode portion SSE-EP of the storage electrode SSE. Figure 5B

[0079] Figure 3 and Figure 4 The second capacitor electrode CE2 is shown as having a quadrilateral shape when viewed in plan, but the shape of the second capacitor electrode CE2 is not limited. In particular, other shapes of the second capacitor electrode CE2 will be described in detail with reference to Figure 6A , Figure 6B and Figure 6C .

[0080] ​​The pixel PXij can further include a third capacitor electrode CE3 extending from the j-th gate line GLj and a fourth capacitor electrode CE4 extending from the output electrode DE. The third capacitor electrode CE3 can extend from the j-th gate line GLj in the first direction DR1 and be disposed in parallel with the control electrode GE. The direction in which the output electrode DE extends over the control electrode GE can be the same as the direction in which the fourth capacitor electrode CE4 extends. The third capacitor electrode CE3 and the fourth capacitor electrode CE4 can face each other by an insulating layer disposed between the third capacitor electrode CE3 and the fourth capacitor electrode CE4. Accordingly, the compensation capacitor Cgs can be defined by the third capacitor electrode CE3 and the fourth capacitor electrode CE4.

[0081] Reference Figure 3 , Figure 5A and Figure 5B The display panel 100 according to an embodiment of the disclosure includes a first substrate DS1, a second substrate DS2 facing the first substrate DS1, and a liquid crystal layer LCL interposed between the first substrate DS1 and the second substrate DS2.

[0082] The first substrate DS1 includes a first base substrate BS1, gate lines GLj and GLj-1, data lines DLi and DLi+1, a switching element TR, a first insulating layer GIL, a second insulating layer PIL, a third insulating layer OL, and a pixel electrode PE.

[0083] The first base substrate BS1 can be formed of a glass substrate or a plastic substrate having light transmittance and flexibility. On one surface of the first base substrate BS1, the gate lines GLj and GLj-1, the control electrode GE, the storage electrode SSE, and the third capacitor electrode CE3 are disposed. Here, the gate lines GLj and GLj-1, the control electrode GE, the storage electrode SSE, and the third capacitor electrode CE3 can be referred to as a first metal layer. The first metal layer can be formed of a first metal material. In an embodiment of the disclosure, the first metal material can include a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti), or an alloy of the above-described metal. In an embodiment of the disclosure, the first metal material can include a metal having a low resistance and a metal having a high resistance. Figure 5A and Figure 5B In the above-described embodiment of the disclosure, the first metal layer has a single layer structure, but embodiments of the disclosure are not limited thereto. That is, the first metal layer can include a multi-layer structure, for example, a titanium layer and a copper layer.

[0084] On one surface of the first base substrate BS1, a first insulating layer GIL for covering the first metal layer is disposed. The first insulating layer GIL can include at least one of an inorganic substance and an organic substance. The inorganic substance can be, for example, any one of silicon nitride and silicon oxide. The first insulating layer GIL can have a multi-layer structure in which a plurality of inorganic substance layers are sequentially stacked. The plurality of inorganic substance layers can be made of different inorganic substances.

[0085] On the first insulating layer GIL, the data lines DLi and DLi+1, the input electrode SE, the output electrode DE, the first and second capacitor electrodes CE1 and CE2, and the fourth capacitor electrode CE4 are provided. Here, the data lines DLi and DLi+1, the input electrode SE, the output electrode DE, the first and second capacitor electrodes CE1 and CE2, and the fourth capacitor electrode CE4 can be referred to as a second metal layer. The second metal layer can be formed of a second metal material. The second metal material can be the same as the first metal material, or can include a different material.

[0086] On the first insulating layer GIL, an active layer of the switching element TR can also be provided. The active layer can include a semiconductor layer AL, and ohmic contact layers OCL1 and OCL2. The semiconductor layer AL can include any one of an amorphous silicon semiconductor, a polysilicon semiconductor, and a metal oxide semiconductor. The active layer can be interposed between the second metal layer and the first insulating layer GIL.

[0087] On the first insulating layer GIL, a second insulating layer PIL for covering the second metal layer and a third insulating layer OL are sequentially provided. The second insulating layer PIL can include an inorganic substance, and the third insulating layer OL can include an organic substance. The third insulating layer OL can provide a flat surface.

[0088] On the third insulating layer OL, a pixel electrode PE and a shield electrode LSE are provided. The pixel electrode PE and the shield electrode LSE can be provided apart from each other and electrically insulated. Also, the pixel electrode PE and the shield electrode LSE can include a transparent electrode material. The pixel electrode PE and the shield electrode LSE can be formed of the same material and simultaneously patterned.

[0089] The pixel electrode PE is electrically connected to the output electrode DE of the switching element TR. Specifically, the first capacitor electrode CE1 extending from the output electrode DE overlaps with an extension PE-EP of the pixel electrode PE. The second and third insulating layers PIL and OL provide a first contact hole CNT1 for exposing the first capacitor electrode CE1, and the extension PE-EP of the pixel electrode PE directly contacts the first capacitor electrode CE1 through the first contact hole CNT1. Accordingly, the output electrode DE of the switching element TR can be electrically connected to the pixel electrode PE through the first capacitor electrode CE1.

[0090] The first capacitor electrode CE1 can overlap with an electrode portion SSE-EP of the storage electrode SSE with respect to the first insulating layer GIL, the semiconductor layer AL, and the ohmic contact layers OCL1 and OCL2 interposed between the first capacitor electrode CE1 and the electrode portion SSE-EP of the storage electrode SSE. Accordingly, a first storage capacitor Cst1 can be defined between the first capacitor electrode CE1 and the electrode portion SSE-EP of the storage electrode SSE.

[0091] The shield electrode LSE is electrically connected to the second capacitor electrode CE2. Specifically, the second capacitor electrode CE2 is disposed to be spaced apart from the first capacitor electrode CE1 and to overlap with the extension LSE-EP of the shield electrode LSE. The second contact hole CNT2 for exposing the second capacitor electrode CE2 is provided to the second insulating layer PIL and the third insulating layer OL, and the extension LSE-EP of the shield electrode LSE is in direct contact with the second capacitor electrode CE2 through the second contact hole CNT2. Accordingly, the second capacitor electrode CE2 can receive the second reference voltage Scom (shown in FIG. 2) through the shield electrode LSE. Figure 8

[0092] The second capacitor electrode CE2 can overlap with the electrode portion SSE-EP of the storage electrode SSE with respect to the first insulating layer GIL, the semiconductor layer AL, and the ohmic contact layers OCL1 and OCL2 interposed between the second capacitor electrode CE2 and the electrode portion SSE-EP of the storage electrode SSE. Accordingly, the second storage capacitor Cst2 can be defined between the second capacitor electrode CE2 and the electrode portion SSE-EP of the storage electrode SSE.

[0093] In an embodiment of the disclosure, the capacitance of the second storage capacitor Cst2 can be greater than the capacitance of the first storage capacitor Cst1. For example, the ratio of the capacitance of the second storage capacitor Cst2 to the first storage capacitor Cst1 can be approximately 7:3. In order to make the capacitance of the second storage capacitor Cst2 greater than the capacitance of the first storage capacitor Cst1, the second capacitor electrode CE2 can have a greater area than the first capacitor electrode CE1.

[0094] The third capacitor electrode CE3 and the fourth capacitor electrode CE4 can face each other with respect to the first insulating layer GIL interposed therebetween. Accordingly, the compensation capacitor Cgs can be defined by the third capacitor electrode CE3 and the fourth capacitor electrode CE4.

[0095] The overlap area disposed between the output electrode DE and the control electrode GE can have a trade-off relationship with the overlap area of the third capacitor electrode CE3 and the fourth capacitor electrode CE4. As Figure 5A ​As shown, when the overlap area W1 between the output electrode DE and the control electrode GE increases, the overlap area W2 between the third capacitor electrode CE3 and the fourth capacitor electrode CE4 can decrease. Conversely, when the overlap area W1 between the output electrode DE and the control electrode GE decreases, the overlap area W2 between the third capacitor electrode CE3 and the fourth capacitor electrode CE4 can increase. Therefore, even if the overlap area W1 between the output electrode DE and the control electrode GE changes from the desired value due to process errors and similar factors, the error can be compensated by the compensation capacitor Cgs, thereby preventing voltage fluctuations.

[0096] The second substrate DS2 includes a second base substrate BS2 and a reference electrode RE. The second base substrate BS2 is positioned facing the first base substrate BS1. The second base substrate BS2 may be formed of a glass substrate or a transparent and flexible plastic substrate.

[0097] A reference electrode RE is provided on one surface of the second base substrate BS2. That is, the reference electrode RE is disposed between the first base substrate BS1 and the second base substrate BS2. The reference electrode RE may comprise a transparent electrode material. The reference electrode RE may be formed on one surface of the second base substrate BS2 in the form of a single cylindrical electrode. The reference electrode RE faces the pixel electrode PE relative to the liquid crystal layer LCL disposed between the reference electrode RE and the pixel electrode PE. A liquid crystal capacitor Clc may be defined by the reference electrode RE, the pixel electrode PE, and the liquid crystal layer LCL. The liquid crystal molecules included in the liquid crystal layer LCL can react according to the data voltage applied to the pixel electrode PE and the first reference voltage Vcom applied to the reference electrode RE. Figure 8 Orientation is achieved by the electric field formed by the voltage difference between the backlight unit 500 and the liquid crystal molecules, as shown in the diagram. The display panel 100 can control the liquid crystal alignment from the backlight unit 500 according to the liquid crystal alignment of the liquid crystal molecules. Figure 1 The transmittance of light (as shown in the figure) is used to display an image with the desired grayscale level.

[0098] The reference electrode RE faces the shield electrode LSE relative to the liquid crystal layer LCL disposed between the reference electrode RE and the shield electrode LSE. The second reference voltage Scom ( Figure 8 (As shown) is applied to the shielding electrode LSE. The data voltage applied to the pixel electrode PE varies depending on the gray level of the image to be displayed in each pixel PXij, but the first reference voltage Vcom and the second reference voltage Scom have a direct current (DC) voltage level. In embodiments of this disclosure, the second reference voltage Scom may have the same voltage level as the first reference voltage Vcom. For example, the first reference voltage Vcom and the second reference voltage Scom may have a voltage level of approximately 6V.

[0099] Accordingly, no electric field is formed between the shield electrode LSE and the reference electrode RE, and liquid crystal molecules of the liquid crystal layer LCL disposed between the shield electrode LSE and the reference electrode RE are not aligned. A non-alignment region is defined between the shield electrode LSE and the reference electrode RE, and light provided from the backlight unit 500 does not pass through the non-alignment region. Accordingly, the non-alignment region can be defined as a light blocking region that blocks light provided from the backlight unit 500.

[0100] Although not shown in the drawings, a color filter layer can be provided for any one of the first substrate DS1 and the second substrate DS2. The color filter layer can include a red color filter, a green color filter, and a blue color filter. In an embodiment of the disclosure, when the color filter layer is provided for the second substrate DS2, the color filter layer can be disposed between the second base substrate BS2 and the reference electrode RE.

[0101] In addition, a black matrix layer (not shown) can be formed in one of the first substrate DS1 and the second substrate DS2. The black matrix layer can be formed of an organic material or a metal material having light blocking properties. The black matrix layer can be provided not to overlap the shield electrode LSE. The black matrix layer can block light leakage generated in a region where liquid crystal control capability cannot reach.

[0102] Figure 6A is an enlarged view partially showing a layout of the pixel PXij according to an embodiment of the disclosure, and Figure 6B is a plan view of the first and second capacitor electrodes according to an embodiment of the disclosure. Figure 6C is a plan view of the first and second capacitor electrodes CE1 and CE2 according to an embodiment of the disclosure. Figure 6D is a cross-sectional view taken along line III-III' shown in Figure 6A

[0103] In the components shown in Figure 6A and Figure 6B , components that are the same as those shown in Figure 4 and Figure 5B are denoted by the same reference numerals, and detailed descriptions of the same reference numerals are omitted.

[0104] Referring to Figure 6A and Figure 6B , a pixel PXij according to an embodiment of the disclosure has the same structure as the pixel PXij shown in Figure 4 except that the second capacitor electrode CE2 has a different shape from the second capacitor electrode CE2 shown in Figure 4

[0105] ​​The second capacitor electrode CE2 can include a first electrode part CE2-1, a second electrode part CE2-2, and a third electrode part CE2-3. The first electrode part CE2-1 has a quadrangular shape when viewed on a plane. The second electrode part CE2-2 extends from one end of the first electrode part CE2-1 in a second direction DR2. A width of the second electrode part CE2-2 in the first direction DR1 is less than a width of the first electrode part CE2-1 in the first direction DR1. The third electrode part CE2-3 extends from one end of the second electrode part CE2-2 in the first direction DR1. A separation space SA1 is formed between the first electrode part CE2-1 and the third electrode part CE2-3, and the first capacitor electrode CE1 can be disposed in the separation space SA1 formed between the first electrode part CE2-1 and the third electrode part CE2-3. Accordingly, the area of the second capacitor electrode CE2 can be increased while effectively utilizing the space within the pixel area.

[0106] As shown in Figure 6C , the second capacitor electrode CE2 can include a first electrode part CE2-1 and a second electrode part CE2-2. The first electrode part CE2-1 has a quadrangular shape when viewed on a plane. The second electrode part CE2-2 extends from one end of the first electrode part CE2-1 in a second direction DR2. In contrast to the second capacitor electrode CE2 shown in Figure 4 , the second capacitor electrode CE2 shown in Figure 6C further includes the second electrode part CE2-2, and thus, Figure 6C the second capacitor electrode CE2 shown in Figure 4 may have a larger area than the second capacitor electrode CE2 shown in . Accordingly, the capacitance of the second storage capacitor Cst2 can be increased in a given space.

[0107] The first capacitor electrode CE1 can be disposed in a space SA2 between the first electrode part CE2-1 and the second electrode part CE2-2. Accordingly, the area of the second capacitor electrode CE2 can be increased while effectively utilizing the space within the pixel area.

[0108] Referring to Figure 6B and Figure 6D , the first electrode part CE2-1 overlaps with the extension part LSE-EP of the shield electrode LSE, and directly contacts with the extension part LSE-EP of the shield electrode LSE through a second contact hole CNT2. The second capacitor electrode CE2 can receive a second reference voltage Scom (shown in Figure 8 ) from the shield electrode LSE through the first electrode part CE2-1. The second electrode part CE2-2 and the third electrode part CE2-3 do not overlap with the extension part LSE-EP of the shield electrode LSE.

[0109] The first electrode portion CE2-1, the second electrode portion CE2-2, and the third electrode portion CE2-3 of the second capacitor electrode CE2 are provided to overlap with the electrode portion SSE-EP of the storage electrode SSE. At least a portion of the second storage capacitor Cst2 is formed in a portion in which the first electrode portion CE2-1, the second electrode portion CE2-2, and the third electrode portion CE2-3 overlap with the electrode portion SSE-EP of the storage electrode SSE.

[0110] Figure 7 is an enlarged view partially illustrating a layout of the pixel PXij according to an embodiment of the disclosure. In Figure 7 , components identical to those shown in Figure 6A are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0111] Referring to Figure 7 , the pixel PXij according to an embodiment of the disclosure has the same structure as the pixel PXij shown in Figure 6A except for the compensation capacitor Cgs.

[0112] That is, the compensation capacitor Cgs defined by the third capacitor electrode CE3 and the fourth capacitor electrode CE4 can be omitted from the pixel PXij of Figure 7 . That is, when the pixel PXij according to an embodiment of the disclosure does not include the compensation capacitor Cgs, the positions, areas, and similar characteristics of the first capacitor electrode CE1 and the second capacitor electrode CE2 in the pixel region can be adjusted.

[0113] Figure 8 is an equivalent circuit diagram of the pixel PXij shown in Figure 7 .

[0114] Referring to Figure 7 and Figure 8 , the pixel PXij according to an embodiment of the disclosure includes a switching element TR, a liquid crystal capacitor Clc connected to an output electrode DE of the switching element TR, a first storage capacitor Cst1 connected to the liquid crystal capacitor Clc, and a second storage capacitor Cst2 connected to the first storage capacitor Cst1.

[0115] The liquid crystal capacitor Clc includes a pixel electrode PE connected to the output electrode DE of the switching element TR as a first electrode and a reference electrode RE for receiving a first reference voltage Vcom as a second electrode (shown in Figure 6D ).

[0116] The first storage capacitor Cst1 includes a storage electrode SSE as a first electrode for receiving a storage voltage Vst through the storage line SL and a first capacitor electrode CE1 as a second electrode connected to the output electrode DE of the switching element TR. In an embodiment of the disclosure, the storage voltage Vst can have a voltage level higher than the first reference voltage Vcom. For example, when the first reference voltage Vcom is about 6 V, the storage voltage Vst can be about 7.5 V.

[0117] The second storage capacitor Cst2 includes a storage electrode SSE as a first electrode for receiving a storage voltage Vst through the storage line SL and a second capacitor electrode CE2 as a second electrode for receiving a second reference voltage Scom through the shield electrode LSE. In an embodiment of the disclosure, the second reference voltage Scom can have the same voltage level as the first reference voltage Vcom. In addition, the second reference voltage Scom can have a different voltage level from the storage voltage Vst.

[0118] The capacitance of the first storage capacitor Cst1 can be different from the capacitance of the second storage capacitor Cst2. In an embodiment of the disclosure, the capacitance of the second storage capacitor Cst2 can be greater than the capacitance of the first storage capacitor Cst1. For example, the ratio of the capacitances of the first storage capacitor Cst1 and the second storage capacitor Cst2 can be about 3:7.

[0119] Figure 9 is an equivalent circuit diagram of the pixel PXij shown in Figure 6A

[0120] Referring to Figure 6A and Figure 9 The pixel PXij according to an embodiment of the disclosure can further include a compensation capacitor Cgs connected between the control electrode GE and the output electrode DE of the switching element TR.

[0121] Due to process errors between the pixels PX in the display panel 100, the parasitic capacitance between the output electrode DE and the control electrode GE of the switching element TR can vary depending on the position of the pixel PX. The compensation capacitor Cgs can compensate for the deviation of the parasitic capacitance. That is, the compensation capacitor Cgs is designed such that, when the parasitic capacitance decreases, the capacitance of the compensation capacitor Cgs increases, and when the parasitic capacitance increases, the capacitance of the compensation capacitor Cgs decreases, so that the change in the parasitic capacitance can be offset by the compensation capacitor Cgs. Accordingly, the difference in the jump voltage between the pixels can be compensated for by the compensation capacitor Cgs.

[0122] Figure 10A is a waveform diagram showing the storage voltage Vst shown in Figure 9 Figure 10B is a waveform diagram showing the storage voltage Vst shown in Figure 9 ​​a waveform diagram of the pixel voltage Vp of the liquid crystal capacitor Clc charged by the data voltage Vd. Figure 10C is an enlarged waveform diagram illustrating Figure 10B the BB region of Figure 10B and Figure 10C , the first curve G1 represents the pixel voltage Vp in the pixel not including the second storage capacitor Cst2, and the second curve G2 represents the pixel voltage Vp in the pixel PXij including the second storage capacitor Cst2.

[0123] Referring to Figure 8 , Figure 9 , Figure 10A , Figure 10B and Figure 10C , the storage line SL to which the storage voltage Vst is applied crosses the data line DLi but does not cross the gate line GLj. Thus, the data voltage periodically applied to the data line DLi can cause a ripple in the storage voltage Vst. If the data voltage has a positive electrode voltage level higher than the first reference voltage Vcom, an upward ripple can be generated in the storage voltage Vst, and if the data voltage has a negative electrode voltage level lower than the first reference voltage Vcom, a downward ripple can be generated in the storage voltage Vst.

[0124] The storage line SL is connected to the pixel PXij through the first storage capacitor Cst1 and the second storage capacitor Cst2. Specifically, the ripple generated in the storage voltage Vst can be reflected on the pixel voltage Vp through the first storage capacitor Cst1 connected to the pixel electrode PE. That is, a ripple can be generated in the pixel voltage Vp in response to the ripple generated in the storage voltage Vst. However, depending on the size of the capacitance of the first storage capacitor Cst1 connected to the pixel electrode PE, the influence of the ripple generated in the storage voltage Vst on the pixel voltage Vp can vary. That is, as the capacitance of the first storage capacitor Cst1 decreases, the influence of the ripple generated in the storage voltage Vst on the pixel voltage Vp decreases.

[0125] As shown in Figure 10C , when all of the storage electrodes SSE Figure 6A and Figure 7 are utilized as the first storage capacitor Cst1, the fluctuation range of the pixel voltage Vp caused by the ripple generated in the storage voltage Vst increases to a first value Vd1 as shown by the first curve G1.

[0126] However, when a part of the storage electrodes SSE is used as the first storage capacitor Cst1 and the remaining part is used as the second storage capacitor Cst2, the fluctuation range of the pixel voltage Vp caused by the ripple generated in the storage voltage Vst decreases to a second value Vd2 as shown by the second curve G2. The fluctuation of the pixel voltage Vp can be reduced by the display device 1000 (refer toFigure 1 The difference in brightness at different positions on the screen is used to represent this phenomenon, and in particular, it can lead to horizontal crosstalk, which can cause horizontal stripe patterns to be observed on the screen. Therefore, by reducing the fluctuation range of the pixel voltage Vp, horizontal crosstalk can be suppressed, and as a result, display quality can be improved.

[0127] Pixel PXij includes a second storage capacitor Cst2. The first storage capacitor Cst1 and the second storage capacitor Cst2 are used to maintain a constant pixel voltage Vp charged in pixel PXij. As mentioned above, if the capacitance of the first storage capacitor Cst1 decreases, the maintenance performance of the pixel voltage Vp may deteriorate. To overcome this problem, pixel PXij also includes a second storage capacitor Cst2. The second storage capacitor Cst2 is used to maintain the pixel voltage Vp, but it is not directly connected to the pixel electrode PE, and therefore, even if the capacitance of the second storage capacitor Cst2 increases, the ripple of the storage voltage Vst will not be reflected in the pixel voltage Vp.

[0128] When the display panel 100 ( Figure 1 When the operating mode (as shown) switches from low-frequency mode to high-frequency mode or vice versa, the charging time of pixel PXij decreases or increases. Due to the difference in charging time, the pixel voltage Vp charging in pixel PXij may not remain constant, which may cause flickering and similar phenomena on the screen. In this case, even with frequency fluctuations, the second storage capacitor Cst2 can keep the pixel voltage Vp charging in pixel PXij constant.

[0129] In this way, since the first storage capacitor Cst1 and the second storage capacitor Cst2 are provided separately in the pixel PXij, the overall display quality of the display panel 100 can be improved.

[0130] In the display device according to embodiments of the present disclosure, a portion of the storage electrode in a pixel is used as a first storage capacitor, while the remainder is used as a second storage capacitor. This prevents degradation of the pixel voltage maintenance performance and suppresses ripple in the pixel voltage that reflects the storage voltage. Therefore, the overall display quality of the display device can be improved.

[0131] Although this disclosure has been described with reference to preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made in this disclosure without departing from the spirit and scope thereof.

[0132] Therefore, the scope of this disclosure is not intended to be limited to what is set forth in the detailed description of the specification, but is intended to be defined by the appended claims.

Claims

1. A display device comprising: a first substrate; a second substrate facing the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate, wherein the first substrate comprises: a gate line; a data line insulated from the gate line; a storage electrode insulated from the gate line and the data line, respectively; a switching element electrically connected to the data line and the gate line; a pixel electrode electrically connected to an output electrode of the switching element; a shield electrode insulated from the pixel electrode and comprising a line portion disposed in alignment with the data line and an extension portion extending from the line portion; a first capacitor electrode extending from the output electrode, overlapping and directly contacting the pixel electrode, and overlapping the storage electrode to define a first storage capacitor; and a second capacitor electrode disposed apart from the first capacitor electrode, overlapping and directly contacting the extension portion of the shield electrode, and overlapping the storage electrode to define a second storage capacitor.

2. The display device according to claim 1, wherein An area of the second capacitor electrode is greater than an area of the first capacitor electrode.

3. The display device according to claim 1, wherein The first substrate further comprises: a first insulating layer disposed on the gate line and the storage electrode, and causing the output electrode, the data line, and the first and second capacitor electrodes to be disposed on the gate line and the storage electrode; and a second insulating layer disposed on the output electrode, the data line, and the first and second capacitor electrodes, and causing the pixel electrode and the shield electrode to be disposed on the output electrode, the data line, and the first and second capacitor electrodes.

4. The display device according to claim 3, wherein The second insulating layer comprises a first contact hole configured to expose the first capacitor electrode and a second contact hole configured to expose the second capacitor electrode, the pixel electrode directly contacts the first capacitor electrode through the first contact hole, and the extension portion of the shield electrode directly contacts the second capacitor electrode through the second contact hole.

5. The display device according to claim 1, wherein The second substrate comprises a reference electrode to which a first reference voltage is applied, and the shield electrode to which a second reference voltage is applied.

6. The display device of claim 5, wherein, A storage voltage is applied to the storage electrode, and the first and second reference voltages each have a voltage level different from the storage voltage.

7. The display device of claim 6, wherein, The first and second reference voltages have the same voltage level.

8. The display device according to claim 1, wherein The first substrate further comprises a storage line insulated from the gate line and the data line, respectively, and the storage line is electrically connected to the storage electrode.

9. The display device of claim 8, wherein, The storage line crosses the data line and does not cross the gate line.

10. The display device of claim 1, wherein, The pixel electrode comprises: a trunk portion for dividing a pixel area into a plurality of domains; and a plurality of branch portions extending from the trunk portion.

11. The display device of claim 10, wherein, The trunk portion comprises: a horizontal trunk portion; and a vertical trunk portion intersecting the horizontal trunk portion, wherein the plurality of branch portions radially extend from the horizontal trunk portion and the vertical trunk portion.

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