Wear leveling in EEPROM emulators constructed from flash memory cells

Abstract

The present invention is entitled "Wear Leveling in an EEPROM Emulator Made of Flash Memory Cells." The present invention relates to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. An embodiment utilizes an index array that stores an index word for each logical address in the emulated EEPROM. Each bit in each index word is associated with a physical address of a physical word in the emulated EEPROM, and the index word keeps track of which physical word is the current word for a particular logical address. The use of the index words enables a wear leveling algorithm to be implemented that allows program commands to a logical address that result in: (i) skipping the programming operation if the data stored in the current word does not contain a "1" that corresponds to a "0" in the data to be stored, (ii) reprogramming one or more bits of the current word in some cases, or (iii) moving to the next physical word and programming it in some cases.

Description

Technical Field

[0001] The present invention relates to a system and method for implementing wear leveling in an electrically erasable programmable read-only memory (EEPROM) emulator constructed from flash memory cells. Background Art

[0002] Non-volatile memory cells are well known in the art. Figure 1 1 shows a first type of non-volatile memory cell 110 of the prior art. Memory cell 110 includes a semiconductor substrate 112 of a first conductivity type (e.g., P-type). Substrate 112 has a surface on which a first region 114 (also referred to as a source line SL terminal) of a second conductivity type (e.g., N-type) is formed. First region 114 is typically connected to a source line (not shown). A second region 116 (also referred to as a drain line), also of N-type, is formed on the surface of substrate 112. Between first region 114 and second region 116 is a channel region 118. A bit line BL terminal 120 is connected to second region 116 and is typically connected to a bit line (not shown). A word line WL terminal 122 is located above a first portion of channel region 118 and is insulated therefrom, and is typically connected to a word line (not shown). Word line terminal 122 barely overlaps or does not overlap second region 116. A floating gate FG 124 is located above another portion of channel region 118. Floating gate 124 is insulated from the other portion and is adjacent to and insulated from word line terminal 122. Floating gate 124 is also adjacent to first region 114. Floating gate 124 may significantly overlap first region 114 to provide strong coupling from first region 114 to floating gate 124.

[0003] An exemplary operation of erasing and programming a nonvolatile memory cell 110 in the prior art is as follows. The nonvolatile memory cell 110 is erased via the Fowler-Nordheim tunneling mechanism by applying a high voltage to the wordline terminal 122 and zero voltage to the bitline terminal 120 and the source line terminal 114. Electrons tunnel from the floating gate 124 into the wordline terminal 122, causing the floating gate 124 to become positively charged, thereby turning on the nonvolatile memory cell 110 under read conditions. The resulting erased state of the cell is referred to as the '1' state. The cell 110 is programmed via the source-side hot electron programming mechanism by applying a high voltage to the source line 114, a low voltage to the wordline terminal 122, and a programming current to the bitline terminal 120. A portion of the electrons flowing through the gap between word line terminal 122 and floating gate 124 gain enough energy to be injected into floating gate 124, making floating gate 124 negatively charged, thereby turning off nonvolatile memory cell 110 under read conditions. The resulting nonvolatile memory cell programmed state is referred to as the '0' state.

[0004] Exemplary voltages that may be used for read, program, erase, and standby operations in memory cell 110 are shown in Table 1 below:

[0005]

[0006] Figure 2 2 shows a second type of nonvolatile memory cell 210 of the prior art. Nonvolatile memory cell 210 includes a semiconductor substrate 212 of a first conductivity type (e.g., P-type). Substrate 212 has a surface on which a first region 214 (also referred to as a source line SL terminal) of a second conductivity type (e.g., N-type) is formed. First region 214 is typically connected to a source line (not shown). A second region 216 (also referred to as a drain line), also of N-type, is formed on the surface of substrate 212. Between first region 214 and second region 216 is a channel region 218. A bit line BL terminal 220 is connected to second region 216 and is typically connected to a bit line (not shown). A word line WL terminal 222 is located above a first portion of channel region 218 and is insulated therefrom, and is typically connected to a word line (not shown). Word line terminal 222 barely overlaps or does not overlap with second region 216. A floating gate FG 224 is located above another portion of channel region 218. The floating gate 224 is insulated from the other portion and is adjacent to and insulated from the word line terminal 222. The floating gate 224 is also adjacent to the first region 214. The floating gate 224 may overlap the first region 214 to provide coupling from the first region 214 to the floating gate 224. A coupling gate CG terminal (also referred to as a control gate terminal) 226 is above and insulated from the floating gate 224 and is also insulated from the word line terminal 222 and is typically connected to a coupling gate or control gate (not shown).

[0007] An exemplary operation of erasing and programming a nonvolatile memory cell 210 in the prior art is as follows. The nonvolatile memory cell 210 is erased via the Fowler-Nordheim tunneling mechanism by applying a high voltage to the wordline terminal 222 while the voltages of the other terminals are zero volts. Electrons tunnel from the floating gate 224 into the wordline terminal 222, becoming positively charged and thus turning the cell 210 on under a read condition. The resulting erased state of the nonvolatile memory cell is referred to as a '1' state. The nonvolatile memory cell 210 is programmed via a source-side hot electron programming mechanism by applying a high voltage to the coupled gate terminal 226, a high voltage to the source line terminal 214, and a programming current to the bitline terminal 220. A portion of the electrons flowing through the gap between the wordline terminal 222 and the floating gate 224 gain sufficient energy to be injected into the floating gate 224, causing the floating gate 224 to become negatively charged, thereby turning the nonvolatile memory cell 210 off under a read condition. The resulting nonvolatile memory cell programmed state is referred to as the '0' state.

[0008] Exemplary voltages that may be used for read, program, erase, and standby operations in memory cell 210 are shown in Table 2 below:

[0009]

[0010] Another exemplary set of voltages that may be used for read, program, and erase operations in the nonvolatile memory cell 210 (when negative voltages may be used for read and program operations) is shown in Table 3 below:

[0011]

[0012]

[0013] Another exemplary set of voltages that may be used for read, program, and erase operations in the nonvolatile memory cell 210 (when negative voltages may be used for read, program, and erase operations) is shown in Table 4 below:

[0014]

[0015] Figure 3, a third type of nonvolatile memory cell 310 is shown. Nonvolatile memory cell 310 includes a semiconductor substrate 312 of a first conductivity type (e.g., P-type). Substrate 312 has a surface on which a first region 314 (also referred to as a source line SL terminal) of a second conductivity type (e.g., N-type) is formed. First region 314 is typically connected to a source line (not shown). A second region 316 (also referred to as a drain line), also of N-type, is formed on the surface of substrate 312. Between first region 314 and second region 316 is a channel region 318. A bit line BL terminal 320 is connected to second region 316 and is typically connected to a bit line (not shown). A word line WL terminal 322 is located above a first portion of channel region 318 and is insulated therefrom, and is typically connected to a word line (not shown). Word line terminal 322 has little or no overlap with second region 316. A floating gate FG 324 is located above another portion of channel region 318. The floating gate 324 is insulated from the other portion and is adjacent to and insulated from the word line terminal 322. The floating gate 324 is also adjacent to the first region 314. The floating gate 324 may overlap the first region 314 to provide coupling from the first region 314 to the floating gate 324. A coupling gate CG terminal (also known as a control gate terminal) 326 is above the floating gate 324 and insulated therefrom and is typically connected to a coupling gate line or a control gate line (not shown). An erase gate EG terminal 328 is adjacent to and insulated from the floating gate 324 and the coupling gate terminal 326 above the first region 314 and is typically connected to an erase gate line (not shown). The top corner of the floating gate 324 may point toward the inner corner of the T-shaped erase gate 328 to improve erase efficiency. The erase gate 328 is also insulated from the first region 314. The non-volatile memory cell 310 is described in more detail in U.S. Patent No. 7,868,375, which is incorporated herein by reference in its entirety.

[0016] An exemplary operation of erasing and programming a prior art nonvolatile memory cell 310 is as follows. The nonvolatile memory cell 310 is erased via the Fowler-Nordheim tunneling mechanism by applying a high voltage to the erase gate terminal 328 while the voltages of the other terminals are equal to zero volts. Electrons tunnel from the floating gate 324 into the erase gate terminal 328, causing the floating gate 324 to become positively charged, thereby turning on the nonvolatile memory cell 310 under read conditions. The resulting erased state of the nonvolatile memory cell is referred to as the '1' state. The nonvolatile memory cell 310 is programmed via a source-side hot electron programming mechanism by applying a high voltage to the coupling gate terminal 326, a high voltage to the source line terminal 314, a medium voltage to the erase gate terminal 328, and a programming current to the bit line terminal 320. A portion of the electrons flowing through the gap between word line terminal 322 and floating gate 324 gain enough energy to be injected into floating gate 324, making floating gate 324 negatively charged, thereby turning off nonvolatile memory cell 310 under read conditions. The resulting nonvolatile memory cell programmed state is referred to as the '0' state.

[0017] Exemplary voltages that may be used for read, program, and erase operations in the nonvolatile memory cell 310 are shown in Table 5 below:

[0018]

[0019] For programming operations, the EG voltage may be applied much higher (e.g., 8 V) than the SL voltage (e.g., 5 V) to enhance the programming operation. In this case, the unselected CG programming voltage is applied at a higher voltage (CG inhibit voltage) (e.g., 6 V) to reduce the undesirable erase effect on neighboring memory cells that share the same EG gate 328 of the selected nonvolatile memory cell.

[0020] Another exemplary set of voltages that may be used for read, program, and erase operations in the nonvolatile memory cell 310 (when negative voltages may be used for read and program operations) is shown in Table 6 below:

[0021]

[0022] Another exemplary set of voltages that may be used for read, program, and erase operations in the nonvolatile memory cell 310 (when negative voltages may be used for read, program, and erase operations) is shown in Table 7 below:

[0023]

[0024] For programming operations, the EG voltage is applied much higher (e.g., 8-9 V) than the SL voltage (e.g., 5 V) to enhance the programming operation. In this case, the unselected CG programming voltage is applied at a higher voltage (CG inhibit voltage) (e.g., 5 V) to reduce the undesirable erase effect on neighboring memory cells that share the same EG gate 328 of the selected nonvolatile memory cell 310.

[0025] Figures 1 to 3 The type of non-volatile memory cell shown is often referred to as a flash memory cell. Flash memory cells are typically arranged in rows and columns to form an array. Because word lines control an entire row of memory cells, and when there is an erase gate (such as Figure 3 When using the type shown), the erase gate is shared by the row pair of memory cells, so the erase operation is performed on the entire row or row pair at a time. Figures 1 to 3 In prior art memory systems of the type of memory cells shown, it has not been possible to erase only one byte of data or one byte pair of data at a time.

[0026] Also known in the prior art are EEPROM devices. Figures 1 to 3 Like flash memory cells, EEPROM devices are non-volatile memory devices. However, in EEPROM devices, cells can be erased one byte at a time, unlike using Figures 1 to 3 The memory cell system is different. EEPROM cell size is usually much larger than Flash cell size.

[0027] Applicant previously disclosed a flash memory device capable of emulating an EEPROM device and being erased byte by byte in U.S. patent application No. 14 / 455,698, filed on August 8, 2014, entitled “Flash Memory System With EEPROM Functionality,” and issued as U.S. Patent No. 9,286,982, which is incorporated herein by reference.

[0028] Figures 4 to 6 One embodiment of a prior art flash memory system that can be used as an EEPROM emulator is shown, which is consistent with the disclosure of US Patent Application No. 14 / 455,698.

[0029] Figure 4An exemplary word 400 is shown, including bytes 401 and 402. Byte 401 includes nonvolatile memory cells 403-0, 403-1, ..., and 403-7. Byte 402 includes nonvolatile memory cells 403-8, 403-9, ..., and 403-15. Thus, each nonvolatile memory cell typically stores one bit (i.e., a "0" or a "1"). Eight bits constitute a byte, and two bytes constitute a word.

[0030] Figure 5 An exemplary sector 500 is shown, which includes words 400-0, 400-1, ..., and 400-15. Thus, each sector includes two adjacent word rows. In this example, each row contains 8 words. Two adjacent word rows typically have separate word lines, but have a shared source line and / or erase gate line.

[0031] Figure 6 An exemplary array 610 is shown, comprising sectors 500-0, 500-1, ..., and 500-i, where array 610 comprises i+1 sectors. Decoder 600 typically receives a logical address 601 from a source external to the non-volatile memory system. Decoder 600 outputs a control signal 602 for a physical address 603. Physical address 603 is a unique address of a physical location in the memory array, typically including a column number and a row number. Control signal 602 asserts the row and column of physical address 603. Decoder 600 may comprise logic circuitry and / or a controller or processor executing software.

[0032] Flash memory systems that emulate EEPROM devices are subject to the risk of uneven wear. Specifically, programming and erase operations stress the physical device, and over time, the device can become unusable. This is especially true if the same portion of the physical device is reused. Furthermore, such devices are susceptible to a phenomenon known as "program disturb." Program disturb occurs when a nonvolatile memory cell is programmed multiple times before being erased. In this case, nonvolatile memory cells adjacent to that nonvolatile memory cell may be inadvertently programmed due to the voltage applied to that cell during the programming operation. This has the undesirable effect of programming adjacent nonvolatile memory cells when the system did not intend to do so.

[0033] These problems can be at least partially alleviated by implementing wear leveling techniques. Figure 7A prior art wear leveling method 700 is shown that can be implemented by decoder 600 or logic external to decoder 600. In this example, sector 500 is used as an EEPROM word 710, which is a unit in which an EEPROM emulator stores a single data word (usually two bytes). Because sector 500 includes 16 physical words (400-0, ... 400-15), this means that a single EEPROM word 710 corresponds to 16 physical locations where it can be stored, i.e., EEPROM word 710 can be stored in any of the 16 physical locations.

[0034] In the wear leveling method 700 of the prior art, when EEPROM word 710 is first programmed, its data is written to word 400-0. When EEPROM word 710 is updated, instead of erasing word 400-0 and then programming the updated data into word 400-0, the updated data is written to word 400-1. At this point, the data stored in word 400-0 is stale. Each subsequent programming operation of EEPROM word 710 uses the next word 400 in sector 500 until the 16th programming operation, when word 400-15 is programmed. At this point, every word in sector 500 has been programmed once since the last erase operation. When another programming operation is commanded for EEPROM word 710, the system will perform a sector erase and erase sector 500, then program the data into word 400-0, thus restarting the process. Those skilled in the art will appreciate that the prior art wear leveling method 700 spreads the "loss" throughout all portions of the sector 500 rather than concentrating the loss in a particular location.

[0035] Although the prior art wear leveling method 700 is beneficial, it also has certain limitations. Specifically, it is a crude wear leveling method because the EEPROM emulator composed of flash memory devices can perform bit-level programming (not just byte-level or word-level programming).

[0036] What is needed is an improved system and method for implementing wear leveling in a flash memory system that emulates an EEPROM device in a manner that fully exploits the functionality of the device, including the ability to perform bit-level programming, and counteracts the program disturb phenomenon. Summary of the Invention

[0037] The present invention relates to systems and methods for implementing wear leveling in flash memory devices that emulate EEPROM. These embodiments utilize an index array that stores an index word for each logical address in the emulated EEPROM. Each bit in each index word is associated with a physical address of a physical word in the emulated EEPROM, and the index word tracks which physical word is the current word for a particular logical address. The use of the index words enables a wear leveling algorithm to be implemented that allows a program command to a logical address that results in: (i) skipping the programming operation if the data stored in the current word does not contain a "1" that corresponds to a "0" in the data to be stored, (ii) reprogramming one or more bits of the current word in some cases, or (iii) moving to the next physical word and programming it in some cases. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 is a cross-sectional view of a prior art non-volatile memory cell, to which the method of the present invention can be applied.

[0039] Figure 2 is a cross-sectional view of a prior art non-volatile memory cell, to which the method of the present invention can be applied.

[0040] Figure 3 is a cross-sectional view of a prior art non-volatile memory cell, to which the method of the present invention can be applied.

[0041] Figure 4 Non-volatile memory cells forming a word are shown.

[0042] Figure 5 The words of non-volatile memory cells forming a sector are shown.

[0043] Figure 6 The sectors of non-volatile memory cells forming an array and the decoder are shown.

[0044] Figure 7 A conventional wear leveling method is shown.

[0045] Figure 8 A wear leveling system is shown.

[0046] Figure 9 Shown Figure 8 Example index words in a wear leveling system.

[0047] Figure 10 Shown Figure 8 Example index words for padding in a wear leveling system.

[0048] Figure 11 A wear leveling method is shown.

[0049] Figure 12A 、 Figure 12B and Figure 12C Shown Figure 11 Additional details on the loss-leveling method. DETAILED DESCRIPTION

[0050] Figure 8 An improved EEPROM emulation system 800 with wear leveling is shown. System 800 includes an index array 802, a wear leveling module 804, and an EEPROM emulation array 807. Index array 802 receives a logical address 801 and outputs an index word 803. Wear leveling module 804 receives index word 803, logical address 801, a command 808 (e.g., a program, erase, or read command), and write data 809 (e.g., data to be written during a programming operation), and outputs a control signal 805 for a physical address 806. Physical address 806 is a unique address of a physical location in EEPROM emulation array 807, typically including a column number and a row number. Control signal 805 asserts the row and column of physical address 806, thereby enabling a read, erase, or program operation to occur at physical address 806. Index array 802 contains a separate index word for each sector in EEPROM emulation array 807. Wear leveling module 804 is implemented using a processor or controller executing software instructions, combinational logic, or other known techniques.

[0051] An example is Figure 9 As shown. Here, index word 803 corresponds to sector 500 in EEPROM emulation array 807. Index word 803 includes 16 index bits, 804-0, 804-1, ..., 804-15. Index bit 804-0 corresponds to physical word 400-0, index bit 804-1 corresponds to physical word 400-1, index bit 804-2 corresponds to physical word 400-2, index bit 804-3 corresponds to physical word 400-3, index bit 804-4 corresponds to physical word 400-4, index bit 804-5 corresponds to physical word 400-5, index bit 804-6 corresponds to physical word 400-6, index bit 804-7 corresponds to physical word 400-7, and index bit 804-8 corresponds to physical word 400-9. 8 corresponds to physical word 400-8, index bit 804-9 corresponds to physical word 400-9, index bit 804-10 corresponds to physical word 400-10, index bit 804-11 corresponds to physical word 400-11, index bit 804-12 corresponds to physical word 400-12, index bit 804-13 corresponds to physical word 400-13, index bit 804-14 corresponds to physical word 400-14, and index bit 804-15 corresponds to physical word 400-15. Physical word 400-0 is the first physical word in sector 500, and physical word 400-15 is the last physical word in sector 500.

[0052] refer to Figure 10 , each particular index bit 804 in index word 803 is set to "1" if its corresponding physical word is not in use, and is set to "0" if its corresponding physical word is in use or has been in use. Here, bits 804-1 and 804-0 are set to "0", indicating that physical words 400-1 and 400-0 are in use or have been in use, with bit 804-0 being the least significant bit. Under this system, the most significant bit containing a "0" corresponds to the current word that was most recently programmed, labeled current word 1010, which in this example is physical word 400-1. In this example, physical word 400-0 was previously in use (at which point physical word 400-0 was current word 1010), but now holds "stale" data.

[0053] Figure 11 A wear leveling method 1100 utilizing an index array 802 and index words such as index word 803 is shown. The use of index array 802 and index words provides the system with greater capabilities than the prior art wear leveling method 700 because the system no longer needs to automatically proceed to the next word when a programming operation occurs. Instead, as described below with reference to Figure 12A 、 Figure 12B and Figure 12C As discussed in more detail, in some cases the system will program certain bits in the current word, or will skip programming certain bits in the current word if appropriate.

[0054] Figure 12A 、 Figure 12B and Figure 12C Shown is a diagram of the system 800 (previously described in Figure 8 ) and how it performs the wear leveling method 1100 (previously in Figure 11 Advantageously, the EEPROM emulator of this embodiment performs wear leveling while still allowing individual bit programming.

[0055] In step 1201 , the wear leveling module 804 receives the command 808 , the logical address 801 , the index word 803 , and the write data 809 (when the command 808 is a program command), and proceeds to step 1202 .

[0056] In step 1202 , the wear leveling module 804 reads the current word 1010 in the EEPROM emulation array 807 using the logical address 801 and the index word 803 and proceeds to step 1203 .

[0057] In step 1203, the wear leveling module 804 determines whether the command 808 is a program command. If yes, proceed to step 1204. If not, proceed to step 1212.

[0058] In step 1204, the wear leveling module 804 generates a mask 1220 based on the current word 1010 and the write data 809, and proceeds to step 1205. The mask 1220 is generated according to Table 8:

[0059]

[0060] In step 1205 , the wear leveling module 1205 determines whether the mask 1220 contains at least one “0” (unmasked) bit. If yes, proceed to step 1207 . If no, proceed to step 1206 .

[0061] In step 1206, the wear leveling module 804 skips the programming operation. It does this because it has concluded that data 809 cannot be stored by the programming operation because data 809 does not contain any "0"s corresponding to the "1"s stored in the current word 1010. Because the programming operation can only change a "1" to a "0" (and not a "0" to a "1"), nothing can be accomplished by the programming operation. It is possible that the write data 809 will contain "1"s corresponding to the "0"s stored in the current word, and there may be a mismatch between the data intended to be stored (write data 809) and the data actually stored (current word 1010). The external system can optionally perform a read-verify operation to ensure that the EEPROM word 710 correctly stores the data intended to be stored (write data 809). If the verify operation fails, the external system can then perform an erase operation and then program the write data 809 again. As shown in Table 8, advantageously, a bit is not programmed twice, which prevents program disturb to adjacent cells and increases endurance.

[0062] In step 1207, the wear leveling module 804 determines whether the current word 1010 is the last physical word in the sector 500. If yes, it proceeds to step 1208. If not, it proceeds to step 1209.

[0063] In step 1208, the wear leveling module 804 programs data 809 into the current word 1010 by asserting control signal 805 for physical address 806 (here, the physical address associated with the current word) and programming data 809 into physical address 806 within the EEPROM emulation array 807 according to those bits that are not masked according to mask 1220. It is possible that the write data 809 will contain "1"s corresponding to the "0"s stored in the current word 1010, and there may be a mismatch between the intended data (write data 809) and the actual data stored (current word 1010). The external system can optionally perform a read-verify operation to ensure that the EEPROM word 710 correctly stores the intended data (write data 809). If the verify operation fails, the external system can then perform an erase operation and then program the write data 809 again. It is worth noting that because the last physical word may have been previously programmed since the last erase operation, the possibility of program disturb increases. However, this is an acceptable outcome because the previous word already contains "stale data" and if its data is disturbed, it will not affect the integrity of the system. In addition, there are no subsequent physical words after the last physical word, so there is no concern about program disturb occurring on that side of the last physical word.

[0064] In step 1209 , the wear leveling module 1209 determines whether the current word 1010 contains all “1s.” If so, it proceeds to step 1210 . If not, it proceeds to step 1211 .

[0065] In step 1210, the wear leveling module 1209 programs the data 809 into the current word 1010. No mismatch will occur because the current word 1010 is in an erased state (all "1s") prior to the programming operation. In addition, since the current word 1010 has not been programmed since it was last erased, there is no problem of program disturb. The wear leveling module 1209 programs the data into the current word 1010 by asserting the control signal 805 for the physical address 806 (here, the physical address associated with the current word 1010) and programming the data 809 into the physical address 806 in the EEPROM emulation array 807 according to the bits that are not masked according to the mask 1220.

[0066] In step 1211, the wear leveling module 1211 programs the data 809 into the next word and transfers to the next word in the index word 803. This is done because in step 1209, the current word 1010 was determined to be not in the erased state (all "1"s), which means that the current word 1010 has already been programmed. This transfer is performed to avoid the possibility of any program disturb occurring. The wear leveling module 1211 programs the data into the next word by asserting the control signal 805 at the physical address 806 (here, the physical address associated with the next word) and programming the data 809 to the physical address 806 within the EEPROM emulation array 807. Moving to the next bit in the index word 803 is done by changing the index bit of the next word from "1" to "0" (which itself requires a programming operation on the index word 803).

[0067] In step 1212, the wear leveling module 804 determines whether the command 808 is an erase command. If so, it proceeds to step 1213. If not, it proceeds to step 1216.

[0068] In step 1213, the wear leveling module 804 determines whether the current word is the last physical word in the sector 500 (meaning the current word is word 400-15, which would be indicated by index bit 804-15 being "0"). If so, the module proceeds to step 1214. If not, the module proceeds to step 1215.

[0069] In step 1214, wear leveling module 804 performs a sector erase on sector 500, which will cause all bits in words 400-0, 400-1, ..., 400-15 to be changed to "1", and will also erase index word 803 so that all bits in index word 803 will be changed to "1".

[0070] In step 1215, the wear leveling module 804 skips the erase operation and moves to the next bit in the index word 803 by changing the index bit of the next physical word from "1" to "0" (which itself requires a program operation on the index word 803). This is effectively the same as an erase because it proceeds to the next word, which has not yet been programmed and contains all "1s."

[0071] In step 1216, wear leveling module 804 performs a read operation because it can infer that command 808 is a read command. The wear leveling module performs a read by asserting control signal 805 at physical address 806 (here, the physical address associated with current word 1010) and reading data from physical address 806 in EEPROM emulation array 807.

[0072] The embodiment described herein has the following advantages over the prior art loss leveling method 700:

[0073] In an embodiment, each particular bit is programmed to a "0" value no more than once between erase operations on that bit, which reduces program disturb phenomena;

[0074] The embodiment allows bit programming while performing wear leveling, whereas the prior art wear leveling method 700 only allows word-level programming; and

[0075] When implementations receive a sector erase command, they will move to the next word without performing an erase until the current word is the last word in the sector.

[0076] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening material, element, or space disposed therebetween) and "indirectly on" (intervening material, element, or space disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intervening material, element, or space disposed therebetween) and "indirectly adjacent" (intervening material, element, or space disposed therebetween), "mounted to" includes "directly mounted to" (no intervening material, element, or space disposed therebetween) and "indirectly mounted to" (intervening material, element, or space disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (no intervening material or element electrically connecting the elements together) and "indirectly electrically coupled to" (intervening material or element electrically connecting the elements together). For example, forming an element "above" a substrate may include forming the element directly on the substrate without intervening material / element therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. An EEPROM emulation system with wear leveling, comprising: an EEPROM emulation array comprising an array of nonvolatile memory cells; and a wear leveling module coupled to the nonvolatile memory cell array and configured to: Receive programming commands, write data and logical addresses; reading a current word based on the logical address and index bits, wherein the current word is located in a sector of a physical word of nonvolatile memory cells in the array of nonvolatile memory cells, the sector of words corresponding to the logical address and including a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; When the write data does not include a "0" for a bit that is "1" in the current word, skipping a programming operation; When the write data includes a “0” for a bit that is a “1” in the current word and the current word is the last physical word in the sector, programming the write data into the current word; as well as When the write data includes a “0” for a bit that is a “1” in the current word, and the current word is not the last physical word in the sector, the write data is programmed into the next word.

2. The system of claim 1, wherein the index bits are bits in an index word.

3. The system of claim 2, wherein the index word comprises a set of bits, wherein each bit in the index word corresponds to a physical word in the array. 4 . The system of claim 3 , wherein each bit in the index word indicates whether a corresponding physical word in the array is used.

5. The system of claim 1, wherein the sector comprises two rows of nonvolatile memory cells in the array of nonvolatile memory cells.

6. The system of claim 1, wherein each of the nonvolatile memory cells comprises a bit line terminal, a source line terminal, a word line terminal, and a floating gate.

7. The system of claim 6, wherein each of the nonvolatile memory cells further comprises a control gate.

8. The system of claim 7, wherein each of the nonvolatile memory cells further comprises an erase gate.

Images