Semiconductor device with vertical guard plate structure

Abstract

A semiconductor device may be provided, comprising: a substrate including a cell array region and a through-electrode region; an electrode stack located on the substrate and including electrodes; a vertical structure extending through the electrode stack within the cell array region; a vertical guard plate structure located within an extension region and surrounding the through-electrode region; and an insulating layer located within a perimeter defined by the vertical guard plate structure and at the same level as the electrodes. The electrodes may include a first protrusion that protrudes between the vertical guard plate structures in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0022332 filed on February 24, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device having a vertical guard plate structure. Background Art

[0004] Three-dimensional nonvolatile memory devices with multi-stack structures have been proposed to achieve compactness and high integration in electronic products. These devices include electrodes, an isolation insulating layer, and a dummy isolation insulating layer. However, this technology has been difficult to arrange the electrodes so that they pass through the isolation insulating layer and the dummy isolation insulating layer. Summary of the Invention

[0005] Some example embodiments of the present disclosure provide a semiconductor device including a vertical guard plate structure.

[0006] A semiconductor device according to an example embodiment of the present disclosure includes: a substrate including a cell array region and an extension region, the extension region extending from the cell array region and including a through-electrode region;

[0007] An electrode stack is located on a substrate, the electrode stack including alternating mold layers and electrodes; a vertical structure passes through the electrode stack within the cell array region; and a vertical guard plate structure is located within the extension region and passes through the electrode stack. The vertical guard plate structure may surround the through-electrode region in a plan view. The distance between adjacent vertical guard plate structures in the vertical guard plate structure may be smaller than the distance between adjacent vertical structures in the vertical structure.

[0008] According to another example embodiment of the present disclosure, a semiconductor device includes: a substrate including a cell array region and an extension region, the extension region extending from the cell array region and including a through-electrode region, the through-electrode region including a through-electrode; an electrode stack located on the substrate, the electrode stack including alternately stacked mold layers and electrodes; a vertical structure passing through the electrode stack in the cell array region; and an internal vertical guard plate structure and an external vertical guard plate structure located in the extension region and passing through the electrode stack. The internal vertical guard plate structure and the external vertical guard plate structure may surround the through-electrode region in a plan view. The distance between each of the internal vertical guard plate structures and a corresponding one of the external vertical guard plate structures may be less than the distance between each of the internal vertical guard plate structures and a corresponding one of the through-electrodes. The distance between each of the internal vertical guard plate structures and a corresponding one of the external vertical guard plate structures may be less than the distance between adjacent vertical structures in the vertical structures.

[0009] According to another example embodiment of the present disclosure, a semiconductor device includes: a substrate, which includes a cell array region and an extension region, the extension region extends from the cell array region and includes a through-electrode region; an electrode stack, which is located on the substrate, the electrode stack including alternatingly stacked molding layers and electrodes; a peripheral circuit structure, which is located between the substrate and the electrode stack; a lower conductive layer, which is located on the peripheral circuit structure; a connecting conductive layer, which is located on the lower conductive layer in the cell array region; a connecting molding layer, which is located on the lower conductive layer in the extension region; a support member, which is located on the connecting conductive layer and the connecting molding layer, and has the electrode stack on the support member; a buried insulating layer, which is located in the through-electrode region and passes through the lower conductive layer, the connecting molding layer and the support member; a vertical structure, which passes through the electrode stack in the cell array region; a vertical guard plate structure, which is located in the extension region and passes through the electrode stack, the vertical guard plate structure surrounding the through-electrode region in a plan view; and an insulating layer, which is located inside the periphery defined by the vertical guard plate structure and is located at the same level as the electrode. The electrode may include a first protrusion configured to contact the vertical guard plate structure in plan view.

[0010] A method for manufacturing a semiconductor device according to an example embodiment of the present disclosure may include forming a substrate including a cell array region and an extension region, the extension region including a through-electrode region; forming a peripheral circuit structure on the substrate; forming a mold stack including alternatingly stacked mold layers and insulating layers on the peripheral circuit structure; forming a vertical structure passing through the mold stack in the cell array region; forming a vertical guard plate structure in the extension region, the vertical guard plate structure passing through the mold stack and surrounding the through-electrode region; forming an isolation insulating layer and a dummy isolation insulating layer, the isolation insulating layer passing through the mold stack and extending in a first horizontal direction, the dummy isolation insulating layer extending between the isolation insulating layers in the first horizontal direction, the isolation insulating layer and the dummy isolation insulating layer being spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; partially removing the insulating layer; and forming electrodes between the mold layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects, features and effects of the inventive concept will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0012] Figure 1 is a layout of a semiconductor device according to example embodiments of the inventive concept.

[0013] Figure 2A and Figure 2B It is intercepted along line IIAA-IIAA', line IIAB-IIAB' and line IIB-IIB' Figure 1 A vertical cross-sectional view of the semiconductor device shown in .

[0014] Figure 2C It was intercepted along the IIC-IIC' line Figure 2A and Figure 2B A horizontal cross-sectional view of the semiconductor device shown in FIG.

[0015] Figure 2D Shown Figure 2C Enlarged views of some parts.

[0016] Figure 3 and Figure 4 yes Figure 2A 1 is an enlarged view of some parts of the semiconductor device shown in FIG.

[0017] Figure 5 is a horizontal cross-sectional view of a semiconductor device according to example embodiments of the inventive concepts.

[0018] Figure 6A and Figure 6B It is intercepted along the lines VIAA-VIAA', VIAB-VIAB' and VIB-VIB' Figure 5A vertical cross-sectional view of the semiconductor device shown in .

[0019] Figure 6C It was intercepted along VIC-VIC' Figure 6A and Figure 6B A horizontal cross-sectional view of the semiconductor device shown in FIG.

[0020] Figure 7 and Figure 8 is a horizontal cross-sectional view of a semiconductor device according to example embodiments of the inventive concepts.

[0021] 9A to 18B are vertical cross-sectional views shown in order of processes of a method of fabricating a semiconductor device according to example embodiments of the inventive concept. DETAILED DESCRIPTION

[0022] Figure 1 is a layout of a semiconductor device according to example embodiments of the inventive concept. Figure 2A and Figure 2B It is intercepted along line IIAA-IIAA', line IIAB-IIAB' and line IIB-IIB' Figure 1 A vertical cross-sectional view of the semiconductor device shown in . Figure 2C It was intercepted along the IIC-IIC' line Figure 2A and Figure 2B A horizontal cross-sectional view of a semiconductor device shown in FIG. A memory device according to example embodiments of the present disclosure may include a flash memory such as a 3D-NAND.

[0023] Reference Figure 1 、 Figure 2A and Figure 2B The semiconductor device 100 according to an example embodiment of the present disclosure may include a cell array region CA and an extension region EA. The extension region EA may include pad regions PA and through-electrode regions TA disposed between the pad regions PA.

[0024] The cell array area CA may include a vertical structure CS. The pad area PA may include a dummy vertical structure DCS, a vertical guard plate structure FS, and an electrode contact WC. The through-electrode area TA may include a through electrode 150. The through-electrode area TA may not include the vertical guard plate structure FS and the dummy vertical structure DCS.

[0025] Isolation insulation layers WLC may be provided in the cell array area CA and the extension area EA. The isolation insulation layers WLC may extend in a first horizontal direction D1 and may be spaced apart from each other in a second horizontal direction D2. Dummy isolation insulation layers DWLC may be provided in a portion of the extension area EA. The dummy isolation insulation layers DWLC may extend in the first horizontal direction D1 and may be spaced apart from each other in a second horizontal direction D2. The dummy isolation insulation layers DWLC may be provided at regular intervals between the isolation insulation layers WLC.

[0026] The semiconductor device 100 of the present disclosure may have a cell-on-periphery (COP) structure. For example, the semiconductor device 100 may include a peripheral circuit structure PS and a cell array structure CAS disposed on the peripheral circuit structure PS. The peripheral circuit structure PS may be formed on a substrate 10 and may include a device isolation layer 12, an impurity region 14, a transistor 20, a contact plug 30, a peripheral circuit wire 32, and a peripheral insulation layer 34.

[0027] Device isolation layer 12 and impurity region 14 may be provided on the top surface of substrate 10. Transistor 20, contact plug 30, and peripheral circuit wire 32 may be provided on substrate 10. Substrate 10 may include a semiconductor material. For example, substrate 10 may be one of a silicon substrate, a germanium substrate, a silicon-germanium substrate, and a silicon-on-insulator (SOI) substrate. In example embodiments, substrate 10 may include one of a Group IV semiconductor, a Group III-V compound semiconductor, and a Group II-VI oxide semiconductor.

[0028] The impurity region 14 may be disposed adjacent to the transistor 20. A peripheral insulating layer 34 may cover the transistor 20 and the contact plug 30. The contact plug 30 may be electrically connected to the impurity region 14. A peripheral circuit conductive line 32 may be connected to the contact plug 30.

[0029] The cell array structure CAS may be disposed on the peripheral insulating layer 34. The cell array structure CAS may include an electrode stack 111, an interlayer insulating layer 116, a vertical structure CS, a dummy vertical structure DCS, a vertical guard plate structure FS, an isolation insulating layer WLC, a dummy isolation insulating layer DWLC, and a through electrode 150. The cell array structure CAS may further include a lower conductive layer 40 disposed below the electrode stack 111, an extended mold layer 42, an extended conductive layer 43, a support member 44, and a buried insulating layer 46.

[0030] The lower conductive layer 40 may be disposed on the peripheral circuit structure PS and may correspond to a common source line (CSL). In an example embodiment, the lower conductive layer 40 may include doped polysilicon. The extended mold layer 42 may be partially disposed on the lower conductive layer 40 within the extension area EA. The extended mold layer 42 may include an insulating layer 42b and a protective layer 42a disposed on the top and bottom surfaces of the insulating layer 42b. The extended conductive layer 43 may be disposed on the lower conductive layer 40 within the cell array area CA. The support member 44 may be disposed on the extended mold layer 42 and the extended conductive layer 43 and may contact the top surface of the lower conductive layer 40 around the isolation insulating layer WLC. The buried insulating layer 46 may be disposed on the peripheral insulating layer 34 within the through-electrode area TA. The top surface of the buried insulating layer 46 may be coplanar with the top surface of the support member 44.

[0031] The electrode stack 111 may include a plurality of mold layers 112 and a plurality of electrodes WL alternately stacked with each other. The electrodes WL may include word lines. At least one of the electrodes WL disposed at the lower portion of the electrode stack 111 may be a ground selection line (GSL). At least one of the electrodes WL disposed at the upper portion of the electrode stack 111 may be a string selection line (SSL) or a drain selection line (DSL). The electrode stack 111 may have a stepped structure within the extension area EA. In the area surrounding the through-electrode area TA, the electrode stack 111 may include a plurality of insulating layers 114 alternately stacked with the plurality of mold layers 112. For example, as Figure 1 As shown in FIG, multiple insulating layers 114 may be disposed within the vertical guard plate structure FS (e.g., within the perimeter defined by the vertical guard plate structure). The multiple insulating layers 114 may be physically and materially isolated from the electrodes WL by the vertical guard plate structure FS. Each insulating layer 114 may be positioned at the same level as its corresponding electrode WL. In an example embodiment, the multiple mold layers 112 may include silicon oxide. The interlayer insulating layer 116 may cover the stepped structure of the electrode stack 111.

[0032] The vertical structure CS may extend in a vertical direction while passing through the extended conductive layer 43 , the support 44 , and the electrode stack 111 within the cell array area CA. The vertical structure CS may be electrically connected to the extended conductive layer 43 .

[0033] The vertical guard plate structure FS can extend in the vertical direction while passing through the extended mold layer 42, the support member 44, and the electrode stack 111 within the extension area EA. Furthermore, the vertical guard plate structure FS can vertically pass through the interlayer insulating layer 116. Conductive pads 134 can be provided on the vertical structure CS and the vertical guard plate structure FS. The configurations of the vertical guard plate structure FS and the dummy vertical structure DCS can be the same or similar to that of the vertical structure CS. The diameter of the vertical guard plate structure FS can be larger than the diameter of the dummy vertical structure DCS.

[0034] The isolation insulating layer WLC and the dummy isolation insulating layer DWLC may vertically pass through the support member 44, the electrode stack 111, the interlayer insulating layer 116, and the first upper insulating layer 140, and may contact the lower conductive layer 40. The dummy isolation insulating layer DWLC may be arranged at regular intervals between the isolation insulating layers WLC. The isolation insulating layer WLC and the dummy isolation insulating layer DWLC may extend in the first horizontal direction D1. The dummy isolation insulating layer DWLC may be arranged in a portion of the extension area EA. The vertical guard plate structure FS may be spaced apart from the dummy isolation insulating layer DWLC in the first horizontal direction D1, and may be arranged between the isolation insulating layers WLC (e.g., an adjacent pair of isolation insulating layers WLC) in the second horizontal direction D2. That is, in a plan view, the isolation insulating layer WLC and the dummy isolation insulating layer DWLC may not overlap with the vertical guard plate structure FS.

[0035] A first upper insulating layer 140 may be disposed on the electrode stack 111 and the interlayer insulating layer 116, and a second upper insulating layer 142 may be disposed on the first upper insulating layer 140. A bit line plug 144 may pass through the first and second upper insulating layers 140 and 142 and may be connected to the conductive pad 134. A bit line 146 may be disposed on the second upper insulating layer 142 and may be connected to the bit line plug 144.

[0036] The through-electrode 150 may be disposed in the through-electrode area TA. The through-electrode 150 may vertically pass through the buried insulating layer 46, the electrode stack 111, and the interlayer insulating layer 116. The connecting wire 152 may be disposed on the through-electrode 150. The through-electrode 150 may electrically connect the peripheral circuit wire 32 of the peripheral circuit structure PS to the connecting wire 152.

[0037] Figure 2C It was intercepted along the IIC-IIC' line Figure 2A and Figure 2B A horizontal cross-sectional view of the semiconductor device shown in FIG.

[0038] Reference Figure 2C , the vertical guard plate structure FS can be arranged to surround the through-electrode area TA in the extension area EA. The vertical guard plate structure FS can be spaced apart from the dummy isolation insulating layer DWLC and can be arranged between the isolation insulating layers WLC. In example embodiments, the vertical guard plate structures FS can be arranged at regular intervals, but the present disclosure is not limited thereto. In example embodiments, the vertical guard plate structures FS can be arranged to contact each other.

[0039] In a plan view, the electrode WL can be disposed outside the vertical guard plate structure FS, while the dummy vertical structure DCS, the insulating layer 114, and the through-electrode 150 can be disposed within the perimeter defined by the vertical guard plate structure FS. The dummy vertical structure DCS can be disposed between the vertical guard plate structure FS and the through-electrode area TA. The diameter of the dummy vertical structure DCS can be different from the diameter of the vertical guard plate structure FS. The distance between the dummy vertical structures DCS can be different from the distance between the vertical guard plate structures FS. For example, the distance between the dummy vertical structures DCS can be greater than the distance between the vertical guard plate structures FS.

[0040] The electrode WL may contact the vertical guard plate structure FS and the insulating layer 42b. A cross-section of the insulating layer 114 may contact the vertical guard plate structure FS and the electrode WL. In an exemplary embodiment, the distance from the dummy isolation insulating layer DWLC to the side surface of the electrode WL (e.g., the side surface of the electrode WL around the vertical guard plate structure FS) may be less than the distance between the dummy isolation insulating layers DWLC. For example, the maximum distance W1 from the dummy isolation insulating layer DWLC along the first horizontal direction D1 to the side surface of the electrode WL (e.g., the side surface of the electrode WL around the vertical guard plate structure FS) may be less than or equal to ½ of the distance W2 between adjacent dummy isolation insulating layers DWLC in the dummy isolation insulating layers DWLC. The maximum distance W3 from the isolation insulating layer WLC along the second horizontal direction D2 to the side surface of the electrode WL (e.g., the side surface of the electrode WL disposed around the vertical guard plate structure FS) may be less than or equal to ½ of the distance W2 between adjacent dummy isolation insulating layers DWLC in the dummy isolation insulating layers DWLC.

[0041] Figure 2D Shown Figure 2C Enlarged views of some parts.

[0042] Reference Figure 2DIn an example embodiment, a portion of the electrode WL may include a first protrusion P1 protruding toward the insulating layer 114. In an example embodiment, a cross-section of the insulating layer 114 may include a second protrusion P2 protruding toward the electrode WL. The first protrusion P1 and the second protrusion P2 may protrude so as to face each other between the vertical guard plate structures FS. In an example embodiment, the first protrusion P1 and the second protrusion P2 may contact each other between the vertical guard plate structures FS. The vertical guard plate structures FS may be arranged more densely than the vertical structures CS. For example, the minimum distance between the vertical guard plate structures FS may be smaller than the minimum distance between the vertical structures CS. In an example embodiment, the distance W4 between the vertical guard plate structures FS may be smaller than the distance W5 between the vertical structures CS. For example, the distance W4 between the vertical guard plate structures FS may be less than 1 / 2 of the distance W5 between the vertical structures CS. Here, the distance W4 between the vertical guard plate structures FS may be the distance between side surfaces of two adjacent ones of the vertical guard plate structures FS, and the distance W5 between the vertical structures CS may be the distance between side surfaces of two adjacent ones of the vertical structures CS.

[0043] In an example embodiment, the diameter of the vertical guard plate structure FS may be greater than or equal to the diameter of the dummy vertical structure DCS, and the diameter of the dummy vertical structure DCS may be greater than or equal to the diameter of the vertical structure CS. For example, the ratio of the diameter of the dummy vertical structure DCS to the diameter of the vertical structure CS may be 1:1 to 2:1. The ratio of the diameter of the vertical guard plate structure FS to the diameter of the vertical structure CS may be 1:1 to 4:1. In an example embodiment, the ratio of the diameter of the dummy vertical structure DCS to the diameter of the vertical structure CS may be 1.2:1 to 1.5:1, and the ratio of the diameter of the vertical guard plate structure FS to the diameter of the vertical structure CS may be 1.2:1 to 2.4:1. In an example embodiment, the ratio of the diameter of the dummy vertical structure DCS to the diameter of the vertical structure CS may be 1.4:1, and the ratio of the diameter of the vertical guard plate structure FS to the diameter of the vertical structure CS may be 1.4:1.

[0044] Figure 3 and Figure 4 yes Figure 2A 1 is an enlarged view of some parts of the semiconductor device shown in FIG.

[0045] Reference Figure 3, the vertical structure CS may include an information storage layer 120, a channel layer 130, and a buried insulating pattern 132. The channel layer 130 may be disposed inside the information storage layer 120, and the buried insulating pattern 132 may be disposed inside the channel layer 130. The information storage layer 120 may include a tunneling insulating layer 122, a charge storage layer 124, and a blocking layer 126. The tunneling insulating layer 122 may be disposed inside the charge storage layer 124, and the charge storage layer 124 may be disposed inside the blocking layer 126. In example embodiments, the channel layer 130 may include polycrystalline silicon. The buried insulating pattern 132 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In example embodiments, the blocking layer 126 and the tunneling insulating layer 122 may include silicon oxide, and the charge storage layer 124 may include silicon nitride. The vertical guard plate structure FS and the dummy vertical structure DCS may have the same or substantially similar structure as the vertical structure CS. For example, the vertical guard plate structure FS may include an information storage layer 120 , a channel layer 130 , and a buried insulating pattern 132 .

[0046] Reference Figure 4 The extended conductive layer 43 may pass through the information storage layer 120 and may make contact with a side surface of the channel layer 130. A portion of the extended conductive layer 43 that makes contact with the channel layer 130 may extend in a vertical direction.

[0047] Figure 5 is a horizontal cross-sectional view of a semiconductor device according to example embodiments of the inventive concepts. Figure 6A and Figure 6B It is intercepted along the lines VIAA-VIAA', VIAB-VIAB' and VIB-VIB' Figure 5 A vertical cross-sectional view of the semiconductor device shown in . Figure 6C It was intercepted along VIC-VIC' Figure 6A and Figure 6B A horizontal cross-sectional view of the semiconductor device shown in FIG.

[0048] Figure 6C is a horizontal cross-sectional view of the lowermost layer in the electrode stack 111 , and shows the vertical guard plate structure FS, the electrode WL, and the insulating layer 114 in the lowermost layer.

[0049] Reference Figure 5 、 Figure 6A and Figure 6B, the semiconductor device 200 may include a vertical guard plate structure FS surrounding the through-electrode area TA. In example embodiments, the vertical guard plate structure FS may be configured so that its side surfaces are in contact with each other, and the electrode WL and the insulating layer 114 may not be in direct contact with each other. In a plan view, the horizontal length of the vertical guard plate structure FS may be greater than the contact length between adjacent vertical guard plate structures FS in the vertical guard plate structures FS. In other words, the horizontal length of the vertical guard plate structure FS may be set so that each of a pair of adjacent vertical guard plate structures FS is connected to each other.

[0050] In a longitudinal cross-sectional view, the vertical structure CS and the vertical guard plate structure FS may have a tapered shape. For example, the horizontal width of the vertical structure CS and the vertical guard plate structure FS may gradually decrease from the upper portion of the device to the lower portion of the device. In a longitudinal cross-sectional view, the horizontal distance from the dummy isolation insulating layer DWLC to the vertical guard plate structure FS may gradually increase from the upper portion of the device to the lower portion of the device.

[0051] Reference Figure 6C , the side surfaces of the vertical guard plate structure FS may not directly contact each other below the electrode stack 111. The lowermost electrode WL may contact the lowermost insulating layer 114. The cross-section (e.g., side surface) of the lowermost electrode WL may be located inside the perimeter defined by the vertical guard plate structure FS, but the present disclosure is not limited thereto. The maximum distance from the dummy isolation insulating layer DWLC along the first horizontal direction D1 to the cross-section of the lowermost electrode WL may be less than or equal to 1 / 2 of the distance between adjacent dummy isolation insulating layers DWLC in the dummy isolation insulating layer DWLC. The maximum distance from the isolation insulating layer WLC along the second horizontal direction to the cross-section (e.g., side surface) of the lowermost electrode WL may be less than or equal to 1 / 2 of the distance between adjacent dummy isolation insulating layers DWLC in the dummy isolation insulating layer DWLC.

[0052] Figure 7 and Figure 8 is a horizontal cross-sectional view of a semiconductor device according to example embodiments of the inventive concepts.

[0053] Reference Figure 7, the semiconductor device 300 may include an internal vertical guard plate structure FS1 and an external vertical guard plate structure FS2 surrounding the through-electrode area TA. The external vertical guard plate structure FS2 may be arranged outside the internal vertical guard plate structure FS1. The internal vertical guard plate structures FS1 may be spaced apart from each other along the periphery (or perimeter) of the through-electrode area TA, and the external vertical guard plate structures FS2 may be spaced apart from each other along the periphery (or perimeter) of the through-electrode area TA. In an example embodiment, the internal vertical guard plate structure FS1 and the external vertical guard plate structure FS2 may be arranged in a zigzag form. For example, a corresponding one of the internal vertical guard plate structures FS2 may be arranged between two adjacent external vertical guard plate structures FS1 in the external vertical guard plate structure FS1.

[0054] The cross section (e.g., side surface) of the electrode WL may be disposed between the inner vertical guard plate structure FS1 and the outer vertical guard plate structure FS2. The cross section of the electrode WL may contact the inner vertical guard plate structure FS1, but the present disclosure is not limited thereto. In example embodiments, the cross section of the electrode WL may not contact the inner vertical guard plate structure FS1.

[0055] The distance between each of the inner vertical guard plate structures FS1 and a corresponding one of the outer vertical guard plate structures FS2 may be smaller than the distance between each of the inner vertical guard plate structures FS1 and the through-electrode 150. In addition, the distance between each of the inner vertical guard plate structures FS1 and a corresponding one of the outer vertical guard plate structures FS2 may be smaller than the distance between the vertical structures CS.

[0056] Reference Figure 8 The semiconductor device 400 may include an inner vertical guard plate structure FS1 and an outer vertical guard plate structure FS2 surrounding the through-electrode area TA. The diameter of the inner vertical guard plate structure FS1 may be different from the diameter of the outer vertical guard plate structure FS2. In an example embodiment, the diameter of the outer vertical guard plate structure FS2 may be larger than the diameter of the inner vertical guard plate structure FS1. In an example embodiment, the diameter of the outer vertical guard plate structure FS2 may be smaller than the diameter of the inner vertical guard plate structure FS1.

[0057] 9A to 18B are vertical cross-sectional views shown in order of processes of a method of fabricating a semiconductor device according to example embodiments of the inventive concept. Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A and Figure 18A It is along Figure 1A vertical cross-sectional view taken along line IIAA-IIAA' and line IIAB-IIAB', Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B and Figure 18B It is along Figure 1 A vertical cross-sectional view taken along line IIB-IIB'.

[0058] Reference Figure 9A and Figure 9B The method of manufacturing semiconductor device 100 may include: forming a peripheral circuit structure PS on substrate 10; forming a lower conductive layer 40 on peripheral circuit structure PS; and forming an extended mold layer 42 on lower conductive layer 40. Peripheral circuit structure PS may include a device isolation layer 12, an impurity region 14, transistor 20, a contact plug 30, a peripheral circuit conductive line 32, and a peripheral insulating layer 34. Device isolation layer 12 and impurity region 14 may be formed on the top surface of substrate 10. In example embodiments, device isolation layer 12 may include an insulating material such as silicon oxide or silicon nitride. Impurity region 14 may include n-type impurities. Transistor 20 may be disposed adjacent to impurity region 14. Peripheral circuit conductive line 32 may be disposed on contact plug 30 and may be connected to impurity region 14 via contact plug 30. Peripheral insulating layer 34 may cover transistor 20, contact plug 30, and peripheral circuit conductive line 32.

[0059] The lower conductive layer 40 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. In an exemplary embodiment, the lower conductive layer 40 may include a doped polysilicon layer. The extended mold layer 42 may include an insulating layer 42b and a protective layer 42a disposed on the top and bottom surfaces of the insulating layer 42b. The extended mold layer 42 may include a material having an etch selectivity relative to the lower conductive layer 40, and the protective layer 42a may include a material having an etch selectivity relative to the insulating layer 42b. In an exemplary embodiment, the protective layer 42a may include silicon oxide, and the insulating layer 42b may include silicon nitride.

[0060] Reference Figure 10A and Figure 10BThe method may include: partially removing the extended mold layer 42; forming a support member 44 on the lower conductive layer 40; and forming a buried insulating layer 46 on the peripheral circuit structure PS. In the extension area EA, the extended mold layer 42 may be partially removed by a patterning process, and the top surface of the lower conductive layer 40 may be partially exposed. The support member 44 may be formed to cover the exposed portion of the lower conductive layer 40 and the extended mold layer 42. In example embodiments, the support member 44 may include polysilicon.

[0061] In the through-electrode area TA, the lower conductive layer 40, the extended mold layer 42, and the support member 44 may be partially removed, and the top surface of the peripheral insulating layer 34 of the peripheral circuit structure PS may be partially exposed. A buried insulating layer 46 may be formed to cover the exposed portion of the peripheral insulating layer 34. Forming the buried insulating layer 46 may include performing a deposition process and a planarization process. The top surface of the buried insulating layer 46 may be coplanar with the top surface of the support member 44.

[0062] Reference Figure 11A and Figure 11B The method may include forming a mold stack 110. Forming the mold stack 110 may include performing a deposition process. The mold stack 110 may include a plurality of mold layers 112 and a plurality of insulating layers 114 alternately stacked on each other. In example embodiments, the mold layers 112 may include silicon oxide, and the insulating layers 114 may include silicon nitride.

[0063] Reference Figure 12A and Figure 12B , the method may include trimming the mold stack 110 and forming an interlayer insulating layer 116. The mold stack 110 may have a stepped structure formed by the trimming process in the extension area EA. In example embodiments, the extension area EA may include a through-electrode area TA formed between the pad areas PA. The mold stack 110 may have a stepped structure in the pad area PA, and may have a flat shape instead of a stepped structure in the through-electrode area TA.

[0064] The interlayer insulating layer 116 may cover the mold stack 110 in the inner extension area EA. The interlayer insulating layer 116 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, a high-k dielectric material, or a combination thereof. In example embodiments, the interlayer insulating layer 116 may include silicon oxide.

[0065] Reference Figure 13A and Figure 13B, the method may include forming a channel hole CH and a guard plate hole FH. The channel hole CH may be formed by anisotropically etching the extended mold layer 42, the support member 44, and the mold stack 110, and the top surface of the lower conductive layer 40 may be exposed. The guard plate hole FH may be formed by anisotropically etching the extended mold layer 42, the support member 44, the mold stack 110, and the interlayer insulating layer 116, and the top surface of the lower conductive layer 40 may be exposed. The channel hole CH may be formed in the cell array area CA, and the guard plate hole FH may be formed in the extension area EA. In an example embodiment, the guard plate hole FH may be formed between the cell array area CA and the through-electrode area TA in the pad area PA, and may surround the through-electrode area TA. In an example embodiment, the diameter of the guard plate hole FH may be formed to be larger than the diameter of the channel hole CH.

[0066] Reference Figure 14A and Figure 14B , the method may include forming a vertical structure CS and forming a vertical guard plate structure FS.

[0067] A vertical structure CS may be formed in the channel hole CH, and a vertical guard plate structure FS may be formed in the guard plate hole FH. Figure 3 , the vertical structure CS may include an information storage layer 120, a channel layer 130, and a buried insulating pattern 132. The channel layer 130 may be disposed inside the information storage layer 120, and the buried insulating pattern 132 may be disposed inside the channel layer 130. The information storage layer 120 may include a blocking layer 126, a charge storage layer 124, and a tunneling insulating layer 122. The charge storage layer 124 may be disposed inside the blocking layer 126, and the tunneling insulating layer 122 may be disposed inside the charge storage layer 124. Figure 1 In example embodiments, a dummy vertical structure DCS may be formed in the extension area EA. The vertical guard plate structure FS and the dummy vertical structure DCS may have substantially the same structure as the vertical structure CS.

[0068] Conductive pads 134 may be formed on the vertical structures CS and dummy vertical structures DCS. Conductive pads 134 may be formed on the vertical guard plate structures FS. Conductive pads 134 may include a conductive layer such as metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or a combination thereof.

[0069] Reference Figure 15A and Figure 15BThe method may include forming an isolation trench T and a dummy isolation trench DT. Forming the isolation trench T and the dummy isolation trench DT may include forming a first upper insulating layer 140 on the mold stack 110 and the interlayer insulating layer 116, and anisotropically etching the extended mold layer 42, the support member 44, and the mold stack 110. The isolation trench T and the dummy isolation trench DT may expose the top surface of the lower conductive layer 40, the side surfaces of the mold layer 112, and the side surfaces of the insulating layer 114, and may extend in the same direction. The isolation trench T may be formed above the cell array area CA and the extension area EA. The dummy isolation trench DT may also be formed above a portion of the cell array area CA and a portion of the extension area EA.

[0070] Reference Figure 16A and Figure 16B , the method may include: removing the extended mold layer 42 from the cell array area CA. Removing the extended mold layer 42 may include performing a wet etching process. Spacers may be formed on the side surfaces of the isolation trenches T to prevent the mold stack 110 and the support members 44 from being etched. The side surfaces of the vertical structures CS may be partially exposed. Further reference is made to Figure 4 , a portion of the information storage layer 120 may be etched to expose the channel layer 130. The extended mold layer 42 in the extension area EA may not be removed.

[0071] Reference Figure 17A and Figure 17B The method may include forming an extended conductive layer 43 and removing the insulating layer 114. The extended conductive layer 43 may be formed between the lower conductive layer 40 and the support member 44 and may contact the side surfaces of the vertical structure CS and the vertical guard plate structure FS. Figure 4 , the extended conductive layer 43 may contact the side surface of the channel layer 130. The extended conductive layer 43 may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0072] Removing the insulating layer 114 may include performing an isotropic etching process. For example, the insulating layer 114 may be removed by a wet etching process via the isolation trenches T and the dummy isolation trenches DT. In the removal process, the mold layer 112 may not be removed, and an opening OP may be formed between the mold layers 112. The opening OP may expose the top and bottom surfaces of the mold layer 112, the side surfaces of the vertical structure CS, and the side surfaces of the vertical guard plate structure FS. In example embodiments, the insulating layer 114 in the area around the through-electrode area TA may not be removed. For example, some portions of the insulating layer 114 located inside the periphery defined by the vertical guard plate structure FS may not be removed. In the removal process, the vertical guard plate structure FS may serve as a barrier to prevent the etchant from being introduced into the periphery (or perimeter) of the through-electrode area TA, and may prevent some portions of the insulating layer 114 from being removed.

[0073] Reference Figure 18A and Figure 18B , the method may include: forming an electrode WL and forming an isolation insulating layer WLC and a dummy isolation insulating layer DWLC. Forming the electrode WL may include performing a deposition process, and the electrode WL may be formed in the opening OP. For example, the electrode WL may be formed in a portion of the cell array area CA and a portion of the pad area PA, and the electrode WL may not be formed inside the periphery defined by the vertical guard plate structure FS. Some of the electrodes WL may be formed at the same level as the insulating layer 114. The electrodes WL may be alternately stacked with the mold layer 112, and the electrodes WL and the mold layer 112 may constitute an electrode stack 111. The electrode WL may include W, WN, Ti, TiN, Ta, TaN, or a combination thereof.

[0074] The isolation insulating layer WLC and the dummy isolation insulating layer DWLC may be formed by filling the isolation trench T and the dummy isolation trench DT with the isolation insulating layer WLC and the dummy isolation insulating layer DWLC. The isolation insulating layer WLC and the dummy isolation insulating layer DWLC may vertically pass through the extended conductive layer 43, the support member 44, and the electrode stack 111. The isolation insulating layer WLC may be formed to extend from the cell array area CA to the extension area. The dummy isolation insulating layer DWLC may extend in the same direction as the isolation insulating layer WLC and may be disposed in a portion of the extension area EA. The isolation insulating layer WLC and the dummy isolation insulating layer DWLC may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0075] Return to reference Figure 2A and Figure 2BThe method may include forming a second upper insulating layer 142, a bit line plug 144, a bit line 146, a through electrode 150, and a connecting wire 152. The second upper insulating layer 142 may be formed on the first upper insulating layer 140. The bit line plug 144 may pass through the first upper insulating layer 140 and the second upper insulating layer 142. The bit line 146 may be formed on the second upper insulating layer 142 and may be connected to the bit line plug 144.

[0076] A through electrode 150 may be formed in the through-electrode area TA. The through electrode 150 may vertically pass through the buried insulating layer 46, the electrode stack 111, the interlayer insulating layer 116, the first upper insulating layer 140, and the second upper insulating layer 142, and may be connected to the peripheral circuit wire 32. A connection wire 152 may be formed on the second upper insulating layer 142. The connection wire 152 may be electrically connected to the peripheral circuit wire 32 via the through electrode 150.

[0077] The first upper insulating layer 140 and the second upper insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The bit line plug 144, the bit line 146, the through electrode 150, and the connecting wire 152 may include metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0078] like Figure 17A 、 Figure 17B and Figure 2C As shown in FIG, the vertical guard plate structure FS can limit the horizontal depth of the opening OP by preventing the insulating layer 114 from being etched. In the process of forming the electrode WL, the introduction and exhaust of the source gas and / or the purge gas can be facilitated. Therefore, the electrode WL can be completely filled in the opening OP, and the formation of voids in the electrode WL can be prevented or reduced.

[0079] As is apparent from the above description, according to example embodiments of the present disclosure, a vertical guard plate structure is provided to surround a through-electrode region, thereby preventing or reducing formation of voids in the electrode and bridging of the electrode.

[0080] Although some example embodiments of the present disclosure have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various modifications may be made without departing from the scope of the present disclosure and without changing its basic characteristics. Therefore, the above example embodiments should be viewed in a descriptive sense only and not for the purpose of limitation.

Claims

1. A semiconductor device comprising: a substrate comprising a cell array region and an extension region, wherein the extension region extends from the cell array region and comprises a through-electrode region; an electrode stack located on the substrate, the electrode stack comprising a mold layer and electrodes alternately stacked in the cell array region, and an insulating layer located in the extension region; a vertical structure passing through the electrode stack in the cell array region; as well as a vertical guard plate structure located in the extension region and passing through the electrode stack, wherein in a plan view, the vertical guard plate structure surrounds the through-electrode region; wherein the distance between adjacent vertical guard plate structures in the vertical guard plate structures is smaller than the distance between adjacent vertical structures in the vertical structures; wherein the insulating layer is located within the perimeter defined by the vertical guard plate structure, and the insulating layer is located at the same level as corresponding electrodes of the electrodes, and Wherein, in the horizontal cross-sectional view, the interface where the electrode contacts the insulating layer is located between the vertical guard plate structures.

2. The semiconductor device according to claim 1, wherein The electrode includes a first protrusion that projects between the vertical guard plate structures in the plan view.

3. The semiconductor device according to claim 2, wherein The insulating layer includes a second protrusion that protrudes between the vertical guard plate structures in the plan view.

4. The semiconductor device according to claim 3, wherein The first protrusion contacts the second protrusion between the vertical guard plate structures.

5. The semiconductor device according to claim 2, further comprising: a pair of isolation insulating layers extending in a first horizontal direction and vertically passing through the electrode stack, the pair of isolation insulating layers being spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; as well as a dummy isolation insulating layer extending in the first horizontal direction and spaced apart from each other in the second horizontal direction between the pair of isolation insulating layers, The vertical guard plate structure is spaced apart from the dummy isolation insulating layer in the first horizontal direction, and is located between the pair of isolation insulating layers in the second horizontal direction. The semiconductor device according to claim 5 , wherein: A first maximum distance from the dummy isolation insulating layer to the first protrusion of the electrode along the first horizontal direction is less than ½ of a distance between a pair of adjacent dummy isolation insulating layers.

7. The semiconductor device according to claim 5, wherein A second maximum distance from the pair of isolation insulating layers to the first protrusion of the electrode along the second horizontal direction is less than ½ of a distance between an adjacent pair of the dummy isolation insulating layers.

8. The semiconductor device according to claim 5, wherein The vertical guard plate structure has a tapered shape in a vertical cross-sectional view.

9. The semiconductor device according to claim 8, wherein A maximum distance from the dummy isolation insulating layer along the first horizontal direction to the first protrusion of the lowermost electrode among the electrodes is less than ½ of a distance between a pair of adjacent dummy isolation insulating layers.

10. The semiconductor device according to claim 1, wherein The distance between adjacent vertical guard plate structures is less than 1 / 2 of the distance between adjacent vertical structures.

11. The semiconductor device according to claim 1, wherein The vertical guard plate structures are in contact with each other.

12. The semiconductor device according to claim 1, further comprising: A dummy vertical structure is provided, which passes through the electrode stack in the extension region.

13. The semiconductor device according to claim 1, further comprising: a peripheral circuit structure located between the substrate and the electrode stack; as well as A through-electrode vertically passes through the electrode stack and is connected to the peripheral circuit structure in the through-electrode region.

14. A semiconductor device comprising: a substrate comprising a cell array region and an extension region, wherein the extension region extends from the cell array region and comprises a through-electrode region, wherein the through-electrode region comprises a through-electrode; an electrode stack located on the substrate, the electrode stack comprising alternately stacked molding layers and electrodes; a vertical structure passing through the electrode stack in the cell array region; as well as an inner vertical guard plate structure and an outer vertical guard plate structure located inside the extension region and passing through the electrode stack, the inner vertical guard plate structure and the outer vertical guard plate structure surrounding the through-electrode region in plan view, wherein the distance between each of the inner vertical guard plate structures and a corresponding one of the outer vertical guard plate structures is smaller than the distance between each of the inner vertical guard plate structures and a corresponding one of the through electrodes, and Wherein, the distance between each of the inner vertical guard plate structures and a corresponding one of the outer vertical guard plate structures is smaller than the distance between adjacent ones of the vertical structures.

15. The semiconductor device according to claim 14, further comprising: an insulating layer, each located at the same level as a corresponding one of the electrodes, the insulating layer being located inside a perimeter defined by the inner and outer vertical guard plate structures and in contact with the electrodes and the inner and outer vertical guard plate structures, wherein the boundary surface between the electrode and the insulating layer is located between the inner vertical guard plate structure and the outer vertical guard plate structure in the plan view, and Wherein, the electrode includes a first protrusion, and the first protrusion is configured to contact the inner vertical guard plate structure and the outer vertical guard plate structure in the plan view.

16. The semiconductor device according to claim 14, wherein The inner vertical guard plate structures are spaced apart from each other along the periphery of the through-electrode region, and The outer vertical guard plate structures are spaced apart from each other along a periphery of the through-electrode region.

17. The semiconductor device according to claim 14, wherein A distance between one of the inner vertical guard plate structures and an outer vertical guard plate structure adjacent to the one inner vertical guard plate structure among the outer vertical guard plate structures is less than 1 / 2 of a distance between the vertical structures.

18. The semiconductor device according to claim 14, wherein The outer vertical guard plate structure has a diameter greater than a diameter of the inner vertical guard plate structure.

19. A semiconductor device comprising: a substrate comprising a cell array region and an extension region, wherein the extension region extends from the cell array region and comprises a through-electrode region; an electrode stack located on the substrate, the electrode stack comprising alternately stacked molding layers and electrodes; a peripheral circuit structure located between the substrate and the electrode stack; a lower conductive layer, located on the peripheral circuit structure; a connecting conductive layer located on the lower conductive layer in the cell array region; a connecting mold layer located on the lower conductive layer in the extension region; a support member located on the connecting conductive layer and the connecting mold layer, and having the electrode stack member on the support member; a buried insulating layer located in the through-electrode region and passing through the lower conductive layer, the connection mold layer and the support member; a vertical structure passing through the electrode stack in the cell array region; a vertical guard plate structure located in the extension region while passing through the electrode stack, the vertical guard plate structure surrounding the through-electrode region in a plan view; as well as an insulating layer located inside the perimeter defined by the vertical guard plate structure and located at the same level as corresponding ones of the electrodes, Wherein, the electrode includes a first protrusion, and the first protrusion is configured to contact the vertical guard plate structure in the plan view.

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