A trench-gate type super barrier rectifier device with low forward voltage drop

Abstract

The present invention discloses a trench-gate type super barrier rectifier device with a low on-state voltage drop, which includes a back metal layer, a first-conductivity-type semiconductor substrate, a first-conductivity-type semiconductor drift region, a gate oxide layer, a polysilicon gate, a first-conductivity-type semiconductor heavily doped region, a second-conductivity-type semiconductor body region, a first-conductivity-type semiconductor heavily doped source region, and a front metal layer. By creatively designing the structural layout of the gate oxide layer, the polysilicon gate, the second-conductivity-type semiconductor body region, and the first-conductivity-type semiconductor heavily doped source region, and through the setting and arrangement of the first-conductivity-type semiconductor heavily doped region, the present invention can form a multi-channel current path distribution. Moreover, due to the first-conductivity-type semiconductor heavily doped region, the voltage of the initial current path is lower and the stability is high, thereby greatly reducing the forward on-state voltage drop and improving the forward over-current capacity of the diode. The process of the present invention is relatively easy to prepare and has strong practicability.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and specifically to a trench-gate type super-barrier rectifier device with a low on-state voltage drop. Background Art

[0002] Rectifiers are widely used in the electronics industry. Traditional PN junction diodes have a large on-state voltage drop and a long reverse recovery time. Schottky diodes have a small forward voltage drop, but a large reverse leakage current. Existing super-barrier rectifiers use a rectifier diode and a MOS transistor integrated in parallel between the anode and the cathode to form a lower forward conduction voltage. However, due to the overall presence of a PN junction, its conduction voltage is still relatively large. Summary of the Invention

[0003] The purpose of the present invention is to provide a trench-gate type super-barrier rectifier device with a low on-state voltage drop, providing a rectifier structure with a lower voltage conduction to overcome the deficiencies of the prior art.

[0004] To achieve the above purpose, the present invention provides the following technical solutions:

[0005] A trench-gate type super-barrier rectifier device with a low on-state voltage drop, comprising:

[0006] A back metal layer;

[0007] A first-conductivity-type semiconductor substrate; the first-conductivity-type semiconductor substrate covers the back metal layer;

[0008] A first-conductivity-type semiconductor drift region; the first-conductivity-type semiconductor drift region covers the first-conductivity-type semiconductor substrate;

[0009] A gate oxide layer; the gate oxide layer covers partial surfaces on both sides of the upper part of the first-conductivity-type semiconductor drift region;

[0010] A polysilicon gate; the polysilicon gate covers the corresponding gate oxide layer;

[0011] A first-conductivity-type semiconductor heavily doped region; the first-conductivity-type semiconductor heavily doped region covers partial surfaces on the first-conductivity-type semiconductor drift region;

[0012] A second-conductivity-type semiconductor body region; the second-conductivity-type semiconductor body region covers partial surfaces on the first-conductivity-type semiconductor drift region, and the second-conductivity-type semiconductor body region is located on both sides of the first-conductivity-type semiconductor heavily doped region, and the part of the first-conductivity-type semiconductor heavily doped region covers the second-conductivity-type semiconductor body region;

[0013] A heavily doped source region of a semiconductor of the first conductivity type; a portion of the surface of the heavily doped source region of the semiconductor of the first conductivity type that covers a corresponding semiconductor body region of the second conductivity type;

[0014] A front metal layer; the front metal layer covers a gate oxide layer, a polysilicon gate, a semiconductor body region of the second conductivity type, a heavily doped source region of a semiconductor of the first conductivity type, and a heavily doped region of a semiconductor of the first conductivity type.

[0015] As a further aspect of the present invention: the gate oxide layer and the polysilicon gate are of a trench gate structure.

[0016] As a further aspect of the present invention: the junction depth of the semiconductor body region of the second conductivity type should be greater than the junction depth of the heavily doped region of the semiconductor of the first conductivity type.

[0017] As a further aspect of the present invention: the heavily doped source region of the semiconductor of the first conductivity type and the front metal layer are in ohmic contact.

[0018] As a further aspect of the present invention: the heavily doped region of the semiconductor of the first conductivity type and the front metal layer are in ohmic contact or Schottky contact.

[0019] As a further aspect of the present invention: the depletion layer formed by the semiconductor body region of the second conductivity type and the polysilicon gate and the semiconductor drift region of the first conductivity type at zero voltage completely surrounds the heavily doped region of the semiconductor of the first conductivity type.

[0020] Compared with the prior art, the beneficial effects of the present invention are: through the creative design of the structural layout of the gate oxide layer, the polysilicon gate, the semiconductor body region of the second conductivity type, and the heavily doped source region of the semiconductor of the first conductivity type, and then through the setting of the heavily doped region of the semiconductor of the first conductivity type and the layout, the present invention can form multiple current path distributions, and due to the heavily doped region of the semiconductor of the first conductivity type, the conduction voltage of the initial current path is lower and the stability is high, thereby greatly reducing the forward conduction voltage drop and improving the forward overcurrent capacity of the diode. The structure of the present invention is simple, the process preparation is relatively easy, and the practicability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of the present invention;

[0022] Figure 2 It is a structural schematic diagram of the current path distribution in the present invention;

[0023] Figure 3 It is a distribution schematic diagram of the depletion layer boundary in the present invention.

[0024] In the figure: 1. Back metal layer; 2. First-conductivity-type semiconductor substrate; 3. First-conductivity-type semiconductor drift region; 4. Gate oxide layer; 5. Polysilicon gate; 6. Second-conductivity-type semiconductor body region; 7. First-conductivity-type semiconductor heavily doped source region; 8. First-conductivity-type semiconductor heavily doped region; 9. Front metal layer. Detailed implementation mode

[0025] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0026] Please refer to Figure 1 , the present invention provides a technical solution: a trench-gate type super-barrier rectifier device with a low on-state voltage drop, including:

[0027] Back metal layer 1;

[0028] First-conductivity-type semiconductor substrate 2; the first-conductivity-type semiconductor substrate 2 covers the back metal layer 1;

[0029] First-conductivity-type semiconductor drift region 3; the first-conductivity-type semiconductor drift region 3 covers the first-conductivity-type semiconductor substrate 2;

[0030] Gate oxide layer 4; the gate oxide layer 4 covers partial surfaces on both sides of the upper part of the first-conductivity-type semiconductor drift region 3;

[0031] Polysilicon gate 5; the polysilicon gate 5 covers the corresponding gate oxide layer 4;

[0032] First-conductivity-type semiconductor heavily doped region 8; the first-conductivity-type semiconductor heavily doped region 8 covers partial surfaces on the first-conductivity-type semiconductor drift region 3;

[0033] Second-conductivity-type semiconductor body region 6; the second-conductivity-type semiconductor body region 6 covers partial surfaces on the first-conductivity-type semiconductor drift region 3, and the second-conductivity-type semiconductor body region 6 is located on both sides of the first-conductivity-type semiconductor heavily doped region 8, and the first-conductivity-type semiconductor heavily doped region 8 covers partial surfaces on the second-conductivity-type semiconductor body region 6;

[0034] First-conductivity-type semiconductor heavily doped source region 7; the first-conductivity-type semiconductor heavily doped source region 7 covers partial surfaces on the corresponding second-conductivity-type semiconductor body region 6;

[0035] The front metal layer 9; the front metal layer 9 covers the gate oxide layer 4, the polysilicon gate 5, the semiconductor body region 6 of the second conductivity type, the heavily doped source region 7 of the semiconductor of the first conductivity type, and the heavily doped region 8 of the semiconductor of the first conductivity type.

[0036] Wherein the gate oxide layer 4 and the polysilicon gate 5 are of a trench gate structure; the junction depth of the semiconductor body region 6 of the second conductivity type should be greater than the junction depth of the heavily doped region 8 of the semiconductor of the first conductivity type; the heavily doped source region 7 of the semiconductor of the first conductivity type and the front metal layer 9 are in ohmic contact; the heavily doped region 8 of the semiconductor of the first conductivity type and the front metal layer 9 are in ohmic contact or Schottky contact; the depletion layer formed between the semiconductor body region 6 of the second conductivity type and the polysilicon gate 5 and the semiconductor drift region 3 of the first conductivity type at zero voltage completely surrounds the heavily doped region 8 of the semiconductor of the first conductivity type.

[0037] Working principle: The traditional PN junction diode has a large conduction voltage drop, and the Schottky diode has a large reverse leakage current.

[0038] In this embodiment, the semiconductor of the first conductivity type is taken as an N-type semiconductor, and the semiconductor of the second conductivity type is taken as a P-type semiconductor as an example; the front metal layer 9 is the anode of the diode, and the back metal layer 1 is the cathode of the diode.

[0039] When conducting forwardly, in the small current state, the current flows from the anode through the N-type heavily doped region 8 in ohmic contact or Schottky contact, into the drift region 3, and out from the cathode 1, as Figure 2 shown by path 1 in the figure. This current path has no PN junction, and a lower conduction voltage drop can be obtained; when the current is larger, there is a voltage difference between the polysilicon gate 5 and the P-type semiconductor body region 6. Due to the body effect, an inversion layer channel is formed on the side of the P-type semiconductor body region 6, providing another current path. The current flows into the drift region 3 through the N-type source region 7 and the inversion layer channel, as Figure 2 shown by path 2 in the figure; when the current further increases, the PN junction between the P-type body region 6 and the N-type drift region 3 conducts, further increasing the overcurrent capacity, as Figure 2 shown by path 3 in the figure.

[0040] When withstanding reverse voltage, a depletion layer withstand voltage is formed between the P-type body region 6 and the polysilicon gate 5 and the N-type drift region 3, as Figure 3 shown.

[0041] Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A trench-gate type super-barrier rectifier device with a low on-state voltage drop, characterized in that Comprising: Back metal layer (1); First-conductivity-type semiconductor substrate (2); the first-conductivity-type semiconductor substrate (2) covers the back metal layer (1); First-conductivity-type semiconductor drift region (3); the first-conductivity-type semiconductor drift region (3) covers the first-conductivity-type semiconductor substrate (2); Gate oxide layer (4); the gate oxide layer (4) covers partial surfaces on both upper sides of the first-conductivity-type semiconductor drift region (3); Polysilicon gate (5); the polysilicon gate (5) covers the corresponding gate oxide layer (4); First-conductivity-type semiconductor heavily doped region (8); the first-conductivity-type semiconductor heavily doped region (8) covers partial surfaces on the first-conductivity-type semiconductor drift region (3); Second-conductivity-type semiconductor body region (6); the second-conductivity-type semiconductor body region (6) covers partial surfaces on the first-conductivity-type semiconductor drift region (3), and the second-conductivity-type semiconductor body region (6) is located on both sides of the first-conductivity-type semiconductor heavily doped region (8), and the part of the first-conductivity-type semiconductor heavily doped region (8) covers the second-conductivity-type semiconductor body region (6); First-conductivity-type semiconductor heavily doped source region (7); the first-conductivity-type semiconductor heavily doped source region (7) covers partial surfaces on the corresponding second-conductivity-type semiconductor body region (6); Front metal layer (9); the front metal layer (9) covers the gate oxide layer (4), the polysilicon gate (5), the second-conductivity-type semiconductor body region (6), the first-conductivity-type semiconductor heavily doped source region (7), and the first-conductivity-type semiconductor heavily doped region (8); The gate oxide layer (4) and the polysilicon gate (5) are of a trench gate structure; The depletion layer formed by the second-conductivity-type semiconductor body region (6) and the polysilicon gate (5) and the first-conductivity-type semiconductor drift region (3) at zero voltage completely surrounds the first-conductivity-type semiconductor heavily doped region (8).

2. The trench-gate type super-barrier rectifier device with a low on-state voltage drop according to claim 1, characterized in that: The junction depth of the second-conductivity-type semiconductor body region (6) should be greater than the junction depth of the first-conductivity-type semiconductor heavily doped region (8).

3. The super barrier rectifier device with low on-state voltage drop according to claim 1, characterized in that: The first-conductivity-type semiconductor heavily doped source region (7) and the front metal layer (9) are in ohmic contact.

4. The super barrier rectifier device with a low on-state voltage drop according to claim 1, wherein: The first-conductivity-type semiconductor heavily doped region (8) and the front metal layer (9) are in ohmic contact or Schottky contact.

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