A selective contact area buried type solar cell and a back contact structure thereof

Abstract

The application belongs to the technical field of solar cells, and provides a selective contact area buried type solar cell and a back contact structure thereof, the back contact structure comprising: grooves arranged at intervals on the back of a silicon substrate; a first dielectric layer arranged on the back of the silicon substrate; a first doped region arranged on the first dielectric layer and in the grooves; a second doped region arranged on the first dielectric layer and outside the grooves; a second dielectric layer arranged between the first doped region and the second doped region, the second dielectric layer being at least one layer; and a conductive layer arranged on the first doped region and the second doped region. The back contact structure provided in the application solves the problems of high control requirement for groove width and poor passivation effect in the prior art.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a selective contact area buried solar cell and a back contact structure thereof. Background Art

[0002] In crystalline silicon solar cells, the efficiency loss of the cell can be divided into two aspects: electrical loss and optical loss. The important components of electrical loss are recombination loss and resistance loss caused by metal-semiconductor contact, while the important component of optical loss is the obstruction of the metal grid line on the light-receiving surface.

[0003] The passivated metal contact structure exhibits remarkable electrical properties, achieving both low contact resistivity and low surface recombination. This structure consists of an ultra-thin tunneling oxide layer and an N-type or P-type doped polysilicon layer. Because the doped polysilicon layer's absorption of light is parasitic and therefore does not contribute to the photocurrent, the passivated metal contact structure is often used on the back side of the cell, completely eliminating metal grid lines from obstructing the front surface. Solar radiation received by the solar cell generates electrons and holes, which migrate to the doped polysilicon layer, generating a voltage difference across the doped polysilicon layer.

[0004] The existing P-type doped polysilicon layer and N-type doped polysilicon layer are deposited directly on the back of the silicon wafer. However, when they are connected together without any barrier, leakage and other undesirable phenomena will occur. Therefore, in order to solve the above-mentioned problem caused by no barrier, a very narrow groove is opened between the P-type doped polysilicon layer and the N-type doped polysilicon layer to separate the P-type doped polysilicon layer and the N-type doped polysilicon layer, thereby avoiding leakage and reducing the open circuit voltage of the battery. However, the existing groove is prepared by laser drilling or wet etching. At this time, since the existing groove width is tens of microns, the width control requirements are high, making the preparation difficult and only using a single layer of dielectric layer for passivation. However, the use of a single layer of dielectric layer for passivation has a poor passivation effect and the resulting internal back reflection effect is poor. Summary of the Invention

[0005] An object of the embodiments of the present invention is to provide a back contact structure for a solar cell, aiming to solve the existing problems of high requirements for trench width control and poor passivation effect.

[0006] The embodiment of the present invention is implemented as follows: a back contact structure of a solar cell, comprising:

[0007] grooves arranged at intervals on the back side of the silicon substrate;

[0008] a first dielectric layer disposed on the back side of the silicon substrate;

[0009] a first doped region disposed on the first dielectric layer and within the groove;

[0010] a second doped region disposed on the first dielectric layer and outside the groove;

[0011] a second dielectric layer disposed between the first doped region and the second doped region, wherein the second dielectric layer is at least one layer; and

[0012] A conductive layer is disposed on the first doped region and the second doped region.

[0013] Furthermore, the first doped region is a P-type doped region, and the second doped region is an N-type doped region; or

[0014] The first doping region is an N-type doping region, and the second doping region is a P-type doping region.

[0015] Furthermore, the second doped region is provided in a partial region outside the groove.

[0016] Furthermore, the total thickness of the first dielectric layer and the first doped region disposed in the groove is less than or equal to the depth of the groove.

[0017] Furthermore, the total thickness of the first dielectric layer and the first doped region disposed in the groove is greater than the depth of the groove.

[0018] Furthermore, the first doped region and the second doped region include doped polysilicon, doped silicon carbide, or doped amorphous silicon.

[0019] Furthermore, the first dielectric layer is a combination of one or more of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer.

[0020] Furthermore, the second dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0021] Furthermore, the second dielectric layer covers the region between the first doping region and the second doping region, or extends to cover the first doping region and / or the second doping region.

[0022] Furthermore, the back side of the silicon substrate located between the first doping region and the second doping region has a rough texture structure.

[0023] Furthermore, the width of the P-type doping region is 300-600 um, the width of the N-type doping region is 100-500 um, and the depth of the groove is 0.01-10 um.

[0024] Furthermore, a horizontal distance between the first doping region and the second doping region is 0-500 um.

[0025] Furthermore, the first dielectric layer covers the first doped region and the second doped region or covers the entire back side of the silicon substrate.

[0026] Furthermore, a third doping region is provided in the silicon substrate located between the first doping region and the second doping region.

[0027] Furthermore, the first dielectric layer is connected to the bottom wall and side walls of the groove.

[0028] Furthermore, the first dielectric layer is connected to the bottom wall of the groove, and the second dielectric layer is also connected to the sidewall of the groove.

[0029] Furthermore, the groove is arc-shaped, trapezoidal, or square.

[0030] Furthermore, the thickness of the first dielectric layer is 1-20 nm, and the total thickness of the first dielectric layer and the first doped region or the second doped region is greater than 20 nm.

[0031] Furthermore, the doped silicon carbide includes doped hydrogenated silicon carbide.

[0032] Furthermore, the first dielectric layer is a tunneling oxide layer and an intrinsic silicon carbide layer.

[0033] Furthermore, the tunneling oxide layer is composed of one or more layers of a silicon oxide layer and an aluminum oxide layer.

[0034] Furthermore, the intrinsic silicon carbide layer in the first dielectric layer includes an intrinsic hydrogenated silicon carbide layer.

[0035] Furthermore, the second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

[0036] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

[0037] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer is composed of at least one first intrinsic silicon carbide film with different refractive indexes.

[0038] Furthermore, the refractive index of each layer of the first intrinsic silicon carbide film decreases sequentially from the back side of the silicon substrate toward the outside.

[0039] Furthermore, the outer layer of the second dielectric layer is further provided with a magnesium fluoride layer.

[0040] Furthermore, the conductive layer is a TCO transparent conductive film and / or a metal electrode.

[0041] Furthermore, the metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode or a silver-clad copper electrode.

[0042] Furthermore, the copper electrode is an electroplated copper prepared by an electroplating process or a copper electrode prepared by physical vapor deposition.

[0043] Furthermore, the first dielectric layer corresponding to the first doped region and the first dielectric layer corresponding to the second doped region are the same as or different from each other.

[0044] Furthermore, the first doped region extends to a portion of the area outside the groove and is not connected to the adjacent second doped region.

[0045] Another embodiment of the present invention is also directed to providing a selective contact region buried solar cell, comprising:

[0046] Silicon substrate;

[0047] A back contact structure as described above provided on the back side of the silicon substrate; and

[0048] A third dielectric layer is provided on the front surface of the silicon substrate.

[0049] Furthermore, the third dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0050] Furthermore, the third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

[0051] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

[0052] Furthermore, the intrinsic silicon carbide layer in the third dielectric layer is composed of at least one second intrinsic silicon carbide film with a different refractive index.

[0053] Furthermore, the refractive index of each layer of the second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate toward the outside.

[0054] Furthermore, the outer layer of the third dielectric layer is further provided with a magnesium fluoride layer.

[0055] Furthermore, an electric field layer or a floating junction is provided between the front surface of the silicon substrate and the third dielectric layer.

[0056] Another embodiment of the present invention aims to provide a battery assembly, which includes the selective contact area buried solar cell described above.

[0057] Another embodiment of the present invention aims to provide a photovoltaic system, which includes the battery assembly described above.

[0058] Another embodiment of the present invention is to provide a method for manufacturing a selective contact region buried solar cell, characterized in that the method comprises:

[0059] A plurality of grooves are formed on the back side of the silicon substrate;

[0060] forming a first dielectric layer on the back side of the silicon substrate;

[0061] Prepare a first doped region and a second doped region inside and outside each of the grooves respectively;

[0062] forming a second dielectric layer and a third dielectric layer on the back and front sides of the silicon substrate respectively;

[0063] A conductive layer is formed on the first doping region and the second doping region.

[0064] Furthermore, the step of preparing the first doped region and the second doped region inside and outside each of the grooves respectively includes:

[0065] depositing intrinsic amorphous silicon or intrinsic silicon carbide inside and outside each groove;

[0066] Doping with different doping types is performed alternately inside and outside each groove;

[0067] High-temperature crystallization treatment is performed to convert intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region arranged in the groove and a second doped region arranged outside the groove.

[0068] Furthermore, the step of preparing the first doped region and the second doped region inside and outside each of the grooves respectively includes:

[0069] depositing intrinsic amorphous silicon or intrinsic silicon carbide inside and outside each groove;

[0070] Different types of diffusion are alternately performed inside and outside each groove through a mask to convert intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, thereby obtaining a first doped region arranged inside the groove and a second doped region arranged outside the groove.

[0071] Furthermore, the step of preparing the first doped region and the second doped region inside and outside each of the grooves respectively includes:

[0072] Alternately depositing doped amorphous silicon or doped amorphous silicon carbide of different doping types inside and outside each groove;

[0073] High-temperature crystallization treatment is performed to convert the doped amorphous silicon or doped amorphous silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region arranged in the groove and a second doped region arranged outside the groove.

[0074] Furthermore, the step of alternately performing doping of different doping types inside and outside each groove includes:

[0075] Alternately implanting first type ions and second type ions into the inside and outside of each groove; or

[0076] Alternately depositing a first type dopant source and a second type dopant source inside and outside each groove; or

[0077] The first type source gas and the second type source gas are alternately introduced into the inside and outside of each groove for doping.

[0078] The back contact structure provided by the embodiment of the present invention is configured by arranging grooves at intervals on the back side of a silicon substrate, and arranging a first doped region in each groove and a second doped region outside each groove, so that the first doped region in the groove and the second doped region outside the groove are blocked by the silicon substrate not covering the first doped region in the groove or by the silicon substrate not covering the second doped region outside the groove. The width control requirements of the arranged grooves are looser than those of existing grooves, and the preparation thereof is easier than that of existing grooves. Moreover, when depositing the first dielectric layer and the first doped region in the grooves, the deposition effect is better. At the same time, due to the arrangement of the grooves, the first dielectric layer and the bottom wall of the grooves are closely connected. The bottom wall and side wall of the groove are in contact with each other, so the carriers generated in the silicon substrate can also be easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the longitudinal and lateral selective transport of carriers can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove; since the second dielectric layer is set as at least one layer, the back side of the silicon substrate is multi-layered passivated by at least one layer of the second dielectric layer, thereby bringing better passivation effect and improving internal back reflection, thereby bringing better passivation effect and internal back reflection effect, solving the existing problems of high requirements for groove width control and poor passivation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figures 1 to 10 1 is a schematic structural diagram of various implementations of a selective contact region buried solar cell provided by one embodiment of the present invention;

[0080] Figure 11 This is a flow chart of a method for manufacturing a selective contact region buried solar cell provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0082] In the present invention, unless otherwise expressly specified or limited, the terms "installed," "connected," "connected," "fixed," and the like should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0083] The present invention arranges grooves at intervals on the back side of a silicon substrate, arranges a first doped region in each groove and arranges a second doped region outside each groove, so that the first doped region in the groove and the second doped region outside the groove are blocked by the silicon substrate in the groove that does not cover the first doped region or by the silicon substrate outside the groove that does not cover the second doped region. The width control requirements of the arranged grooves are looser than those of existing grooves, and the preparation is easier than that of existing grooves. When depositing the first dielectric layer and the first doped region in the grooves, the deposition effect is better. At the same time, due to the arrangement of the grooves, the first dielectric layer is in contact with both the bottom wall and the sidewall of the grooves. Therefore, the carriers generated in the silicon substrate can also be easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the longitudinal and lateral selective transport of carriers can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove; since the second dielectric layer is set as at least one layer, the back side of the silicon substrate is multi-layered passivated by at least one layer of the second dielectric layer, thereby bringing better passivation effect and improving internal back reflection, thereby bringing better passivation effect and internal back reflection effect, solving the existing problems of high requirements for groove width control and poor passivation effect.

[0084] Example 1

[0085] The first embodiment of the present invention provides a back contact structure of a solar cell. For the sake of convenience, only the parts related to the embodiment of the present invention are shown. Figures 1-10 As shown, the back contact structure of the solar cell provided by the embodiment of the present invention includes:

[0086] Grooves are arranged at intervals on the back side of the silicon substrate 10;

[0087] A first dielectric layer 20 is provided on the back side of the silicon substrate 10;

[0088] A first doped region 30 disposed on the first dielectric layer 20 and within the groove;

[0089] A second doped region 40 disposed on the first dielectric layer 20 and outside the groove;

[0090] a second dielectric layer 50 disposed between the first doped region 30 and the second doped region 40 , wherein the second dielectric layer 50 is at least one layer and has a refractive index that decreases from the back surface of the silicon substrate 10 outward; and

[0091] A conductive layer 60 is disposed on the first doping region 30 and the second doping region 40 .

[0092] In one embodiment of the present invention, the silicon substrate 10 has a front side facing the sun during normal operation and a back side opposite the front side. The front side is the light-receiving side. The back side is located on the other side of the silicon substrate 10 relative to the front side. In other words, the front side and the back side are located on different and opposite sides of the silicon substrate 10. In this embodiment, the silicon substrate 10 is an N-type silicon wafer. It will be understood that in other embodiments, the silicon substrate 10 may also be other silicon wafers. The back side of the silicon substrate 10 is provided with grooves spaced apart. The grooves can be formed by laser ablation or by a combination of wet and dry etching using a mask (such as a hard mask, silicon oxide mask, silicon nitride mask, or photoresist mask). In this case, the grooves spaced apart on the back side of the silicon substrate 10 result in the region between two adjacent grooves of the silicon substrate 10 being generally in the shape of a convex platform. Therefore, the back side pattern of the silicon substrate 10 generally exhibits an alternating arrangement of grooves and convex platforms.

[0093] Furthermore, in one embodiment of the present invention, the first dielectric layer 20 is located on the back side of the silicon substrate 10 and covers at least the first doped region 30 and the second doped region 40. In a specific implementation, the first dielectric layer 20 may only cover the first doped region 30 and the second doped region 40, or may also cover the entire back side of the silicon substrate 10. In one embodiment of the present invention, referring to Figure 1 As shown, the first dielectric layer 20 only covers the first doping region 30 and the second doping region 40. At this time, the back surface of the silicon substrate 10 located between the first doping region 30 and the second doping region 40 is not covered by the first dielectric layer 20. In another embodiment of the present invention, referring to Figure 2 As shown, the first dielectric layer 20 covers the entire back side of the silicon substrate 10, that is, the first dielectric layer 20 covers the entire back side formed by the grooves and bosses of the silicon substrate 10. It should be noted that, Figure 1 and Figure 2 As shown, when the first dielectric layer 20 covers the first doped region 30 , the first dielectric layer 20 is connected to the bottom wall and sidewalls of the groove.

[0094] Furthermore, in one embodiment of the present invention, the first doped region 30 is a P-type doped region, and the second doped region 40 is an N-type doped region; or the first doped region 30 is an N-type doped region, and the second doped region 40 is a P-type doped region. That is, the first dielectric layer 20 and the P-type doped region can be disposed within the groove, and the first dielectric layer 20 and the N-type doped region can be disposed outside the groove; or the first dielectric layer 20 and the N-type doped region can be disposed within the groove, and the first dielectric layer 20 and the P-type doped region can be disposed outside the groove, so that the first dielectric layer 20 and the first doped region 30, and the first dielectric layer 20 and the second doped region 40 are alternately disposed inside and outside the groove. In this case, the first doped region 30 inside the groove and the second doped region 40 outside the groove are blocked by the silicon substrate inside the groove that does not cover the first doped region 30 or by the silicon substrate outside the groove that does not cover the second doped region 40.

[0095] Among them, the first dielectric layer 20 is located between the silicon substrate 10 and the first doped region 30 set in the groove and the second doped region 40 set outside the groove, and is used as a tunneling structure; and the first dielectric layer 20 and the highly doped first doped region 30 or the second doped region 40 connected and covered therewith together form a passivation contact structure. The passivation contact structure provides good surface passivation for the back side of the silicon substrate 10. At the same time, generally speaking, the first dielectric layer 20 has a sufficiently thin thickness, in which one type of carrier is selectively transmitted through the tunneling principle, while the other type of carrier is difficult to tunnel through the first dielectric layer 20 due to the existence of potential barriers and field effects in the doped region. Therefore, the first dielectric layer 20 can allow one type of carrier to tunnel into the doped region while blocking the other type of carrier from passing through, causing recombination, which can significantly reduce the recombination at the interface, so that the solar cell has a higher open circuit voltage and short circuit current, thereby increasing the photoelectric conversion efficiency. At the same time, Figures 1 to 10 As shown, the surface where the silicon substrate 10 contacts the first dielectric layer 20 forms a plurality of inner diffusion regions corresponding to the first doped regions 30 or the second doped regions 40. Furthermore, in this embodiment, due to the provision of the groove, the first dielectric layer 20 contacts both the bottom and side walls of the groove. Therefore, carriers generated in the silicon substrate 10 are easily separated by the first dielectric layer 20 on the side walls of the groove and selectively collected into the corresponding first doped regions 30, thereby facilitating multi-dimensional collection of carriers in the bottom and side walls of the groove.

[0096] Furthermore, in one embodiment of the present invention, the first dielectric layer 20 is preferably a combination of one or more of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer. As some examples of the present invention, for example, the first dielectric layer 20 can be a tunneling oxide layer of a single material, a combination of a tunneling oxide layer and an intrinsic amorphous silicon layer of multiple materials, or a combination of multiple layers of intrinsic amorphous silicon with different refractive indices of a single material. It can be understood that the specific structural arrangement of the first dielectric layer 20 includes but is not limited to the several methods listed above. The first dielectric layer 20 is configured accordingly according to actual usage needs and is not specifically limited here.

[0097] In a preferred embodiment of the present invention, the first dielectric layer 20 is preferably a tunneling oxide layer and an intrinsic silicon carbide layer. In this case, the tunneling oxide layer and the intrinsic silicon carbide layer are arranged sequentially from the silicon substrate 10 outward, with the tunneling oxide layer contacting the back surface of the silicon substrate 10, and the intrinsic silicon carbide layer contacting the first doped region 30 or the second doped region 40. Furthermore, the tunneling oxide layer is preferably composed of one or more layers of a silicon oxide layer and an aluminum oxide layer; therefore, the first dielectric layer 20 can also be a combination of a silicon oxide layer and an aluminum oxide layer in the tunneling oxide layer. The intrinsic silicon carbide layer in the first dielectric layer 20 includes an intrinsic hydrogenated silicon carbide layer. In this case, the tunneling oxide layer and the intrinsic silicon carbide layer reduce the interface state density between the silicon substrate 10 and the first doped region 30 and the second doped region 40 through chemical passivation. For example, hydrogen in the intrinsic hydrogenated silicon carbide layer enters the silicon substrate 10 under the action of the diffusion mechanism and thermal effect, neutralizing the dangling bonds on the back side of the silicon substrate 10 and passivating the defects on the back side of the silicon substrate 10, thereby transferring the energy band in the band gap into the valence band or the conduction band, thereby increasing the probability of carriers passing through the first dielectric layer 20 into the first doped region 30 or the second doped region 40.

[0098] Generally speaking, as some specific examples of the present invention, when used specifically, the first dielectric layer 20 preferably adopts a 1-2nm silicon oxide layer and a 2-5nm intrinsic silicon carbide layer. Compared with using only a silicon oxide layer as a tunneling structure, the intrinsic silicon carbide layer can also provide an additional hydrogen passivation effect, which increases the preparation process window of the tunneling structure without affecting the tunneling effect; of course, a 1-2nm silicon oxide layer, or a 1nm silicon oxide layer and a 1nm aluminum oxide layer, or 2 or more layers of intrinsic amorphous silicon layers with different refractive indices can also be directly used. It can be understood that the specific structural arrangement of the first dielectric layer 20 includes but is not limited to the several specific examples listed above. In addition, the first dielectric layer 20 can also be an intrinsic microcrystalline silicon layer, an intrinsic microcrystalline silicon oxide layer, an intrinsic amorphous silicon oxide layer, etc. Among them, as Figures 1-10As shown, it only shows that the first dielectric layer 20 is a one-layer structure. It can be understood that the specific structure of the first dielectric layer 20 is set according to actual needs and is not completely in accordance with the figures shown in the specification.

[0099] It should be noted that when the first dielectric layer 20 only covers the first doped region 30 and the second doped region 40, since each first dielectric layer 20 is separated from each other, the structure of the first dielectric layer 20 disposed on the first doped region 30 and the second doped region 40 can be the same or different. Specifically, the first dielectric layer 20 corresponding to the first doped region 30 and the first dielectric layer 20 corresponding to the second doped region 40 can be the same or different. For example, the first dielectric layer 20 can both be a silicon oxide layer and an intrinsic silicon carbide layer. Alternatively, the first dielectric layer 20 in the groove where the first doped region 30 is disposed can be a silicon oxide layer and an intrinsic silicon carbide layer, and the first dielectric layer 20 in the boss where the second doped region 40 is disposed can be an aluminum oxide layer and an intrinsic silicon carbide layer, etc. The film structure of the first dielectric layer 20 on each first doped region 30 and the second doped region 40 can be set accordingly according to actual use needs and is not specifically limited here.

[0100] Furthermore, in one embodiment of the present invention, the first doped region 30 and the second doped region 40 are respectively arranged inside and outside each groove, and the first doped region 30 and the second doped region 40 preferably include doped polysilicon, doped silicon carbide, or doped amorphous silicon; wherein the doped silicon carbide may include doped hydrogenated silicon carbide, and the doped hydrogenated silicon carbide is specifically by adding hydrogen when depositing silicon carbide. It should be noted that when the first dielectric layer 20 is the silicon oxide layer and the intrinsic silicon carbide layer described above, the first doped region 30 and the second doped region 40 are specifically doped silicon carbide. When the first dielectric layer 20 is the silicon oxide layer or other combination described above, the first doped region 30 and the second doped region 40 can be doped polysilicon, etc. When the first dielectric layer 20 is the intrinsic amorphous silicon layer described above, the first doped region 30 and the second doped region 40 are specifically doped amorphous silicon. It should also be pointed out that the first doping region 30 and the second doping region 40 can be selected to be the same or different, for example, the first doping region 30 and the second doping region 40 are both doped polysilicon; or the first doping region 30 is doped polysilicon, and the second doping region 40 is doped silicon carbide, etc.; the first doping region 30 and the second doping region 40 are set accordingly according to actual use needs, and no specific limitation is made here.

[0101] Furthermore, in one embodiment of the present invention, the second doping region 40 is provided in a partial region outside the groove. Figure 1As shown, since the second doped region 40 is only located in a part of the area of ​​the boss, the first doped region 30 and the second doped region 40 can be isolated by the silicon substrate 10. At this time, the total thickness of the first dielectric layer 20 and the first doped region 30 disposed in the groove can be greater than, less than, or equal to the depth of the groove, that is, the first doped region 30 can be disposed in the groove or can be disposed to extend out of the groove. Figure 1 and Figure 2 As shown, the total thickness of the first dielectric layer 20 and the first doped region 30 is less than the depth of the groove. Figure 3 As shown, the total thickness of the first dielectric layer 20 and the first doped region 30 is equal to the depth of the groove. Figure 4 As shown, the total thickness of the first dielectric layer 20 and the first doped region 30 is greater than the depth of the groove. It should also be pointed out that, in one embodiment of the present invention, Figure 5 As shown, when the first dielectric layer 20 covers the entire back side of the silicon substrate 10 and the total thickness of the first dielectric layer 20 and the first doped region 30 is greater than the depth of the groove, the first doped region 30 can also extend to a portion of the platform area outside the groove and is not connected to the adjacent second doped region 40. In this case, the first dielectric layer 20 and the first doped region 30 arranged on the platform area outside the groove also form a passivation contact structure and are connected to the first dielectric layer 20 and the first doped region 30 in the groove, thereby increasing the contact area of ​​the first dielectric layer 20 through which carriers selectively pass.

[0102] Furthermore, in other embodiments of the present invention, the second doped region 40 is provided in the entire region outside the groove. Figure 6 As shown, since the second doping region 40 is arranged on the entire platform outside the groove, in order to achieve isolation between the first doping region 30 and the second doping region 40, the total thickness of the first dielectric layer 20 and the first doping region 30 arranged in the groove needs to be less than or equal to the depth of the groove, so that the isolation between the first doping region 30 and the second doping region 40 is achieved through the silicon substrate in the groove that does not cover the first doping region 30.

[0103] Furthermore, in one embodiment of the present invention, the thickness of the first dielectric layer 20 is 1-20 nm, the total thickness of the first dielectric layer 20 and the first doped region 30 is greater than 20 nm, and the total thickness of the first dielectric layer 20 and the second doped region 40 is greater than 20 nm. At the same time, the horizontal distance between the first doped region 30 and the second doped region 40 is 0-500 μm, that is, the second doped region 40 described above can cover the entire platform and be horizontally adjacent to the first doped region 30, or the second doped region 40 can cover a portion of the area outside the groove. Specifically, when the first doped region 30 is a P-type doped region, the groove width of the P-type doped region is set to 300-600 μm, the width of the N-type doped region set in the platform is 100-500 μm, and the depth of the groove is 0.01-10 μm. When the first doped region 30 is an N-type doped region, the width of the groove of the N-type doped region is set to 100-500um, the width of the P-type doped region set in the boss is 300-600um, and the depth of the groove is 0.01-10um. As a preferred embodiment of the present invention, the width of the P-type doped region is preferably 500um; the width of the N-type doped region is preferably 300um, and the distance between the first doped region 30 and the second doped region 40 is preferably 100um. As can be seen from the above, the control requirements for the width of the groove set are more relaxed than the tens of microns of the existing groove width, and the preparation is easier than the preparation of the existing groove.

[0104] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 covers the region between the first doping region 30 and the second doping region 40, or extends to cover the first doping region 30 and / or the second doping region 40. In other words, referring to Figure 7 As shown, the second dielectric layer 50 may only cover the area between the first doping region 30 and the second doping region 40. Correspondingly, the conductive layer 60 covers the first doping region 30 and the entire back surface of the first doping region 30 for electrical connection. Figure 1As shown, the second dielectric layer 50 may also extend from the protrusion to cover the first doped region 30 and / or the second doped region 40. Accordingly, the second dielectric layer 50 may extend to cover a portion of the first doped region 30, or a portion of the second doped region 40, or a portion of both the first doped region 30 and the second doped region 40. In this case, the conductive layer 60 covers the backside of the remaining portion of the first doped region 30 and the second doped region 40 that is not covered by the second dielectric layer 50, thereby forming electrical connections with the first doped region 30 and the second doped region 40, respectively. Of course, the second dielectric layer 50 may also completely cover the entire backside of the back contact structure during the preparation process. In this case, when preparing the conductive layer 60, the conductive layer 60 is penetrated through the second dielectric layer 50 by means of perforations, etc., thereby forming electrical connections with the first doped region 30 and the second doped region 40, respectively. It should be noted that when the first dielectric layer 20 only covers the first doped region 30 and the second doped region 40, the second dielectric layer 50 directly contacts the back surface of the silicon substrate 10. Figure 1 When the first dielectric layer 20 covers the entire back side of the silicon substrate 10, the second dielectric layer 50 is in contact with the first dielectric layer 20. Figure 2 shown.

[0105] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 is preferably a combination of one or more of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer. The second dielectric layer 50 has a passivation effect, and the second dielectric layer 50 is at least a layer structure, and the refractive index of each layer is arranged to decrease from the silicon substrate 10 outward, so that the film layer close to the silicon substrate 10 has a passivation effect, while the film layer away from the silicon substrate 10 has an anti-reflection effect, so that the anti-reflection effect can be enhanced, thereby increasing the absorption and utilization of light by the silicon substrate 10, thereby increasing the short-circuit current density. In addition, the second dielectric layer 50 can also be a doped silicon layer (such as a doped microcrystalline silicon layer, a doped amorphous silicon layer, or a doped polycrystalline silicon layer), a doped silicon carbide layer (such as a doped polycrystalline silicon carbide layer), a doped silicon oxide layer (such as a doped polycrystalline silicon oxide or a doped amorphous silicon oxide), etc. In addition, each layer of the film with different structures in the second dielectric layer 50 can also be composed of a multilayer film with different refractive indices, and arranged in a manner such that the refractive index of each film layer decreases from the silicon substrate 10 outward as described above. For example, the silicon oxide layer in the second dielectric layer 50 can be composed of a multilayer silicon oxide film with a refractive index decreasing from the silicon substrate 10 outward.

[0106] According to the above, as some specific examples of the present invention, for example, the second dielectric layer 50 can be a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer, an intrinsic silicon carbide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / aluminum oxide layer located in the first inner layer is greater than 0.5 nm, the thickness of the intrinsic silicon carbide layer located in the second layer is greater than 1 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50 nm.

[0107] As some specific examples of the present invention, for example, the second dielectric layer 50 can also be a two-layer structure consisting of an aluminum oxide layer and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the aluminum oxide layer located on the inner first layer is greater than 1 nm; the thickness of the silicon nitride layer / silicon oxynitride layer located on the outer second layer is greater than 50 nm.

[0108] As some specific examples of the present invention, for example, the second dielectric layer 50 can also be a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer, a doped polysilicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / aluminum oxide layer located in the first inner layer is 0.5-3nm, the thickness of the doped polysilicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer located in the second layer is 20-100nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50nm.

[0109] As some specific examples of the present invention, for example, the second dielectric layer 50 can also be a three-layer structure consisting of an intrinsic amorphous silicon layer, a doped amorphous silicon layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the intrinsic amorphous silicon layer located in the first inner layer is 2-10nm, the thickness of the doped amorphous silicon layer / doped amorphous silicon oxide layer located in the second layer is 2-50nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50nm.

[0110] As some specific examples of the present invention, for example, the second dielectric layer 50 can also be a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer, an intrinsic silicon carbide layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / aluminum oxide layer located in the first inner layer is 0.5-3nm, the thickness of the intrinsic silicon carbide layer / doped amorphous silicon oxide layer located in the second layer is 10-50nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50nm.

[0111] It is understood that the specific structural arrangement of the second dielectric layer 50 includes but is not limited to the several specific examples listed above. Figure 1As shown, the second dielectric layer 50 is preferably a two-layer structure of an aluminum oxide layer and an intrinsic silicon carbide layer, or a two-layer structure of a silicon oxide layer and an intrinsic silicon carbide layer. At this time, the overall thickness of the second dielectric layer 50 is greater than 25nm, of which the thickness is generally 70-80nm during normal production and preparation. At this time, the intrinsic silicon carbide layer not only provides a hydrogen passivation effect, but also reduces parasitic light absorption due to its large optical band gap and small absorption coefficient compared to the intrinsic amorphous silicon layer, the doped polycrystalline silicon layer, etc. Furthermore, the thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer 50 is less than 25nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer 50 is greater than 10nm. It should be pointed out that in the multi-layer structures indicated in the embodiments of the present invention, the order is arranged from the silicon substrate 10 to the outside. For example, when the second dielectric layer 50 described above is an aluminum oxide layer and an intrinsic silicon carbide layer, the aluminum oxide layer is close to the silicon substrate 10, and the intrinsic silicon carbide layer is close to the outside. It should also be pointed out that in the drawings of the specification, as Figures 1-10 As shown, it only shows that the second dielectric layer 50 has a two-layer structure. It is understandable that the second dielectric layer 50 can also have other numbers of layers. Its specific structure is set according to actual needs and does not completely follow the drawings in the specification. It should also be pointed out that in the various drawings of the present invention, it is only used to describe the specific structural distribution of the back contact structure, but it does not correspond to the actual size of each structure. For example, the thickness of the first dielectric layer 20 described above is 1-20nm, and the thickness of the second dielectric layer 50 is greater than 25nm. The drawings do not completely correspond to the actual size of the embodiment, and should be based on the specific parameters provided in the embodiment.

[0112] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer 50 is composed of at least one first intrinsic silicon carbide film with different refractive indices. The refractive index of each first intrinsic silicon carbide film decreases from the back of the silicon substrate 10 to the outside. Optionally, the refractive indices of the above-mentioned various materials can generally be selected as follows: the refractive index of single-crystalline silicon is 3.88; the refractive index of amorphous silicon is 3.5-4.2; the refractive index of polycrystalline silicon is 3.93, the refractive index of silicon carbide is 2-3.88, the refractive index of silicon nitride is 1.9-3.88, the refractive index of silicon oxynitride is 1.45-3.88, the refractive index of silicon oxide is 1.45, and the refractive index of aluminum oxide is 1.63. It is understandable that the refractive indices of the above-mentioned various materials can also be set to other values ​​according to actual use needs, and are not specifically limited here.

[0113] Furthermore, in one embodiment of the present invention, the outer layer of the second dielectric layer 50 is further provided with a magnesium fluoride layer. That is, in addition to the aforementioned combination of the aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer, and silicon oxide layer selected for the second dielectric layer 50, the outer layer of the second dielectric layer 50 may further be provided with a magnesium fluoride layer. The refractive index of the magnesium fluoride layer is required to be the lowest, generally set at 1.4, and is used to enhance the optical anti-reflection effect.

[0114] Furthermore, in one embodiment of the present invention, the conductive layer 60 is a TCO transparent conductive film and / or a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode or a silver-clad copper electrode. Furthermore, the copper electrode is an electroplated copper prepared by an electroplating process or a copper electrode prepared by physical vapor deposition. The electroplated copper uses nickel, chromium, titanium, or tungsten electrodes as its seed layer or protective layer. When the back contact structure is applied to a low-temperature HBC cell (cross-finger back contact heterojunction solar cell), the conductive layer 60 is a TCO transparent conductive film and a metal electrode, and when the back contact structure is applied to a high-temperature POLO-IBC cell (passivated contact IBC cell), the conductive layer 60 is a metal electrode. However, it should be noted that the metal electrode using low-temperature silver paste can only be applied to low-temperature HBC cells.

[0115] Furthermore, in one embodiment of the present invention, the groove is in the shape of an arc, a trapezoid, or a square. Figure 1 As shown, in one embodiment, the groove is square. Figure 8 As shown, in another specific embodiment, the groove is trapezoidal. The groove is preferably configured as an arc or trapezoid, because the inner wall of the groove reflects light better when the groove is configured as an arc or trapezoid, and it can also increase the surface area of ​​contact between the first dielectric layer 20 and the silicon substrate 10, which is specifically used as the tunneling structure. Of course, since the actual production process is simpler when the groove is configured as a square, the shape of the groove is configured accordingly according to actual use requirements and is not specifically limited here.

[0116] It should be noted that in other embodiments of the present invention, the first dielectric layer 20 may be connected to the bottom wall of the groove, and the second dielectric layer 50 may also be connected to the sidewalls of the groove. This is mainly because when a mask is used to cover the groove area, the subsequent removal of the mask will corrode the silicon in the silicon substrate 10 adjacent to the first doped region 30, thereby widening the groove. When the second dielectric layer 50 is subsequently deposited, it will be deposited in this vacant area, so that the second dielectric layer 50 is connected to the sidewalls of the groove. Alternatively, when preparing an arc-shaped groove (such as an elliptical groove), it may be impossible to deposit the first dielectric layer 20 and the first doped region 30 onto the inner wall of the arc-shaped groove in the long axis direction. Therefore, when depositing the second dielectric layer 50, it will fill the empty area, so that the second dielectric layer 50 is connected to the sidewall of the arc-shaped groove. Alternatively, it may be impossible to deposit the second dielectric layer 50 into the empty area, resulting in a certain gap between the sidewall of the arc-shaped groove and the first dielectric layer 20 and the first doped region 30. Of course, it should be pointed out that in the embodiment of the present invention, the back contact structure preferably has the first dielectric layer 20 directly connected to the sidewall of the groove, which can enable the first dielectric layer 20 disposed on the sidewall of the groove to selectively pass carriers and achieve multi-dimensional collection.

[0117] Further, in one embodiment of the present invention, referring to Figure 9As shown, a third doped region 70 is provided in the silicon substrate 10 located between the first doped region 30 and the second doped region 40. That is, the third doped region 70 can be provided on the entire platform outside the groove, or on a portion of the platform. Specifically, the third doped region 70 is a diffusion layer formed by doping different types of diffusion sources into the silicon substrate 10 of each platform. Therefore, the diffusion layer is formed by diffusion of the portion of the silicon substrate 10 located on the platform. The diffusion layer can be a P-type diffusion layer or an N-type diffusion layer. A P-type diffusion layer is formed by diffusion of boron, aluminum, gallium, etc., while an N-type diffusion layer is formed by diffusion of nitrogen, phosphorus, arsenic, etc. In this case, the N-type diffusion layer is an N+ layer relative to the silicon substrate 10, which is specifically an N-type silicon wafer. In other words, the diffusion layer is formed by localized heavy diffusion. It should be noted that each third doped region 70 provided on the silicon substrate 10 can be configured as a P-type diffusion layer or an N-type diffusion layer according to actual needs, and this is not specifically limited here. Preferably, different types of diffusion are alternately performed on each boss of the silicon substrate 10 to form a P-type diffusion layer and an N-type diffusion layer. At this time, since the sidewalls of the groove and the boss outside the groove are provided with the first dielectric layer 20, and the third doped region 70 is formed by diffusion between the first doped region 30 and the second doped region 40 in the silicon substrate 10, the carriers in the third doped region 70 can be more easily selectively separated through the first dielectric layer 20 in the adjacent groove sidewall and collected in the corresponding first doped region 30, and selectively separated through the first dielectric layer 20 on the boss and collected in the corresponding second doped region 40.

[0118] Further, in one embodiment of the present invention, referring to Figure 10As shown, the back side of the silicon substrate 10 located between the first doped region 30 and the second doped region 40 has a rough texture structure 80. That is, the rough texture structure 80 is present on the surface of the platform of the silicon substrate 10, wherein when the first dielectric layer 20 only covers the first doped region 30 and the second doped region 40, the rough texture structure 80 is located at a position where the second dielectric layer 50 contacts the back side of the silicon substrate 10; when the first dielectric layer 20 covers the entire back side of the silicon substrate 10, the rough texture structure 80 is located at a position where the first dielectric layer 20 contacts the back side of the silicon substrate 10. The rough texture structure 80 is usually formed by texturing, which can be an irregular hemispherical texture formed by acid texturing, a pyramid-shaped texture formed by alkali texturing, or a pyramid-shaped texture formed by alkali texturing and then the pyramid tip is smoothed by acid texturing. It can be understood that the rough texture structure 80 can also be set to the entire back side of the silicon substrate 10, that is, the silicon substrate 10 located in the groove also has a rough texture structure 80. In this case, the entire back side of the silicon substrate 10 after the groove is formed can be textured directly, without the need for a subsequent process of removing the rough texture structure 80 in the first doping region 30 and the second doping region 40, thereby simplifying the process. However, it should be pointed out that in this embodiment, it is preferred that the surface of the area between the first doping region 30 and the second doping region 40 of the silicon substrate 10 is textured, so as to increase the reflection of the incident light inside the silicon substrate 10, thereby increasing the light absorption rate, and the surface of the first doping region 30 and the second doping region 40 of the silicon substrate 10 is not textured.

[0119] Tests have shown that HBC and POLO-IBC cells fabricated using the back contact structure provided by the present invention, compared to a control group of POLO-IBC cells fabricated using the conventional trench method, have significantly improved conversion efficiency to approximately 26.0%, significantly enhancing reliability. The electrical performance results are shown in Table 1 below:

[0120] Table 1

[0121] Compared with the existing embodiments, the embodiments of the present invention have the following advantages:

[0122] 1. Since grooves are arranged at intervals on the back side of the silicon substrate, and a first doped region is arranged in each groove and a second doped region is arranged outside each groove, the first doped region in the groove and the second doped region outside the groove are blocked by the silicon substrate not covering the first doped region in the groove or by the silicon substrate not covering the second doped region outside the groove. The width control requirements of the grooves are looser than those of existing grooves, and the preparation of the grooves is easier than that of existing grooves. Moreover, when depositing the first dielectric layer and the first doped region in the grooves, the deposition effect is better.

[0123] 2. Due to the setting of the groove, the first dielectric layer is in contact with the bottom wall and side walls of the groove. Therefore, the carriers generated in the silicon substrate can be easily separated by the first dielectric layer on the side walls of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the selective transport of carriers in the vertical and horizontal directions can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side walls of the groove.

[0124] 3. Since at least one second dielectric layer is provided, the back side of the silicon substrate is multi-layered and passivated through at least one second dielectric layer, thereby achieving a better passivation effect. Furthermore, by controlling the refractive index of each layer to decrease from the silicon substrate outward, the reflection of long-wavelength light on the inner back side of the silicon substrate can be improved, thereby increasing the short-circuit current density.

[0125] 4. Since the groove has a certain depth, the hard mask only directly contacts the raised part between the two grooves, so that the hard mask will not directly contact the bottom of the groove, reducing impurity contamination. Therefore, it can play a certain protective role on the silicon substrate at the bottom wall of the groove. There is no need to worry about the hard mask causing damage to the silicon substrate. The damage caused by the hard mask contacting the convex surface of the silicon substrate can also be removed through the subsequent texturing process.

[0126] 5. When using a hard mask to selectively deposit the first or second doped regions, such as when depositing the first doped region in a recessed region, the hard mask can be used to cover the bosses outside the recessed region. Since the recesses have a certain depth, the hard mask will not directly contact the bottom of the recesses, resulting in better deposition. Furthermore, since the recesses are separated by silicon substrate boss structures of a certain width, the alignment of the hard mask does not need to be very precise when depositing in the recessed region using the hard mask. A moderate amount of deviation can be allowed, making alignment of the hard mask simpler and reducing the difficulty of the process.

[0127] 6. In the prior art, due to the limitations of width and depth of the groove area, the chemical solution cannot completely penetrate the bottom of the groove for chemical wet texturing due to the hydrophobicity of water and silicon wafers. In this embodiment, due to the provision of grooves, the back side of the silicon substrate between adjacent grooves is relatively a convex platform, which makes it easier to achieve texturing to obtain a rough texture structure than the existing groove structure. By texturing the convex platform on the back side of the silicon substrate, the reflection of light on the inner back side of the silicon substrate is increased, thereby increasing the light absorption rate of the silicon substrate.

[0128] 7. Since a third doped region is provided in the region between the first doped region and the second doped region in the silicon substrate, the carriers in the third doped region can be more easily selectively separated through the first dielectric layer in the adjacent groove sidewall and collected into the corresponding first doped region, and selectively separated through the first dielectric layer on the boss and collected into the corresponding second doped region.

[0129] Example 2

[0130] The second embodiment of the present invention provides a selective contact region buried type solar cell. For ease of description, only the parts related to the embodiment of the present invention are shown. Figures 1-10 As shown, the selective contact region buried type solar cell provided by the embodiment of the present invention includes:

[0131] Silicon substrate 10;

[0132] The back contact structure described in the above embodiment is provided on the back side of the silicon substrate 10; and

[0133] A third dielectric layer 90 is provided on the front surface of the silicon substrate 10 .

[0134] Furthermore, in one embodiment of the present invention, the second dielectric layer 50 and the third dielectric layer 90 can be prepared by the same process on the front and back surfaces of the silicon substrate 10, respectively. In this case, the third dielectric layer 90 can have the same structure as the second dielectric layer 50 in the aforementioned embodiment. Therefore, with reference to the aforementioned embodiment, the third dielectric layer 90 can also preferably be one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0135] As some examples of the present invention, the third dielectric layer 90 can also be a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer and a doped polycrystalline silicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer and a silicon nitride layer / silicon oxynitride layer, or a three-layer structure consisting of an intrinsic amorphous silicon layer and a doped amorphous silicon layer / doped amorphous silicon oxide layer and a silicon nitride layer / silicon oxynitride layer, or a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer and an intrinsic silicon carbide layer / doped amorphous silicon oxide layer and a silicon nitride layer / silicon oxynitride layer.

[0136] Further, in a preferred embodiment of the present invention, referring to Figure 1As shown, the third dielectric layer 90 is also preferably a two-layer structure of a silicon oxide layer and an intrinsic silicon carbide layer, or a two-layer structure of an aluminum oxide layer and an intrinsic silicon carbide layer. The thickness of the third dielectric layer 90 is greater than 50 nm. The thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer 90 is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer 90 is greater than 10 nm. In this case, the intrinsic silicon carbide layer not only provides hydrogen passivation but also reduces parasitic light absorption due to its large optical bandgap and low absorption coefficient compared to intrinsic amorphous silicon layers and doped polycrystalline silicon layers. Furthermore, the intrinsic silicon carbide layer in the third dielectric layer 90 is composed of at least one second intrinsic silicon carbide film with a different refractive index. The refractive index of each second intrinsic silicon carbide film decreases from the front side of the silicon substrate 10 outward. Furthermore, in one embodiment of the present invention, the outer layer of the third dielectric layer 90 is also provided with a magnesium fluoride layer. The refractive index of the outermost magnesium fluoride layer is required to be the lowest, and is generally set to 1.4, which is used to enhance the optical effect of anti-reflection.

[0137] Of course, the third dielectric layer 90 may also have a different structural arrangement from the second dielectric layer 50 in the aforementioned embodiment. The second dielectric layer 50 and the third dielectric layer 90 may have different film layer structures according to actual use needs, which is not specifically limited here.

[0138] Furthermore, in one embodiment of the present invention, an electric field layer or a floating junction is provided between the front surface of the silicon substrate 10 and the third dielectric layer 90. Specifically, the electric field layer is obtained by phosphorus diffusion on the silicon substrate 10, or the floating junction is obtained by boron diffusion on the silicon substrate 10. In this case, the electric field layer or the floating junction serves as the front surface electric field (FSF) of the buried solar cell in the selective contact area.

[0139] In this embodiment, grooves are arranged at intervals on the back side of the silicon substrate, and a first doped region is arranged in each groove and a second doped region is arranged outside each groove, so that the first doped region in the groove and the second doped region outside the groove are blocked by the silicon substrate not covering the first doped region in the groove or by the silicon substrate not covering the second doped region outside the groove. The width control requirements of the grooves are looser than those of the existing grooves, and the preparation is easier than that of the existing grooves. When the first dielectric layer and the first doped region are deposited in the grooves, the deposition effect is better. At the same time, due to the arrangement of the grooves, the first dielectric layer is in contact with the bottom wall and side walls of the grooves. Therefore, the carriers generated in the silicon substrate can be easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the longitudinal and lateral selective transport of carriers can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove; since the second dielectric layer is set as at least one layer, the back side of the silicon substrate is multi-layered passivated by at least one second dielectric layer, thereby bringing better passivation effect and improving internal back reflection, thereby bringing better passivation effect and internal back reflection effect, solving the existing problems of high requirements for groove width control and poor passivation effect.

[0140] Example 3

[0141] The third embodiment of the present invention provides a method for manufacturing a selective contact region buried type solar cell. For ease of description, only the part related to the embodiment of the present invention is shown. Figure 11 As shown, the method for manufacturing a selective contact region buried type solar cell provided in an embodiment of the present invention is used to prepare the selective contact region buried type solar cell as described in the above embodiment. Specifically, the method includes:

[0142] Step S11, forming a plurality of grooves spaced apart on the back side of the silicon substrate;

[0143] Before step S11, the silicon substrate should also be pre-processed;

[0144] The above-mentioned pretreatment includes cleaning the silicon substrate and removing the damaged layer. Specifically, it includes:

[0145] (1) RCA standard cleaning to remove particles and organic matter on the surface of the silicon substrate;

[0146] (2) After cleaning the silicon substrate, place it in a 2-5% KOH alkaline solution (potassium hydroxide) or TMAH solution (tetramethylammonium hydroxide, i.e., developer) at a temperature of 50-80°C for 1-5 minutes to remove the surface damage layer caused by the slicing process;

[0147] (3) using HCl to pickle the surface of the silicon substrate to neutralize the alkali solution remaining on the surface of the silicon substrate and remove the metal impurities remaining on the surface of the silicon wafer;

[0148] (4) Cleaning the silicon substrate with HF solution to remove the silicon dioxide layer on the surface of the silicon wafer and form Si-H passivation bonds with the dangling bonds on the surface of the silicon substrate, and finally drying with nitrogen for later use.

[0149] Furthermore, after the silicon substrate is pre-processed, the grooves may be formed in the following ways:

[0150] Method 1: Directly groove at the desired intervals by laser to remove local silicon crystals on the back of the silicon substrate to form the desired grooves; Method 2: Thermally oxidize the silicon substrate to form a layer of silicon oxide on the entire surface of the silicon substrate, remove the silicon oxide in the local area on the front and back of the silicon substrate by laser groove, and then remove the silicon oxide by wet etching and acid (such as HF) to form the desired grooves; Method 3: Use PECVD to deposit a layer of silicon nitride on the back of the silicon substrate, remove the silicon nitride in the local area on the back by laser groove, and then remove the silicon nitride by wet etching. The desired groove is formed; Method 4: silicon nitride is deposited on the back of the silicon substrate or the silicon substrate is thermally oxidized to form silicon oxide, and then a photoresist mask is deposited on the back, and development is performed in the development area by patterning the screen and exposing, and the development area is wet-removed with a developer, and the silicon nitride / silicon oxide in the development area is removed with an acid (such as HF), and then the photoresist mask and silicon nitride / silicon oxide are wet-etched and removed to form the desired groove; Method 5: a patterned slurry is printed on the back of the silicon substrate as a mask, and then the slurry is wet-etched and removed to form the desired groove.

[0151] In the embodiment of the present invention, the groove is preferably formed using the second method. In the second method, the thermal oxidation treatment step specifically includes: performing dry oxygen oxidation / water vapor oxidation / wet oxygen oxidation (i.e., dry oxygen + water vapor) in a quartz tube, wherein the reactants are oxygen and / or high-purity water vapor, the reaction pressure is 50-1000 mbar, the reaction temperature is 900-1200°C, and the thickness of the silicon oxide produced by the reaction is greater than 10 nm. The laser groove removal step specifically includes: using a laser with a wavelength of 532 nm, a laser power of 10-60 W, a laser frequency of less than or equal to 250 to 1500 kHz, and a laser pulse width of 3-50 ns to groove and remove the silicon oxide to be removed. The wet etching step uses an alkaline solution and isopropyl ketone, wherein the alkaline solution is KOH or TMAH, the alkaline solution concentration is 1-5%, the isopropyl ketone content is 1-10%, the reaction temperature is 60-85°C, and the reaction time is 10-30 min. The acid solution in the step of removing silicon oxide with acid is HF, the concentration of the acid solution is 1-5%, the reaction temperature is room temperature, and the reaction time is 3-10 minutes.

[0152] Specifically, after the grooves are formed by the second method described above, the depth of each groove is 0.01-10 μm. The grooves formed can be arc-shaped, trapezoidal, or square. In the prior art, the grooves are formed by laser drilling or wet etching, which requires high control of the groove width and is difficult to prepare. However, the groove preparation in this embodiment is easier than the existing groove preparation and does not require the strict width control of the existing grooves.

[0153] Step S21, preparing a first dielectric layer on the back side of the silicon substrate;

[0154] Before step S21, the specific production process may also include texturing the front side of the silicon substrate. In this embodiment, texturing the front side mainly adopts alkali corrosion, and the alkali reacts with the silicon substrate to generate a water-soluble compound, and at the same time forms a pyramid-shaped velvet structure on the surface. At this time, due to the presence of the velvet structure, after the incident light is reflected by the velvet for the first time, the reflected light is not directly incident into the air, but encounters the adjacent velvet surface, and is reflected by the velvet for the second or even third time before being incident into the air. In this way, the incident light is utilized multiple times, thereby reducing the front reflectivity. When the back side of the silicon substrate also needs to have a rough texture structure, the front and back sides of the silicon substrate can be texturized at the same time; and when the back side of the silicon substrate does not need to have a rough texture structure, a silicon nitride protective layer can be first deposited on the back side of the silicon substrate, and then the front side is texturized, and then the silicon nitride protective layer on the back side is removed by laser to avoid texturing the back side of the silicon substrate.

[0155] Specifically, a first dielectric layer is prepared on the back side of the silicon substrate according to a high-temperature oxidation process or a deposition process. The first dielectric layer is set according to the type of the first dielectric layer specifically deposited, which is not specifically limited here. In this case, the first dielectric layer is a combination of one or more of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer, and the thickness of the first dielectric layer is 1-20 nm. In this case, the first dielectric layer covers the entire back side of the silicon substrate. When the first dielectric layer is not needed in the area between the first doped region and the second doped region in the silicon substrate, the first dielectric layer covering the area between the first doped region and the second doped region in the silicon substrate can be removed by laser.

[0156] Step S31, preparing a first doped region and a second doped region inside and outside each groove respectively;

[0157] The first doped region and the second doped region are prepared inside and outside each groove respectively by two deposition methods: in-situ deposition and ex-situ deposition.

[0158] Specifically, in one embodiment of the present invention, when in-situ deposition is adopted, step S31 includes:

[0159] Alternately depositing doped amorphous silicon or doped amorphous silicon carbide of different doping types inside and outside each groove;

[0160] High-temperature crystallization treatment is performed to convert the doped amorphous silicon or doped amorphous silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region arranged in the groove and a second doped region arranged outside the groove.

[0161] In one of the possible implementation schemes, when the first doping region (such as a P-type doping region) is deposited in situ in the groove, the boss position that does not need to be deposited is covered by a masking method, and P-type amorphous silicon / P-type amorphous silicon carbide is deposited in situ in the groove. It is correspondingly pointed out that since the groove has a certain depth, the mask is in a position that conflicts with the boss and does not directly contact the bottom of the groove, so that impurity contamination at the bottom of the groove can be reduced. When the groove deposition is completed, the impurity contamination caused by the mask (such as a silicon nitride mask or a silicon oxide mask) or the mask (such as a hard mask) on the boss can be removed by laser, and then the groove can be blocked by the mask to in-situ deposit N-type amorphous silicon / N-type amorphous silicon carbide on the part of the boss outside the groove where the second doping region is required to be deposited. After P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide are alternately deposited inside and outside each groove, the temperature is directly raised to 700-1000°C by directly using high temperature or laser heating methods. Therefore, under high temperature crystallization treatment, the P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide inside and outside each groove are converted into P-type polycrystalline silicon / P-type silicon carbide and N-type polycrystalline silicon / N-type silicon carbide to obtain a first doping region (i.e., a P-type doping region) arranged inside the groove and a second doping region (i.e., an N-type doping region) arranged outside the groove. The mask may be a hard mask, a silicon nitride mask, a silicon oxide mask, or a photoresist mask, etc. Since in-situ deposited doped amorphous silicon or doped silicon carbide may be deposited on the side and front of the silicon substrate, a wet etching process is required after high-temperature crystallization to achieve de-coating.

[0162] In another possible implementation scheme, a first doped region (specifically, a P-type doped region) is in-situ deposited on the entire back side of the silicon substrate, where P-type amorphous silicon / P-type amorphous silicon carbide is deposited on the entire back side of the silicon substrate, and then the P-type amorphous silicon / P-type amorphous silicon carbide in all areas outside the grooves in the silicon substrate is completely removed by laser ablation. Then, N-type amorphous silicon / N-type amorphous silicon carbide is deposited on the entire back side of the silicon substrate, and then all N-type amorphous silicon / N-type amorphous silicon carbide on the bosses in the silicon substrate except the second doped region is completely removed by laser ablation. Then, by directly utilizing high temperature or laser heating methods, the temperature reaches 700-1000°C, thereby converting the P-type amorphous silicon / P-type amorphous silicon carbide and N-type amorphous silicon / N-type amorphous silicon carbide inside and outside each groove into P-type polycrystalline silicon / P-type silicon carbide and N-type polycrystalline silicon / N-type silicon carbide, so as to obtain a first doped region arranged in the groove and a second doped region arranged outside the groove.

[0163] Specifically, in one embodiment of the present invention, when non-in-situ deposition is adopted, step S31 includes:

[0164] depositing intrinsic amorphous silicon or intrinsic silicon carbide inside and outside each groove;

[0165] Doping with different doping types is performed alternately inside and outside each groove;

[0166] High-temperature crystallization treatment is performed to convert intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region arranged in the groove and a second doped region arranged outside the groove.

[0167] The step of alternately performing doping of different doping types in each groove specifically includes:

[0168] Alternately implanting first type ions and second type ions into the inside and outside of each groove; or

[0169] Alternately depositing a first type dopant source and a second type dopant source inside and outside each groove; or

[0170] The first type source gas and the second type source gas are alternately introduced into the inside and outside of each groove for doping.

[0171] In one possible implementation scheme, specifically, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited in each groove, and then different types of ions are implanted inside and outside the groove. For example, when the first doped region in the groove is a P-type doped region, P-type ions containing elements such as boron, aluminum, and gallium are implanted in the groove, while N-type ions containing elements such as nitrogen, phosphorus, and arsenic are locally implanted outside the groove. Then, high-temperature crystallization is performed to convert the original intrinsic amorphous silicon or original intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide. Since the deposited intrinsic amorphous silicon or intrinsic silicon carbide may be deposited on the side and front of the silicon substrate, a wet etching process is required after the high-temperature crystallization to achieve de-coating.

[0172] In one of the possible implementation schemes, specifically, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited inside and outside each groove, and then different doping types of doping sources are alternately deposited inside and outside the groove by a mask method for doping. For example, when the first doping region is specifically a P-type doping region, a P-type doping source (such as borosilicate glass) containing boron, aluminum, gallium, etc. is deposited in the groove for doping to form P-type amorphous silicon / P-type silicon carbide, and then an N-type doping source (such as phosphosilicate glass) containing nitrogen, phosphorus, arsenic, etc. is locally deposited outside the groove for doping to form N-type amorphous silicon / N-type silicon carbide. After the P-type doping source and the N-type doping source are alternately deposited inside and outside each groove, a high-temperature crystallization treatment is then performed to convert the original intrinsic amorphous silicon or the original intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide. It should be pointed out that after depositing different doping sources for doping and high-temperature crystallization treatment, the doping source needs to be removed by laser or other means.

[0173] The mask includes a hard mask, a silicon nitride mask, a silicon oxide mask, and a photoresist mask. Specifically, in the case of a hard mask, for example, the hard mask is first used to cover the boss of the silicon substrate, and then the first type of dopant source is deposited in the groove. The groove is then covered with a hard mask, and then the second type of dopant source is locally deposited outside the groove, thereby depositing dopant sources of different doping types inside and outside the groove for doping. Specifically, in the case of a silicon nitride mask, for example, silicon nitride is first deposited on the back side, and then the groove is opened by laser drilling to remove the silicon nitride in the groove. The first type of dopant source is then deposited in the groove. Silicon nitride is then deposited on the back side so that the silicon nitride covers the first type of dopant source for protection. The boss is then opened by laser drilling to remove the silicon nitride and the first type of dopant source on the boss. The second type of dopant source is then deposited on the boss. The second type of dopant source and the silicon nitride deposited in the groove are then removed by laser drilling, thereby depositing dopant sources of different doping types inside and outside the groove for doping. The silicon oxide mask is similar to the silicon nitride mask and will not be described in detail here.

[0174] In one of the possible implementation schemes, specifically, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited inside and outside each groove, and then different doping types of source gases are introduced into the groove through a mask method for doping. For example, when the first doping region is a P-type doping region, a P-type source gas containing elements such as boron, aluminum, and gallium (such as borane gas or a carrier gas carrying boron trichloride or boron tribromide) is introduced into the groove for doping to form P-type amorphous silicon / P-type silicon carbide, and an N-type source gas containing elements such as nitrogen, phosphorus, and arsenic (such as phosphine gas or a carrier gas carrying phosphorus oxychloride) is locally introduced outside the groove for doping to form N-type amorphous silicon / N-type silicon carbide. After the first type source gas and the second type source gas of different doping types are alternately introduced into the inside and outside of each groove for doping, high-temperature crystallization treatment is performed to make the intrinsic amorphous silicon or intrinsic silicon carbide become doped polycrystalline silicon or doped silicon carbide. The mask includes a hard mask, a silicon nitride mask, a silicon oxide mask, and a photoresist mask, etc. The specific implementation can refer to the above description.

[0175] Specifically, in another embodiment of the present invention, when non-in-situ deposition is adopted, step S31 may further include:

[0176] depositing intrinsic amorphous silicon or intrinsic silicon carbide inside and outside each groove;

[0177] Different types of diffusion are alternately performed inside and outside each groove through a mask to convert intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, thereby obtaining a first doped region arranged inside the groove and a second doped region arranged outside the groove.

[0178] In one possible implementation, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited inside and outside each groove. A first-type diffusion is then performed directly within the groove using a mask to form a first doped region. A second-type diffusion is then performed locally outside the groove to form a second doped region. For example, if the first doped region is a P-type doped region, boron is diffused within the groove to form a P-type doped region, and phosphorus is diffused locally outside the groove to form an N-type doped region. The mask may include a hard mask, a silicon nitride mask, a silicon oxide mask, or a photoresist mask. The specific implementation can refer to the above description.

[0179] It should be pointed out that in the process of alternately preparing the first doped region and the second doped region, due to the need for a high-temperature crystallization process, the thinner first dielectric layer will be partially broken. At this time, during the high-temperature diffusion process, it will adhere to the broken parts of the first dielectric layer and the back side of the silicon substrate, so that the surface where the silicon substrate contacts the first dielectric layer forms multiple inner diffusion regions corresponding to the first doped region or the second doped region.

[0180] Specifically, first doped regions and second doped regions are alternately prepared inside and outside each groove, and the first doped regions and the second doped regions include doped polysilicon or doped silicon carbide or doped amorphous silicon, and the total thickness of the first dielectric layer and the first doped region or the second doped region is greater than 20nm.

[0181] Step S41, forming a second dielectric layer and a third dielectric layer on the back and front sides of the silicon substrate respectively;

[0182] Among them, before this step S41, it can also include alternating different types of diffusion at a position between the first doping region and the second doping region on the back side of the silicon substrate, so that different types of third doping regions are diffused at a local position of the back side boss of the silicon substrate. When the third doping region is a P-type diffusion layer, its specific preparation process includes: method one: introducing a source gas containing elements such as boron, aluminum, gallium, etc. (such as borane gas or a carrier gas carrying boron trichloride or boron tribromide) to perform thermal diffusion to form a P-type diffusion layer; method two: depositing a doping source containing boron, aluminum, gallium, etc. (such as borosilicate glass) to perform thermal diffusion to form a P-type diffusion layer; method three: preparing an aluminum electrode above the diffusion layer, and then forming an aluminum-doped P-type diffusion layer through a high-temperature process; method four: spin-coating a doping source containing boron, aluminum, gallium, etc. (such as boron tribromide) to perform thermal diffusion to form a P-type diffusion layer; method five: injecting ions containing elements such as boron, aluminum, gallium, etc., and performing high-temperature diffusion to form a P-type diffusion layer.

[0183] When the third doped region is an N-type diffusion layer, its specific preparation process is as follows: Method 1: introducing a source gas containing elements such as nitrogen, phosphorus, and arsenic (such as phosphine gas or a carrier gas carrying phosphorus oxychloride) to perform thermal diffusion to form an N-type diffusion layer; Method 2: depositing a doping source containing nitrogen, phosphorus, arsenic, etc. (such as phosphosilicate glass) to perform thermal diffusion to form an N-type diffusion layer; Method 3: spin coating a doping source containing nitrogen, phosphorus, arsenic, etc. (such as phosphorus oxychloride) to perform thermal diffusion to form an N-type diffusion layer; Method 4: injecting ions containing elements such as nitrogen, phosphorus, and arsenic, and performing high-temperature diffusion to form an N-type diffusion layer. It should be noted that after the deposited doping source is thermally diffused, it is necessary to remove the doping source by means of a laser or other method.

[0184] Furthermore, before step S41 , the process may further include texturing the back surface of the silicon substrate between the first doping region and the second doping region to obtain a rough texture structure. The specific texturing process may refer to the above description.

[0185] Specifically, during the process of forming the second and third dielectric layers on the back and front sides of the silicon substrate, respectively, the second and third dielectric layers are prepared based on their specific composition types, which are not specifically limited herein. Accordingly, the second and third dielectric layers can be one or more combinations of aluminum oxide layers, silicon nitride layers, silicon oxynitride layers, intrinsic silicon carbide layers, intrinsic amorphous silicon layers, and silicon oxide layers. Furthermore, when the second and third dielectric layers are arranged in a multilayer structure, the refractive index of each layer is arranged to decrease from the silicon substrate outward, and the outermost layer can also be a magnesium fluoride layer with the lowest refractive index requirement.

[0186] At the same time, before preparing the third dielectric layer on the front side of the silicon substrate, an electric field layer or a floating junction can also be prepared first. Specifically, the electric field layer is prepared by phosphorus diffusion on the silicon substrate, or the floating junction is prepared by boron diffusion. At this time, the electric field layer or the floating junction serves as the front surface electric field (FSF) of the buried solar cell in the selective contact area.

[0187] Step S51 : preparing a conductive layer on the first doping region and the second doping region.

[0188] Specifically, when the second dielectric layer only covers the area between the first doped region and the second doped region in the silicon substrate, the conductive layer covers the entire back side of the first doped region and the second doped region for electrical connection; when the second dielectric layer extends to cover the first doped region and the second doped region, the conductive layer covers the back side of the remaining part of the first doped region and the second doped region that is not covered by the second dielectric layer for electrical connection; when the second dielectric layer covers the entire back side of the silicon substrate, the conductive layer is passed through the second dielectric layer by means of perforations or the like to be electrically connected to the first doped region and the second doped region, so that a first electrode is formed in the first doped region and a second electrode is formed in the second doped region.

[0189] When preparing HBC cells (interdigitated back-contact heterojunction solar cells) for low-temperature processes, the conductive layer is a TCO transparent conductive film and a metal electrode, while when preparing POLO-IBC cells (passivated contact IBC cells) for high-temperature processes, the conductive layer is a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode, or a silver-clad copper electrode. Furthermore, the copper electrode is an electroplated copper prepared by an electroplating process or a copper electrode prepared by physical vapor deposition. The electroplated copper uses nickel, chromium, titanium, or tungsten electrodes as its seed layer or protective layer.

[0190] Compared with the existing embodiments, the embodiments of the present invention have the following advantages:

[0191] 1. Since grooves are arranged at intervals on the back side of the silicon substrate, and a first doped region is arranged in each groove and a second doped region is arranged outside each groove, the first doped region in the groove and the second doped region outside the groove are blocked by the silicon substrate not covering the first doped region in the groove or by the silicon substrate not covering the second doped region outside the groove. The width control requirements of the grooves are looser than those of existing grooves, and the preparation of the grooves is easier than that of existing grooves. Moreover, when depositing the first dielectric layer and the first doped region in the grooves, the deposition effect is better.

[0192] 2. Due to the setting of the groove, the first dielectric layer is in contact with the bottom wall and side walls of the groove. Therefore, the carriers generated in the silicon substrate can be easily separated by the first dielectric layer on the side walls of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the selective transport of carriers in the vertical and horizontal directions can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side walls of the groove.

[0193] 3. Since at least one second dielectric layer is provided, the back side of the silicon substrate is multi-layered and passivated through at least one second dielectric layer, thereby achieving a better passivation effect. Furthermore, by controlling the refractive index of each layer to decrease from the silicon substrate outward, the reflection of long-wavelength light on the inner back side of the silicon substrate can be improved, thereby increasing the short-circuit current density.

[0194] 4. Since the groove has a certain depth, the hard mask only directly contacts the raised part between the two grooves, so that the hard mask will not directly contact the bottom of the groove, reducing impurity contamination. Therefore, it can play a certain protective role on the silicon substrate at the bottom wall of the groove. There is no need to worry about the hard mask causing damage to the silicon substrate. The damage caused by the hard mask contacting the convex surface of the silicon substrate can also be removed through the subsequent texturing process.

[0195] 5. When using a hard mask to selectively deposit the first or second doped regions, such as when depositing the first doped region in a recessed region, the hard mask can be used to cover the bosses outside the recessed region. Since the recesses have a certain depth, the hard mask will not directly contact the bottom of the recesses, resulting in better deposition. Furthermore, since the recesses are separated by silicon substrate boss structures of a certain width, the alignment of the hard mask does not need to be very precise when depositing in the recessed region using the hard mask. A moderate amount of deviation can be allowed, making alignment of the hard mask simpler and reducing the difficulty of the process.

[0196] 6. In the prior art, due to the limitations of width and depth of the groove area, the chemical solution cannot completely penetrate the bottom of the groove for chemical wet texturing due to the hydrophobicity of water and silicon wafers. In this embodiment, due to the provision of grooves, the back side of the silicon substrate between adjacent grooves is relatively a convex platform, which makes it easier to achieve texturing to obtain a rough texture structure than the existing groove structure. By texturing the convex platform on the back side of the silicon substrate, the reflection of light on the inner back side of the silicon substrate is increased, thereby increasing the light absorption rate of the silicon substrate.

[0197] 7. Since a third doped region is provided in the region between the first doped region and the second doped region in the silicon substrate, the carriers in the third doped region can be more easily selectively separated through the first dielectric layer in the adjacent groove sidewall and collected into the corresponding first doped region, and selectively separated through the first dielectric layer on the boss and collected into the corresponding second doped region.

[0198] Example 4

[0199] A fourth embodiment of the present invention further provides a battery assembly, which includes the selective contact region buried solar cell described in the above embodiment.

[0200] The battery assembly in this embodiment sets grooves at intervals on the back side of the silicon substrate by setting a selective contact area buried solar cell, and sets a first doped region in each groove and a second doped region outside each groove, so that the first doped region in the groove and the second doped region outside the groove are blocked by the silicon substrate that does not cover the first doped region in the groove or by the silicon substrate that does not cover the second doped region outside the groove. The width control requirements of the groove are looser than those of the existing grooves, and the preparation is easier than that of the existing grooves. When the first dielectric layer and the first doped region are deposited in the groove, the deposition effect is better. At the same time, due to the setting of the groove, the first dielectric layer Since the first dielectric layer is in contact with the bottom wall and side wall of the groove, the carriers generated in the silicon substrate can be easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the longitudinal and lateral selective transport of carriers can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove; since the second dielectric layer is set as at least one layer, the back side of the silicon substrate is multi-layered passivated by at least one second dielectric layer, thereby bringing better passivation effect and improving internal back reflection, thereby bringing better passivation effect and internal back reflection effect, solving the existing problems of high requirements for groove width control and poor passivation effect.

[0201] Example 5

[0202] A fifth embodiment of the present invention further provides a photovoltaic system, comprising the battery assembly as described in the above embodiments.

[0203] In the photovoltaic system of this embodiment, grooves are arranged at intervals on the back side of the silicon substrate through the selective contact area buried solar cell arranged by the battery assembly, and a first doped region is arranged in each groove and a second doped region is arranged outside each groove, so that the first doped region in the groove and the second doped region outside the groove are blocked by the silicon substrate not covering the first doped region in the groove or by the silicon substrate not covering the second doped region outside the groove. The width control requirements of the grooves are looser than those of the existing grooves, and the preparation is easier than that of the existing grooves. When the first dielectric layer and the first doped region are deposited in the grooves, the deposition effect is better. At the same time, due to the setting of the grooves, the first dielectric layer and the first doped region are blocked. The dielectric layer is in contact with both the bottom wall and the side wall of the groove, so the carriers generated in the silicon substrate can also be easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the longitudinal and lateral selective transport of carriers can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove; because the second dielectric layer is provided in at least one layer, the back side of the silicon substrate is multi-layered passivated by at least one second dielectric layer, thereby bringing about a better passivation effect and improving the internal back reflection, thereby bringing about a better passivation effect and internal back reflection effect, solving the existing problems of high requirements for groove width control and poor passivation effect.

[0204] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A back contact structure of a solar cell, characterized in that: include: grooves arranged at intervals on the back side of the silicon substrate; a first dielectric layer disposed on the back side of the silicon substrate; a first doped region disposed on the first dielectric layer and only within the groove, wherein the total thickness of the first dielectric layer and the first doped region disposed in the groove is less than or equal to the depth of the groove; a second doped region disposed on the first dielectric layer and outside the groove, wherein the second doped region is disposed in a partial region outside the groove; a second dielectric layer disposed between the first doped region and the second doped region, wherein the second dielectric layer is at least one layer; and A conductive layer is arranged on the first doped region and the second doped region, and the second dielectric layer includes a first part, a second part and a third part, the first part covers the top surface of the first doped region, and the first part is arranged in the groove, the second part covers the top surface of the second doped region, and the first doped region and the second doped region are arranged at intervals, and the third part is arranged between the first part and the second part and covers another part of the area outside the groove.

2. The back contact structure according to claim 1, wherein: The first doped region is a P-type doped region, and the second doped region is an N-type doped region; or The first doping region is an N-type doping region, and the second doping region is a P-type doping region.

3. The back contact structure according to claim 1, wherein: The first doping region and the second doping region include doped polysilicon, doped silicon carbide, or doped amorphous silicon.

4. The back contact structure according to claim 1, wherein: The first dielectric layer is one or more combinations of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer.

5. The back contact structure according to claim 1, wherein: The second dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

6. The back contact structure according to claim 1, wherein: The back side of the silicon substrate located between the first doping region and the second doping region has a rough texture structure.

7. The back contact structure according to claim 2, wherein: The width of the P-type doping region is 300-600 um, the width of the N-type doping region is 100-500 um, and the depth of the groove is 0.01-10 um.

8. The back contact structure according to claim 1, wherein: The horizontal distance between the first doping region and the second doping region is 0-500 um.

9. The back contact structure according to claim 1, wherein: The first dielectric layer covers the first doped region and the second doped region or covers the entire back side of the silicon substrate.

10. The back contact structure according to claim 1, wherein: A third doping region is provided in the silicon substrate located between the first doping region and the second doping region.

11. The back contact structure according to claim 1, wherein: The first dielectric layer is connected to the bottom wall and the sidewalls of the groove.

12. The back contact structure according to claim 1, wherein: The first dielectric layer is connected to the bottom wall of the groove, and the second dielectric layer is also connected to the sidewall of the groove.

13. The back contact structure according to claim 1, wherein: The groove is in an arc shape, a trapezoidal shape, or a square shape.

14. The back contact structure according to claim 1, wherein: The thickness of the first dielectric layer is 1-20 nm, and the total thickness of the first dielectric layer and the first doped region or the second doped region is greater than 20 nm.

15. The back contact structure according to claim 3, wherein: The doped silicon carbide includes doped hydrogenated silicon carbide.

16. The back contact structure according to claim 4, wherein: The first dielectric layer is a tunneling oxide layer and an intrinsic silicon carbide layer.

17. The back contact structure according to claim 4 or 16, characterized in that: The tunneling oxide layer is composed of one or more layers of a silicon oxide layer and an aluminum oxide layer.

18. The back contact structure according to claim 4 or 16, characterized in that The intrinsic silicon carbide layer in the first dielectric layer includes an intrinsic hydrogenated silicon carbide layer.

19. The back contact structure according to claim 5, wherein: The second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

20. The back contact structure according to claim 19, wherein: The thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

21. The back contact structure according to claim 5 or 19, characterized in that The intrinsic silicon carbide layer in the second dielectric layer is composed of at least one first intrinsic silicon carbide film having a different refractive index.

22. The back contact structure according to claim 21, wherein: The refractive index of each layer of the first intrinsic silicon carbide film decreases sequentially from the back side of the silicon substrate toward the outside.

23. The back contact structure according to claim 4, wherein: The outer layer of the second dielectric layer is further provided with a magnesium fluoride layer.

24. The back contact structure according to claim 1, wherein: The conductive layer is a TCO transparent conductive film and / or a metal electrode.

25. The back contact structure according to claim 24, wherein: The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode or a silver-clad copper electrode.

26. The back contact structure according to claim 25, wherein: The copper electrode is electroplated copper prepared by an electroplating process or a copper electrode prepared by physical vapor deposition.

27. The back contact structure according to claim 9, wherein: The first dielectric layer corresponding to the first doped region and the first dielectric layer corresponding to the second doped region are the same as or different from each other.

28. A selective contact region buried type solar cell, characterized in that: include: Silicon substrate; A back contact structure according to any one of claims 1 to 27 provided on the back side of a silicon substrate; and A third dielectric layer is provided on the front surface of the silicon substrate.

29. The selective contact region buried type solar cell according to claim 28, wherein: The third dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

30. The selective contact region buried type solar cell according to claim 29, wherein: The third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

31. The selective contact region buried type solar cell according to claim 29, wherein: The thickness of the aluminum oxide layer or the silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

32. The selective contact region buried type solar cell according to claim 29 or 30, wherein: The intrinsic silicon carbide layer in the third dielectric layer is composed of at least one second intrinsic silicon carbide film having a different refractive index.

33. The selective contact region buried type solar cell according to claim 32, wherein: The refractive index of each layer of the second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate toward the outside.

34. The selective contact region buried type solar cell according to claim 29, wherein: The outer layer of the third dielectric layer is further provided with a magnesium fluoride layer.

35. The selective contact region buried type solar cell according to claim 28, wherein: An electric field layer or a floating junction is further provided between the front surface of the silicon substrate and the third dielectric layer.

36. A battery assembly, characterized in that: The battery assembly includes the selective contact area buried solar cell according to any one of claims 28 to 35.

37. A photovoltaic system, characterized in that: The photovoltaic system includes the battery assembly according to claim 36.

38. A method for manufacturing a selective contact region buried type solar cell, applied to the manufacturing of a selective contact region buried type solar cell according to any one of claims 28 to 35, characterized in that: The method comprises: A plurality of grooves are formed on the back side of the silicon substrate; forming a first dielectric layer on the back side of the silicon substrate; Prepare a first doped region and a second doped region inside and outside each of the grooves respectively; forming a second dielectric layer and a third dielectric layer on the back and front sides of the silicon substrate respectively; A conductive layer is formed on the first doping region and the second doping region.

39. The method for manufacturing a selective contact region buried solar cell according to claim 38, wherein: The step of preparing the first doped region and the second doped region inside and outside each of the grooves respectively includes: depositing intrinsic amorphous silicon or intrinsic silicon carbide inside and outside each groove; Doping with different doping types is performed alternately inside and outside each groove; High-temperature crystallization treatment is performed to convert intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region arranged in the groove and a second doped region arranged outside the groove.

40. The method for manufacturing a selective contact region buried solar cell according to claim 38, wherein: The step of preparing the first doped region and the second doped region inside and outside each of the grooves respectively includes: depositing intrinsic amorphous silicon or intrinsic silicon carbide inside and outside each groove; Different types of diffusion are alternately performed inside and outside each groove through a mask to convert intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, thereby obtaining a first doped region arranged inside the groove and a second doped region arranged outside the groove.

41. The method for manufacturing a selective contact region buried solar cell according to claim 38, wherein: The step of preparing the first doped region and the second doped region inside and outside each of the grooves respectively includes: Alternately depositing doped amorphous silicon or doped amorphous silicon carbide of different doping types inside and outside each groove; High-temperature crystallization treatment is performed to convert the doped amorphous silicon or doped amorphous silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region arranged in the groove and a second doped region arranged outside the groove.

42. The method for manufacturing a selective contact region buried solar cell according to claim 39, wherein: The step of alternately performing doping of different doping types inside and outside each groove comprises: Alternately implanting first type ions and second type ions into the inside and outside of each groove; or Alternately depositing a first type dopant source and a second type dopant source inside and outside each groove; or The first type source gas and the second type source gas are alternately introduced into the inside and outside of each groove for doping.

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