A selective contact area buried solar cell and its back contact structure

Abstract

The present invention, applicable to the field of solar cell technology, provides a selective contact region buried solar cell and its back contact structure. The back contact structure comprises grooves spaced apart on the back side of a silicon substrate; first and second conductive regions alternately disposed in each groove, the first conductive region comprising a first dielectric layer and a first doped region sequentially disposed on the groove, and the second conductive region comprising a second doped region; a second dielectric layer disposed between the first and second conductive regions, the second dielectric layer being at least one layer; and a conductive layer disposed on the first and second conductive regions. The back contact structure provided by the present invention addresses the existing issues of high trench width control requirements and poor passivation performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a selective contact area buried solar cell and a back contact structure thereof. Background Art

[0002] In crystalline silicon solar cells, the efficiency loss of the cell can be divided into two aspects: electrical loss and optical loss. The important components of electrical loss are recombination loss and resistance loss caused by metal-semiconductor contact, while the important component of optical loss is the obstruction of the metal grid line on the light-receiving surface.

[0003] The passivated metal contact structure exhibits remarkable electrical properties, achieving both low contact resistivity and low surface recombination. This structure consists of an ultrathin tunneling oxide layer and an N-type or P-type doped polysilicon layer. Because the doped polysilicon layer's absorption of light is parasitic and therefore does not contribute to the photocurrent, the passivated metal contact structure is often used on the back of the cell, completely eliminating the obstruction of the metal grid lines on the front surface. Solar radiation received by the solar cell generates electrons and holes, which migrate to the doped polysilicon layer, generating a voltage difference between the doped polysilicon layers. A solar cell can be constructed by combining the aforementioned passivated metal contact structure and the passivated metal contact structure, or by combining the aforementioned passivated metal contact structure and a diffusion structure.

[0004] The existing passivation metal contact structure and diffusion structure are deposited directly on the back of the silicon wafer. However, when they are connected together without a barrier, leakage and other undesirable phenomena will occur. Therefore, to solve the above-mentioned problem caused by the lack of barrier, a very narrow groove is opened between the passivation metal contact structure and the diffusion structure to separate the passivation metal contact structure and the diffusion structure, thereby avoiding leakage and reducing the open circuit voltage of the battery. However, the existing groove is prepared by laser drilling or wet etching. At this time, the existing groove width is tens of microns, and the width control requirements are high, making preparation difficult. Only a single layer of dielectric layer is used for passivation. However, the use of a single layer of dielectric layer for passivation has poor passivation effect and poor internal back reflection effect. Summary of the Invention

[0005] An object of the embodiments of the present invention is to provide a back contact structure for a solar cell, aiming to solve the existing problems of high requirements for trench width control and poor passivation effect.

[0006] The embodiment of the present invention is implemented as follows: a back contact structure of a solar cell, comprising:

[0007] grooves arranged at intervals on the back side of the silicon substrate;

[0008] A first conductive region and a second conductive region are alternately arranged in each of the grooves, wherein the first conductive region includes a first dielectric layer and a first doped region sequentially arranged on the groove, and the second conductive region includes a second doped region;

[0009] a second dielectric layer disposed between the first conductive region and the second conductive region, wherein the second dielectric layer is at least one layer; and

[0010] A conductive layer is disposed on the first conductive region and the second conductive region.

[0011] Furthermore, the first doped region is a P-type doped region, and the second doped region is an N-type doped layer; or

[0012] The first doping region is an N-type doping region, and the second doping region is a P-type doping layer.

[0013] Furthermore, the first doped region includes doped polysilicon, doped silicon carbide, or doped amorphous silicon.

[0014] Furthermore, the first dielectric layer is a combination of one or more of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer.

[0015] Furthermore, the second dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0016] Furthermore, the second dielectric layer covers the area between the first conductive region and the second conductive region, or extends to cover the first conductive region and / or the second conductive region.

[0017] Furthermore, the back surface of the silicon substrate located between the first conductive region and the second conductive region has a rough texture structure.

[0018] Furthermore, a first doped layer having the same conductivity type as that of the first doped region is provided in the silicon substrate located in the region between the first conductive region and the second conductive region.

[0019] Furthermore, the first dielectric layer covers the bottom wall and sidewall of the groove, or extends to cover the area between each groove.

[0020] Furthermore, the first doped region and / or the second doped region extends to a portion of the region between the grooves.

[0021] Furthermore, the groove is arc-shaped, trapezoidal, or square.

[0022] Furthermore, the thickness of the first dielectric layer is 1-20 nm, and the thickness of the first conductive region is greater than 20 nm.

[0023] Furthermore, the junction depth of the second doped region is 0.01-1 μm, the square resistance is 10-500 ohm / sqr, and the surface concentration is 1E18-1E21 cm -3 .

[0024] Furthermore, the depth of each groove is 0.01-10 μm, and the distance between each groove is 20-500 μm.

[0025] Furthermore, the groove width of the P-type doping region is set to 300-600 um, or the groove width of the N-type doping region is set to 100-500 um.

[0026] Furthermore, the doped silicon carbide includes doped hydrogenated silicon carbide.

[0027] Furthermore, the first dielectric layer is a tunneling oxide layer and an intrinsic silicon carbide layer.

[0028] Furthermore, the tunneling oxide layer is composed of one or more layers of a silicon oxide layer and an aluminum oxide layer.

[0029] Furthermore, the intrinsic silicon carbide layer in the first dielectric layer includes an intrinsic hydrogenated silicon carbide layer.

[0030] Furthermore, the second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

[0031] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

[0032] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer is composed of at least one first intrinsic silicon carbide film with different refractive indexes.

[0033] Furthermore, the refractive index of each layer of the first intrinsic silicon carbide film decreases sequentially from the back side of the silicon substrate toward the outside.

[0034] Furthermore, the outer layer of the second dielectric layer is further provided with a magnesium fluoride layer.

[0035] Furthermore, the conductive layer is a TCO transparent conductive film and / or a metal electrode.

[0036] Furthermore, the metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode or a silver-clad copper electrode.

[0037] Furthermore, the copper electrode is an electroplated copper prepared by an electroplating process or a copper electrode prepared by physical vapor deposition.

[0038] Another embodiment of the present invention is also directed to providing a selective contact region buried solar cell, comprising:

[0039] Silicon substrate;

[0040] A back contact structure as described above provided on the back side of the silicon substrate; and

[0041] A third dielectric layer is provided on the front surface of the silicon substrate.

[0042] Furthermore, the third dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0043] Furthermore, the third dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0044] Furthermore, the third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

[0045] Furthermore, the thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

[0046] Furthermore, the intrinsic silicon carbide layer in the third dielectric layer is composed of at least one second intrinsic silicon carbide film with a different refractive index.

[0047] Furthermore, the refractive index of each layer of the second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate toward the outside.

[0048] Furthermore, the outer layer of the third dielectric layer is further provided with a magnesium fluoride layer.

[0049] Another embodiment of the present invention aims to provide a battery assembly, which includes the selective contact area buried solar cell as described above.

[0050] Another embodiment of the present invention aims to provide a photovoltaic system, which includes the battery assembly described above.

[0051] Another embodiment of the present invention is also directed to providing a method for manufacturing a selective contact region buried solar cell, the method comprising:

[0052] A plurality of grooves are formed on the back side of the silicon substrate;

[0053] preparing first conductive regions and second conductive regions alternately arranged in each of the grooves, wherein the first conductive regions include a first dielectric layer and a first doped region sequentially arranged on the grooves, and the second conductive regions include a second doped region;

[0054] forming a second dielectric layer and a third dielectric layer on the back and front sides of the silicon substrate respectively;

[0055] A conductive layer is formed on the first conductive region and the second conductive region.

[0056] Furthermore, the step of preparing the first conductive areas and the second conductive areas alternately arranged in each of the grooves includes:

[0057] sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove;

[0058] A second doped region having a second conductivity type is prepared in a second groove adjacent to the first groove, where the first conductivity type is opposite to the second conductivity type.

[0059] Furthermore, the step of sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove includes:

[0060] preparing a first dielectric layer in the first groove;

[0061] depositing intrinsic amorphous silicon or intrinsic silicon carbide on the first dielectric layer;

[0062] Doping the intrinsic amorphous silicon or intrinsic silicon carbide with a first conductivity type;

[0063] A high-temperature crystallization process is performed to convert the intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region having a first conductivity type.

[0064] Furthermore, the step of sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove includes:

[0065] preparing a first dielectric layer in the first groove;

[0066] depositing intrinsic amorphous silicon or intrinsic silicon carbide on the first dielectric layer;

[0067] Diffusion of the first conductivity type is performed on the intrinsic amorphous silicon or the intrinsic silicon carbide to convert the intrinsic amorphous silicon or the intrinsic silicon carbide into doped polysilicon or doped silicon carbide, thereby obtaining a first doped region with the first conductivity type.

[0068] Furthermore, the step of sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove includes:

[0069] preparing a first dielectric layer in the first groove;

[0070] depositing doped amorphous silicon or doped amorphous silicon carbide of a first conductivity type on the first dielectric layer;

[0071] A high-temperature crystallization process is performed to convert the doped amorphous silicon or doped amorphous silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region having a first conductivity type.

[0072] Furthermore, the step of preparing a second doped region having a second conductivity type in a second groove adjacent to the first groove includes:

[0073] A source gas corresponding to the second conductivity type is introduced into the second groove for thermal diffusion to form a second doped region having the second conductivity type; or

[0074] Depositing or spin-coating a doping source corresponding to the second conductivity type in the second groove and performing thermal diffusion to form a second doped region having the second conductivity type; or

[0075] Ions corresponding to the second conductivity type are implanted into the second groove and thermally diffused to form a second doped region having the second conductivity type.

[0076] Furthermore, the step of doping the intrinsic amorphous silicon or intrinsic silicon carbide with the first conductivity type includes:

[0077] Implanting ion doping of the first conductivity type into the intrinsic amorphous silicon or intrinsic silicon carbide; or

[0078] depositing a dopant source of a first conductivity type on the intrinsic amorphous silicon or intrinsic silicon carbide; or

[0079] A source gas of the first conductivity type is introduced into the intrinsic amorphous silicon or the intrinsic silicon carbide for doping.

[0080] The back contact structure of a solar cell provided by an embodiment of the present invention is characterized by providing grooves at intervals on the back side of a silicon substrate, and alternately providing a first conductive region and a second conductive region in each groove, so that the first conductive region and the second conductive region in the groove can be blocked by the boss structure between the grooves of the silicon substrate itself. The width control requirements of the provided grooves are more relaxed than those of existing grooves, and the preparation is easier than that of existing grooves. The first dielectric layer and the first doped region are deposited in the grooves, and the deposition effect is better. At the same time, the first conductive region having the first dielectric layer and the first doped region is provided in one groove, and the second conductive region having the second doped region is provided in another adjacent groove, which can reduce the process steps. The cost is reduced; at the same time, due to the setting of the groove, the first dielectric layer is in contact with the bottom wall and side wall of the groove, so the carriers generated in the silicon substrate are also easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the longitudinal and lateral selective transport of carriers can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove; since the second dielectric layer is set as at least one layer, the back side of the silicon substrate is multi-layered passivated and the internal back reflection is enhanced through the at least one second dielectric layer, thereby bringing better passivation effect and internal back reflection effect, and solving the existing problems of high requirements for groove width control and poor passivation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figures 1 to 9 1 is a schematic structural diagram of various implementations of a selective contact region buried solar cell provided by one embodiment of the present invention;

[0082] Figure 10 This is a flow chart of a method for manufacturing a selective contact region buried solar cell provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0083] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0084] In the present invention, unless otherwise expressly specified or limited, the terms "installed," "connected," "connected," "fixed," and the like should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0085] The present invention arranges grooves at intervals on the back side of the silicon substrate, and alternately arranges the first conductive region and the second conductive region in each groove, so that the first conductive region and the second conductive region in the groove can be blocked by the boss structure between the grooves of the silicon substrate itself. The width control requirements of the arranged grooves are looser than those of the existing grooves, and the preparation is easier than that of the existing grooves. The first dielectric layer and the first doped region are deposited in the grooves, and the deposition effect is better. At the same time, the first conductive region having the first dielectric layer and the first doped region is arranged in one groove, and the second conductive region having the second doped region is arranged in another adjacent groove, which can reduce the process steps and reduce costs. At the same time, due to the grooves The arrangement of the groove enables the first dielectric layer to contact both the bottom wall and the sidewalls of the groove. Therefore, carriers generated in the silicon substrate can be easily separated by the first dielectric layer on the sidewalls of the groove and selectively collected into the corresponding first doped region, thereby reducing leakage current and achieving selective carrier transport in the longitudinal and lateral directions, which is conducive to multi-dimensional collection of carriers in the bottom wall and sidewalls of the groove. Since the second dielectric layer is provided in at least one layer, the back side of the silicon substrate is multi-layered passivated and internal back reflection is enhanced through the at least one second dielectric layer, thereby achieving better passivation and internal back reflection effects, and solving the existing problems of high requirements for groove width control and poor passivation effect.

[0086] Example 1

[0087] The first embodiment of the present invention provides a back contact structure of a solar cell. For the sake of convenience, only the parts related to the embodiment of the present invention are shown. Figures 1-9 As shown, the back contact structure of the solar cell provided by the embodiment of the present invention includes:

[0088] Grooves are arranged at intervals on the back side of the silicon substrate 10;

[0089] First conductive regions 20 and second conductive regions 30 are alternately arranged in each groove, wherein the first conductive region 20 includes a first dielectric layer 21 and a first doped region 22 sequentially arranged on the groove, and the second conductive region 30 includes a second doped region;

[0090] a second dielectric layer 40 disposed between the first conductive region 20 and the second conductive region 30 , wherein the second dielectric layer 40 is at least one layer and has a refractive index that decreases from the back surface of the silicon substrate 10 outward; and

[0091] The conductive layer 50 is disposed on the first conductive region 20 and the second conductive region 30 .

[0092] In one embodiment of the present invention, the silicon substrate 10 has a front side that faces the sun during normal operation and a back side that is opposite to the front side. The front side is the light-receiving side. The back side is located on the other side of the silicon substrate 10 relative to the front side. In other words, the front side and the back side are located on different and opposite sides of the silicon substrate 10. In this embodiment, the silicon substrate 10 is an N-type silicon wafer. It will be understood that in other embodiments, the silicon substrate 10 may also be other silicon wafers. The back side of the silicon substrate 10 has grooves spaced apart. The grooves can be formed by laser ablation or by a combination of wet / dry etching using a mask (such as a hard mask, silicon oxide mask, silicon nitride mask, and photoresist mask). In this case, the grooves spaced apart on the back side of the silicon substrate 10 cause the area between two adjacent grooves in the silicon substrate 10 to generally form a platform. Therefore, the back side pattern of the silicon substrate 10 generally appears to be formed by an alternating arrangement of grooves and platforms.

[0093] Furthermore, in one embodiment of the present invention, a first conductive region 20 and a second conductive region 30 are alternately arranged in each groove. Specifically, the first conductive region 20 includes a first dielectric layer 21 and a first doped region 22 sequentially arranged on the groove, and the second conductive region 30 includes a second doped region. Further, in one embodiment of the present invention, the first doped region 22 and the second doped region have opposite conductivity types. If the first doped region 22 is a P-type doped region, the second doped region is an N-type doped layer; or if the first doped region 22 is an N-type doped region, the second doped region is a P-type doped layer.

[0094] Furthermore, in one embodiment of the present invention, the first dielectric layer 21 is located on the back side of the silicon substrate 10 and at least covers the groove in which it is located. The first dielectric layer 21 covering the groove in which it is located specifically refers to covering the bottom wall and side walls of the groove. Therefore, at this time, the first dielectric layer 21 is connected to the bottom wall and side walls of the groove. Alternatively, the first dielectric layer 21 can also extend to cover the area between each groove (i.e., the boss area), and even the first dielectric layer 21 can extend to cover the side wall of the groove where the second conductive region 30 is located, close to or adjacent to the second doped region. In one embodiment of the present invention, referring to Figure 1 As shown, the first dielectric layer 21 covers the groove in which it is located. In another embodiment of the present invention, referring to Figure 2 As shown, the first dielectric layer 21 covers the grooves and the areas between the grooves.

[0095] Furthermore, in one embodiment of the present invention, the first dielectric layer 21 is located between the silicon substrate 10 and the first doped region 22 provided in the groove, and is used as a tunneling structure; the first dielectric layer 21 and the first doped region 22 connected and covered therewith together form a passivation contact structure. The passivation contact structure provides good surface passivation for the back side of the silicon substrate 10. At the same time, generally speaking, the first dielectric layer 21 has a sufficiently thin thickness, in which one type of carrier is selectively transmitted through the tunneling principle, while the other type of carrier is difficult to tunnel through the first dielectric layer 21 due to the potential barrier and the field effect of the doped region. Therefore, the first dielectric layer 21 can allow one type of carrier to tunnel into the first doped region 22 while blocking the other type of carrier from passing through, thereby causing recombination, which can significantly reduce the recombination at the interface, so that the solar cell has a higher open circuit voltage and short circuit current, thereby increasing the photoelectric conversion efficiency. At the same time, as Figures 1 to 9 As shown, the surface where the silicon substrate 10 contacts the first dielectric layer 21 forms a plurality of inner diffusion regions corresponding to the first doped regions 22. Furthermore, in this embodiment, due to the provision of the groove, the first dielectric layer 21 contacts both the bottom and side walls of the groove. Therefore, carriers generated in the silicon substrate 10 are easily separated by the first dielectric layer 21 on the side walls of the groove and selectively collected in the first doped regions 22, thereby facilitating multi-dimensional collection of carriers in the bottom and side walls of the groove.

[0096] Furthermore, in one embodiment of the present invention, the first dielectric layer 21 is preferably a combination of one or more of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer. As some examples of the present invention, for example, the first dielectric layer 21 can be a tunneling oxide layer of a single material, or a combination of a tunneling oxide layer and an intrinsic amorphous silicon layer of multiple materials, or a combination of multiple layers of intrinsic amorphous silicon with different refractive indices of a single material. It can be understood that the specific structural arrangement of the first dielectric layer 21 includes but is not limited to the several methods listed above. The first dielectric layer 21 is set accordingly according to actual usage needs and is not specifically limited here.

[0097] In a preferred embodiment of the present invention, specifically, the first dielectric layer 21 is preferably a tunneling oxide layer and an intrinsic silicon carbide layer. In this case, the tunneling oxide layer and the intrinsic silicon carbide layer are arranged sequentially from the silicon substrate 10 outward, with the tunneling oxide layer contacting the back surface of the silicon substrate 10 within the groove, and the intrinsic silicon carbide layer contacting the first doped region 22. Furthermore, the tunneling oxide layer is preferably composed of one or more layers of a silicon oxide layer and an aluminum oxide layer; therefore, the first dielectric layer 21 can also be a combination of a silicon oxide layer and an aluminum oxide layer in the tunneling oxide layer. The intrinsic silicon carbide layer in the first dielectric layer 21 includes an intrinsic hydrogenated silicon carbide layer. In this case, the tunneling oxide layer and the intrinsic silicon carbide layer reduce the interface state density between the silicon substrate 10 and the first doped region 22 through chemical passivation. For example, hydrogen in the intrinsic hydrogenated silicon carbide layer enters the silicon substrate 10 under the action of the diffusion mechanism and thermal effect, neutralizing the dangling bonds on the back side of the silicon substrate 10 and passivating the defects on the back side of the silicon substrate 10, thereby transferring the energy band in the band gap into the valence band or conduction band, thereby increasing the probability of carriers passing through the first dielectric layer 21 into the first doped region 22.

[0098] Generally speaking, as some specific examples of the present invention, when used specifically, the first dielectric layer 21 preferably adopts a 1-2nm silicon oxide layer and a 2-5nm intrinsic silicon carbide layer. Compared with using only a silicon oxide layer as a tunneling structure, the intrinsic silicon carbide layer can also provide an additional hydrogen passivation effect, which increases the preparation process window of the tunneling structure without affecting the tunneling effect; of course, a 1-2nm silicon oxide layer, or a 1nm silicon oxide layer and a 1nm aluminum oxide layer, or 2 or more layers of intrinsic amorphous silicon layers with different refractive indices can also be directly used. It can be understood that the specific structural arrangement of the first dielectric layer 21 includes but is not limited to the several specific examples listed above. In addition, the first dielectric layer 21 can also be an intrinsic microcrystalline silicon layer, an intrinsic microcrystalline silicon oxide layer, an intrinsic amorphous silicon oxide layer, etc. Among them, as Figures 1-9 As shown, it only shows that the first dielectric layer 21 is a one-layer structure. It can be understood that the specific structure of the first dielectric layer 21 is set according to actual needs and is not completely in accordance with the figures shown in the specification.

[0099] Furthermore, in one embodiment of the present invention, the first doped region 22 preferably includes doped polysilicon, doped silicon carbide, or doped amorphous silicon; wherein the doped silicon carbide may include doped hydrogenated silicon carbide, and the doped hydrogenated silicon carbide is specifically formed by adding hydrogen when depositing silicon carbide. It should be noted that when the first dielectric layer 20 is the silicon oxide layer and the intrinsic silicon carbide layer described above, the first doped region 22 is specifically doped silicon carbide. When the first dielectric layer 20 is the silicon oxide layer or other combination described above, the first doped region 22 can be doped polysilicon, etc. When the first dielectric layer 20 is the intrinsic amorphous silicon layer described above, the first doped region is specifically doped amorphous silicon.

[0100] Furthermore, in one embodiment of the present invention, the first conductive region 20 composed of the first dielectric layer 21 and the first doped region 22 is set in the groove by deposition or other methods. At this time, the thickness of the first dielectric layer 21 is 1-20nm, and the thickness of the first conductive region 20 is greater than 20nm, that is, the total thickness of the first dielectric layer 21 and the first doped region 22 is greater than 20nm, and the depth of the groove is set to 0.01-10um, and the distance between each groove is 20-500um. Therefore, the total thickness of the first conductive region 20 can be greater than or less than or equal to the depth of the groove, that is, the first conductive region 20 can be set in the groove, or it can be set to extend out of the groove. It should be pointed out that in one embodiment of the present invention, if Figure 3As shown, when the first dielectric layer 21 covers the grooves and the platform areas extending between each groove, and the thickness of the first conductive region 20 is greater than the depth of the grooves, its first doped region 22 can also extend to the area between each groove. Specifically, the first doped region 22 can extend to part or all of the platform area. In this case, the first dielectric layer 21 and the first doped region 22 disposed on the platform area also form a passivation contact structure and are connected to the first dielectric layer 21 and the first doped region 22 in the grooves, thereby increasing the contact area of ​​the first dielectric layer 21 through which carriers selectively pass. It should be noted that when the first doped region 22 is a P-type doped region, the groove width of the P-type doped region is 300-600 μm; when the first doped region 22 is an N-type doped region, the groove width of the N-type doped region is 100-500 μm. As a preferred embodiment of the present invention, the groove width of the P-type doped region is preferably 500 μm; the groove width of the N-type doped region is preferably 300 μm, and the distance between each groove is preferably 100 μm. As can be seen from the above, the width of the grooves provided is more relaxed than the tens of microns required for conventional grooves, making the fabrication process easier than conventional grooves. It should also be noted that the width and depth of the grooves providing the first conductive region 20 and the grooves providing the second conductive region 30 can be the same or different, depending on actual use needs and are not specifically limited here.

[0101] Furthermore, in one embodiment of the present invention, the second conductive region 30 includes a second doped region, and the second doped region is a doped layer. It should be noted that its doped layer is different from the first conductive region 20 grown by deposition or other methods as described above in the groove. Its doped layer is a diffusion structure formed by doping different types of diffusion sources into the silicon substrate 10 at the bottom of the groove. Therefore, its doped layer does not grow in the groove, but the silicon substrate 10 at the bottom of the groove partially diffuses to become a doped layer. Therefore, its doped layer must be at the bottom of the groove, and the first conductive region 20 is located in an adjacent groove. At this time, the first conductive region 20 and the second conductive region 30 in different grooves can be blocked by the boss area between each groove. The junction depth of the second doped region is 0.01-1um, the square resistance is 10-500ohm / sqr, and the surface concentration is 1E18-1E21cm -3. At the same time, the second doping region can be a P-type doping layer or an N-type doping layer, which can be set as a doping layer of the opposite conductive type according to the specific conductive type of the first doping region 22, wherein the P-type doping layer is formed by diffusion of boron, aluminum, gallium, etc., and the N-type doping layer is formed by diffusion of nitrogen, phosphorus, arsenic, etc. At this time, the N-type doping layer is an N+ layer relative to the silicon substrate 10 which is specifically an N-type silicon wafer, that is, its doping layer is formed by local heavy doping. It should be pointed out that when the diffusion source is diffused to form a doping layer at the bottom of the groove, it may also diffuse to form a doping layer on the sidewall of the groove, so that its doping layer extends to part of the area between the grooves, for specific reference Figure 4 As shown, in one embodiment of the present invention, the first doping region 22 and / or the second doping region may extend to the partial area between each groove, that is, the first doping region 22 may extend from the groove to the partial area between each groove; or the second doping region may extend from the side wall of the groove to the partial area between each groove; or the first doping region 22 may extend from the groove to the partial area between each groove, and the second doping region may extend from the side wall of the groove to the partial area between each groove.

[0102] Furthermore, in one embodiment of the present invention, the second dielectric layer 40 covers the area between the first conductive region 20 and the second conductive region 30, or extends to cover the first conductive region 20 and / or the second conductive region 30. In other words, the second dielectric layer 40 may only cover the area between the first conductive region 20 and the second conductive region 30 (i.e., on the platform of the silicon substrate 10), referring to Figure 5 As shown, correspondingly, at this time, the conductive layer 50 covers the entire back surface of the first conductive area 20 and the second conductive area 30 for electrical connection; the second dielectric layer 40 can also extend from the boss to cover the first conductive area 20 and / or the second conductive area 30, for specific reference Figure 1 As shown, accordingly, the second dielectric layer 40 can extend from the boss to cover a portion of the first conductive region 20, or extend from the boss to cover a portion of the second conductive region 30, or extend from the boss to cover a portion of the first conductive region 20 and the second conductive region 30. In this case, the conductive layer 50 covers the remaining portion of the back surface of the first conductive region 20 and the second conductive region 30 that is not covered by the second dielectric layer 40, thereby forming electrical connections with the first conductive region 20 and the second conductive region 30, respectively. Of course, the second dielectric layer 40 can also completely cover the entire back surface of the back contact structure during the preparation process. In this case, when preparing the conductive layer 50, the conductive layer 50 is penetrated through the second dielectric layer 40 by means of perforations, etc., thereby forming electrical connections with the first conductive region 20 and the second conductive region 30, respectively.

[0103] It should be noted that when the first dielectric layer 21 only covers the corresponding groove, the second dielectric layer 40 directly contacts the back surface of the boss in the silicon substrate 10, which can be referred to Figure 1 When the first dielectric layer 21 covers the corresponding grooves and the areas between the grooves, the second dielectric layer 40 contacts the first dielectric layer 21. Figure 2 shown.

[0104] Furthermore, in one embodiment of the present invention, the second dielectric layer 40 is preferably a combination of one or more of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer. The second dielectric layer 40 has a passivation effect, and the second dielectric layer 40 is at least a layer structure, and the refractive index of each layer is arranged to decrease from the silicon substrate 10 outward, so that the film layer close to the silicon substrate 10 has a passivation effect, while the film layer away from the silicon substrate 10 has an anti-reflection effect, so that the anti-reflection effect can be enhanced, thereby increasing the absorption and utilization of light by the silicon substrate 10, thereby increasing the short-circuit current density. In addition, the second dielectric layer 40 can also be a doped silicon layer (such as a doped microcrystalline silicon layer, a doped amorphous silicon layer, or a doped polycrystalline silicon layer), a doped silicon carbide layer (such as a doped polycrystalline silicon carbide layer), a doped silicon oxide layer (such as a doped polycrystalline silicon oxide or a doped amorphous silicon oxide), etc. In addition, each layer of the film with different structures in the second dielectric layer 40 can also be composed of a multilayer film with different refractive indices, and the refractive index of each film layer can be arranged in a manner that decreases from the silicon substrate 10 outward as described above. For example, the silicon oxide layer in the second dielectric layer 40 can be composed of a multilayer silicon oxide film with a refractive index that decreases from the silicon substrate 10 outward.

[0105] According to the above, as some specific examples of the present invention, for example, the second dielectric layer 40 can be a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer, an intrinsic silicon carbide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / aluminum oxide layer located on the inner first layer is greater than 0.5 nm, the thickness of the intrinsic silicon carbide layer located on the second layer is greater than 1 nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located on the outer third layer is greater than 50 nm.

[0106] As some specific examples of the present invention, for example, the second dielectric layer 40 can also be a two-layer structure consisting of an aluminum oxide layer and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the aluminum oxide layer located on the inner first layer is greater than 1 nm; the thickness of the silicon nitride layer / silicon oxynitride layer located on the outer second layer is greater than 50 nm.

[0107] As some specific examples of the present invention, for example, the second dielectric layer 40 can also be a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer, a doped polysilicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / aluminum oxide layer located in the first inner layer is 0.5-3nm, the thickness of the doped polysilicon layer / doped polycrystalline silicon carbide layer / doped polycrystalline silicon oxide layer located in the second layer is 20-100nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50nm.

[0108] As some specific examples of the present invention, for example, the second dielectric layer 40 can also be a three-layer structure consisting of an intrinsic amorphous silicon layer, a doped amorphous silicon layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the intrinsic amorphous silicon layer located in the first inner layer is 2-10nm, the thickness of the doped amorphous silicon layer / doped amorphous silicon oxide layer located in the second layer is 2-50nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50nm.

[0109] As some specific examples of the present invention, for example, the second dielectric layer 40 can also be a three-layer structure consisting of a silicon oxide layer / aluminum oxide layer, an intrinsic silicon carbide layer / doped amorphous silicon oxide layer, and a silicon nitride layer / silicon oxynitride layer. In this case, the thickness of the silicon oxide layer / aluminum oxide layer located in the first inner layer is 0.5-3nm, the thickness of the intrinsic silicon carbide layer / doped amorphous silicon oxide layer located in the second layer is 10-50nm, and the thickness of the silicon nitride layer / silicon oxynitride layer located in the third outer layer is greater than 50nm.

[0110] It is understood that the specific structural arrangement of the second dielectric layer 40 includes but is not limited to the several specific examples listed above. Figure 1 As shown, the second dielectric layer 40 is preferably a two-layer structure of an aluminum oxide layer and an intrinsic silicon carbide layer, or a two-layer structure of a silicon oxide layer and an intrinsic silicon carbide layer. At this time, the overall thickness of the second dielectric layer 40 is greater than 25nm, of which the thickness is generally 70-80nm during normal production and preparation. At this time, the intrinsic silicon carbide layer not only provides a hydrogen passivation effect, but also reduces parasitic light absorption due to its large optical band gap and small absorption coefficient compared to the intrinsic amorphous silicon layer, the doped polycrystalline silicon layer, etc. Furthermore, the thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer 40 is less than 25nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer 40 is greater than 10nm. It should be pointed out that in the multi-layer structures pointed out in the embodiments of the present invention, the order is arranged from the silicon substrate 10 to the outside. For example, when the second dielectric layer 40 mentioned above is an aluminum oxide layer and an intrinsic silicon carbide layer, the aluminum oxide layer is close to the silicon substrate 10, and the intrinsic silicon carbide layer is close to the outside. It should also be pointed out that in the drawings of the specification, as Figures 1-9As shown, it only shows that the second dielectric layer 40 has a two-layer structure. It is understandable that the second dielectric layer 40 can also have other numbers of layers. Its specific structure is set according to actual needs and does not completely follow the drawings in the specification. It should also be pointed out that in the various drawings of the present invention, it is only used to describe the specific structural distribution of the back contact structure, but it does not correspond to the actual size of each structure. For example, the thickness of the first dielectric layer 21 described above is 1-20nm, and the thickness of the second dielectric layer 40 is greater than 25nm. The drawings do not completely correspond to the actual size of the embodiment, and should be based on the specific parameters provided in the embodiment.

[0111] Furthermore, the intrinsic silicon carbide layer in the second dielectric layer 40 is composed of at least one first intrinsic silicon carbide film with different refractive indices. The refractive index of each first intrinsic silicon carbide film decreases from the back of the silicon substrate 10 to the outside. Optionally, the refractive indices of the above-mentioned various materials can generally be selected as follows: the refractive index of single-crystalline silicon is 3.88; the refractive index of amorphous silicon is 3.5-4.2; the refractive index of polycrystalline silicon is 3.93, the refractive index of silicon carbide is 2-3.88, the refractive index of silicon nitride is 1.9-3.88, the refractive index of silicon oxynitride is 1.45-3.88, the refractive index of silicon oxide is 1.45, and the refractive index of aluminum oxide is 1.63. It can be understood that the refractive indices of the above-mentioned various materials can also be set to other values ​​according to actual use needs, and are not specifically limited here.

[0112] Furthermore, in one embodiment of the present invention, the outer layer of the second dielectric layer 40 is further provided with a magnesium fluoride layer. That is, in addition to the aforementioned combination of the aluminum oxide layer, silicon nitride layer, silicon oxynitride layer, intrinsic silicon carbide layer, intrinsic amorphous silicon layer, and silicon oxide layer selected for the second dielectric layer 40, the outer layer of the second dielectric layer 40 may further be provided with a magnesium fluoride layer. The refractive index of the magnesium fluoride layer is required to be the lowest, generally set at 1.4, and is used to enhance the optical anti-reflection effect.

[0113] Furthermore, in one embodiment of the present invention, the conductive layer 50 is a TCO transparent conductive film and / or a metal electrode. The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode, or a silver-clad copper electrode. Furthermore, the copper electrode is an electroplated copper electrode prepared by an electroplating process or a copper electrode prepared by physical vapor deposition. The electroplated copper electrode uses a nickel, chromium, titanium, or tungsten electrode as its seed layer or protective layer.

[0114] Furthermore, in one embodiment of the present invention, each groove is arc-shaped, trapezoidal, or square. It should be noted that the groove for setting the first conductive area 20 and the groove for setting the second conductive area 30 may be the same or different, for example Figure 1As shown in FIG, in one embodiment, each groove may be square. As shown in FIG, in another embodiment, the groove for setting the first conductive area 20 is arc-shaped, while the groove for setting the second conductive area 30 is square. Figure 7 As shown, in another specific embodiment, the groove for providing the first conductive region 20 is trapezoidal, while the groove for providing the second conductive region 30 is square. The grooves are preferably configured in an arc or trapezoidal shape. Arc or trapezoidal shapes provide better light reflection from the inner walls of the grooves, and also increase the surface area of ​​contact between the corresponding first and second conductive regions 20 and 30 and the silicon substrate 10 at the bottom of the grooves. Of course, square grooves simplify the actual production process, and therefore can be configured in a square shape. The specific shape of each groove is determined based on actual usage requirements and is not specifically limited here.

[0115] It should be pointed out that in other embodiments of the present invention, in the groove in which the first conductive region 20 is provided, there is a possibility that the first dielectric layer 21 is connected to the bottom wall of the groove, and the second dielectric layer 40 is also connected to the side wall of the groove. This is mainly because when a mask is used to cover the groove area, the silicon in the silicon substrate 10 next to the first conductive region 20 will be corroded during subsequent mask removal, thereby expanding the width of the groove. When the second dielectric layer 40 is subsequently deposited, the second dielectric layer 40 will be deposited in the empty area, so that the second dielectric layer 40 is connected to the side wall of the groove. Alternatively, when preparing an arc-shaped groove (such as an elliptical groove), it may be impossible to deposit the first dielectric layer 21 and the first doped region 22 on the inner wall of the arc-shaped groove in the long axis direction. Therefore, when depositing the second dielectric layer 40, it will fill the empty area, so that the second dielectric layer 40 is connected to the sidewall of the arc-shaped groove. Alternatively, it may be impossible to deposit the second dielectric layer 40 in the empty area, resulting in a certain gap between the sidewall of the arc-shaped groove and the first dielectric layer 21 and the first doped region 22. Of course, it should be pointed out that in the embodiment of the present invention, the back contact structure preferably has the first dielectric layer 21 directly connected to the sidewall of the groove, which can enable the first dielectric layer 21 disposed on the sidewall of the groove to selectively pass carriers and achieve multi-dimensional collection.

[0116] Further, in one embodiment of the present invention, referring to Figure 8As shown, a first doped layer 60 of the same conductivity type as the first doped region 22 is provided in the silicon substrate 10 located between the first conductive region 20 and the second conductive region 30. In other words, a first doped layer 60 is provided in each platform of the silicon substrate 10. The first doped layer 60 can be provided on the entire platform or on a portion of the platform. The first doped layer 60 can be a P-type diffusion layer or an N-type diffusion layer, depending on the conductivity type of the first doped region 22. For example, if the first doped region 22 is a P-type doped region, the first doped layer 60 is a P-type diffusion layer. Because the first dielectric layer 21 is provided on the sidewalls of the groove, and the first doped layer 60 is formed by diffusion in the portion of the silicon substrate 10 located at the platform, carriers in the first doped layer 60 are more easily selectively separated by the first dielectric layer 21 in the adjacent groove sidewalls and collected in the corresponding first doped region 22.

[0117] Further, in one embodiment of the present invention, referring to Figure 9 As shown, the back side of the silicon substrate 10 located between the first conductive region 20 and the second conductive region 30 has a rough texture structure 70. That is, the rough texture structure 70 is present on the surface of the boss of the silicon substrate 10. When the first dielectric layer 21 only covers the corresponding grooves, the rough texture structure 70 is located at the position where the second dielectric layer 40 contacts the back side of the silicon substrate 10. When the first dielectric layer 21 covers the corresponding grooves and the areas between the grooves, the rough texture structure 70 is located at the position where the first dielectric layer 21 contacts the back side of the silicon substrate 10. The rough texture structure 70 is usually formed by texturing, which can be an irregular hemispherical texture formed by acid texturing, a pyramid-shaped texture formed by alkali texturing, or a pyramid-shaped texture formed by alkali texturing followed by acid texturing to smooth the pyramid tip. It can be understood that the rough texture structure 70 can also be set to the entire back side of the silicon substrate 10, that is, the silicon substrate 10 located in the groove also has a rough texture structure 70. In this case, the entire back side of the silicon substrate 10 after the groove is formed can be textured directly, and there is no need for a subsequent process to remove the rough texture structure 70 in the groove, which simplifies the process. However, it should be pointed out that in this embodiment, it is preferred to texture only the surface of the boss of the silicon substrate 10, so as to increase the reflection of the incident light inside the silicon substrate 10, thereby increasing the absorption rate of light, and the inner surface of the groove is not textured. In this case, the entire back side of the silicon substrate 10 after the groove is prepared is textured directly, and then the rough texture structure 70 in the groove is removed by laser.

[0118] Tests have shown that the experimental group of cells fabricated using the back contact structure provided by the present invention, compared to the control group of cells fabricated using the conventional trench method, has a significantly improved conversion efficiency of approximately 25.7%, significantly enhancing reliability. The electrical performance results are shown in Table 1 below:

[0119] Table 1

[0120] Name UOC JSC FF EF Experimental group 728 41.8 84.4％ 25.7％ control group 720 41.6 84.3％ 25.2％

[0121] Compared with the existing embodiments, the embodiments of the present invention have the following advantages:

[0122] 1. Since grooves are arranged at intervals on the back side of the silicon substrate, and the first conductive region and the second conductive region are alternately arranged in each groove, the first conductive region and the second conductive region in the groove can be blocked by the boss structure between the grooves of the silicon substrate itself. The width control requirements of the grooves are more relaxed than those of existing grooves, and the preparation is easier than that of existing grooves. The first dielectric layer and the first doped region are deposited in the grooves, and the deposition effect is better. At the same time, the first conductive region having the first dielectric layer and the first doped region is arranged in one groove, and the second conductive region having the second doped region is arranged in another adjacent groove. This can reduce the process steps in the preparation process and reduce costs.

[0123] 2. Due to the setting of the groove, the first dielectric layer is in contact with the bottom wall and side walls of the groove. Therefore, the carriers generated in the silicon substrate can be easily separated by the first dielectric layer on the side walls of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the selective transport of carriers in the vertical and horizontal directions can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side walls of the groove.

[0124] 3. Since at least one second dielectric layer is provided, the back side of the silicon substrate is passivated by at least one second dielectric layer and the first dielectric layer, thereby achieving a better passivation effect. Furthermore, by controlling the refractive index of each layer to decrease from the silicon substrate outward, the reflection of long-wavelength light on the inner back side of the silicon substrate can be improved, thereby increasing the short-circuit current density.

[0125] 4. Since the groove has a certain depth, the hard mask only directly contacts the raised part between the two grooves, so that the hard mask will not directly contact the bottom of the groove, reducing impurity contamination. Therefore, it can play a certain protective role on the silicon substrate at the bottom wall of the groove. There is no need to worry about the hard mask causing damage to the silicon substrate. The damage caused by the hard mask contacting the convex surface of the silicon substrate can also be removed through the subsequent texturing process.

[0126] 5. In the process of selectively depositing the first doped area using a hard mask, since there is a silicon substrate boss structure with a certain width between each groove for isolation, when the hard mask covers one of the grooves and deposits another adjacent groove area, the alignment requirements for the hard mask do not need to be very precise, and a moderate deviation can be allowed, making the alignment of the hard mask simpler, thereby reducing the difficulty of the process.

[0127] 6. In the prior art, due to the limitations of width and depth of the groove area, the chemical solution cannot completely penetrate the bottom of the groove for chemical wet texturing due to the hydrophobicity of water and silicon wafers. In this embodiment, due to the provision of grooves, the back side of the silicon substrate between adjacent grooves is relatively a convex platform, which makes it easier to achieve texturing to obtain a rough texture structure than the existing groove structure. By texturing the convex platform on the back side of the silicon substrate, the reflection of light on the inner back side of the silicon substrate is increased, thereby increasing the light absorption rate of the silicon substrate.

[0128] 7. Since the first doped layer is provided in the region between each groove in the silicon substrate, the carriers in the first doped layer can be more easily selectively separated through the first dielectric layer in the adjacent groove sidewall and collected into the corresponding first doped region.

[0129] Example 2

[0130] The second embodiment of the present invention provides a selective contact region buried type solar cell. For ease of description, only the parts related to the embodiment of the present invention are shown. Figures 1-9 As shown, the selective contact region buried type solar cell provided by the embodiment of the present invention includes:

[0131] Silicon substrate 10;

[0132] The back contact structure described in the above embodiment is provided on the back side of the silicon substrate 10; and

[0133] A third dielectric layer 80 is provided on the front surface of the silicon substrate 10 .

[0134] Furthermore, in one embodiment of the present invention, the second dielectric layer 40 and the third dielectric layer 80 can be prepared by the same process on the front and back surfaces of the silicon substrate 10, respectively. In this case, the third dielectric layer 80 can have the same structure as the second dielectric layer 40 in the aforementioned embodiment. Therefore, with reference to the aforementioned embodiment, the third dielectric layer 80 can also preferably be one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

[0135] As some examples of the present invention, the third dielectric layer 80 can also be a three-layer structure consisting of a silicon oxide layer / an aluminum oxide layer and a doped polycrystalline silicon layer / a doped polycrystalline silicon carbide layer / a doped polycrystalline silicon oxide layer and a silicon nitride layer / a silicon oxynitride layer, or a three-layer structure consisting of an intrinsic amorphous silicon layer and a doped amorphous silicon layer / a doped amorphous silicon oxide layer and a silicon nitride layer / a silicon oxynitride layer, or a three-layer structure consisting of a silicon oxide layer / an aluminum oxide layer and an intrinsic silicon carbide layer / a doped amorphous silicon oxide layer and a silicon nitride layer / a silicon oxynitride layer.

[0136] Further, in a preferred embodiment of the present invention, referring to Figure 1 As shown, the third dielectric layer 80 is also preferably a two-layer structure of a silicon oxide layer and an intrinsic silicon carbide layer, or a two-layer structure of an aluminum oxide layer and an intrinsic silicon carbide layer. The thickness of the third dielectric layer 80 is greater than 50 nm. In this case, the intrinsic silicon carbide layer not only provides hydrogen passivation, but also reduces parasitic light absorption due to its large optical bandgap and low absorption coefficient compared to intrinsic amorphous silicon layers, doped polycrystalline silicon layers, etc. The thickness of the aluminum oxide layer or silicon oxide layer in the third dielectric layer 80 is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer 80 is greater than 10 nm. Furthermore, the intrinsic silicon carbide layer in the third dielectric layer 80 is composed of at least one second intrinsic silicon carbide film with a different refractive index. The refractive index of each second intrinsic silicon carbide film decreases from the front surface of the silicon substrate 10 outward. Furthermore, in one embodiment of the present invention, the outer layer of the third dielectric layer 80 is also provided with a magnesium fluoride layer. The refractive index of the outermost magnesium fluoride layer is required to be the lowest, and is generally set to 1.4, which is used to enhance the optical effect of anti-reflection.

[0137] Of course, the third dielectric layer 80 may also have a different structural arrangement from the second dielectric layer 40 in the aforementioned embodiment. The second dielectric layer 40 and the third dielectric layer 80 may have different film layer structures according to actual use needs, which is not specifically limited here.

[0138] Furthermore, in one embodiment of the present invention, an electric field layer or a floating junction is provided between the front surface of the silicon substrate 10 and the third dielectric layer 80. Specifically, the electric field layer is obtained by phosphorus diffusion on the silicon substrate 10, or the floating junction is obtained by boron diffusion on the silicon substrate 10. In this case, the electric field layer or the floating junction serves as the front surface electric field (FSF) of the buried solar cell in the selective contact area.

[0139] In this embodiment, grooves are arranged at intervals on the back side of the silicon substrate, and the first conductive region and the second conductive region are alternately arranged in each groove, so that the first conductive region and the second conductive region in the groove can be blocked by the boss structure between the grooves of the silicon substrate itself, and the width control requirements of the grooves are looser than those of the existing grooves, and the preparation is easier than that of the existing grooves, and the first dielectric layer and the first doped region are deposited in the grooves, and the deposition effect is better; at the same time, the first conductive region having the first dielectric layer and the first doped region is arranged in one groove, and the second conductive region having the second doped region is arranged in another adjacent groove, which can reduce the process flow in terms of preparation steps and reduce costs; at the same time, Due to the arrangement of the groove, the first dielectric layer is in contact with both the bottom wall and the side wall of the groove. Therefore, carriers generated in the silicon substrate are easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, thereby reducing leakage current and achieving selective carrier transport in the longitudinal and lateral directions, which is beneficial to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove. Since the second dielectric layer is provided in at least one layer, the back side of the silicon substrate is subjected to multi-layer passivation and enhanced internal back reflection through the at least one second dielectric layer, thereby achieving better passivation and internal back reflection effects, and solving the existing problems of high requirements for groove width control and poor passivation effect.

[0140] Example 3

[0141] The third embodiment of the present invention provides a method for manufacturing a selective contact region buried type solar cell. For ease of description, only the part related to the embodiment of the present invention is shown. Figure 10 As shown, the method for manufacturing a selective contact region buried type solar cell provided in an embodiment of the present invention is used to prepare the selective contact region buried type solar cell as described in the above embodiment. Specifically, the method includes:

[0142] Step S11, forming a plurality of grooves spaced apart on the back side of the silicon substrate;

[0143] Before step S11, the silicon substrate should also be pre-processed;

[0144] The above-mentioned pretreatment includes cleaning the silicon substrate and removing the damaged layer. Specifically, it includes:

[0145] (1) RCA standard cleaning to remove particles and organic matter on the surface of the silicon substrate;

[0146] (2) After cleaning the silicon substrate, place it in a 2-5% KOH alkaline solution (potassium hydroxide) or TMAH solution (tetramethylammonium hydroxide, i.e., developer) at a temperature of 50-80°C for 1-5 minutes to remove the surface damage layer caused by the slicing process;

[0147] (3) using HCl to pickle the surface of the silicon substrate to neutralize the alkali solution remaining on the surface of the silicon substrate and remove the metal impurities remaining on the surface of the silicon wafer;

[0148] (4) Cleaning the silicon substrate with HF solution to remove the silicon dioxide layer on the surface of the silicon wafer and form Si-H passivation bonds with the dangling bonds on the surface of the silicon substrate, and finally drying with nitrogen for later use.

[0149] Furthermore, after the silicon substrate is pre-processed, the grooves may be formed in the following ways:

[0150] Method 1: Directly groove at the desired intervals by laser to remove local silicon crystals on the back of the silicon substrate to form the desired grooves; Method 2: Thermally oxidize the silicon substrate to form a layer of silicon oxide on the entire surface of the silicon substrate, remove the silicon oxide in the local area on the front and back of the silicon substrate by laser groove, and then remove the silicon oxide by wet etching and acid (such as HF) to form the desired grooves; Method 3: Use PECVD to deposit a layer of silicon nitride on the back of the silicon substrate, remove the silicon nitride in the local area on the back by laser groove, and then remove the silicon nitride by wet etching. The desired groove is formed; Method 4: silicon nitride is deposited on the back of the silicon substrate or the silicon substrate is thermally oxidized to form silicon oxide, and then a photoresist mask is deposited on the back, and development is performed in the development area by patterning the screen and exposing, and the development area is wet-removed with a developer, and the silicon nitride / silicon oxide in the development area is removed with an acid (such as HF), and then the photoresist mask and silicon nitride / silicon oxide are wet-etched and removed to form the desired groove; Method 5: a patterned slurry is printed on the back of the silicon substrate as a mask, and then the slurry is wet-etched and removed to form the desired groove.

[0151] In the embodiment of the present invention, the groove is preferably formed using the second method. In the second method, the thermal oxidation treatment step specifically includes: performing dry oxygen oxidation / water vapor oxidation / wet oxygen oxidation (i.e., dry oxygen + water vapor) in a quartz tube, wherein the reactants are oxygen and / or high-purity water vapor, the reaction pressure is 50-1000 mbar, the reaction temperature is 900-1200°C, and the thickness of the silicon oxide produced by the reaction is greater than 10 nm. The laser groove removal step specifically includes: using a laser with a wavelength of 532 nm, a laser power of 10-60 W, a laser frequency of less than or equal to 250 to 1500 kHz, and a laser pulse width of 3-50 ns to groove and remove the silicon oxide to be removed. The wet etching step uses an alkaline solution and isopropyl ketone, wherein the alkaline solution is KOH or TMAH, the alkaline solution concentration is 1-5%, the isopropyl ketone content is 1-10%, the reaction temperature is 60-85°C, and the reaction time is 10-30 min. The acid solution in the step of removing silicon oxide with acid is HF, the concentration of the acid solution is 1-5%, the reaction temperature is room temperature, and the reaction time is 3-10 minutes.

[0152] Specifically, after the grooves are formed by the second method described above, the depth of each groove is 0.01-10 μm, and the distance between each groove is 20-500 μm. The grooves formed can be arc-shaped, trapezoidal, or square. In the prior art, the grooves are prepared by laser drilling or wet etching, which requires high control over the width of the grooves and is difficult to prepare. However, the groove preparation in this embodiment is easier than the existing groove preparation and does not have the strict width control requirements of the existing grooves.

[0153] Step S21, preparing a first conductive region and a second conductive region alternately arranged in each groove, wherein the first conductive region includes a first dielectric layer and a first doped region sequentially arranged on the groove, and the second conductive region includes a second doped region;

[0154] Before step S21, the specific production process may also include texturing the front side of the silicon substrate. In this embodiment, texturing the front side mainly adopts alkali corrosion, and the alkali reacts with the silicon substrate to generate a water-soluble compound, and at the same time forms a pyramid-shaped velvet structure on the surface. At this time, due to the presence of the velvet structure, after the incident light is reflected by the velvet for the first time, the reflected light is not directly incident into the air, but encounters the adjacent velvet surface, and is reflected by the velvet for the second or even third time before being incident into the air. In this way, the incident light is utilized multiple times, thereby reducing the front reflectivity. When the back side of the silicon substrate also needs to have a rough texture structure, the front and back sides of the silicon substrate can be texturized at the same time; and when the back side of the silicon substrate does not need to have a rough texture structure, a silicon nitride protective layer can be first deposited on the back side of the silicon substrate, and then the front side is texturized, and then the silicon nitride protective layer on the back side is removed by laser to avoid texturing the back side of the silicon substrate.

[0155] The alternating arrangement of the first conductive areas and the second conductive areas in each groove is achieved by the following steps:

[0156] sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove;

[0157] A second doped region having a second conductivity type is prepared in a second groove adjacent to the first groove, where the first conductivity type is opposite to the second conductivity type.

[0158] It should be pointed out that the conductivity type of the first doping region is opposite to the conductivity type of the second doping region. If the first doping region is a P-type doping region, the second doping region corresponds to an N-type doping layer; if the first doping region is an N-type doping region, the second doping region corresponds to a P-type doping layer.

[0159] Among them, since the steps of preparing the alternating first conductive regions and second conductive regions in each groove cannot be prepared simultaneously through the process flow, it is only possible to prepare the first conductive region first, then the second conductive region; or prepare the second conductive region first, then the first conductive region. Accordingly, the order of preparing the first conductive region and the second conductive region is set according to the convenience of the actual process flow and is not specifically limited here. Preferably, in this embodiment, the first conductive region is first prepared in the first groove for arranging the first conductive region, and then the second conductive region is prepared in the adjacent second groove for preparing the second conductive region.

[0160] Furthermore, the above-mentioned sequential preparation of the first dielectric layer and the first doped region with the first conductivity type in the first groove is specifically to first prepare the first dielectric layer in the first groove, and then prepare the first doped region with the first conductivity type on the first dielectric layer by two deposition methods, in-situ deposition or non-in-situ deposition. It should be pointed out that since it is impossible to achieve separate deposition of specific grooves during process manufacturing, the preparation of alternating first conductive regions and second conductive regions in each groove may be specifically to first prepare the first dielectric layer and the first doped region in sequence on the back side of the silicon substrate, and then remove the first dielectric layer and the first doped region in the second groove by laser or other means, and then prepare the second doped region in the second groove.

[0161] Specifically, the first dielectric layer is formed in the first groove by a high-temperature oxidation process or a deposition process. The first dielectric layer is arranged according to the type of the first dielectric layer deposited, which is not specifically limited here. In this case, the first dielectric layer is a combination of one or more of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer, and the thickness of the first dielectric layer is 1-20 nm. In this case, the first dielectric layer covers the entire back side of the silicon substrate. Therefore, it is necessary to remove the first dielectric layer in the second groove by means of a laser or the like. If it is also necessary to remove the first dielectric layer provided on the boss area between the first and second grooves, the first dielectric layer covering the boss area of ​​the silicon substrate can be further removed by means of a laser or the like.

[0162] Specifically, in one embodiment of the present invention, when the first doped region is prepared by in-situ deposition, the step of preparing the first doped region on the first dielectric layer includes:

[0163] depositing doped amorphous silicon or doped amorphous silicon carbide of a first conductivity type on the first dielectric layer;

[0164] A high-temperature crystallization process is performed to convert the doped amorphous silicon or doped amorphous silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region having a first conductivity type.

[0165] In one possible implementation, when in-situ deposition of a P-type doped region is performed on the first groove, a mask is used to cover the second groove that does not need to be deposited. At this time, P-type amorphous silicon / P-type amorphous silicon carbide is in-situ deposited in the first groove. Then, by directly using high temperature or laser heating methods, the temperature reaches 700-1000°C. As a result, under high temperature crystallization treatment, the P-type amorphous silicon / P-type amorphous silicon carbide in the first groove is converted into P-type polycrystalline silicon / P-type silicon carbide to obtain a P-type doped region, that is, a first doped region with a first conductivity type. It is correspondingly pointed out that because the groove has a certain depth, the mask is located in a position that conflicts with the boss and does not directly contact the bottom of the covered second groove, thereby reducing impurity contamination at the bottom of the second groove. The mask can be a hard mask, a silicon nitride mask, a silicon oxide mask, and a photoresist mask.

[0166] Specifically, in one embodiment of the present invention, when the first doped region is prepared by ex-situ deposition, the step of preparing the first doped region on the first dielectric layer includes:

[0167] depositing intrinsic amorphous silicon or intrinsic silicon carbide on the first dielectric layer;

[0168] Doping the intrinsic amorphous silicon or intrinsic silicon carbide with a first conductivity type;

[0169] A high-temperature crystallization process is performed to convert the intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region having a first conductivity type.

[0170] The step of doping the intrinsic amorphous silicon or intrinsic silicon carbide with the first conductivity type specifically includes:

[0171] Implanting ion doping of the first conductivity type into the intrinsic amorphous silicon or intrinsic silicon carbide; or

[0172] depositing a dopant source of a first conductivity type on the intrinsic amorphous silicon or intrinsic silicon carbide; or

[0173] A source gas of the first conductivity type is introduced into the intrinsic amorphous silicon or the intrinsic silicon carbide for doping.

[0174] In one of the possible implementation schemes, specifically, intrinsic amorphous silicon or intrinsic silicon carbide is first deposited on the first dielectric layer, and then ions of the first conductive type are implanted into the intrinsic amorphous silicon or intrinsic silicon carbide for doping (when the first doping region is a P-type doping region, P-type ions containing elements such as boron, aluminum, and gallium are implanted; and when the first doping region is an N-type doping region, N-type ions containing elements such as nitrogen, phosphorus, and arsenic are implanted); or a doping source of the first conductive type is deposited on the intrinsic amorphous silicon or intrinsic silicon carbide by a mask method for doping (when the first doping region is a P-type doping region, a P-type doping source containing boron, aluminum, gallium, etc. (such as borosilicate glass) is deposited for doping to form P-type amorphous silicon / P-type silicon carbide; and when the first doping region is an N-type doping region, an N-type doping source containing nitrogen, phosphorus, arsenic, etc. (such as phosphosilicate glass) is deposited for doping to form P-type amorphous silicon / P-type silicon carbide. ) is doped to form N-type amorphous silicon / N-type silicon carbide); or a first conductive type source gas is introduced into the intrinsic amorphous silicon or intrinsic silicon carbide through a mask method for doping (for example, when the first doping region is a P-type doping region, a P-type source gas containing elements such as boron, aluminum, and gallium (such as borane gas or a carrier gas carrying boron trichloride or boron tribromide) is introduced to dope to form P-type amorphous silicon / P-type silicon carbide; for example, when the first doping region is an N-type doping region, an N-type source gas containing elements such as nitrogen, phosphorus, and arsenic (such as phosphine gas or a carrier gas carrying phosphorus oxychloride) is introduced to dope to form N-type amorphous silicon / N-type silicon carbide), and further, after the doping is completed, a high-temperature crystallization treatment is performed to convert the intrinsic amorphous silicon or the intrinsic silicon carbide into doped polycrystalline silicon or doped silicon carbide to obtain a first doping region with the first conductive type. Since the deposited intrinsic amorphous silicon or intrinsic silicon carbide may be deposited on the side and front of the silicon substrate, a wet etching process is required after high-temperature crystallization to achieve de-coating. It should also be noted that after depositing the first conductivity type dopant source, performing doping and high-temperature crystallization, the dopant source needs to be removed using a laser or other method.

[0175] Specifically, in another embodiment of the present invention, when the first doped region is prepared by ex-situ deposition, the step of preparing the first doped region on the first dielectric layer further includes:

[0176] depositing intrinsic amorphous silicon or intrinsic silicon carbide on the first dielectric layer;

[0177] Diffusion of the first conductivity type is performed on the intrinsic amorphous silicon or the intrinsic silicon carbide to convert the intrinsic amorphous silicon or the intrinsic silicon carbide into doped polysilicon or doped silicon carbide, thereby obtaining a first doped region with the first conductivity type.

[0178] It should be pointed out that in the process of preparing the first doped region, due to the need for a high-temperature crystallization process, its thinner first dielectric layer will be partially broken. At this time, the high-temperature diffusion process will adhere to the broken parts of the first dielectric layer and the back side of the silicon substrate, so that the surface where the silicon substrate contacts the first dielectric layer forms multiple inner diffusion regions corresponding to the first doped region.

[0179] Furthermore, the step of preparing a second doped region having a second conductivity type in a second groove adjacent to the first groove includes:

[0180] A source gas corresponding to the second conductivity type is introduced into the second groove for thermal diffusion to form a second doped region having the second conductivity type; or

[0181] Depositing or spin-coating a doping source corresponding to the second conductivity type in the second groove and performing thermal diffusion to form a second doped region having the second conductivity type; or

[0182] Ions corresponding to the second conductivity type are implanted into the second groove and thermally diffused to form a second doped region having the second conductivity type.

[0183] Specifically, when the second doping region is a P-type doping layer, its specific preparation process includes: Method 1: introducing a source gas containing elements such as boron, aluminum, gallium, etc. (such as borane gas or a carrier gas carrying boron trichloride or boron tribromide) for thermal diffusion to form a P-type doping layer; Method 2: depositing a doping source containing boron, aluminum, gallium, etc. (such as borosilicate glass) for thermal diffusion to form a P-type doping layer; Method 3: preparing an aluminum electrode above the doping layer, and then forming a P-type doping layer doped with aluminum through a high-temperature process; Method 4: spin coating a doping source containing boron, aluminum, gallium, etc. (such as boron tribromide) for thermal diffusion to form a P-type doping layer; Method 5: injecting ions containing elements such as boron, aluminum, gallium, etc., and forming a P-type doping layer through high-temperature diffusion.

[0184] When the second doping region is an N-type doping layer, its specific preparation process is as follows: Method 1: introducing a source gas containing elements such as nitrogen, phosphorus, and arsenic (such as phosphine gas or a carrier gas carrying phosphorus oxychloride) for thermal diffusion to form an N-type doping layer; Method 2: depositing a doping source containing nitrogen, phosphorus, arsenic, etc. (such as phosphosilicate glass) for thermal diffusion to form an N-type doping layer; Method 3: spin coating a doping source containing nitrogen, phosphorus, arsenic, etc. (such as phosphorus oxychloride) for thermal diffusion to form an N-type doping layer; Method 4: injecting ions containing elements such as nitrogen, phosphorus, arsenic, etc., and forming an N-type doping layer through high-temperature diffusion. It should be pointed out that after the deposited doping source is thermally diffused, it is also necessary to remove the doping source by means of laser or other methods.

[0185] Step S31, forming a second dielectric layer and a third dielectric layer on the back and front sides of the silicon substrate respectively;

[0186] Among them, before this step S31, it can also include performing diffusion of the first conductive type at the boss position between each groove of the silicon substrate, so that a first doping layer with the same conductive type as the first doping region is diffused at the back boss position of the silicon substrate. The specific diffusion process can refer to the above description.

[0187] Furthermore, before step S41, the process may further include texturing the bosses between the grooves on the back side of the silicon substrate to obtain a rough texture structure. The specific texturing process may refer to the above description.

[0188] Specifically, during the process of forming the second and third dielectric layers on the back and front sides of the silicon substrate, respectively, the second and third dielectric layers are prepared based on their specific composition types, which are not specifically limited herein. Accordingly, the second and third dielectric layers can be one or more combinations of aluminum oxide layers, silicon nitride layers, silicon oxynitride layers, intrinsic silicon carbide layers, intrinsic amorphous silicon layers, and silicon oxide layers. Furthermore, when the second and third dielectric layers are arranged in a multilayer structure, the refractive index of each layer is arranged to decrease from the silicon substrate outward, and the outermost layer can also be a magnesium fluoride layer with the lowest refractive index requirement.

[0189] At the same time, before preparing the third dielectric layer on the front side of the silicon substrate, an electric field layer or a floating junction can also be prepared first. Specifically, the electric field layer is prepared by phosphorus diffusion on the silicon substrate, or the floating junction is prepared by boron diffusion. At this time, the electric field layer or the floating junction serves as the front surface electric field (FSF) of the buried solar cell in the selective contact area.

[0190] Step S41 : preparing a conductive layer on the first conductive region and the second conductive region.

[0191] Specifically, when the second dielectric layer only covers the area between the first conductive region and the second conductive region of the silicon substrate, the conductive layer covers the entire back side of the first conductive region and the second conductive region for electrical connection; when the second dielectric layer extends to cover the first conductive region and the second conductive region, the conductive layer covers the back side of the remaining portion of the first conductive region and the second conductive region that is not covered by the second dielectric layer for electrical connection; when the second dielectric layer covers the entire back side of the silicon substrate, the conductive layer is penetrated through the second dielectric layer by means of perforation or the like to be electrically connected to the first conductive region and the second conductive region, so that a first electrode is formed in the first conductive region and a second electrode is formed in the second conductive region.

[0192] Compared with the existing embodiments, the embodiments of the present invention have the following advantages:

[0193] 1. Since grooves are arranged at intervals on the back side of the silicon substrate, and the first conductive region and the second conductive region are alternately arranged in each groove, the first conductive region and the second conductive region in the groove can be blocked by the boss structure between the grooves of the silicon substrate itself. The width control requirements of the grooves are more relaxed than those of existing grooves, and the preparation is easier than that of existing grooves. The first dielectric layer and the first doped region are deposited in the grooves, and the deposition effect is better. At the same time, the first conductive region having the first dielectric layer and the first doped region is arranged in one groove, and the second conductive region having the second doped region is arranged in another adjacent groove. This can reduce the process steps in the preparation process and reduce costs.

[0194] 2. Due to the setting of the groove, the first dielectric layer is in contact with the bottom wall and side walls of the groove. Therefore, the carriers generated in the silicon substrate can be easily separated by the first dielectric layer on the side walls of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the selective transport of carriers in the vertical and horizontal directions can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side walls of the groove.

[0195] 3. Since at least one second dielectric layer is provided, the back side of the silicon substrate is passivated by at least one second dielectric layer and the first dielectric layer, thereby achieving a better passivation effect. Furthermore, by controlling the refractive index of each layer to decrease from the silicon substrate outward, the reflection of long-wavelength light on the inner back side of the silicon substrate can be improved, thereby increasing the short-circuit current density.

[0196] 4. Since the groove has a certain depth, the hard mask only directly contacts the raised part between the two grooves, so that the hard mask will not directly contact the bottom of the groove, reducing impurity contamination. Therefore, it can play a certain protective role on the silicon substrate at the bottom wall of the groove. There is no need to worry about the hard mask causing damage to the silicon substrate. The damage caused by the hard mask contacting the convex surface of the silicon substrate can also be removed through the subsequent texturing process.

[0197] 5. In the process of selectively depositing the first doped area using a hard mask, since there is a silicon substrate boss structure with a certain width between each groove for isolation, when the hard mask covers one of the grooves and deposits another adjacent groove area, the alignment requirements for the hard mask do not need to be very precise, and a moderate deviation can be allowed, making the alignment of the hard mask simpler, thereby reducing the difficulty of the process.

[0198] 6. In the prior art, due to the limitations of width and depth of the groove area, the chemical solution cannot completely penetrate the bottom of the groove for chemical wet texturing due to the hydrophobicity of water and silicon wafers. In this embodiment, due to the provision of grooves, the back side of the silicon substrate between adjacent grooves is relatively a convex platform, which makes it easier to achieve texturing to obtain a rough texture structure than the existing groove structure. By texturing the convex platform on the back side of the silicon substrate, the reflection of light on the inner back side of the silicon substrate is increased, thereby increasing the light absorption rate of the silicon substrate.

[0199] 7. Since the first doped layer is provided in the region between each groove in the silicon substrate, the carriers in the first doped layer can be more easily selectively separated through the first dielectric layer in the adjacent groove sidewall and collected into the corresponding first doped region.

[0200] Example 4

[0201] A fourth embodiment of the present invention further provides a battery assembly, which includes the selective contact region buried solar cell described in the above embodiment.

[0202] The battery assembly in this embodiment sets grooves on the back side of the silicon substrate by setting a selective contact area buried solar cell, and alternately sets the first conductive area and the second conductive area in each groove, so that the first conductive area and the second conductive area in the groove can be blocked by the boss structure between the grooves of the silicon substrate itself. The width control requirements of the grooves are looser than those of the existing grooves, and the preparation is easier than that of the existing grooves. The first dielectric layer and the first doped area are deposited in the grooves, and the deposition effect is better. At the same time, a first conductive area with a first dielectric layer and a first doped area is set in one groove, and a second conductive area with a second doped area is set in another adjacent groove, which can reduce the process steps. The process is simplified and the cost is reduced. At the same time, due to the provision of the groove, the first dielectric layer is in contact with both the bottom wall and the side wall of the groove. Therefore, the carriers generated in the silicon substrate are easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the longitudinal and lateral selective transport of carriers can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove. Since the second dielectric layer is provided in at least one layer, the back side of the silicon substrate is multi-layered passivated and the internal back reflection is enhanced through the at least one second dielectric layer, thereby bringing better passivation effect and internal back reflection effect, and solving the existing problems of high requirements for groove width control and poor passivation effect.

[0203] Example 5

[0204] A fifth embodiment of the present invention further provides a photovoltaic system, comprising the battery assembly as described in the above embodiments.

[0205] The photovoltaic system in this embodiment has grooves arranged at intervals on the back side of the silicon substrate through the selective contact area buried solar cell set by the battery assembly, and the first conductive area and the second conductive area are alternately arranged in each groove, so that the first conductive area and the second conductive area in the groove can be blocked by the boss structure between the grooves of the silicon substrate itself, and the width control requirements of the grooves are looser than those of the existing grooves, and the preparation is easier than that of the existing grooves, and the first dielectric layer and the first doped area are deposited in the grooves, and the deposition effect is better; at the same time, a first conductive area having a first dielectric layer and a first doped area is arranged in one groove, and a second conductive area having a second doped area is arranged in another adjacent groove, which can reduce the number of preparation steps. The invention reduces the number of process steps and reduces the cost. At the same time, due to the provision of the groove, the first dielectric layer is in contact with both the bottom wall and the side wall of the groove. Therefore, the carriers generated in the silicon substrate are easily separated by the first dielectric layer on the side wall of the groove and selectively collected into the corresponding first doped region, so that the leakage current can be reduced and the longitudinal and lateral selective transport of carriers can be achieved, which is conducive to the multi-dimensional collection of carriers in the bottom wall and side wall of the groove. Since the second dielectric layer is provided in at least one layer, the back side of the silicon substrate is multi-layered passivated and the internal back reflection is enhanced through the at least one second dielectric layer, thereby bringing about better passivation effect and internal back reflection effect, and solving the existing problems of high requirements for groove width control and poor passivation effect.

[0206] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A back contact structure of a solar cell, characterized in that: include: grooves arranged at intervals on the back side of the silicon substrate; a first conductive region and a second conductive region alternately disposed in each of the grooves, wherein the first conductive region comprises a first dielectric layer and a first doped region sequentially disposed on the grooves, the first dielectric layer and the first doped region connected and covered therewith jointly forming a passivation contact structure, the first dielectric layer being in contact with both the bottom wall and the sidewalls of the grooves, and the second conductive region comprising a second doped region; a second dielectric layer disposed between the first conductive region and the second conductive region, wherein the second dielectric layer is at least one layer; and a conductive layer disposed on the first conductive region and the second conductive region, The thickness of the multiple first conductive regions is less than the depth of the multiple grooves, and the first dielectric layer and the first doped region are enclosed in the multiple grooves. The second dielectric layer includes a first part, a second part and a third part. The first part covers the top surface of the first doped region, and the first part is arranged in the multiple grooves of the multiple first conductive regions. The second part covers the side walls of the multiple grooves of the multiple second conductive regions and the top surface of the second conductive region, and the second part is arranged in the multiple grooves of the multiple second conductive regions. The third part is arranged between the first part and the second part and covers the bosses between adjacent grooves.

2. The back contact structure according to claim 1, wherein: The first doped region is a P-type doped region, and the second doped region is an N-type doped layer; or The first doping region is an N-type doping region, and the second doping region is a P-type doping layer.

3. The back contact structure according to claim 1, wherein: The first doped region includes doped polysilicon, doped silicon carbide, or doped amorphous silicon.

4. The back contact structure according to claim 1, wherein: The first dielectric layer is one or more combinations of a tunneling oxide layer, an intrinsic silicon carbide layer, and an intrinsic amorphous silicon layer.

5. The back contact structure according to claim 1, wherein: The second dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

6. The back contact structure according to claim 1, wherein: The back side of the silicon substrate located between the first conductive region and the second conductive region has a rough texture structure.

7. The back contact structure according to claim 1, wherein: A first doping layer having the same conductivity type as that of the first doping region is provided in the silicon substrate located in the region between the first conductive region and the second conductive region.

8. The back contact structure according to claim 1, wherein: The first dielectric layer covers the bottom wall and the side wall of the groove, or extends to cover the area between each groove.

9. The back contact structure according to claim 8, wherein: The first doping region and / or the second doping region extends to a partial region between the grooves.

10. The back contact structure according to claim 1, wherein: The groove is in an arc shape, a trapezoidal shape, or a square shape.

11. The back contact structure according to claim 1, wherein: The thickness of the first dielectric layer is 1-20 nm, and the thickness of the first conductive region is greater than 20 nm.

12. The back contact structure according to claim 1, wherein: The junction depth of the second doped region is 0.01-1 μm, the sheet resistance is 10-500 ohm / sqr, and the surface concentration is 1E18-1E21 cm -3 .

13. The back contact structure according to claim 1, wherein: The depth of each groove is 0.01-10 μm, and the distance between each groove is 20-500 μm.

14. The back contact structure according to claim 2, wherein: The groove width of the P-type doping region is set to 300-600 um, or the groove width of the N-type doping region is set to 100-500 um.

15. The back contact structure according to claim 3, wherein: The doped silicon carbide includes doped hydrogenated silicon carbide.

16. The back contact structure according to claim 4, wherein: The first dielectric layer is a tunneling oxide layer and an intrinsic silicon carbide layer.

17. The back contact structure according to claim 4 or 16, characterized in that: The tunneling oxide layer is composed of one or more layers of a silicon oxide layer and an aluminum oxide layer.

18. The back contact structure according to claim 4 or 16, characterized in that The intrinsic silicon carbide layer in the first dielectric layer includes an intrinsic hydrogenated silicon carbide layer.

19. The back contact structure according to claim 5, wherein: The second dielectric layer is an aluminum oxide layer and an intrinsic silicon carbide layer, or a silicon oxide layer and an intrinsic silicon carbide layer, and the thickness of the second dielectric layer is greater than 25 nm.

20. The back contact structure according to claim 19, wherein: The thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer is less than 25 nm, and the thickness of the intrinsic silicon carbide layer in the second dielectric layer is greater than 10 nm.

21. The back contact structure according to claim 5 or 19, characterized in that The intrinsic silicon carbide layer in the second dielectric layer is composed of at least one first intrinsic silicon carbide film having a different refractive index.

22. The back contact structure according to claim 21, wherein: The refractive index of each layer of the first intrinsic silicon carbide film decreases sequentially from the back side of the silicon substrate toward the outside.

23. The back contact structure according to claim 5, wherein: The outer layer of the second dielectric layer is further provided with a magnesium fluoride layer.

24. The back contact structure according to claim 1, wherein: The conductive layer is a TCO transparent conductive film and / or a metal electrode.

25. The back contact structure according to claim 24, wherein: The metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode or a silver-clad copper electrode.

26. The back contact structure according to claim 25, wherein: The copper electrode is electroplated copper prepared by an electroplating process or a copper electrode prepared by physical vapor deposition.

27. A selective contact region buried type solar cell, characterized in that: include: Silicon substrate; A back contact structure according to any one of claims 1 to 26 provided on the back side of the silicon substrate; and A third dielectric layer is provided on the front surface of the silicon substrate.

28. The selective contact region buried type solar cell according to claim 27, wherein: The third dielectric layer is one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, an intrinsic silicon carbide layer, an intrinsic amorphous silicon layer, and a silicon oxide layer.

29. The selective contact region buried type solar cell according to claim 28, wherein: The third dielectric layer is a silicon oxide layer and an intrinsic silicon carbide layer, or an aluminum oxide layer and an intrinsic silicon carbide layer, and the thickness of the third dielectric layer is greater than 50 nm.

30. The selective contact region buried type solar cell according to claim 29, wherein: The thickness of the aluminum oxide layer or the silicon oxide layer in the third dielectric layer is less than 40 nm, and the thickness of the intrinsic silicon carbide layer in the third dielectric layer is greater than 10 nm.

31. The selective contact region buried type solar cell according to claim 28 or 29, characterized in that: The intrinsic silicon carbide layer in the third dielectric layer is composed of at least one second intrinsic silicon carbide film having a different refractive index.

32. The selective contact region buried type solar cell according to claim 31, wherein: The refractive index of each layer of the second intrinsic silicon carbide film decreases sequentially from the front side of the silicon substrate toward the outside.

33. The selective contact region buried type solar cell according to claim 28, wherein: The outer layer of the third dielectric layer is further provided with a magnesium fluoride layer.

34. The selective contact region buried type solar cell according to claim 27, wherein: An electric field layer or a floating junction is further provided between the front surface of the silicon substrate and the third dielectric layer.

35. A battery assembly, characterized in that: The battery assembly includes the selective contact area buried solar cell according to any one of claims 27 to 34.

36. A photovoltaic system, characterized in that: The photovoltaic system includes the battery assembly according to claim 35.

37. A method for manufacturing a selective contact region buried type solar cell, applied to the selective contact region buried type solar cell according to any one of claims 27 to 34, characterized in that: The method comprises: A plurality of grooves are formed on the back side of the silicon substrate; preparing first conductive regions and second conductive regions alternately arranged in each of the grooves, wherein the first conductive regions include a first dielectric layer and a first doped region sequentially arranged on the grooves, and the second conductive regions include a second doped region; forming a second dielectric layer and a third dielectric layer on the back and front sides of the silicon substrate respectively; A conductive layer is formed on the first conductive region and the second conductive region.

38. The method for manufacturing a selective contact region buried solar cell according to claim 37, wherein: The step of preparing the first conductive areas and the second conductive areas alternately arranged in each of the grooves comprises: sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove; A second doped region having a second conductivity type is prepared in a second groove adjacent to the first groove, where the first conductivity type is opposite to the second conductivity type.

39. The method for manufacturing a selective contact region buried solar cell according to claim 38, wherein: The step of sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove comprises: preparing a first dielectric layer in the first groove; depositing intrinsic amorphous silicon or intrinsic silicon carbide on the first dielectric layer; Doping the intrinsic amorphous silicon or intrinsic silicon carbide with a first conductivity type; A high-temperature crystallization process is performed to convert the intrinsic amorphous silicon or intrinsic silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region having a first conductivity type.

40. The method for manufacturing a selective contact region buried solar cell according to claim 38, wherein: The step of sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove comprises: preparing a first dielectric layer in the first groove; depositing intrinsic amorphous silicon or intrinsic silicon carbide on the first dielectric layer; Diffusion of the first conductivity type is performed on the intrinsic amorphous silicon or the intrinsic silicon carbide to convert the intrinsic amorphous silicon or the intrinsic silicon carbide into doped polysilicon or doped silicon carbide, thereby obtaining a first doped region with the first conductivity type.

41. The method for manufacturing a selective contact region buried solar cell according to claim 38, wherein: The step of sequentially preparing a first dielectric layer and a first doped region having a first conductivity type in the first groove comprises: preparing a first dielectric layer in the first groove; depositing doped amorphous silicon or doped amorphous silicon carbide of a first conductivity type on the first dielectric layer; A high-temperature crystallization process is performed to convert the doped amorphous silicon or doped amorphous silicon carbide into doped polysilicon or doped silicon carbide, so as to obtain a first doped region having a first conductivity type.

42. The method for manufacturing a selective contact region buried solar cell according to claim 38, wherein: The step of preparing a second doped region having a second conductivity type in a second groove adjacent to the first groove comprises: A source gas corresponding to the second conductivity type is introduced into the second groove for thermal diffusion to form a second doped region having the second conductivity type; or Depositing or spin-coating a doping source corresponding to the second conductivity type in the second groove and performing thermal diffusion to form a second doped region having the second conductivity type; or Ions corresponding to the second conductivity type are implanted into the second groove and thermally diffused to form a second doped region having the second conductivity type.

43. The method for manufacturing a selective contact region buried solar cell according to claim 39, wherein: The step of doping the intrinsic amorphous silicon or intrinsic silicon carbide with the first conductivity type comprises: Implanting ion doping of the first conductivity type into the intrinsic amorphous silicon or intrinsic silicon carbide; or depositing a dopant source of a first conductivity type on the intrinsic amorphous silicon or intrinsic silicon carbide; or A source gas of the first conductivity type is introduced into the intrinsic amorphous silicon or the intrinsic silicon carbide for doping.

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