Feedback for power management of memory die using capacitive coupling

Abstract

The present application relates to feedback for power management of a memory die using capacitive coupling. A memory device may include a pin for receiving a direct current (DC) voltage indicative of an operational configuration setting of the memory device and for transmitting an alternating current (AC) voltage signal providing feedback to a power management component. The memory device may determine that a supply voltage is outside a target range and may drive the AC signal onto the pin based on determining that the supply voltage is outside the range. The pin may be coupled to a capacitive component that passes the AC signal and blocks the DC signal. The power management component may receive the capacitively coupled AC signal and may maintain or adjust the supply voltage based on the received AC signal.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 16 / 798,893, filed on February 24, 2020, by Choi et al., entitled “FEEDBACK FOR POWER MANAGEMENT OF A MEMORY DIEUSING CAPACITIVE COUPLING,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to feedback for power management of memory dies using capacitive coupling. Background Art

[0004] The following relates generally to one or more memory systems, and more specifically, to feedback for power management of memory dies using capacitive coupling.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, usually indicated by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write a state or program a state in the memory device.

[0006] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), optional memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Non-volatile memory such as FeRAM can maintain its stored logic state for a long time, even if no external power is present. Volatile memory devices such as DRAM may lose their stored state when disconnected from the external power supply. Summary of the invention

[0007] An apparatus is described. The apparatus may include: an array of memory cells; a pin for transmitting a direct current (DC) voltage indicative of an operational configuration setting of the apparatus; a capacitive component coupled to the pin and for transmitting an alternating current (AC) signal at the pin; and a controller operable to cause the apparatus to determine that a supply voltage of the array of memory cells exceeds a target range associated with the supply voltage and to generate an AC signal at the pin based at least in part on the determination that the supply voltage exceeds the target range.

[0008] A system is described. The system may include: a power management component operable to provide a supply voltage to a plurality of memory devices; a first memory device of the plurality of memory devices including a first pin coupled to a first direct current (DC) voltage, the first DC voltage indicating a first operational configuration setting of the first memory device; a second memory device of the plurality of memory devices including a second pin coupled to a second DC voltage, the second DC voltage indicating a second operational configuration setting of the second memory device; a first capacitive component positioned along a first signal path between the first pin and the power management component, the first capacitive component for transmitting a first alternating current (AC) signal at the first pin to the power management component, wherein the first memory device is operable to determine that the supply voltage is outside a target range and to generate the first AC signal at the first pin based at least in part on the determination that the supply voltage is outside the target range; and a second capacitive component positioned along a second signal path between the second pin and the power management component, the second capacitive component for transmitting a second AC signal at the second pin to the power management component, wherein the second memory device is operable to determine that the supply voltage is outside a target range and to generate the second AC signal at the second pin based at least in part on the determination that the supply voltage is outside the target range.

[0009] A method is described. The method may include: identifying at a memory device a configuration setting of the memory device based at least in part on a direct current (DC) voltage at a pin of the memory device; determining, after identifying the configuration setting, that a supply voltage of the memory device exceeds a target range associated with the supply voltage; and generating an alternating current (AC) signal at the pin of the memory device based at least in part on determining that the supply voltage exceeds the target range.

[0010] A device is described. The device may include: a memory cell array; a pin for providing an output of loopback information based at least in part on a setting of the device; a capacitive component coupled to the pin and for transmitting an alternating current (AC) signal at the pin; and a controller operable to determine that the loopback setting indicates that the device is operating in a mode other than the loopback mode, set the pin to an inactive state based at least in part on determining that the device is operating in a mode other than the loopback mode, determine that a supply voltage of the memory cell array exceeds a target range associated with the supply voltage after setting the pin to the inactive state, and generate the AC signal at the pin based at least in part on determining that the supply voltage exceeds the target range. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting feedback for power management of a memory die using capacitive coupling according to examples disclosed herein is described.

[0012] Figure 2

[00136] An example of a system supporting feedback for power management of a memory die using capacitive coupling according to examples disclosed herein is shown.

[0013] Figure 3

[00136] An example of a system supporting feedback for power management of a memory die using capacitive coupling according to examples disclosed herein is shown.

[0014] Figure 4

[00136] An example of a system supporting feedback for power management of a memory die using capacitive coupling according to examples disclosed herein is shown.

[0015] Figure 5 A block diagram of a memory device supporting feedback for power management of a memory die using capacitive coupling is shown according to examples disclosed herein.

[0016] Figure 6 and 7 A flow chart illustrating one or more methods of supporting feedback for power management of a memory die using capacitive coupling according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0017] In some memory systems, a power management component, such as a power management integrated circuit (PMIC), may be used to manage power supplied to one or more memory devices by controlling the voltage of a power rail. In some cases, the voltage on the power rail may decay at locations that are relatively far from the power management component due to, for example, parasitic capacitance along the rail or other factors. For memory devices that are relatively far from the power management component, the voltage on the power rail may decay sufficiently to be below a minimum supply voltage, which may result in errors at the memory devices. However, the power management component may not have access to information about the voltage at various locations along the rail, and may not be able to adjust the power supplied to the rail to compensate for these deviations from a target range of voltage levels.

[0018] A memory device may include one or more pins that can be used to configure various operational configuration settings of the memory device, such as command addressing modes, test modes, or other configuration settings, by setting (e.g., providing, maintaining) a direct current (DC) voltage (e.g., a constant voltage) at the pin. In some instances, the pin may be coupled to a voltage source that is set to a specific DC voltage to configure the operational configuration settings of the memory device. In some instances, the memory device may determine (e.g., identify, detect) the DC voltage at the pin during a startup or initialization procedure, and may subsequently operate based on the configuration settings associated with this voltage (e.g., perform memory access operations, such as read or write operations, or perform other operations). In some instances, once the configuration settings have been determined, the memory device may not continuously monitor the voltage at the pin, or may occasionally check the voltage at the pin after the startup or initialization procedure. Therefore, such configuration pins may be used by the memory device for other purposes (e.g., for transmitting signals) at some or all of the time after the voltage has been detected by the memory device. However, since the pin may be coupled to a voltage source that maintains the DC voltage at the pin, it may be challenging to use the pin to transmit other signals.

[0019] The memory device may use (e.g., reuse) such pins to provide feedback to the power management component regarding the voltage level of the power rail at the memory device. The memory device may provide such feedback by generating an alternating current (AC) signal at the pin that may be transmitted to the power management component using a capacitive coupling method that blocks the DC voltage at the pin and passes the AC signal. For example, if the memory device determines that the supply voltage is outside a target range associated with the supply voltage, the memory device may generate an AC feedback signal at a configuration pin of the memory device (e.g., by generating one or more voltage pulses or other non-constant voltage signals) to indicate that the supply voltage is outside the target range. The target range may be, for example, a voltage range of the supply voltage that the memory device is designed to operate properly, such as a supply voltage range specified by a standard file associated with the memory device.

[0020] The AC signal generated at the pin may be provided to the power management component using capacitive coupling, in which a capacitive component located within a feedback signal path between the memory device and the power management component passes the AC feedback signal while blocking the DC voltage signal. For example, a pin of the memory device may be coupled to the power management component with the aid of an in-line capacitor between the memory device and the power management component. The in-line capacitor may enable capacitive coupling (e.g., transmission) of the AC signal generated at the pin while blocking (e.g., filtering out) the DC voltage signal generated by the voltage source. In other examples, a pin of the memory device may be coupled to a conductive line that is in close proximity to another conductive line coupled to the power management component, and the AC signal may be capacitively coupled across the conductive line with the aid of parasitic capacitance in the circuit system.

[0021] The power management component may then operate to detect the capacitively coupled AC signal provided by the memory device.The power management component may use this feedback information to determine whether and how to adjust the power (eg, supply voltage) supplied to the memory device via the power rail.

[0022] In some cases, a memory system may include multiple memory devices, each of which may include a configuration pin coupled to a power management component by means of an in-line capacitor (or by means of parasitic capacitance, or both). Each of the memory devices may provide feedback to the power management component by generating an AC signal at a corresponding pin of each memory device as described above. In the case where the power management component is coupled to multiple memory devices that each provide feedback by generating an AC signal, the power management component may be operable to detect these feedbacks for each memory device separately, or to detect combined feedback from all memory devices. The power management component may then adjust the voltage of the rail based on the feedback received from one or more memory devices.

[0023] The use of capacitive coupling for transmitting an AC feedback signal from a memory device to a power management component as described herein can enable the memory device to provide such feedback using existing pins (rather than by adding new pins), thereby reducing the cost and area associated with providing such feedback and potentially achieving backward compatibility with existing designs.

[0024] References below Figure 1 Features of the present disclosure are further described in the context of memory systems and dies. Figures 2 to 4 Features of the present disclosure are described in the context of a memory system. Figures 5 to 7 These and other features of the present disclosure are further illustrated and described with reference to the device diagrams and flow diagrams in the accompanying drawings.

[0025] Figure 1 An example of a system 100 utilizing one or more memory devices according to examples disclosed herein is illustrated. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include the one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0026] The system 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, etc. The memory device 110 may be a component of the system that is operable to store data for one or more other components of the system 100.

[0027] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes (e.g., within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, or some other fixed or portable electronic device), among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0028] Memory device 110 may be a separate device or component operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme to modulate a signal, various pin configurations for transmitting a signal, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0029] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0030] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using a bus 135.

[0031] The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 can be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a system on a chip (SoC), among other examples. In some examples, the external memory controller 120 can be implemented by the processor 125 or as part of the processor 125.

[0032] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of a read-only memory (ROM), flash memory, or other non-volatile memory.

[0033] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support the desired capacity or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more sectors), where each memory cell is operable to store at least one bit of data. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

[0034] In some examples, memory die 160 may be coupled with a power management component that is operable to provide one or more supply voltages to memory die 160. For example, the power management component may use a power rail (e.g., a conductive line) to supply a VDD voltage, a VSS voltage, a VDDQ voltage, etc. The power management component may be operable to maintain a substantially constant supply voltage on the rail to provide power to memory device 110 or memory die 160 during operation. The power management component may include or may be coupled to one or more voltage source components that are operable to generate the appropriate supply voltages. In some cases, the power management component may be referred to as a PMIC or a registered clock device (RCD).

[0035] In some cases, the voltage along the power rail may decrease along the rail as the distance from the power management component increases due to, for example, parasitic capacitance along the power rail. Thus, if multiple memory dies 160 are coupled to a power rail that provides a supply voltage to the memory dies 160, then memory dies 160 that are relatively far from the power management component may receive a lower supply voltage than memory dies 160 that are closer to the power management component. In some cases, if the supply voltage drops below a lower voltage threshold, the memory dies 160 may experience a memory error.

[0036] In some examples, memory die 160 (or memory device 110) may include configuration pins that can be used to transmit (e.g., receive) a DC voltage that indicates an operational configuration setting of the memory die. The configuration pins may be coupled with a voltage source that sets the voltage at the pins to a DC voltage that indicates a particular operational configuration setting of the memory die 160, such as an operational mode that may be specified to the memory die 160 after startup or initialization. In some cases, such a DC voltage may not be controlled by a controller (e.g., may be uncontrolled), such as a controller of the memory die 160 or another controller. That is, the DC voltage may be maintained at a relatively constant value by the voltage source, rather than being controlled and potentially changed by the controller.

[0037] In some examples, memory die 160 may use (eg, reuse) this pin for providing feedback to the power management component regarding the supply voltage on the power rail at the memory die, thereby enabling the power management component to adjust the supply voltage appropriately.

[0038] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0039] A local memory controller 165 (e.g., local to the memory die 160) is operable to control the operation of the memory die 160. In some examples, the local memory controller 165 is operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165 or an external memory controller 120 that may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0040] The local memory controller 165 of the memory die 160 is operable to determine whether the supply voltage is outside a target range associated with the supply voltage. If the local memory controller 165 determines that the supply voltage is outside the target range, the local memory controller 165 may generate an AC signal at a pin of the memory die 160 indicating that the supply voltage is out of range. For example, the local memory controller 165 may cause a driver to generate (e.g., drive) an AC signal onto a pin of the memory die 160, such as by driving one or more voltage pulses onto the pin.

[0041] The external memory controller 120 is operable to enable one or more of information, data, or commands to be transferred between a component of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between a component of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or the functions thereof described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or the functions thereof described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0042] Components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, a channel 115 may include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin may be an example of a conductive input or output point of a device of the system 100, and the pin may be operable to serve as part of a channel.

[0043] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, information may be transmitted via channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on a rising and falling edge of a clock signal).

[0044] Figure 2 An example of a system 200 that supports feedback for power management of a memory die using capacitive coupling is described. The system 200 can include a power management component 205, a memory device 210 including a memory array 215, and a feedback path 230 and a supply path 225 between the power management component 205 and the memory device 210. In the example of the system 200, the feedback path 230 and / or the supply path 225 can include conductive lines that couple the power management component 205 to the memory device 210. The memory device 210 can be a reference Figure 1 1. The memory array 215 may be a reference to an example of a memory device 110. Figure 1 An example of a memory array 170 is described.

[0045] The power management component 205 may include a supply interface 235, low dropout regulators (LDO) 240, 245, power supplies (SWA, SWB) 250, 255 (e.g., switching regulators), and a multi-time programmable memory (MTP) 260. The supply interface 235 is operable to receive power to activate the power management component 205 and to be distributed to other components of the memory system (e.g., the memory device 210) by the power management component 205.

[0046] The low dropout regulators 240, 245 may be used to output power (e.g., DC power) to memory devices of the memory system, including the memory device 210. In some cases, the low dropout regulators 240, 245 may be used to regulate an output voltage, such as a supply voltage. The power supplies 250, 255 may be used to output power to memory devices of the memory system, including the memory device 210. The power management component 205 may include any number of low dropout regulators (e.g., one, two, three, four, five, six, seven, eight), or may include any number of power supplies (e.g., one, two, three, four, five, six, seven, eight), or any number of both.

[0047] The multi-time programmable memory 260 can be any type of memory used by the power management component 205 for performing the functions described herein. In some cases, the multi-time programmable memory 260 can be an instance of an electrically erasable programmable read-only memory (EEPROM) or other type of memory technology. The multi-time programmable memory 260 can be used to protect circuits, improve the reliability of power-on or power-off sequences, set output voltages, set output pull-down resistances, or other functions, or any combination thereof.

[0048] Memory device 210 may include pins 220, which may be used to configure operational aspects of memory device 210 and may be repeatedly used to provide feedback to power management component 205. Pins 220 may be, for example, conductive terminals of an integrated circuit package that allow the integrated circuit to connect to other components or circuit systems. Pins 220 may also be referred to as, for example, pads, sockets, connectors, contacts, or balls (of a ball grid array package). In some cases, pins 220 may be conductive points located within the integrated circuit package or external to the integrated circuit package.

[0049] The feedback path 230 may be a signal path capable of transmitting (e.g., transmitting) an AC signal from the pin 220 of the memory device 210 to the power management component 205 with the aid of a capacitive component 265 positioned along the feedback path 230 between the pin 220 and the power management component 205. The capacitive component 265 may be, for example, one or more discrete capacitors coupled between a first conductive portion 230-a (e.g., a conductive line) of the feedback path 230 and a second conductive portion 230-b (e.g., a conductive line) of the feedback path 230. In some examples, the capacitive component 265 may represent a parasitic capacitance between the first conductive portion 230-a and the second conductive portion 230-b. The feedback path 230 may include any collection of one or more conductive lines that establish a communication link between the memory device 210 and the power management component 205.

[0050] Supply path 225 can be a power rail (or can be coupled to a power rail) to, for example, enable power management component 205 to provide a supply voltage to memory device 210. The supply voltage can be used by memory device 210 during operation of memory device 210 and can include, for example, a VDD voltage, a VSS voltage, or another supply voltage. Figure 2 2 , but the memory device may include multiple supply paths 225 between the memory device 210 and the power management component 205, so that the power management component 205 can provide multiple different supply voltages to the memory device 210.

[0051] Techniques are provided herein for using pin 220 to provide feedback to power management component 205 based on a determination that a supply voltage provided by power management component 205 is outside a target range by generating an AC signal at pin 220. The AC signal generated at pin 220 can be transmitted (e.g., transmitted) to power management component 205 using capacitive coupling. The capacitively coupled AC signal can be detected by power management component 205 (and / or by another device, such as a host device) and can be used by power management component 205 to adjust (e.g., maintain or adjust) a voltage supplied to memory device 210 (e.g., using supply path 225) or to adjust another operational aspect of memory device 210.

[0052] Figure 3 An example of a system 300 according to examples disclosed herein is illustrated. The system 300 includes a host device 305 and a memory system 310. The host device 305 and the memory system 310 can be coupled or connected to each other (e.g., electrically) via a channel 315 (e.g., a common channel, a shared channel). The host device 305 can refer to a device that uses the memory system 310 for data storage or otherwise coordinates the use of the memory system 310 for data storage.

[0053] The memory system 310 may include one or more memory devices 110 (eg, memory devices 110-a, 110-b), which may be reference Figure 1 10, such as a DRAM device. Each memory device 110 may include pins 220 (e.g., pins 220-a, 220-b) for configuring operational aspects of the corresponding memory device 110 and for providing feedback to the power management component 205-a. The power management component 205-a may be a reference Figure 2 An example of a power management component 205 is described.

[0054] In some examples, memory system 310 may refer to a set of components, such as a memory module or memory assembly, that is physically distinct from host device 305. For example, memory system 310 may refer to a single in-line memory module (SIMM), a dual in-line memory module (DIMM), or another type of module or assembly. In some cases, a SIMM or DIMM may include a power management component 205-a, such as depicted in memory system 310. In some cases, power management component 205-a may be external to a SIMM or DIMM.

[0055] In some cases, memory system 310 may include a single DRAM integrated circuit (e.g., a single memory device 110). Memory system 310 may include a first amount of pins (e.g., 72 pins or another amount of pins) that may be used, for example, to couple memory system 310 with power management components, a host processor, or other electronic components, or to configure operational aspects of memory device 110. Each pin of memory system 310 may support 32-bit data transfers.

[0056] In some cases, memory system 310 may include a series of DRAM integrated circuits, such as a series of memory devices 110. Memory system 310 may include a second amount of pins (e.g., 100, 144, 168, 172, 184, 204, 214, 240, or another amount of pins), which may be used, for example, to couple memory system 310 with power management components, a host processor, or other electronic components, or to configure operational aspects of memory devices 110. Each pin of memory system 310 may support 64-bit data transfers. In some cases, DRAMs in memory system 310 are coupled to one or more power rails, and DRAMs that are farther from the voltage source may receive a lower voltage on the power rail than DRAMs that are closer to the voltage source.

[0057] In some examples, a pin (e.g., a configuration pin) of memory device 110 may be coupled to a voltage source that biases (e.g., sets, drives) the voltage at the pin to a DC voltage that indicates an operational configuration setting (e.g., a configuration for a command address mode or a configuration for a test mode) of memory device 110. Memory device 110 may include one or more such configuration pins, each of which may be coupled to the same or different voltage sources, and may be biased to the same or different voltages.

[0058] In some examples, the memory device 110 may include one or more pins for receiving a DC voltage indicating an operational configuration of a command address mode of the memory device. The memory device may perform access operations, such as read operations, write operations, or other operations, on the memory array based on the operational configuration of the command address mode.

[0059] For example, memory device 110 may include a MIR (mirror) pin that may be used to configure memory device 110 for operation in a mirrored command addressing mode or a standard command addressing mode. For example, if the MIR pin is biased to a first DC voltage (e.g., to VDDQ), memory device 110 may internally swap even-numbered command addresses with the next higher odd-numbered command addresses. If the MIR pin is biased to a second DC voltage (e.g., to VSSQ), memory device 110 may not perform such internal swapping of command addresses.

[0060] For example, memory device 110 may include a CAI (command and address inversion) pin that may be used to configure memory device 110 for operation with or without inversion of the logic levels of command address signals. For example, if the CAI pin is biased to a first DC voltage (e.g., to VDDQ), memory device 110 may internally invert the logic levels present on all command address signals. If the CAI pin is biased to a second DC voltage (e.g., to VSSQ), memory device 110 may not perform such internal inversion of the logic levels of command address signals.

[0061] In some examples, the memory device 110 may include one or more pins for receiving a DC voltage indicating an operational configuration of a test mode of the memory device 110. The memory device 110 may perform a test operation on the memory cell array based on the operational configuration of the test mode or may operate normally. For example, the memory device 110 may include a TEN (connectivity test mode enable) pin, which is used to configure the memory device 110 when the connectivity test mode operation is enabled. If the TEN pin is biased to a first voltage (e.g., a high voltage, or another voltage signal), the connectivity test mode may be enabled, and if the TEN pin is biased to a second voltage, the connectivity test mode may be disabled. When the connectivity test mode is enabled, some of the pins of the memory device 110 may be used as test inputs, and other pins may be used as test outputs. The memory device 110 may be tested by providing a test signal at the test input pin and monitoring the output at the test output pin. For example, such a test mode may be enabled for testing memory device 110 before memory device 110 is shipped to a customer, and such a test mode may be disabled during normal operation. Thus, during normal operation of memory device 110, the TEN pin may be biased to a DC voltage (e.g., VSS) indicating that the connectivity test mode is disabled. In some examples, the TEN pin may be directly coupled to a VSS voltage source or ground, or may be internally pulled down to the VSS voltage via a weak pull-down resistor.

[0062] In some examples, memory device 110 may include other pins that are not used some or all of the time during normal operation of memory device 110. For example, memory device 110 may include one or more LBDQ (Loopback Data Output) pins that may operate as output pins for outputting loopback information when a loopback setting of memory device 110 indicates that a loopback mode is enabled (e.g., for testing memory device 110 or for other purposes). These LBDQ pins may be set to an inactive state (e.g., terminated or set to a high impedance state), for example, during normal operation of memory device 110 when the loopback setting indicates that the loopback mode is disabled. Thus, when memory device 110 is not operating in a loopback mode, the LBDQ pins may be used to transmit feedback information to a power management component.

[0063] Memory device 110 may include some or all of the one or more configuration pins described above that are not used some or all of the time during normal operation of memory device 110, and may include additional such pins not described herein but that may be used to provide feedback to power management components as described herein.

[0064] In some cases, memory device 110 may determine whether a supply voltage used during operation of memory device 110 is outside a target range. If memory device 110 determines that the supply voltage is outside the target range, memory device 110 may generate an AC signal at pin 220 indicating that the supply voltage is outside the target range. For example, memory device 110 may drive one or more voltage pulses, sine waves, or other types of AC signals onto pin 220 to indicate that the supply voltage is outside the target range. In some examples, memory device 110 may generate a first AC signal if the memory device determines that the supply voltage is below a lower voltage threshold of the target range, and may generate a second (e.g., different) AC signal based on determining that the supply voltage is above an upper voltage threshold of the target range.

[0065] In some examples, memory device 110 is operable to determine a value of a supply voltage (e.g., a voltage value). Memory device 110 may indicate the value of the supply voltage by driving an amount of voltage pulses at pin 220, wherein the amount of the voltage pulses indicates the value of the supply voltage. For example, the memory device may drive a first amount of pulses onto pin 220 based on determining a first value of the supply voltage, and may drive a second amount of pulses onto pin 220 based on determining a second value of the supply voltage.

[0066] The power management component 205-a is operable to receive (e.g., detect) an AC signal generated at the pin 220 and transmitted to the power management component 205-a using capacitive coupling (e.g., with the aid of the capacitive component 265 in the feedback path 230). For example, the power management component 205-a is operable to detect a certain amount of voltage pulses (e.g., a certain amount of voltage pulses initiated by the memory device 110) generated at the pin 220 and transmitted to the power management component 205-a using capacitive coupling.

[0067] The power management component 205-a may maintain or adjust the power supplied to the memory device 110 based on the received AC signal. The power management component 205-a may use the LDO 240, 245, SWA 250, SWB 255, MTP 260, or a combination of these components to, for example, maintain, increase, or decrease the voltage on the power rail. The memory device 110 is operable to receive an adjusted supply voltage (e.g., from the power management component 205-a) based on (e.g., after generating the AC signal at the pin 220) the AC signal at the pin 220.

[0068] The power management component 205-a may be coupled to the plurality of memory devices 110-a, 110-b using a feedback path 230-c. Each memory device 110-a, 110-b may be coupled to a corresponding capacitive component 265-a, 265-b to capacitively couple an AC signal at a corresponding pin 220-a, 220-b of the memory devices 110-a, 110-b. The capacitive components 265-a, 265-b may be coupled between the pins 220-a, 220-b and the power management component 205-a along corresponding branches of the feedback path 230-c. Each memory device 110-a, 110-b may provide an indication of a supply voltage at the memory device 110 (e.g., by generating an AC signal at a corresponding pin 220-a, 220-b indicative of the supply voltage).

[0069] In some cases, each memory device 110 may apply a different drive strength at pin 220 to weight the AC feedback signal of each memory device 110. In some cases, the drive strength may be the amount of current that flows out (e.g., supplies) or flows into (e.g., receives) at pin 220 while outputting or maintaining a given voltage at pin 220. For example, each memory device 110 may be preconfigured to apply a particular drive strength at pin 220 based on, for example, the location of the memory device 110 within the memory system 310 or the proximity (e.g., electrical proximity) of the memory device 110 to a power source.

[0070] In some cases, each memory device 110 may be coupled to the power management component 205-a using a separate point-to-point connection (e.g., a separate feedback path), and the power management component 205-a may internally weight or otherwise process feedback from each memory device 110 to determine how to adjust the supply voltage.

[0071] Figure 4 An example of a system 400 for supporting feedback for power management of a memory die using capacitive coupling according to examples disclosed herein is depicted. The system 400 includes a memory device 110-c coupled with a power management component 205-b by means of a capacitive component 265-c. For example, the capacitive component 265-c may include a discrete capacitor, or may represent a parasitic capacitance, or both.

[0072] Memory device 110-c includes pins 220-c, which may be, for example, reference Figure 3 110-c, or may be another type of pin. Pin 220-c may be coupled to a voltage source 325-c that may bias a voltage at pin 220-c to specify an operational configuration setting for memory device 110-c. In some examples, voltage source 325-c may be a VDD voltage source, a VDDQ voltage source, a VSS voltage source, or a ground voltage (e.g., pin 220-c may be tied to ground).

[0073] The memory device 110-c may include a driver 405 that is coupled to the pin 220-c and is operable to drive (e.g., generate) an AC signal onto the pin 220-c, such as by driving one or more voltage pulses or other non-constant voltage signals onto the pin 220-c. Although the driver 405 is depicted as part of the memory device 110-c, in some cases, the driver 405 may be located outside the memory device 110-c. For example, the memory device 110-c may generate and drive the AC signal onto the pin 220-c based on determining that the supply voltage is outside the target range. In some cases, if the memory device 110-c determines that the supply voltage is within the target range, the memory device 110-c may not generate an AC signal, or may generate an AC signal (e.g., a different AC signal) indicating that the supply voltage is within the target range. Therefore, the memory device 110-c may generate an AC signal at the pin 220-c some or all of the time.

[0074] Thus, the voltage signal at pin 220-c may be a combination of a DC voltage signal (e.g., provided by voltage source 325-c) and sometimes an AC voltage signal (e.g., generated by driver 405). The AC component of the signal at pin 220-c may be transmitted to power management component 205-b using capacitive component 265-c, which is coupled to pin 220-c and may pass (e.g., transmit, transmit) the AC voltage signal and block the DC voltage signal. That is, capacitive component 265-c and the resistor within the possible circuit system may act as a high pass filter that allows the AC voltage signal to be transmitted while filtering out the DC voltage signal. Thus, power management component 205-b may receive the AC voltage signal but not the DC voltage signal. Power management component 205-b may maintain or adjust the supply voltage based on the received AC voltage signal as previously described.

[0075] Figure 5 A block diagram 500 is shown of a memory device 505 that supports feedback for power management of a memory die using capacitive coupling according to examples disclosed herein. The memory device 505 may be a reference Figures 1 to 4 An example of aspects of a memory device described herein. Memory device 505 may include an identification component 510, a determination component 515, and an AC signal generation component 520. Each of these modules may communicate with each other directly or indirectly (eg, via one or more buses).

[0076] Identification component 510 can identify a configuration setting of a memory device at a memory device based at least in part on a direct current (DC) voltage at a pin of the memory device. In some examples, the configuration setting indicates a configuration of a command address mode of the memory device or a configuration of a test mode of the memory device.

[0077] In some examples, the determining component 515 can determine that the supply voltage of the memory device exceeds a target range associated with the supply voltage after identifying the configuration setting. In some examples, the determining component 515 can determine a value of the supply voltage. In some examples, the determining component 515 can determine that the supply voltage is below a lower voltage threshold of the target range or above a high voltage threshold of the target range.

[0078] The AC signal generating component 520 can generate an AC signal at a pin of the memory device based on determining that the supply voltage is outside the target range. In some examples, the AC signal generating component 520 can generate the AC signal by generating an amount of voltage pulses based on the value of the supply voltage or based on determining that the supply voltage is below a lower voltage threshold of the target range. In some examples, the amount of the voltage pulses indicates the value of the supply voltage.

[0079] The memory access component 525 can perform a first access operation based at least in part on the configuration settings of the memory device. In some examples, the first access operation is a read operation, a write operation, or a test operation.

[0080] Figure 6 A flow chart illustrating one or more methods 600 for supporting feedback for power management of a memory die using capacitive coupling according to examples disclosed herein is shown. The operations of the method 600 may be described with reference to Figures 1 to 4 In some examples, the operations of method 600 may be implemented by reference to Figure 5 The memory device described herein performs. In some examples, the memory device may execute instruction sets to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0081] At 605, the memory device may identify a configuration setting of the memory device based at least in part on a DC voltage at a pin of the memory device. Figures 2 to 4 The method described herein performs the operation of 605. In some examples, aspects of the operation of 605 may be described by reference to Figure 5 The identification components described are performed.

[0082] At 610, the memory device may determine that a supply voltage of the memory device exceeds a target range associated with the supply voltage after identifying the configuration setting. Figures 2 to 4 The method described herein performs the operation of 610. In some examples, aspects of the operation of 610 may be described with reference to Figure 5 Determine the components to perform the description.

[0083] At 615, the memory device may generate an AC signal at the pin based at least in part on determining that the supply voltage is outside the target range. Figures 2 to 4 The method described herein performs the operation of 615. In some examples, aspects of the operation of 615 may be described by reference to Figure 5 The AC signal generating components described are performed.

[0084] In some examples, an apparatus as described herein may perform one or more methods, such as method 600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for identifying, at a memory device, a configuration setting of the memory device based at least in part on a DC voltage at a pin of the memory device.

[0085] Some examples of the methods 600 and apparatus described herein may further include operations, features, means, or instructions for determining, after identifying the configuration setting, that a supply voltage of the memory device is outside a target range associated with the supply voltage. Some examples of the methods 600 and apparatus described herein may further include operations, features, means, or instructions for generating an alternating current (AC) signal at a pin of the memory device based at least in part on determining that the supply voltage is outside the target range.

[0086] Figure 7 A flowchart illustrating one or more methods 700 of supporting feedback for power management of a memory die using capacitive coupling according to examples disclosed herein is shown. In some examples, the operations of the method 700 may be performed by reference to Figures 1 to 4 In some examples, the operations of method 700 may be implemented by reference to Figure 5 The memory device described herein performs. In some examples, the memory device may execute instruction sets to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0087] At 705, the memory device may identify a configuration setting of the memory device based at least in part on a DC voltage at a pin of the memory device. Figures 2 to 4 The method described herein performs the operation of 705. In some examples, aspects of the operation of 705 may be described by reference to Figure 5 The identification components described are performed.

[0088] At 710, a memory device may perform a first access operation based at least in part on a configuration setting of the memory device. Figures 2 to 4 The method described herein performs the operations of 710. In some examples, aspects of the operations of 710 may be described with reference to Figure 5 The memory access components described are executed.

[0089] At 715, the memory device may determine that a supply voltage of the memory device exceeds a target range associated with the supply voltage. Figures 2 to 4 The method described herein performs the operation of 715. In some examples, aspects of the operation of 715 may be described by reference to Figure 5 Determine the components to perform the description.

[0090] At 720, the memory device may generate an AC signal at a pin of the memory device based at least in part on determining that the supply voltage is outside the target range. Figures 2 to 4 The method described herein performs the operations of 720. In some examples, aspects of the operations of 720 may be described with reference to Figure 5The AC signal generating components described are performed.

[0091] In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for identifying a configuration setting of a memory device based at least in part on a DC voltage at a pin of the memory device.

[0092] Some examples of the methods 700 and apparatus described herein may further include operations, features, components, or instructions for performing a first access operation based at least in part on a configuration setting of the memory device. Some examples of the methods 700 and apparatus described herein may further include operations, features, components, or instructions for determining, after identifying the configuration setting, that the supply voltage exceeds a target range associated with the supply voltage. Some examples of the methods 700 and apparatus described herein may further include operations, features, components, or instructions for generating an AC signal at a pin of the memory device based at least in part on determining that the supply voltage exceeds the target range.

[0093] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more of the methods may be combined.

[0094] An apparatus is described. The apparatus may include: an array of memory cells; a pin for transmitting a DC voltage indicative of an operational configuration setting of the apparatus; a capacitive component coupled to the pin and for transmitting an AC signal at the pin; and a controller operable to cause the apparatus to determine that a supply voltage of the memory cell array exceeds a target range associated with the supply voltage and to generate an AC signal at the pin based on the determination that the supply voltage exceeds the target range.

[0095] Some examples of the apparatus may include a driver coupled to the pin and the controller and operable to generate an AC signal by generating a certain amount of voltage pulses at the pin based on a signal received from the controller. Some examples may further include determining a value of a supply voltage, wherein the amount of the voltage pulses may be based on the value of the supply voltage. Some examples of the apparatus may include a voltage source coupled to the pin and configured to generate a DC voltage.

[0096] Some examples may further include determining an operational configuration of the device based on the DC voltage at the pin, wherein the operational configuration indicates a configuration of a command address mode of the device or a configuration of a test mode of the device. Some examples may further include performing an access operation on the memory cell array based on the operational configuration before determining that the supply voltage may be outside the target range.

[0097] Some examples may further include performing a test operation on the memory cell array based on the operation configuration before determining that the supply voltage may exceed the target range. Some examples may further include: determining at a first time that the supply voltage may be below a lower voltage threshold of the target range, wherein determining that the supply voltage may exceed the target range may be based on determining that the supply voltage may be below the lower voltage threshold; and generating a first AC signal based on determining that the supply voltage may be below the lower voltage threshold, wherein generating the AC signal includes generating the first AC signal.

[0098] Some examples may further include: determining at a second time different from the first time that the supply voltage may be above an upper voltage threshold of the target range; and generating a second AC signal based on determining that the supply voltage may be above the upper voltage threshold. In some examples, the capacitive component includes a discrete capacitor.

[0099] An apparatus is described. The apparatus may include: an array of memory cells; a pin for providing an output of loopback information based on a loopback setting of the apparatus; a capacitive component coupled to the pin, the capacitive component for transmitting an AC signal at the pin; and a controller operable to cause the apparatus to set the pin to an inactive state based on determining that the apparatus is operating in a mode other than a loopback mode, determine that a supply voltage of the memory cell array exceeds a target range associated with the supply voltage after setting the pin to the inactive state, and generate an AC signal at the pin based on determining that the supply voltage exceeds the target range.

[0100] In some examples, setting the pin to an inactive state may include an operation, feature, means, or instruction for setting the pin to a high impedance state or terminating the pin. Some examples may further include: determining that the loopback setting indicates that the device can operate in a loopback mode; and providing an output based on determining that the loopback setting indicates that the device can operate in the loopback mode. In some examples, generating the AC signal may include an operation, feature, means, or instruction for generating a certain amount of voltage pulses at the pin.

[0101] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0102] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are electronically connected with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0103] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to be transmitted between components via conductive paths, to a closed circuit relationship between components, in which signals are able to be transmitted between components via conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0104] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch positioned between the two components are isolated from one another when the switch is open. When a controller isolates two components, the controller implements a change that blocks a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0105] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0106] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by a conductive material such as a metal. The source and drain may be conductive and may include a heavily doped (e.g., degenerate) semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are signals), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0107] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0108] In the drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0109] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0110] The various illustrative blocks and modules described in conjunction with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0111] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted by a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Also, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0112] The description herein is provided to enable those skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: a memory cell array; a pin for transmitting a direct current (DC) voltage indicative of an operational configuration setting of the memory device; a capacitor component coupled to the pin and used to transmit an alternating current (AC) signal at the pin; as well as A controller operable to cause the memory device to: determining that a supply voltage of the memory cell array exceeds a target range associated with the supply voltage, and The AC signal is generated at the pin based at least in part on determining that the supply voltage is outside the target range.

2. The memory device of claim 1 , further comprising: A driver is coupled to the pin and the controller and is operable to generate the AC signal by generating a voltage pulse of a magnitude at the pin based at least in part on a signal received from the controller.

3. The memory device of claim 2, wherein the controller is further operable to cause the memory device to: A value of the supply voltage is determined, wherein an amount of voltage pulses is based at least in part on the value of the supply voltage.

4. The memory device of claim 1 , further comprising: A voltage source is coupled to the pin and configured to generate the DC voltage.

5. The memory device of claim 1 , wherein the controller is further operable to cause the memory device to: The operational configuration setting of the memory device is determined based at least in part on the DC voltage at the pin, wherein the operational configuration setting indicates a configuration of a command address mode of the memory device or a configuration of a test mode of the memory device.

6. The memory device of claim 5, wherein the controller is further operable to cause the memory device to: Prior to determining that the supply voltage is outside the target range, an access operation is performed on the memory cell array based at least in part on the operational configuration setting.

7. The memory device of claim 5, wherein the controller is further operable to cause the memory device to: Prior to determining that the supply voltage is outside the target range, a test operation is performed on the memory cell array based at least in part on the operational configuration settings.

8. The memory device of claim 1, wherein the controller is further operable to cause the memory device to: determining, at a first time, that the supply voltage is below a lower voltage threshold of the target range, wherein determining that the supply voltage is outside the target range is based at least in part on determining that the supply voltage is below the lower voltage threshold; and A first AC signal is generated based at least in part on determining that the supply voltage is below the lower voltage threshold, wherein generating the AC signal includes generating the first AC signal.

9. The memory device of claim 8, wherein the controller is further operable to cause the memory device to: determining, at a second time different from the first time, that the supply voltage is above an upper voltage threshold of the target range; and A second AC signal is generated based at least in part on determining that the supply voltage is above the upper voltage threshold.

10. The memory device of claim 1, wherein the capacitive component comprises a discrete capacitor.

11. A memory system comprising: a power management component operable to provide a supply voltage to the plurality of memory devices; a first memory device of the plurality of memory devices comprising a first pin coupled to a first direct current (DC) voltage, the first DC voltage indicating a first operational configuration setting of the first memory device; a second memory device of the plurality of memory devices comprising a second pin coupled to a second DC voltage, the second DC voltage indicating a second operational configuration setting of the second memory device; a first capacitive component positioned along a first signal path between the first pin and the power management component, the first capacitive component for transmitting a first alternating current (AC) signal at the first pin to the power management component, wherein the first memory device is operable to determine that the supply voltage is outside a target range and to generate the first AC signal at the first pin based at least in part on determining that the supply voltage is outside the target range; as well as a second capacitive component positioned along a second signal path between the second pin and the power management component, the second capacitive component being used to transmit a second AC signal at the second pin to the power management component, wherein the second memory device is operable to determine that the supply voltage exceeds the target range and to generate the second AC signal at the second pin based at least in part on determining that the supply voltage exceeds the target range.

12. The memory system of claim 11, wherein the power management component is configured to: receiving the first AC signal via the first capacitive component; receiving the second AC signal via the second capacitive component; and The supply voltage is adjusted based at least in part on the first AC signal, the second AC signal, or both.

13. The memory system of claim 11, further comprising a first voltage source coupled to the first pin and configured to generate the first DC voltage.

14. The memory system of claim 11, further comprising a second voltage source coupled to the second pin and configured to generate the second DC voltage.

15. The memory system of claim 11, wherein: The first memory device includes a first driver configured to generate the first AC signal at the first pin by generating a first amount of voltage pulses at the first pin based at least in part on the first memory device determining that the supply voltage is outside the target range; and The second memory device includes a second driver configured to generate the second AC signal at the second pin by generating a second amount of voltage pulses at the second pin based at least in part on the second memory device determining that the supply voltage is outside the target range.

16. A method for a memory device, the method comprising: identifying, at the memory device, a configuration setting of the memory device based at least in part on a direct current (DC) voltage at a pin of the memory device; determining, after identifying the configuration setting, that a supply voltage of the memory device is outside a target range associated with the supply voltage; and An alternating current (AC) signal is generated at the pin of the memory device based at least in part on determining that the supply voltage is outside the target range.

17. The method according to claim 16, further comprising: Prior to determining that the supply voltage is outside the target range, a first access operation is performed based at least in part on the configuration setting of the memory device.

18. The method of claim 16, wherein the configuration setting indicates a configuration of a command address mode of the memory device or a configuration of a test mode of the memory device.

19. The method of claim 16, further comprising: A value of the supply voltage is determined, wherein generating the AC signal at the pin includes generating an amount of voltage pulses at the pin based at least in part on the value of the supply voltage.

20. The method of claim 19, wherein an amount of voltage pulses is indicative of the value of the supply voltage.

21. The method of claim 16, further comprising: determining that the supply voltage is below a lower voltage threshold of the target range, wherein determining that the supply voltage is outside the target range is based at least in part on determining that the supply voltage is below the lower voltage threshold, and Wherein generating the AC signal at the pin includes generating a voltage pulse of a certain amount at the pin based at least in part on determining that the supply voltage is below the lower voltage threshold.

22. A memory device comprising: a memory cell array; a pin for providing output of loopback information based at least in part on a loopback setting of the memory device; A capacitor component coupled to the pin, the capacitor component is used to transmit an alternating current (AC) signal at the pin; as well as A controller operable to cause the memory device to: determining that the loopback setting indicates that the memory device operates in a mode other than a loopback mode; setting the pin to an inactive state based at least in part on determining that the memory device is operating in the mode different than the loopback mode; After setting the pin to the inactive state, determining that a supply voltage of the memory cell array exceeds a target range associated with the supply voltage; and The AC signal is generated at the pin based at least in part on determining that the supply voltage is outside the target range.

23. The memory device of claim 22, wherein setting the pin to the inactive state comprises setting the pin to a high impedance state or terminating the pin.

24. The memory device of claim 22, wherein the controller is further operable to cause the memory device to: determining that the loopback setting indicates that the memory device is operating in the loopback mode; and The output is provided based at least in part on determining that the loopback setting indicates that the memory device is operating in the loopback mode.

25. The memory device of claim 22, wherein generating the AC signal comprises generating a voltage pulse of a certain magnitude at the pin.

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