High bandwidth memory with multiple channels

Abstract

Disclosed herein is a device comprising: a control chip; a plurality of memory chips stacked on the control chip, the plurality of memory chips comprising a first and a second memory chip; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors comprises a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory chips substantially simultaneously output read data read from the first channel to the first and second via conductors, respectively.

Description

Background Art

[0001] A memory device called HBM (High Bandwidth Memory) has a structure in which memory chips each having a plurality of channels are stacked. The channels can operate asynchronously and non-exclusively with each other. Since different data paths are respectively assigned to the channels, HBM can input or output a large amount of data at high speed.

[0002] When access to a certain channel in a general HBM is requested from the controller, a memory cell array included in any one of the stacked memory chips is selected. Therefore, when access is concentrated in the same channel, current consumption is concentrated in the same area of ​​the same memory chip, which may cause a change in power potential. Summary of the invention

[0003] Disclosed herein is an example device for a high bandwidth memory with multiple channels. In one aspect of the present disclosure, a device includes: a control chip; a plurality of memory chips stacked on the control chip, the plurality of memory chips including a first and a second memory chip; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory chips output read data read from the first channel to the first and second via conductors, respectively, substantially simultaneously.

[0004] Additionally or alternatively, the first and second memory chips simultaneously receive write data to be written to the first channel from the first and second via conductors, respectively.

[0005] Additionally or alternatively, the first channel in the first memory chip is located at the same planar position as the first channel in the second memory chip.

[0006] Additionally or alternatively, the first channel in each of the first and second memory chips has a plurality of memory banks including a first memory bank, and the first memory bank in the first memory chip is located at a different planar position than the first memory bank in the second memory chip.

[0007] Additionally or alternatively, each of the first and second memory chips has first and second read FIFO circuits connected to the first and second via conductors, respectively.

[0008] Additionally or alternatively, the first memory chip has a first read FIFO circuit commonly assigned to the first and second via conductors, and the second memory chip has a second read FIFO circuit commonly assigned to the first and second via conductors.

[0009] Additionally or alternatively, the first read FIFO circuit is operably connected to the first via conductor without being operably connected to the second via conductor, and wherein the second read FIFO circuit is operably connected to the second via conductor without being operably connected to the first via conductor.

[0010] Additionally or alternatively, the first and second via conductors are arranged adjacent to each other.

[0011] Additionally or alternatively, each of the first and second memory chips is divided into four channels including the first channel and second to fourth channels.

[0012] Additionally or alternatively, the plurality of memory chips further include third and fourth memory chips, and each of the third and fourth memory chips is divided into four channels including fifth to eighth channels.

[0013] Additionally or alternatively, the plurality of memory chips further include fifth to eighth memory chips, each of the fifth and sixth memory chips being divided into four channels including the first to fourth channels, and each of the seventh and eighth memory chips being divided into four channels including the fifth to eighth channels.

[0014] Additionally or alternatively, the first via conductor is commonly connected to the first channel in the first and fifth memory chips, and the second via conductor is commonly connected to the first channel in the second and sixth memory chips.

[0015] Additionally or alternatively, one of the first channels in the first and second memory chips and the first channels in the fifth and sixth memory chips is exclusively activated.

[0016] In another aspect of the present disclosure, a device includes a first memory chip that outputs first n-bit data; a second memory chip that is stacked on the first memory chip, the second memory chip outputting second n-bit data; and first and second n-bit via conductors that penetrate at least the first memory chip. In response to a read command, the first and second n-bit data are simultaneously output to the first and second n-bit via conductors, respectively, thereby outputting 2n-bit data in parallel.

[0017] Additionally or alternatively, the first n-bit via conductors are operably connected to the first memory chip without being operably connected to the second memory chip, and the second n-bit via conductors are operably connected to the second memory chip without being operably connected to the first memory chip.

[0018] Additionally or alternatively, the first and second n-bit via conductors further penetrate the second memory chip.

[0019] Additionally or alternatively, further included are third and fourth n-bit via conductors penetrating at least the first memory chip. The first and second memory chips further output third and fourth n-bit data, respectively. In response to another read command, the third and fourth n-bit data are simultaneously output to the third and fourth n-bit via conductors, respectively, thereby outputting another 2n-bit data asynchronously and in parallel with the 2n-bit data.

[0020] In another aspect of the present disclosure, a device includes a first memory chip; a second memory chip stacked on the first chip; and first and second via conductors that penetrate at least the first memory chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The first channel in the first memory chip includes a first read FIFO circuit commonly assigned to the first and second via conductors. The first channel in the second memory chip includes a second read FIFO circuit commonly assigned to the first and second via conductors. The first read FIFO circuit is operably connected to the first via conductor without being operably connected to the second via conductor. The second read FIFO circuit is operably connected to the second via conductor without being operably connected to the first via conductor.

[0021] Additionally or alternatively, the first and second via conductors are arranged adjacent to each other.

[0022] Additionally or alternatively, the first channels in the first and second memory chips are activated simultaneously so that data is output in parallel via conductors to the first and second via conductors. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a schematic exploded perspective view showing an example of a semiconductor device according to the present disclosure.

[0024] Figure 2 is a schematic exploded perspective view for explaining an example of an access path included in the semiconductor device according to the present disclosure.

[0025] Figure 3A and 3Bis a plan view showing the plan view of a memory chip.

[0026] Figure 4 A diagram showing how eight memory banks are used for seamless read access.

[0027] Figure 5 is a diagram showing a layout of via conductors arranged in a via forming region.

[0028] Figure 6 is a table showing the layout of via conductors arranged in one area of ​​the via forming region.

[0029] Figure 7 is a circuit diagram showing an example of the connection relationship between via conductors and a memory cell array.

[0030] Figure 8 is a diagram showing another layout of via conductors arranged in the via forming region.

[0031] Fig.9A and 9B It is a table showing the layout of via conductors arranged in predetermined areas respectively.

[0032] Fig.10 is a circuit diagram showing another example of the connection relationship between the via conductor and the memory cell array.

[0033] Fig.11 is a schematic exploded perspective view showing another example of a semiconductor device according to the present disclosure. DETAILED DESCRIPTION

[0034] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0035] Figure 1The semiconductor device 1 shown in has a control chip 20 and four memory chips 10 to 13 stacked on the control chip 20. The memory chips 10 to 13 are, for example, DRAMs (dynamic random access memories). Each of the memory chips 10 to 13 is divided into four channels, and the channels can operate independently of each other. Therefore, terminals such as data input / output terminals, address terminals, command terminals, and clock terminals are assigned to each of the channels. Memory chips 10 and 11 are divided into channels Ch0, Ch2, Ch4, and Ch6, and memory chips 12 and 13 are divided into channels Ch1, Ch3, Ch5, and Ch7. Therefore, the semiconductor device 1 has a configuration including a total of eight channels. The terminals such as data input / output terminals, address terminals, command terminals, and clock terminals assigned to channels Ch0 to Ch7 are connected to the control chip 20 by providing via conductors that penetrate the memory chips 10 to 13.

[0036] As in Figure 1 As shown in FIG. , the channel Ch0 included in the memory chips 10 and 11 and the channel Ch1 included in the memory chips 12 and 13 are located at the same position in a plan view, the channel Ch2 included in the memory chips 10 and 11 and the channel Ch3 included in the memory chips 12 and 13 are located at the same position in a plan view, the channel Ch4 included in the memory chips 10 and 11 and the channel Ch5 included in the memory chips 12 and 13 are located at the same position in a plan view, and the channel Ch6 included in the memory chips 10 and 11 and the channel Ch7 included in the memory chips 12 and 13 are located at the same position in a plan view. Each of the channels Ch0 to Ch7 is divided into pseudo channels PC0 and PC1. When one of the channels Ch0 to Ch7 is to be accessed, the access is performed by specifying the pseudo channel PC0 or PC1. Two pseudo channels PC0 and PC1 in the same channel cannot be accessed at the same time. At the same time, different channels Ch0 to Ch7 can be accessed asynchronously and non-exclusively.

[0037] In the present embodiment, the number of I / O bits per channel is 144 bits, of which 128 bits are actual data and 16 bits are ECC (error correction code) data. Half of the 128 bits of actual data, i.e., 64 bits, are assigned to one of the pseudo channels, i.e., pseudo channel PC0, and the remaining 64 bits are assigned to another pseudo channel PC1. Eight bits of ECC data are assigned to each of pseudo channels PC0 and PC1. The 64 bits of data assigned to pseudo channel PC0 are composed of a group DW0 (DWord0) containing 32 bits and a group DW1 (DWord1) containing 32 bits. Similarly, the 64 bits of data assigned to pseudo channel PC1 are composed of a group DW2 containing 32 bits and a group DW3 containing 32 bits. Four bits of ECC data are assigned to each of the groups.

[0038] The two groups constituting the same pseudo channel in the same channel are respectively assigned to different memory chips. For example, in the pseudo channel PC0 of the channel Ch0, the group DW0 is assigned to the memory chip 10, and the group DW1 is assigned to the memory chip 11. Therefore, for example, when a read request is issued to the pseudo channel PC0 of the channel Ch0, 32-bit data is output in parallel from the memory chips 10 and 11, respectively. Figure 2 As shown in FIG. 1 , the via conductor 31 of the group DW0 assigned to the pseudo channel PC0 in the channel Ch0 and the via conductor 32 of the group DW1 assigned to the pseudo channel PC0 in the channel Ch0 are provided independently. That is, the control chip 20 and the memory chips 10 to 13 are connected in a one-to-one relationship, and one via conductor is not assigned to a plurality of memory chips. Therefore, even when there is a difference in the operating speed among the memory chips 10 to 13 due to process variation, data will not conflict in the via conductor. In addition, the memory cell array activated with one access is distributed to the two memory chips, and thus the change of the power potential due to the concentration of current consumption can also be suppressed.

[0039] Figure 3A is a plan view showing a plan view of memory chips 10 and 12, and Figure 3B 1 is a plan view showing a plan view of the memory chips 11 and 13. Figure 3A and 3B As shown in FIG. 1 , each of the pseudo channels in each channel is divided into 16 memory banks including memory banks B0 to B15. The positions of memory banks B0 to B15 on the memory chips are different between memory chips 10 and 12 and memory chips 11 and 13. The positions of memory banks B0 to B15 on memory chips 10 and 12 are 180 degrees different from the positions of memory banks B0 to B15 on memory chips 11 and 13. Therefore, the planar positions of memory banks B0 to B15 constituting the same pseudo channel in the same channel are different between the two memory chips. For example, the planar position of memory bank B0 included in the pseudo channel PC0 of channel Ch0 is different between memory chip 10 and memory chip 11.

[0040] Figure 4 2 is a diagram showing an example of executing access to the pseudo channel PC0 in the channel Ch0 and access to the pseudo channel PC0 in the channel Ch4 in parallel. Figure 4 In the example shown in , seamless read access using eight memory banks is performed in each of channels Ch0 and Ch4. In the present embodiment, even in the case of performing such seamless read access, the positions of the accessed memory banks can be allocated, and therefore, changes in power potential due to concentration of current consumption can be suppressed.

[0041] exist Figure 3A and 3B In the illustrated via forming region 30, a plurality of via conductors penetrating the memory chip are arranged. Figure 5 Layout of via conductors arranged in the via forming region 30 is shown in FIG. Figure 5 The signals SID0 to SID3 shown in FIG. 1 are chip IDs corresponding to the memory chips 10 to 13, respectively. For example, the via conductors of the group DW0 corresponding to the pseudo channel PC0 in the channel Ch0 of the memory chip 10 are arranged in the area 31. Similarly, the via conductors of the group DW1 corresponding to the pseudo channel PC0 in the channel Ch0 of the memory chip 11 are arranged in the area 32. Figure 5 The via conductors in regions 31 and 32 shown in FIG. Figure 2 The via conductors 31 and 32 are shown in FIG.

[0042] When read access is performed on the pseudo channel PC0 in the channel Ch0, 32-bit read data read from the memory chip 10 is supplied to the control chip 20 through the via conductors arranged in the area 31, and 32-bit read data read from the memory chip 11 is supplied to the control chip 20 through the via conductors arranged in the area 32. The 32-bit read data read from the memory chip 10 and the 32-bit read data read from the memory chip 11 are transmitted substantially at the same time. When write access is performed on the pseudo channel PC0 in the channel Ch0, 32-bit write data to be written to the memory chip 10 is supplied from the control chip 20 to the memory chip 10 through the via conductors arranged in the area 31, and 32-bit write data to be written to the memory chip 11 is supplied from the control chip 20 to the memory chip 11 through the via conductors arranged in the area 32. The 32-bit write data to be written to the memory chip 10 and the 32-bit write data to be written to the memory chip 11 are transmitted substantially at the same time. A plurality of via conductors for supplying address signals to the memory chips 10 to 13 are arranged in the area 33.

[0043] Figure 6 is a table showing the layout of via conductors arranged in the area 31. Figure 6As shown in FIG. 1 , the via conductors arranged in the area 31 include 32 via conductors corresponding to the data DQ0R to DQ31R, respectively, and 32 via conductors corresponding to the data DQ0F to DQ31F, respectively. The data DQ0R to DQ31R are 32-bit data simultaneously input / output in synchronization with the rising edge of the clock signal, and the data DQ0F to DQ31F are 32-bit data simultaneously input / output in synchronization with the falling edge of the clock signal. Other via conductors such as via conductors corresponding to the data mask signals DM0R to DM3R and DM0F to DM3F and via conductors corresponding to the read clock signal and the write clock signal are also included in the area 31. In FIG. Figure 6 In the example shown in , pairs of data (eg, data DQ0R and data DQ0F) are arranged adjacent to each other.

[0044] Figure 7 is a circuit diagram showing an example of the connection relationship between via conductors and a memory cell array. Figure 7 In the example shown in FIG, a read path including an internal buffer 43, a read FIFO circuit 44, a parallel-serial conversion circuit 45, and an output buffer 46, and a write path including an input receiver 47, a serial-parallel conversion circuit 48, and an internal buffer 49 are connected in parallel between a via conductor 41 and a memory cell array 42 corresponding to data DQ0R. Similarly, a read path including an internal buffer 53, a read FIFO circuit 54, a parallel-serial conversion circuit 55, and an output buffer 56, and a write path including an input receiver 57, a serial-parallel conversion circuit 58, and an internal buffer 59 are connected in parallel between a via conductor 51 and a memory cell array 52 corresponding to data DQ0F. In this way, Figure 7 In the example shown in , the read path and the write path are individually assigned to each of the via conductors.

[0045] Figure 8 Another layout of via conductors arranged in the via forming region 30 is shown. Figure 8 In the example shown in FIG. 1 , multiple via conductors corresponding to the same pseudo channel in the same channel are not collectively arranged for each of the memory chips, that is, for each of the groups DW, multiple via conductors corresponding to two groups DW are mixed in one area. For example, the via conductors of the groups DW0 and DW1 corresponding to the pseudo channel PC0 in the channel Ch0 are arranged in areas 34 and 35 in a mixed manner.

[0046] Fig.9A and 9B The layout of the via conductors arranged in areas 34 and 35 is shown respectively. Fig.9A and 9BAlthough the layout of the via conductors arranged in areas 34 and 35 is similar to that arranged in Figure 6 3 is the same as that in the region 31 shown in FIG. 3 , but the via conductors adjacent in the row direction are assigned to different memory chips. That is, the via conductors arranged in columns A, C, E, and G are assigned to the memory chip 10 (SID0 / DW0), and the via conductors arranged in columns B, D, F, and H are assigned to the memory chip 11 (SID1 / DW1) in the region 34. At the same time, the via conductors arranged in columns A, C, E, and G are assigned to the memory chip 11 (SID1 / DW1), and the via conductors arranged in columns B, D, F, and H are assigned to the memory chip 10 (SID0 / DW0) in the region 35.

[0047] Fig.10 is a circuit diagram showing another example of the connection relationship between the via conductor and the memory cell array, and showing a layout suitable for the via conductor in which Figure 8 , 9A and 9B. Fig.10 , the output buffer 62, the input receiver 63, the parallel-serial conversion circuit 64, and the serial-parallel conversion circuit 65 are assigned to the via conductor 61 corresponding to the data DQ0R, and the output buffer 72, the input receiver 73, the parallel-serial conversion circuit 74, and the serial-parallel conversion circuit 75 are assigned to the via conductor 71 corresponding to the data DQ0F. The memory cell array 81 is commonly assigned to the parallel-serial conversion circuits 64 and 74 via the internal buffer 82 and the read FIFO circuit 83, and is commonly assigned to the serial-parallel conversion circuits 65 and 75 via the internal buffer 84. However, one of the paths is deactivated and is not operably connected to the memory cell array 81. For example, when the output buffer 62, the input receiver 63, the parallel-serial conversion circuit 64, and the serial-parallel conversion circuit 65 corresponding to the via conductor 61 are activated, the output buffer 72, the input receiver 73, the parallel-serial conversion circuit 74, and the serial-parallel conversion circuit 75 corresponding to the via conductor 71 are deactivated. Therefore, the via conductor 71 and the memory cell array 81 are not operatively connected to each other. In this case, the via conductor 61 and the memory cell array 81 are operatively connected to each other.

[0048] In this way, when Figure 8 , 9A When the via conductors are arranged in the layout shown in FIG. 9B , adjacent via conductors are assigned to different memory chips, and thus the internal buffers 82 and 84 and the read FIFO circuit 83 can be assigned to two via conductors in common. This reduces the number of internal buffers 82 and 84 and the read FIFO circuit 83 by half, and thus the chip area can be reduced.

[0049] exist Fig.11 The semiconductor device 2 shown in FIG. 1 has a control chip 20, and eight memory chips 10 to 17 stacked on the control chip 20. That is, the semiconductor device 2 has a structure in which four memory chips 14 to 17 are added to the control chip 20. Figure 1 1. The memory chips 14 to 17 have the same address configuration as that of the memory chips 10 to 13, respectively, except for the chip address (SID). For example, the selection of the memory chips 10 to 13 and the memory chips 14 to 17 may be performed using the least significant bit of the chip address.

[0050] Therefore, for example, when a read request is issued to the pseudo channel PC0 in the channel Ch4 and when the least significant bit of the chip address is 0 (zero), the memory chips 10 and 11 are selected so that 32-bit read data is output from the memory chip 10 through the via conductor 91 of the group DW0 assigned to the pseudo channel PC0 in the channel Ch4, and 32-bit read data is output from the memory chip 11 through the via conductor 92 of the group DW1 assigned to the pseudo channel PC0 in the channel Ch4. In this case, the pseudo channel PC0 of the channel Ch4 included in the memory chips 14 and 15 is not accessed. On the other hand, when a read request is issued to the pseudo channel PC0 in the channel Ch4 and the least significant bit of the chip address is 1, the memory chips 14 and 15 are selected so that 32-bit read data is output from the memory chip 14 through the via conductor 91, and 32-bit read data is output from the memory chip 15 through the via conductor 92. In this case, the pseudo channel PC0 of the channel Ch4 included in the memory chips 10 and 11 is not accessed. As described above, Figure 1 Compared with the semiconductor device 1 shown in Fig.11 The number of memory chips in the semiconductor device 2 shown is doubled, and thus the connection between the control chip 20 and the memory chips 10 to 17 has a one-to-two relationship.

[0051] The number of memory chips is not specifically limited. For example, twelve memory chips may be stacked on the control chip. In this case, the connection between the control chip and the memory chips has a one-to-three relationship. In addition, the number of memory chips may also be two.

[0052] Although the present invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specific disclosed embodiments to other alternative embodiments and / or uses of the present invention and obvious modifications and equivalents thereof. In addition, based on this disclosure, other modifications within the scope of the present invention will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations may be made to the specific features and aspects of the embodiments and still fall within the scope of the present invention. It should be understood that the various features and aspects of the disclosed embodiments may be combined or substituted with each other to form a variation pattern of the disclosed invention. Therefore, it is desired that the scope of at least some of the present invention disclosed herein should not be limited by the specific disclosed embodiments described above.

Claims

1. A device comprising: Control chip; A plurality of memory chips stacked on the control chip, the plurality of memory chips comprising a first memory chip and a second memory chip; and a plurality of via conductors connected between the plurality of memory chips and the control chip, wherein each of the first and second memory chips is divided into a plurality of channels including a first channel, wherein the plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip, wherein the first and second memory chips substantially simultaneously output the read data read from the first channel to the first and second via conductors, respectively, and Each of the first and second memory chips has first and second read FIFO circuits connected to the first and second via conductors, respectively. 2 . The apparatus of claim 1 , wherein the first and second memory chips simultaneously receive write data to be written to the first channel from the first and second via conductors, respectively. 3 . The apparatus of claim 1 , wherein the first channel in the first memory chip is located at the same planar position as the first channel in the second memory chip.

4. The device according to claim 3, wherein the first channel in each of the first and second memory chips has a plurality of memory banks including a first memory bank, and The first memory bank in the first memory chip is located at a different plane position from the first memory bank in the second memory chip.

5. The device according to claim 1, wherein the first read FIFO circuit of the first memory chip is commonly assigned to the first and second via conductors, and The second read FIFO circuit of the second memory chip is commonly assigned to the first and second via conductors.

6. The device according to claim 5, wherein the first read FIFO circuit is operably connected to the first via conductor and is not operably connected to the second via conductor, and Wherein the second read FIFO circuit is operably connected to the second via conductor and is not operably connected to the first via conductor. The apparatus of claim 6 , wherein the first and second via conductors are arranged adjacent to each other.

8. The apparatus of claim 1, wherein each of the first and second memory chips is divided into four channels including the first channel and second to fourth channels.

9. The device according to claim 8, wherein the plurality of memory chips further include third and fourth memory chips, and Wherein each of the third and fourth memory chips is divided into four channels including fifth to eighth channels.

10. The device according to claim 9, wherein the plurality of memory chips further include fifth to eighth memory chips, wherein each of the fifth and sixth memory chips is divided into four channels including the first to fourth channels, and Wherein each of the seventh and eighth memory chips is divided into four channels including the fifth to eighth channels.

11. The device according to claim 10, wherein the first via conductor is commonly connected to the first channels in the first and fifth memory chips, and The second via conductor is commonly connected to the first channels in the second and sixth memory chips. 12 . The apparatus of claim 11 , wherein one of the first channels in the first and second memory chips and the first channels in the fifth and sixth memory chips is exclusively activated.

13. An apparatus comprising: A first memory chip outputs first n-bit data; A second memory chip is stacked on the first memory chip, the second memory chip outputting second n-bit data; and first and second n-bit via conductors penetrating at least the first memory chip, wherein in response to a read command, the first and second n-bit data are simultaneously output to the first and second n-bit via conductors, respectively, thereby outputting 2n-bit data in parallel, and Each of the first and second memory chips has first and second read FIFO circuits connected to the first and second n-bit via conductors, respectively.

14. The device according to claim 13, wherein the first n-bit via conductors are operably connected to the first memory chip and are not operably connected to the second memory chip, and The second n-bit via conductors are operably connected to the second memory chip and are not operably connected to the first memory chip.

15. The apparatus of claim 14, wherein the first and second n-bit via conductors further penetrate the second memory chip.

16. The apparatus of claim 13, further comprising third and fourth n-bit via conductors penetrating at least the first memory chip, The first and second memory chips further output third and fourth n-bit data respectively. In response to another read command, the third and fourth n-bit data are simultaneously output to the third and fourth n-bit via conductors, respectively, thereby outputting another 2n-bit data in parallel asynchronously with the 2n-bit data.

17. An apparatus comprising: a first memory chip; a second memory chip stacked on the first chip; and first and second via conductors penetrating at least the first memory chip, wherein each of the first and second memory chips is divided into a plurality of channels including a first channel, wherein the first channel in the first memory chip includes a first read FIFO circuit commonly assigned to the first and second via conductors, wherein the first channel in the second memory chip includes a second read FIFO circuit commonly assigned to the first and second via conductors, wherein the first read FIFO circuit is operably connected to the first via conductor and is not operably connected to the second via conductor, and Wherein the second read FIFO circuit is operably connected to the second via conductor and is not operably connected to the first via conductor.

18. The apparatus of claim 17, wherein the first and second via conductors are arranged adjacent to each other.

19. The apparatus of claim 17, wherein the first channels in the first and second memory chips are activated simultaneously so that data is output to the first and second via conductors in parallel.

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