Control Method for Multiple Storage Devices and Related Memory System

Abstract

The present invention provides a control method for multiple storage devices, where the multiple storage devices include a first storage device and a second storage device, and the control method includes: determining a first operation timing and a second operation timing at least according to whether a first instruction signal that a first memory controller needs to transmit to the first storage device belongs to an access instruction or a non-access instruction; controlling the first memory controller to transmit the first instruction signal to the first storage device according to the first operation timing; and controlling the second memory controller to transmit a second instruction signal to the second storage device according to the second operation timing.

Description

Technical Field

[0001] The present invention relates to a control method for multiple storage devices and a related memory system. Background Art

[0002] In modern electronic system design, a dynamic random access memory (DRAM) system with double data rate (DDR) is often divided into two parts: a memory control logic and a physical layer. A double data rate physical layer interface (DFI) is defined between the memory controller logic and the physical layer to achieve standard interconnection between the two. Briefly, the DFI standard is proposed to define a general interface between the memory control logic and the physical layer, that is, to convert the instruction signals and data signals transmitted by the memory controller into specifications that conform to the memory device (such as a dual in-line memory module (DIMM)), and then transmit them to the storage device. Similarly, the data signals transmitted by the storage device can also be converted into specifications that conform to the memory controller through the DFI interface and then transmitted to the memory controller.

[0003] Traditional memory controllers can be connected to multiple storage devices (such as double-data-rate fourth generation synchronous dynamic random access memory (DDR4)). Each time the memory controller transmits instruction signals (such as read, write, active, precharge, auto-refresh, self-refresh, etc.), they are transmitted to each memory device through the DFI interface. Therefore, each memory device operates simultaneously. For example, a memory controller is connected to three memory devices. When the memory controller wants to read a memory device, in the case of a shared instruction interface, it will receive three times the size of the reply data (taking DDR4 which can access 16 bits of data each time as an example, a data width of 16 bits * 3 = 48 bits is required, resulting in an increase in the required bandwidth). If you want to access a single memory device separately, you need to increase an additional set of instruction interfaces through a shunt method, thereby reducing the required data width (only 16 bits * 1 = 16 bits of data width). However, the additional instruction interface also means that the memory controller requires additional pins to separately control the memory devices, resulting in layout limitations and increased costs on the circuit board. Summary of the Invention

[0004] Accordingly, the main object of the present invention is to provide a time-sharing control method and related apparatus for a storage device, and has a preferred bandwidth utilization mechanism to solve the above problems.

[0005] In one embodiment of the present invention, a control method for multiple storage devices is provided, where the multiple storage devices include a first storage device and a second storage device, and the control method includes: determining a first operation timing and a second operation timing at least according to whether a first instruction signal to be transmitted from a first memory controller to the first storage device belongs to an access instruction or a non-access instruction; controlling the first memory controller to transmit the first instruction signal to the first storage device according to the first operation timing; and controlling the second memory controller to transmit a second instruction signal to the second storage device according to the second operation timing.

[0006] In another embodiment of the present invention, a memory system is provided, which includes a first storage device and a second storage device, a first flash memory controller and a second flash memory controller for respectively accessing the first storage device and the second storage device, and a timing management device. During the operation of the memory system, the timing management device determines a first operation timing and a second operation timing at least according to whether a first instruction signal to be transmitted from a first memory controller to the first storage device belongs to an access instruction or a non-access instruction, so as to control the first memory controller to transmit the first instruction signal to the first storage device according to the first operation timing, and control the second memory controller to transmit the second instruction signal to the second storage device according to the second operation timing. Description of the Drawings

[0007] Figure 1 A schematic diagram of a memory system according to an embodiment of the present invention;

[0008] Figure 2 A schematic diagram of a transmission timing according to an embodiment of the present invention;

[0009] Figure 3 A schematic diagram of a transmission timing according to another embodiment of the present invention;

[0010] Figure 4 A flowchart of a control method for multiple storage devices according to an embodiment of the present invention;

[0011] Figure 5 A schematic diagram of a transmission timing according to another embodiment of the present invention;

[0012] Figure 6 A flowchart of a control method for multiple storage devices according to another embodiment of the present invention. Detailed Description of the Invention

[0013] Figure 1 Schematic diagram of a memory system 100 according to an embodiment of the present invention. As Figure 1As shown, the memory system 100 includes a timing management device 110, multiple memory controllers (three memory controllers 120_1 to 120_3 in this embodiment), a double data rate physical layer interface (hereinafter simply referred to as DFI interface) 130, and multiple storage devices (three storage devices 140_1 to 140_3 in this embodiment). The timing management device 110 is used to allocate different operation timings to each of the memory controllers 120_1 to 120_3 according to the frequency signal generated by a frequency generator (not shown in the figure). For example, the processing circuit 112 in the timing management device 110 allocates the first operation timing OT1 to the memory controller 120_1, allocates the second operation timing OT2 to the memory controller 120_2, and allocates the third operation timing OT3 to the memory controller 120_3. The length and interval of each operation timing can be configured according to the length of the frequency period. Therefore, the memory controller 120_1 transmits an instruction signal C1 during the first operation timing OT1, the memory controller 120_2 transmits an instruction signal C2 during the second operation timing OT2, and the memory controller 120_3 transmits an instruction signal C3 during the third operation timing OT3, where the first operation timing OT1, the second operation timing OT2, and the third operation timing OT3 do not have overlapping times. Further, after the DFI interface 130 receives the instruction signals C1 / C2 / C3 (such as read, write, active, precharge, auto-refresh, self-refresh, etc. instructions), it will convert them into chip select instructions (chip select, CS), row address control instructions (Row Address Strobe, RAS), column address control instructions (Column Address Strobe, CAS), and write enable instructions (Write Enable, WE) with high or low levels according to the operations indicated by the instruction signals, and transmit them to the memory devices 140_1 to 140_3. It should be noted that the memory controllers 120_1 to 120_3 of the present invention share the same group of instruction signal lines CMD and address signal lines (not shown in the figure), but are respectively provided with chip select signal lines. Therefore, the chip select instruction can achieve the function of time-division transmission. Briefly speaking, the chip select instruction CS1 of the memory controller 120_1 will be transmitted to the memory device 140_1 during the first operation timing OT1, so that the memory controller 120_1 can access the memory device 140_1 during the first operation timing OT1. Similarly, the chip select instruction CS2 of the memory controller 120_2 will be transmitted to the memory device 140_2 during the second operation timing OT2, so that the memory controller 120_2 can access the memory device 140_2 during the second operation timing OT2, and so on.On the other hand, the column address control instructions, row address control instructions, and write enable instructions of the memory controllers 120_1, 120_2, or 120_3 are simultaneously transmitted to the memory devices 140_1 to 140_3, so that the mechanism of sharing the DFI interface 130 can be realized.

[0014] In the above timing control of the memory controllers 120_1 to 120_3, the timing management device 100 divides the time series into multiple intervals, so that the instruction signals C1 to C3 of the memory controllers 120_1 to 120_3 are only transmitted in the allocated intervals. Therefore, multiple memory controllers 120_1 to 120_3 can share a set of instruction signal lines CMD and address signal lines, thereby reducing the number of pins of the DFI interface 130. In addition, each of the memory controllers 120_1 to 120_3 has an independently set chip select signal line, which is mapped to an independent storage device 140_1 to 140_3. Therefore, each of the memory controllers 120_1 to 120_3 only controls its own corresponding instruction timing and accesses the storage device through the corresponding chip select signals CS1 / CS2 / CS3.

[0015] Although Figure 1 the memory system 100 shown can effectively reduce the number of pins of the DFI interface 130 by sharing a set of instruction signal lines CMD and time-division transmission, however, the use of time-division transmission will also cause a delay in the instruction signals, thus affecting the overall bandwidth of the memory system 100. Therefore, in order to reduce the impact of the bandwidth reduction caused by time-division transmission, an arbiter 114 is additionally provided in the timing management device 110 in this embodiment to allocate the time intervals that the memory controllers 120_1 to 120_3 can use while minimizing the bandwidth loss.

[0016] For the convenience of the following description, in the following narrative, only Figure 1The memory controllers 120_1 and 120_2 shown will be described. That is, it is assumed that the timing management device 100 only needs to divide the time series into multiple intervals for the two memory controllers 120_1 and 120_2 to use. In the following embodiment, it is assumed that the bandwidth of the memory controller 120_1 is higher than that of the memory controller 120_2. For example, the memory controller 120_1 may have a 32-bit bandwidth, while the memory controller 120_2 has a 16-bit bandwidth. In the operation of the timing management device 100, the arbiter 114 receives the first information INFO1 and the second information INFO2 from the memory controllers 120_1 and 120_2 respectively. The first information INFO1 includes information about the instruction signal C1 that the memory controller 120_1 needs to transmit to the storage device 140_1, and the second information INFO2 includes information about the instruction signal C2 that the memory controller 120_2 needs to transmit to the storage device 140_2. Then, the arbiter 114 determines whether the instruction signal C1 is an access command or a non-access command according to the first information INFO1 and the second information INFO2. The access command includes read and write commands, and the non-access command includes activation command, precharge command, auto-refresh command, and self-refresh command. In one embodiment, if both the instruction signal C1 and the instruction signal C2 are access commands, the arbiter 114 will notify the processing circuit 112 to determine the first operation timing OT1 and the second operation timing OT2 with time evenly distributed and interleaved, so as to Figure 2 illustrate. In the figure, "CK" is the frequency signal in the memory system 100, "CMD1" corresponds to multiple instruction signals (including the instruction signal C1) from the memory controller 120_1, "CMD2" corresponds to multiple instruction signals (including the instruction signal C2) from the memory controller 120_2, and since the access command and the non-access command have different performances in the column address control instruction (RAS) and the row address control instruction (CAS), the access command is represented by the row address control instruction in the figure. As Figure 2 shown, since multiple instruction signals CMD1 and multiple instruction signals CMD2 are both access commands, the instruction signal CMD1 is in the time intervals 2T, 4T, 6T, 8T, and the instruction signal CMD2 is in the time intervals 1T, 3T, 5T, 7T for interleaved transmission.

[0017] In another embodiment, if the instruction signal C1 belongs to a non-access instruction and the instruction signal C2 belongs to an access instruction, since the non-access instruction is regarded as the main factor reducing the bandwidth, the arbiter 114 will notify the processing circuit 112 to determine that the first operation timing OT1 takes precedence over the second operation timing OT2, so that the time when the instruction signal C1 is transmitted to the first storage device 140_1 takes precedence over the time when the instruction signal C2 is transmitted to the second storage device 140_2. For Figure 3 example, in the figure, the access instruction is represented by the row address control instruction, and the non-access instruction is represented by the column address control instruction. As shown in Figure 3, the processing circuit 112 can control the memory controllers 120_1 and 120_2 so that a plurality of instruction signals CMD1 including the instruction signal C1 are transmitted in time intervals 2T, 4T, 5T, 6T, 8T, and a plurality of instruction signals CMD2 including the instruction signal C2 are transmitted in time intervals 1T, 3T, 7T, that is, the instruction signal CMD1 with the non-access instruction can interrupt the transmission of the access instruction in the instruction signal CMD2, so that the first memory controller 120_1 can transmit a plurality of instruction signals including the non-access instruction in three consecutive time intervals (i.e., three frequency cycles). In Figure 3 the illustrated embodiment, if the first operation timing OT1 and the second operation timing OT2 are not adjusted according to the access instruction and the non-access instruction, the memory controller 110_1 with a larger bandwidth will cause serious bandwidth loss because it has to transmit the non-access instruction itself. Therefore, by using the time interval "5T" originally used to transmit the instruction signal CMD2 to transmit the non-access instruction of the memory controller 110_1, the bandwidth loss can be borne by the memory controller 110_2 with a smaller bandwidth, so the overall bandwidth loss can be effectively reduced.

[0018] Figure 4 FIG. 8 is a flowchart of a control method for a plurality of storage devices according to an embodiment of the present invention. Referring to the content described in the above embodiments, the flow of the control method is as follows.

[0019] Step 400: The process starts.

[0020] Step 402: Determine whether the first instruction signal that the first memory controller needs to transmit to the first storage device belongs to an access instruction or a non-access instruction. If the first instruction signal belongs to an access instruction, the process proceeds to step 404; if the first instruction signal belongs to a non-access instruction, the process proceeds to step 406.

[0021] Step 404: Determine the first operation timing and the second operation timing with time interleaving.

[0022] Step 406: Determine a first operation timing sequence and a second operation timing sequence such that the time when the first instruction signal is transmitted to the first storage device is prior to the time when the second instruction signal is transmitted to the second storage device.

[0023] Step 408: Control the first memory controller to transmit the first instruction signal to the first storage device according to the first operation timing sequence, and control the second memory controller to transmit the second instruction signal to the second storage device according to the second operation timing sequence.

[0024] It should be noted that although Figure 2 、 Figure 3 the embodiments only use the memory controllers 120_1 and 120_2 as examples for illustration, those of ordinary skill in the art should be able to understand examples applied to three memory controllers 120_1 to 120_3 or more memory controllers. Similarly, the real-time timing management device 110 will also receive the third information INFO3 from the memory controller 120_3 for determining the first operation timing sequence OT1, the second operation timing sequence OT2, and the third operation timing sequence OT3 respectively for the memory controllers 120_1 to 120_3.

[0025] In the above Figures 2 - 4In the illustrated embodiment, the timing management device 110 mainly generates the first operation timing OT1 and the second operation timing OT2 based on whether the instruction signal C1 that the memory controller 120_1 needs to transmit to the storage device 140_1 is an access instruction or a non-access instruction. However, the above decision mechanism can also refer to the busy degrees of the memory controllers 120_1 and 120_2 at the same time. Specifically, assume that the bandwidth of the memory controller 120_1 is higher than that of the memory controller 120_2. For example, the memory controller 120_1 can have a 32-bit bandwidth, while the memory controller 120_2 has a 16-bit bandwidth. Then, in the operation of the timing management device 100, the arbiter 114 receives the first information INFO1 and the second information INFO2 from the memory controllers 120_1 and 120_2 respectively. The first information INFO1 includes the instruction signal C1 that the memory controller 120_1 needs to transmit to the storage device 140_1 and the current busy degree, and the second information INFO2 includes the instruction signal C2 that the memory controller 120_2 needs to transmit to the storage device 140_2 and the current busy degree. In an embodiment, the busy degree can be the number of instruction signals to be processed by the memory controller, and the larger the number of instruction signals to be processed, the higher the busy degree. Then, the arbiter 114 determines whether the instruction signal C1 is an access instruction or a non-access instruction according to the first information INFO1 and the second information INFO2. The access instructions include read and write instructions, and the non-access instructions include start instruction, precharge instruction, auto-refresh instruction, and self-refresh instruction. In an embodiment, if both the instruction signals C1 and C2 are access instructions, the arbiter 114 will notify the processing circuit 112 to determine the time-interleaved first operation timing OT1 and second operation timing OT2 as shown in Figure 2 In another embodiment, if the instruction signal C1 is a non-access instruction, the instruction signal C2 is an access instruction, and the difference in the busy degree of the memory controller 120_2 being higher than that of the memory controller 120_1 does not meet a preset condition (for example, the difference in the busy degree is within a range), or the difference in the busy degree of the memory controller 120_1 being higher than that of the memory controller 120_2 meets a preset condition, then the arbiter 114 determines that the first operation timing OT1 takes precedence over the second operation timing OT2, so that the time for the instruction signal C1 to be transmitted to the storage device 140_1 is prior to the time for the instruction signal C2 to be transmitted to the storage device 140_2. For example Figure 3The non-access instructions in the instruction signal CMD1 shown can interrupt the transmission of the access instructions in the instruction signal CMD2, so that the first memory controller 120_1 can transmit a plurality of instruction signals including non-access instructions in three consecutive time intervals (i.e., three frequency cycles). In another embodiment, if the instruction signal C1 belongs to a non-access instruction, the instruction signal C2 belongs to an access instruction, and the difference in the busy degree of the memory controller 120_2 being higher than that of the memory controller 120_1 meets the preset condition (for example, the difference in the busy degree exceeds the range), then since the arbiter 114 will notify the processing circuit 112 to determine as Figure 5 the time-interleaved first operation timing OT1 and second operation timing OT2 shown. In Figure 5 , although using the time interval "4T" by the memory controller 120_1 to transmit non-access instructions will cause a large bandwidth loss, in order not to affect the memory controller 120_2 with a high busy degree, the time-interleaved first operation timing OT1 and second operation timing OT2 are still adopted.

[0026] Figure 6 FIG. is a flowchart of a control method for multiple storage devices according to another embodiment of the present invention. Referring to the content described in the above embodiments, the flow of the control method is as follows.

[0027] Step 600: The process starts.

[0028] Step 602: Determine whether the first instruction signal that the first memory controller needs to transmit to the first storage device belongs to an access instruction or a non-access instruction. If the first instruction signal belongs to an access instruction, the process proceeds to step 604; if the first instruction signal belongs to a non-access instruction, the process proceeds to step 606.

[0029] Step 604: Determine the time-interleaved first operation timing and second operation timing.

[0030] Step 606: Determine whether the difference in the busy degree of the second memory controller being higher than that of the first memory controller meets the default condition. If so, the process proceeds to step 604; if not, the process proceeds to step 608.

[0031] Step 608: Determine the first operation timing and the second operation timing so that the time for the first instruction signal to be transmitted to the first storage device takes precedence over the time for the second instruction signal to be transmitted to the second storage device.

[0032] Step 610: Control the first memory controller to transmit the first instruction signal to the first storage device according to the first operation timing, and control the second memory controller to transmit the second instruction signal to the second storage device according to the second operation timing.

[0033] Briefly summarize the present invention. In the control method for multiple storage devices and the related memory system of the present invention, through time-sharing control, the memory system can effectively reduce the number of pins of the DFI interface by sharing a set of instruction signals and time-sharing transmission. In addition, in order to reduce the impact of the above time-sharing control on bandwidth, this embodiment further proposes a mechanism that allows non-access instructions of a first memory controller with higher bandwidth to interrupt access instructions of a second memory controller with higher bandwidth, so as to minimize the overall bandwidth loss.

[0034] The above are only the preferred embodiments of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the scope of the patent application of the present invention.

[0035]

Symbol Explanation

[0036] 100: Memory system

[0037] 110: Timing management device

[0038] 112: Processing circuit

[0039] 114: Arbiter

[0040] 120_1~120_3: Memory controller

[0041] 130: DFI interface

[0042] 140_1~140_3: Storage device

[0043] 400~408, 600~610: Steps

[0044] C1~C3: Instruction signal

[0045] CAS: Row address control instruction

[0046] CK: Frequency signal

[0047] CMD: Instruction signal line

[0048] CMD1: Instruction signal

[0049] CMD2: Instruction signal

[0050] CS1~CS3: Chip select instruction

[0051] DQ1~DQ3: Data signal

[0052] INFO1: First information

[0053] INFO2: Second information

[0054] INFO3: Third information

[0055] RAS: Column Address Strobe Instruction

[0056] OT1: First Operation Timing

[0057] OT2: Second Operation Timing

[0058] OT3: Third Operation Timing

Claims

1. A control method for multiple storage devices, where the multiple storage devices include a first storage device and a second storage device, and the control method includes: Determining a first operation timing sequence and a second operation timing sequence at least based on whether a first instruction signal that a first memory controller needs to transmit to the first storage device belongs to an access instruction or a non-access instruction; Controlling the first memory controller to transmit the first instruction signal to the first storage device according to the first operation timing sequence; And Controlling a second memory controller to transmit a second instruction signal to the second storage device according to the second operation timing sequence, where the bandwidth of the first memory controller is greater than the bandwidth of the second memory controller, and the step of determining the first operation timing sequence and the second operation timing sequence includes: If both the first instruction signal and the second instruction signal are the access instructions, determining the time-interleaved first operation timing sequence and second operation timing sequence; and If the first instruction signal is the non-access instruction and the second instruction signal is the access instruction, determining the first operation timing sequence and the second operation timing sequence such that the time for transmitting the first instruction signal to the first storage device is prior to the time for transmitting the second instruction signal to the second storage device.

2. The control method according to claim 1, characterized in that, The step of determining the first operation timing sequence and the second operation timing sequence includes: If the first instruction signal is the non-access instruction and the second instruction signal is the access instruction, determining the first operation timing sequence and the second operation timing sequence such that the first memory controller transmits a plurality of instruction signals including the first instruction signal to the first storage device in three consecutive frequency cycles.

3. The control method according to claim 1, wherein The step of determining the first operation timing sequence and the second operation timing sequence includes: Determining the priorities of the first operation timing sequence and the second operation timing sequence at least based on the first instruction signal that the first memory controller needs to transmit to the first storage device and based on the busy degrees of the first memory controller and the second memory controller.

4. The control method according to claim 3, wherein The step of determining the first operation timing sequence and the second operation timing sequence includes: If the first instruction signal is the non-access instruction, the second instruction signal is the access instruction, and the difference in the busy degree of the first memory controller being higher than that of the second memory controller meets a preset condition, determining the first operation timing sequence and the second operation timing sequence such that the time for transmitting the first instruction signal to the first storage device is prior to the time for transmitting the second instruction signal to the second storage device.

5. The control method according to claim 4, wherein The step of determining the first operation timing sequence and the second operation timing sequence includes: If the first instruction signal is the non-access instruction, the second instruction signal is the access instruction, and the difference in the busy degree of the first memory controller being higher than that of the second memory controller meets the preset condition, determine the first operation timing and the second operation timing, so that the first memory controller transmits a plurality of instruction signals including the first instruction signal to the first storage device in three consecutive frequency cycles.

6. The control method according to claim 3, wherein The bandwidth of the first memory controller is greater than the bandwidth of the second memory controller, and the step of determining the first operation timing and the second operation timing includes: If the first instruction signal is the non-access instruction, the second instruction signal is the access instruction, and the difference in the busy degree of the second memory controller being higher than that of the first memory controller meets a preset condition, determine the first operation timing and the second operation timing with time interleaving; and If the first instruction signal is the non-access instruction, the second instruction signal is the access instruction, and the difference in the busy degree of the second memory controller being higher than that of the first memory controller does not meet the preset condition, determine the first operation timing and the second operation timing, so that the time for the first instruction signal to be transmitted to the first storage device takes precedence over the time for the second instruction signal to be transmitted to the second storage device.

7. The control method according to claim 6, wherein The step of determining the first operation timing and the second operation timing includes: If the first instruction signal is the non-access instruction, the second instruction signal is the access instruction, and the difference in the busy degree of the second memory controller being higher than that of the first memory controller does not meet the preset condition, determine the first operation timing and the second operation timing, so that the first memory controller transmits a plurality of instruction signals including the first instruction signal to the first storage device in three consecutive frequency cycles.

8. A memory system, comprising: A first storage device and a second storage device; A first memory controller and a second memory controller for respectively accessing the first storage device and the second storage device; And A timing management device, coupled to the first memory controller and the second memory controller, for at least determining a first operation timing and a second operation timing according to whether a first instruction signal that the first memory controller needs to transmit to the first storage device belongs to an access instruction or a non-access instruction, to control the first memory controller to transmit the first instruction signal to the first storage device according to the first operation timing, and to control the second memory controller to transmit a second instruction signal to the second storage device according to the second operation timing, Among them, the bandwidth of the first memory controller is greater than that of the second memory controller, and if both the first instruction signal and the second instruction signal are the access instructions, the timing management device determines the first operation timing and the second operation timing with time interleaving; and if the first instruction signal is the non-access instruction and the second instruction signal is the access instruction, the timing management device determines the first operation timing and the second operation timing so that the time when the first instruction signal is transmitted to the first storage device takes precedence over the time when the second instruction signal is transmitted to the second storage device.

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