Display device

Abstract

The present application relates to a display device. The display device includes a display panel, a data driver, a gate driver, and a controller. The display panel includes a plurality of pixels. The data driver provides a data voltage to the plurality of pixels through data lines during an active period of a frame period, and provides a blanking voltage to the plurality of pixels through the data lines during a blanking period of the frame period. The gate driver provides a gate-on voltage to the plurality of pixels through gate lines during the active period, and provides a gate-off voltage to the plurality of pixels through the gate lines during the blanking period. The controller controls the data driver and the gate driver. When the time in the blanking period reaches a predetermined time, the blanking voltage increases and the gate-off voltage increases.

Description

Technical Field

[0001] The present disclosure generally relates to a display device and a method of operating the display device. More particularly, the present disclosure relates to a display device supporting a variable frame mode and a method of operating the display device. Background Art

[0002] A display device is provided with frame data from a host processor (e.g., a graphics processing unit (GPU)) and displays an image at a constant frame rate and is driven at approximately 60 Hertz (Hz). At the same time, in order to provide rich images, the host processor may perform rendering, and it takes a long time to render high-definition game images, virtual reality images, etc. in the host processor. Therefore, it may take a long time for the host processor to provide an image signal to the display device. In other words, when the frame rate of the host processor changes, the frame rate of the host processor and the frame rate of the display device may not match each other. Due to this mismatch between the frame rate of the host processor and the frame rate of the display device, a boundary line may be visually recognized in the image displayed on the display device, or the image displayed on the display device may be delayed.

[0003] To prevent the visibility of such a boundary line and the delay of the image, the frame rate of the host processor and the frame rate of the display device can be synchronized by synchronizing the start of the frame with the time when the main processor performs rendering. This technology is called a variable frame mode (e.g., a free-sync mode, a G-sync mode, etc.). Summary of the Invention

[0004] However, compared to the blank period in a normal mode of displaying an image at a constant frame rate, the blank period of a display device supporting a variable frame mode may increase. Therefore, due to the leakage current leaking during the increased blank period, the brightness may be further reduced and the image quality may deteriorate.

[0005] Embodiments of the inventive concept provide a display device capable of improving image quality in a variable frame mode.

[0006] Another embodiment of the inventive concept provides a method of operating the display device.

[0007] According to an embodiment of the inventive concept, a display device includes a display panel, a data driver, a gate driver, and a controller. The display panel includes a plurality of pixels. The data driver provides a data voltage to the plurality of pixels through data lines during an active period of a frame period and provides a blanking voltage to the plurality of pixels through the data lines during a blanking period of the frame period. The gate driver provides a gate-on voltage to the plurality of pixels through gate lines during the active period and provides a gate-off voltage to the plurality of pixels through the gate lines during the blanking period. The controller controls the data driver and the gate driver. When a time in the blanking period reaches a predetermined time, the blanking voltage increases and the gate-off voltage increases.

[0008] In an embodiment, the active period may have a constant time length, and the blanking period may have a variable time length.

[0009] In an embodiment, the predetermined time may be a time length of the blanking period corresponding to a maximum frame rate within a variable frame rate range supported by the display device.

[0010] In an embodiment, the gate-off voltage may have a first negative value before reaching the predetermined time, and the gate-off voltage may have a second negative value after the predetermined time. An absolute value of the second negative value may be less than an absolute value of the first negative value.

[0011] In an embodiment, the gate-off voltage may be constant after the predetermined time.

[0012] In an embodiment, the gate-off voltage may gradually increase as time in the blanking period increases after the predetermined time.

[0013] In an embodiment, the blanking voltage may be set to an average value of data voltages provided to the plurality of pixels during the active period after the predetermined time.

[0014] In an embodiment, the blanking voltage may be set to a maximum value of data voltages provided to the plurality of pixels during the active period after the predetermined time.

[0015] In an embodiment, the blanking voltage may be set to the same value as a data voltage corresponding to a maximum gray level after the predetermined time.

[0016] In an embodiment, the blanking voltage may be set for each of the data lines after the predetermined time.

[0017] In an embodiment, leakage currents of the plurality of pixels may be reduced based on the blanking voltage during the blanking period after the predetermined time.

[0018] According to an embodiment of the inventive concept, a method of operating a display device includes: providing a data voltage to a plurality of pixels during an active period of a frame period; providing a gate-on voltage to the plurality of pixels during the active period; providing a blank voltage to the plurality of pixels during a blank period of the frame period; providing a gate-off voltage to the plurality of pixels during the blank period; increasing the blank voltage when a time in the blank period reaches a predetermined time; and increasing the gate-off voltage when the time in the blank period reaches the predetermined time.

[0019] In an embodiment, the active period may have a constant time length, and the blank period may have a variable time length.

[0020] In an embodiment, the predetermined time may be a time length of the blank period corresponding to a maximum frame rate within a variable frame rate range supported by the display device.

[0021] In an embodiment, the gate-off voltage may be constant after the predetermined time.

[0022] In an embodiment, the gate-off voltage may gradually increase as the time in the blank period increases after the predetermined time.

[0023] In an embodiment, the blank voltage may be set to an average value of the data voltages provided to the plurality of pixels during the active period after the predetermined time.

[0024] In an embodiment, the blank voltage may be set to a maximum value of the data voltages provided to the plurality of pixels during the active period after the predetermined time.

[0025] In an embodiment, the blank voltage may be set to the same value as the data voltage corresponding to the maximum gray level after the predetermined time.

[0026] In an embodiment, the blank voltage may be set for each of the data lines after the predetermined time.

[0027] Accordingly, in a display device according to an embodiment, during the blank period after the predetermined time, the blank voltage provided to the pixels may be increased, and the gate-off voltage provided to the pixels may be increased. Accordingly, the display device may reduce leakage current leaking from the pixels during the blank period after the predetermined time. Accordingly, even if the time length of the blank period for each frame period is different, the deviation in the amount of leakage current leaking for each frame period may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other features of the inventive concept will become more apparent by describing embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0029] Figure 1is a block diagram showing a display device according to an embodiment of the inventive concept;

[0030] Figure 2 is a flowchart showing a method of operating a display device according to an embodiment of the inventive concept;

[0031] Figure 3 is showing according to Figure 2 an example of a timing diagram for changing a blanking voltage and a gate-off voltage in a method of operating a display device;

[0032] Figures 4 to 9 is a diagram for explaining an example of a blanking voltage increased during a blanking period after a predetermined time;

[0033] Figure 10 is showing included in Figure 1 a circuit diagram of a pixel in a display device;

[0034] Figure 11 is a flowchart showing a method of operating a display device according to another embodiment of the inventive concept;

[0035] Figure 12 is showing according to Figure 11 an example of a timing diagram for changing a blanking voltage and a gate-off voltage in a method of operating a display device; and

[0036] Figures 13 to 16 is a timing diagram showing an example of changing a blanking voltage and a gate-off voltage according to still another embodiment of the inventive concept. Detailed Description

[0037] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. It will be understood that although terms such as "first", "second", and "third" may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the teachings herein, a "first element", "first component", "first region", "first layer", or "first section" discussed below may be referred to as a second element, second component, second region, second layer, or second section. The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms (including "at least one") unless the context clearly dictates otherwise. "At least one" will not be construed as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises", "comprising", "includes", and / or "including" indicate the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0038] Figure 1 is a block diagram showing a display device according to an embodiment of the inventive concept.

[0039] Referring to Figure 1 , the display device 1000 according to the inventive concept may include a display panel 100, a data driver 200, a gate driver 300, and a controller 400. The display panel 100 may include data lines DL, gate lines GL, and a plurality of pixels PX. The data driver 200 may provide a data signal DS (e.g., a data voltage or a blank voltage) to the plurality of pixels PX through the data lines DL. The gate driver 300 may provide a gate signal GS (e.g., a gate-on voltage or a gate-off voltage) to the plurality of pixels PX through the gate lines GL. The controller 400 may control the data driver 200 and the gate driver 300.

[0040] The display panel 100 may include data lines DL, gate lines GL, and a plurality of pixels PX connected to the data lines DL and the gate lines GL. For example, the display panel 100 may be a liquid crystal display (“LCD”), but the present invention is not limited thereto, and may be any display panel.

[0041] Each of the plurality of pixels PX may include a switching transistor TR, a liquid crystal capacitor CLC connected to the switching transistor TR, and a storage capacitor CST connected to the switching transistor TR.

[0042] The switching transistor TR may be electrically connected to the gate line GL and the data line DL. The switching transistor TR may output a data signal DS in response to a gate signal GS. The liquid crystal capacitor CLC and the storage capacitor CST may be charged based on the data signal DS (e.g., data voltage) output from the switching transistor TR. The liquid crystal capacitor CLC may change the alignment of the liquid crystal director of the liquid crystal display, and the storage capacitor CST may maintain the alignment of the liquid crystal director of the liquid crystal display for a preset time.

[0043] Since the cut-off characteristics of the switching transistor TR are weakened during the blank period, the data voltage charged into the liquid crystal capacitor CLC and the storage capacitor CST may leak through the switching transistor TR. Specifically, when a blank voltage having a lower voltage level is provided to the switching transistor TR through the data line DL, a larger amount of current may leak through the switching transistor TR.

[0044] The data driver 200 may generate a data signal DS based on the image data ODAT and the data control signal DCTRL provided from the controller 400, and may provide the data signal DS to the plurality of pixels PX. In an embodiment, the data driver 200 may provide a data voltage corresponding to the image data ODAT as the data signal DS to the plurality of pixels PX through the data line DL during the effective period of the frame period, and may provide a blank voltage as the data signal DS to the plurality of pixels PX through the data line DL during the blank period of the frame period. For example, the data control signal DCTRL may include an output data enable signal, a horizontal start signal, and a load signal. In an embodiment, the data driver 200 may be implemented using one or more integrated circuits (“ICs”). In another embodiment, the data driver 200 may be directly mounted on the display panel 100, may be connected to the display panel 100 in the form of a chip on film (“COF”), or may be integrated on the periphery of the display panel 100.

[0045] The gate driver 300 may generate a gate signal GS based on a gate control signal GCTRL provided from the controller 400, and may transmit the gate signal GS to a plurality of pixels PX through a gate line GL. For example, the gate control signal GCTRL may include a vertical start signal, a clock signal, etc. In addition, the gate driver 300 may also be provided with a gate-on voltage and a gate-off voltage from the controller 400 or a power management circuit (not shown), and may provide the gate-on voltage and the gate-off voltage to each pixel PX as the gate signal GS. In an embodiment, the gate driver 300 may sequentially provide a gate-on voltage as the gate signal GS to a plurality of pixels PX through the gate line GL in pixel row units (i.e., pixels PX connected to the same gate line GL) during an active period, and may provide a gate-off voltage as the gate signal GS to a plurality of pixels PX through the gate line GL during a blank period. In an embodiment, the gate driver 300 may be directly mounted on the display panel 100. In another embodiment, the gate driver 300 may be connected to the display panel 100 in the form of a COF.

[0046] The controller 400 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a GPU). For example, the input image data IDAT may be RGB data including red (R) image data, green (G) image data, and blue (B) image data. In addition, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 400 may provide the gate control signal GCTRL to the gate driver 300 based on the input image data IDAT and the control signal CTRL, and provide image data ODAT and a data control signal DCTRL to the data driver 200.

[0047] In the display device 1000 according to an embodiment of the inventive concept, when the time of the blank period reaches a predetermined time, the controller 400 may control the data driver 200 to increase the blank voltage, and when the time of the blank period reaches a predetermined time, the controller 400 may control the gate driver 300 to increase the gate-off voltage. Accordingly, in the plurality of pixels PX of the display device 1000, the leakage current leaking during the blank period after the predetermined time may be reduced. Accordingly, even if the time length of the blank period for each frame period is different, the display device 1000 may reduce the deviation of the leakage current leaking in each frame period.

[0048] Figure 2 is a flowchart showing a method of operating a display device according to an embodiment of the inventive concept. Figure 3 is shown according to Figure 2Timing diagram of an example of a method for operating a display device to change a blanking voltage and a gate-off voltage. Figures 4 to 9 A diagram for explaining an example of a blanking voltage increased during a blanking period after a predetermined time. Figure 10 It shows included in Figure 1 A circuit diagram of pixels in the display device of

[0049] Referring to Figure 1 、 Figure 2 and Figure 3 ,The data driver 200 may provide a data voltage as a data signal DS (S110) to a plurality of pixels PX during an active period of a frame period. The gate driver 300 may provide a gate-on voltage as a gate signal GS (S130) to the plurality of pixels PX during the active period. In other words, the gate-on voltage may be sequentially provided to the plurality of pixels PX in units of pixel rows during the active period, and the liquid crystal capacitance CLC and the storage capacitance CST of each of the plurality of pixels PX may receive the data voltage through a switching transistor TR turned on in response to the gate-on voltage. Therefore, the data voltage may be charged into the liquid crystal capacitance CLC and the storage capacitance CST.

[0050] The data driver 200 may provide a blanking voltage as a data signal DS (S150) to the plurality of pixels PX during a blanking period after the active period. The gate driver 300 may provide a gate-off voltage as a gate signal GS (S170) to the plurality of pixels PX during the blanking period. In other words, the blanking voltage may be provided to the source of the switching transistor TR of each of the plurality of pixels PX, and the gate-off voltage may be provided to the gate of the switching transistor TR of each of the plurality of pixels PX. In an embodiment, the blanking voltage may be the same as the data voltage corresponding to the minimum gray level, but the present invention is not limited thereto.

[0051] The controller 400 may compare the time of the blanking period with a predetermined time (S190). In an embodiment, the active period may be a fixed active period having a constant time length, and the blanking period may be a variable blanking period having a variable time length. In addition, the predetermined time may be the time of the blanking period corresponding to the maximum frame rate within the variable frame rate range supported by the display device 1000. A detailed description thereof will be given later with reference to Figure 3 for a detailed description thereof.

[0052] When the time of the blank period reaches a predetermined time, if the blank period ends and the next frame period starts (S190: No), the controller 400 may control the data driver 200 such that the data driver 200 provides data voltages to the plurality of pixels PX during the active period of the next frame period (S110), and may control the gate driver 300 such that the gate driver 300 provides gate-on voltages to the plurality of pixels PX during the active period of the next frame period (S130).

[0053] On the other hand, when the time of the blank period reaches a predetermined time, if the blank period continues without ending (S190: Yes), the controller 400 may control the data driver 200 such that the data driver 200 provides increased blank voltages to the plurality of pixels PX during the blank period after the predetermined time (S210), and may control the gate driver 300 such that the gate driver 300 provides increased gate-off voltages to the plurality of pixels PX during the blank period after the predetermined time (S230).

[0054] For example, as Figure 3 shown, the periods or frequencies of the renderings 410, 430, and 450 executed by the host processor may not be constant, and the host processor may provide input image data IDAT (i.e., frame data FD1, FD2, and FD3) to the display device 1000 in synchronization with the non-constant periods or frequencies of the renderings 410, 430, and 450. Accordingly, the frame periods F1, F2, and F3 of the display device 1000 may each include fixed active periods ACT1, ACT2, and ACT3 having a constant time length, and variable blank periods BLANK1, BLANK2, and BLANK3 having a variable time length. As the frame rate increases, the time length of one frame period may decrease, and as the frame rate decreases, the time length of one frame period may increase. The frame rate may mean the number of frames transmitted per second (Hz or frames / second).

[0055] Specifically, when rendering the second frame data FD2 at a frequency greater than about 144 Hz in the first frame period F1, the host processor may provide the first frame data FD1 to the display device 1000 at a frame rate of about 144 Hz. In addition, the host processor may output the second frame data FD2 during the active period ACT2 of the second frame period F2, and may continue the blank period BLANK2 of the second frame period F2 until the rendering 430 of the third frame data FD3 is completed. Thus, when rendering the third frame data FD3 at a frequency of about 60 Hz in the second frame period F2, the host processor may provide the second frame data FD2 to the display device 1000 at a frame rate of about 60 Hz by increasing the blank period BLANK2 of the second frame period F2. When rendering the fourth frame data FD4 at a frequency of about 144 Hz again in the third frame period F3, the host processor may provide the third frame data FD3 to the display device 1000 at a frame rate of about 144 Hz again.

[0056] One frame period of the display device 1000 may include an active period in which frame data is output and a blank period after the active period. For example, the first frame period F1 of the display device 1000 may include an active period ACT1 in which the first frame data FD1 is output and a blank period BLANK1 after the active period ACT1. The second frame period F2 of the display device 1000 may include an active period ACT2 in which the second frame data FD2 is output and a blank period BLANK2 after the active period ACT2. During each active period ACT1, ACT2, and ACT3, data voltage may be charged into the plurality of pixels PX, and thus, the display device 1000 may display an image. During each blank period BLANK1, BLANK2, and BLANK3, the data voltage may be stored in the plurality of pixels PX, and thus, the display device 1000 may hold the displayed image.

[0057] In an embodiment, the active period (e.g., ACT1) may be a fixed active period having a constant time length. In other words, the time lengths of the active periods ACT1, ACT2, and ACT3 may be the same. On the other hand, the blank period may be a variable blank period having a variable time length. In other words, depending on the time lengths of the frame periods F1, F2, and F3, the time lengths of the blank periods BLANK1, BLANK2, and BLANK3 may be different from each other. For example, the time length of the blank period BLANK2 of the second frame period F2 may be longer than the time length of the blank period BLANK1 of the first frame period F1.

[0058] The frame periods F1, F2, and F3 may respectively include active periods ACT1, ACT2, and ACT3 having a constant time length, and blank periods BLANK1, BLANK2, and BLANK3 having a variable time length. A technique of synchronizing the time length of the frame period with the time length of the host processor's execution of rendering by changing the time length of the blank period may be referred to as a variable frame mode. In a display device 1000 that supports the variable frame mode (which is different from a display device that supports a normal mode), a boundary line caused by a frame rate mismatch may not be visually recognized, and an image displayed on the display device 1000 may not be delayed.

[0059] Data voltages charged in the liquid crystal capacitor CLC and the storage capacitor CST during the active period must be maintained during the blank period. However, during the blank period when a blank voltage is applied to the switching transistor TR, the data voltages charged in the liquid crystal capacitor CLC and the storage capacitor CST may leak through the switching transistor TR. Specifically, since the time lengths of the blank periods are different from each other as described above, the amounts of leakage current leaking through the switching transistor TR for each of the frame periods F1, F2, and F3 may be different.

[0060] However, in an embodiment, when the time of the blank period reaches a predetermined time, the controller 400 may control the data driver 200 to increase the blank voltage, and may control the gate driver 300 to increase the gate cut-off voltage VSS. In other words, when the time of the blank period reaches a predetermined time, the blank voltage may be increased, and the gate cut-off voltage VSS may be increased. Therefore, the amount of leakage current leaking during the blank period after the predetermined time may be reduced. Accordingly, in the embodiment, the deviation between the amount of leakage current leaking during the blank period whose time length is equal to the predetermined time and the amount of leakage current leaking during the blank period whose time length is greater than the predetermined time may be reduced. In other words, the deviation between the amount of leakage current leaking during the blank period BLANK1 of the first frame period F1 and the amount of leakage current leaking during the blank period BLANK2 of the second frame period F2 may be reduced.

[0061] In an embodiment, the predetermined time is the time of the blank period corresponding to the maximum frame rate within the variable frame rate range supported by the display device 1000. For example, the variable frame rate range supported by the display device 1000 may be from about 48 Hz to about 144 Hz. In this case, the maximum frame rate may be 144 Hz, and the time of the blank period corresponding to the maximum frame rate may be the same as the time of the blank period BLANK1 of the first frame period F1. Additionally, the time of the blank period corresponding to the maximum frame rate may be the same as the time of the blank period BLANK3 of the third frame period F3.

[0062] As described above, the time of the blank period BLANK2 of the second frame period F2 can be longer than the time of the blank period BLANK1 of the first frame period F1. Therefore, the blank period BLANK2 of the second frame period F2 can be divided into a blank period BLANK2_1 and a blank period BLANK2_2. The blank period BLANK2_1 corresponds to a predetermined time, and the blank period BLANK2_2 is the period after the predetermined time. Therefore, in the second frame period F2, the time of the blank period BLANK2_1 can be the same as the time of the blank period BLANK1 of the first frame period F1.

[0063] As described above, when the time of the blank period BLANK2 of the second frame period F2 reaches a predetermined time, the controller 400 can control the gate driver 300 to increase the gate cut-off voltage VSS (S230). In other words, the plurality of pixels PX can receive the increased gate cut-off voltage VSS during the blank period BLANK2_2.

[0064] In an embodiment, the gate cut-off voltage VSS can have a first negative value before reaching the predetermined time, and the increased gate cut-off voltage VSS can have a second negative value after the predetermined time. The absolute value of the second negative value is smaller than the absolute value of the first negative value. In an embodiment, for example, in the second frame period F2, the increased gate cut-off voltage VSS provided to the plurality of pixels PX during the blank period BLANK2_2 after the predetermined time can be approximately -7 volts (V), and the gate cut-off voltage VSS provided to the plurality of pixels PX during the blank period BLANK2_1 before reaching the predetermined time can be approximately -9V.

[0065] In addition, during the blank period after the predetermined time, the increased gate cut-off voltage VSS can be constant. For example, in the second frame period F2, the gate cut-off voltage VSS provided to the plurality of pixels PX during the blank period BLANK2_2 after the predetermined time can be constant at approximately -7V.

[0066] As described above, when the blank period BLANK2 of the second frame period F2 reaches a predetermined time, the controller 400 can control the data driver 200 to increase the blank voltage (S210). In other words, the plurality of pixels PX can receive the increased blank voltage during the blank period BLANK2_2 after the predetermined time.

[0067] Refer to Figure 1 、 Figure 4 and Figure 5 , the display panel 100 can include a plurality of pixels PX. Specifically, the display panel 100 can include gate lines GL, data lines DL, and pixels PX formed at the regions where the gate lines GL and the data lines DL cross each other. For example, as Figure 4 andFigure 5 As shown, the display panel 100 may include 16 pixels PX.

[0068] In an embodiment, as Figure 4 shown, the increased blanking voltage may be set to the average value of the data voltages provided to the plurality of pixels PX disposed on the display panel 100 during the active period. Specifically, the data voltage meter 10 may represent the data voltages provided to the 16 pixels PX during the active period ACT2 of the second frame period F2. The first blanking voltage meter 21 may represent the increased blanking voltage provided to the display panel 100 during the blanking period BLANK2_2 after a predetermined time during the blanking period BLANK2 of the second frame period F2. The increased blanking voltage may be set to the average value of the data voltages provided to the 16 pixels PX during the active period ACT2.

[0069] In another embodiment, as Figure 5 shown, the increased blanking voltage may be set to the maximum value of the data voltages provided to the plurality of pixels PX disposed on the display panel 100 during the active period. Specifically, the data voltage meter 10 may represent the data voltages provided to the 16 pixels PX during the active period ACT2 of the second frame period F2. The second blanking voltage meter 22 may represent the increased blanking voltage provided to the display panel 100 during the blanking period BLANK2_2 after a predetermined time during the blanking period BLANK2 of the second frame period F2. For example, since the maximum value of the data voltages provided to the 16 pixels PX during the active period ACT2 is about 6V, the increased blanking voltage may be set to about 6V.

[0070] In another embodiment, the increased blanking voltage may be set to the same value as the data voltage corresponding to the maximum gray level. For example, each of the plurality of pixels PX may display a gray level within 0 to 255 gray levels, and the increased blanking voltage may be set to the same value as the data voltage corresponding to the 255 gray level.

[0071] Referring to Figure 6 and Figure 7 , the display panel 100 may be divided into a plurality of regions, and each of the regions may include a plurality of pixels PX. For example, as Figure 6 and Figure 7 shown, the display panel 100 may be divided into two regions, and each region may include eight pixels PX.

[0072] In an embodiment, as Figure 6As shown, the increased blanking voltage can be set to the average value of the data voltages supplied to the multiple pixels PX provided in each of the regions during the active period. Specifically, the data voltage table 10 can represent the data voltages supplied to 16 pixels PX during the active period ACT2 of the second frame period F2. The third blanking voltage table 23 can represent the increased blanking voltage supplied to the two regions during the blanking period BLANK2_2 after a predetermined time during the blanking period BLANK2 of the second frame period F2. Each of the increased blanking voltages can be set to the average value of the data voltages supplied to eight pixels PX provided in each of the regions during the active period ACT2. In other words, for example, the increased blanking voltage supplied to the eight pixels PX provided in the first region (i.e., the left half region) can be approximately 3.5V, which is the average value of the data voltages supplied to the eight pixels PX provided in the first region. In addition, the increased blanking voltage supplied to the eight pixels PX provided in the second region (i.e., the right half region) can be approximately 2.5V, which is the average value of the data voltages supplied to the eight pixels PX provided in the second region.

[0073] In another embodiment, as Figure 7 shown, the increased blanking voltage can be set to the maximum value of the data voltages supplied to the multiple pixels PX provided in each of the regions during the active period. Specifically, the data voltage table 10 can represent the data voltages supplied to 16 pixels PX during the active period ACT2 of the second frame period F2. The fourth blanking voltage table 24 can represent the increased blanking voltage supplied to the two regions during the blanking period BLANK2_2 after a predetermined time during the blanking period BLANK2 of the second frame period F2. The increased blanking voltage can be set to the maximum value of the data voltages supplied to eight pixels PX provided in each of the regions during the active period ACT2. In other words, for example, the increased blanking voltage supplied to the eight pixels PX provided in the first region (i.e., the left half region) can be approximately 5V, which is the maximum value of the data voltages supplied to the eight pixels PX provided in the first region. In addition, the increased blanking voltage supplied to the eight pixels PX provided in the second region (i.e., the right half region) can be approximately 6V, which is the maximum value of the data voltages supplied to the eight pixels PX provided in the second region.

[0074] Referring to Figure 6 and Figure 7 , a method for driving the operation display device 1000 of the display panel 100 by dividing the display panel 100 into two regions is described, but the inventive concept is not limited thereto. In another embodiment, for example, the display panel 100 can be divided into four regions, and multiple pixels PX arranged in a matrix form can be provided in each of the four regions.

[0075] Reference Figure 8 and Figure 9 The increased blanking voltage can be set for each of the data lines DL.

[0076] In an embodiment, as shown in Figure 8 , the increased blanking voltage provided to each of the data lines DL can be set to the average value of the data voltages provided to each of the data lines DL. Specifically, the data voltage table 10 can represent the data voltages provided to 16 pixels PX during the active period ACT2 of the second frame period F2. The fifth blanking voltage table 25 can represent the increased blanking voltage provided to four regions during the blanking period BLANK2_2 after a predetermined time during the blanking period BLANK2 of the second frame period F2. For example, the data voltages provided to the first data line (i.e., the leftmost data line) can be approximately 1V, 4V, 3V, and 4V, and the increased blanking voltage provided to the first data line can be set to approximately 3V, which is the average value of the data voltages of the first data line. In addition, the data voltages provided to the second data line (i.e., the data line adjacent to the first data line) can be approximately 4V, 5V, 5V, and 2V, and the increased blanking voltage provided to the second data line can be set to approximately 4V, which is the average value of the data voltages of the second data line.

[0077] In another embodiment, as shown in Figure 9 , the increased blanking voltage provided to each of the data lines DL can be set to the maximum value of the data voltages provided to each of the data lines DL. Specifically, the data voltage table 10 can represent the data voltages provided to 16 pixels PX during the active period ACT2 of the second frame period F2. The sixth blanking voltage table 26 can represent the increased blanking voltage provided to four regions during the blanking period BLANK2_2 after a predetermined time during the blanking period BLANK2 of the second frame period F2. For example, the data voltages provided to the first data line (i.e., the leftmost data line) can be approximately 1V, 4V, 3V, and 4V, and the increased blanking voltage provided to the first data line can be set to approximately 4V, which is the maximum value of the data voltages of the first data line. In addition, the data voltages provided to the second data line (i.e., the data line adjacent to the first data line) can be approximately 4V, 5V, 5V, and 2V, and the increased blanking voltage provided to the second data line can be set to approximately 5V, which is the maximum value of the data voltages of the second data line.

[0078] The method of setting the increased blanking voltage according to the inventive concept is not limited to the method described with reference to Figures 4 to 9 . In another embodiment, for example, the increased blanking voltage can have a preset value, or in another embodiment, the increased blanking voltage can gradually increase (or decrease) according to the time length of the blanking period.

[0079] Referring to Figure 10 , in the display device 1000, when the blanking voltage VBLANK supplied to the source S of the switching transistor TR increases during the blanking period after a predetermined time (e.g., BLANK2_2 in Figure 3 ), the difference between the voltage at the drain D of the switching transistor TR (e.g., the data voltage stored in the liquid crystal capacitor CLC and the storage capacitor CST) and the blanking voltage VBLANK can be reduced. Therefore, the source-drain voltage difference of the switching transistor TR can be reduced, and the leakage current LI leaking from the liquid crystal capacitor CLC and the storage capacitor CST to the data line DL can be reduced.

[0080] In addition, in the display device 1000, when the blanking voltage VBLANK supplied to the source S of the switching transistor TR and the gate cut-off voltage VSS supplied to the gate G of the switching transistor TR increase during the blanking period after a predetermined time (e.g., BLANK2_2 in Figure 3 ), the blanking voltage VBLANK can be set to be greater than the voltage at the drain D of the switching transistor TR. For example, the voltage at the drain D can be the data voltage stored in the liquid crystal capacitor CLC and the storage capacitor CST. Therefore, the source voltage of the switching transistor TR (i.e., the voltage at the source S) can be greater than the drain voltage of the switching transistor TR (i.e., the voltage at the drain D), and the brightness can be prevented from decreasing during the blanking period after a predetermined time.

[0081] The display device 1000 can increase the blanking voltage VBLANK supplied to the source S of the switching transistor TR and the gate cut-off voltage VSS supplied to the gate G of the switching transistor TR during the blanking period after a predetermined time. Therefore, even if the time length of the blanking period for each frame period is different, the deviation between the amounts of leakage current leaking for each frame period can be reduced. Therefore, the display device 1000 can prevent the brightness from decreasing during the blanking period after a predetermined time.

[0082] Figure 11 is a flowchart showing a method of operating a display device according to another embodiment of the inventive concept. Figure 12 is a timing diagram showing an example of changing the blanking voltage and the gate cut-off voltage of a method of operating a display device according to Figure 11 .

[0083] Referring to Figure 1 , Figure 11 and Figure 12, the data driver 200 may provide a data voltage as a data signal DS to a plurality of pixels PX during an active period of a frame period (S310). The gate driver 300 may provide a gate-on voltage as a gate signal GS to a plurality of pixels PX during an active period of a frame period (S330).

[0084] The data driver 200 may provide a blank voltage as a data signal DS to a plurality of pixels PX during a blank period after the active period (S350). The gate driver 300 may provide a gate-off voltage as a gate signal GS to a plurality of pixels PX during the blank period (S370).

[0085] The controller 400 may compare the time of the blank period with a predetermined time (S390). In an embodiment, the active period may be a fixed active period having a constant time length, and the blank period may be a variable blank period having a variable time length. Further, the predetermined time may be the time of the blank period corresponding to the maximum frame rate within the variable frame rate range supported by the display device 1000.

[0086] When the time of the blank period reaches the predetermined time, if the blank period ends and the next frame period starts (S390: No), the controller 400 may control the data driver 200 such that the data driver 200 provides a data voltage to a plurality of pixels PX during an active period of the next frame period (S310), and may control the gate driver 300 such that the gate driver 300 provides a gate-on voltage to a plurality of pixels PX during an active period of the next frame period (S330).

[0087] On the other hand, when the time of the blank period reaches the predetermined time, if the blank period continues without ending (S390: Yes), the controller 400 may control the data driver 200 such that the data driver 200 provides an increased blank voltage to a plurality of pixels PX during a blank period after the predetermined time (S410). Further, the controller 400 may control the gate driver 300 such that the gate driver 300 provides a gradually increasing gate-off voltage to a plurality of pixels PX during a blank period after the predetermined time (S430).

[0088] In other words, when the time of the blank period reaches the predetermined time, if the blank period continues without ending (S390: Yes), the data driver 200 may provide an increased blank voltage to a plurality of pixels PX during a blank period BLANK2_2 after the predetermined time.

[0089] In addition, when the time of the blank period reaches a predetermined time and the blank period continues without ending (S390: Yes), the gate driver 300 may supply a gradually increasing gate cut-off voltage VSS to the plurality of pixels PX during the blank period BLANK2_2 after the predetermined time. For example, during the blank period BLANK2_1 before the predetermined time elapses, a gate cut-off voltage VSS of approximately -9V may be supplied to the plurality of pixels PX, and during the blank period BLANK2_2 after the predetermined time, a gate cut-off voltage VSS that gradually increases to approximately -7V may be supplied to the plurality of pixels PX.

[0090] Since the gate cut-off voltage VSS gradually increases, during a period when the gate cut-off voltage VSS is relatively low in the blank period BLANK2_2 after the predetermined time, the amount of current flowing through the switching transistor TR may be relatively small. Therefore, the data voltage charged in the liquid crystal capacitor CLC and the storage capacitor CST may not leak through the switching transistor TR. In addition, during a period when the gate cut-off voltage VSS is relatively high in the blank period BLANK2_2 after the predetermined time, an increased blank voltage may be supplied to the liquid crystal capacitor CLC and the storage capacitor CST through the switching transistor TR. Therefore, the data voltage charged in the liquid crystal capacitor CLC and the storage capacitor CST may not leak through the switching transistor TR.

[0091] Figures 13 to 16 It is a timing diagram showing an example of changing the blank voltage and the gate cut-off voltage according to still another embodiment of the inventive concept.

[0092] Referring to Figures 13 to 16 , since it is substantially the same as that described above except for the blank period BLANK3 of the third frame period F3, the blank period BLANK3 of the third frame period F3 will be described below.

[0093] In the variable frame mode described above, the time lengths of the blank periods BLANK1, BLANK2, and BLANK3 may vary according to the time lengths of each of the frame periods F1, F2, and F3. For example, the time length of the blank period BLANK2 of the second frame period F2 may be increased compared to the time length of the blank period BLANK1 of the first frame period F1, and the time length of the blank period BLANK3 of the third frame period F3 may be increased compared to the time length of the blank period BLANK2 of the second frame period F2.

[0094] For example, the host processor may output the third frame data FD3 during the active period ACT3 of the third frame period F3, and may continue the blank period BLANK3 of the third frame period F3 until the rendering 470 of the fourth frame data FD4 is completed. Therefore, when the fourth frame data FD4 is rendered 470 at a frequency of approximately 48 Hz in the third frame period F3, the host processor may provide the third frame data FD3 to the display device 1000 at a frame rate of approximately 48 Hz by increasing the blank period BLANK3 of the third frame period F3.

[0095] Therefore, the blank period BLANK3 of the third frame period F3 may be divided into a blank period BLANK3_1 before a predetermined time and blank periods BLANK3_2 and BLANK3_3 after the predetermined time. The blank periods BLANK3_2 and BLANK3_3 of the third frame period F3 after the predetermined time may include the blank period BLANK3_2 and the blank period BLANK3_3 after the blank period BLANK3_2, where the time length of the blank period BLANK3_2 is the same as the time length of the blank period BLANK2_2 after the predetermined time in the blank period BLANK2 of the second frame period F2.

[0096] In an embodiment, as Figure 13 shown, the controller 400 may control the gate driver 300 to gradually increase the gate cut-off voltage VSS according to the time length of the blank period BLANK3 of the third frame period F3. For example, a constant gate cut-off voltage VSS may be provided to the plurality of pixels PX during the blank period BLANK3_1 before the predetermined time is reached, a gate cut-off voltage VSS that gradually increases at a constant slope may be provided to the plurality of pixels PX during the subsequent blank period BLANK3_2, and a gate cut-off voltage VSS that gradually increases at a slope greater than the constant slope of the subsequent blank period BLANK3_2 may be provided to the plurality of pixels PX during the subsequent blank period BLANK3_3.

[0097] In another embodiment, a constant gate cut-off voltage VSS may be provided to the plurality of pixels PX during the blank period BLANK3_1 before the predetermined time is reached, a gate cut-off voltage VSS that gradually increases at a constant slope may be provided to the plurality of pixels PX during the subsequent blank period BLANK3_2, and a gate cut-off voltage VSS that gradually increases at a slope smaller than the constant slope of the subsequent blank period BLANK3_2 may be provided to the plurality of pixels PX during the subsequent blank period BLANK3_3 (not shown).

[0098] In yet another embodiment, as Figure 14As shown, the controller 400 may control the gate driver 300 to increase the gate cut-off voltage VSS in a stepped shape according to the time length of the blanking period BLANK3 of the third frame period F3. For example, a constant gate cut-off voltage VSS may be provided to the plurality of pixels PX during the blanking period BLANK3_1 before a predetermined time has elapsed, an increased constant gate cut-off voltage VSS may be provided to the plurality of pixels PX during the subsequent blanking period BLANK3_2, and a further increased constant gate cut-off voltage VSS may be provided to the plurality of pixels PX during the subsequent blanking period BLANK3_3.

[0099] In yet another embodiment, as Figure 15 As shown, the controller 400 may control the gate driver 300 to increase the gate cut-off voltage VSS in a convex-up shape according to the time length of the blanking period BLANK3 of the third frame period F3. For example, a constant gate cut-off voltage VSS may be provided to the plurality of pixels PX during the blanking period BLANK3_1 before a predetermined time has elapsed, and a gate cut-off voltage VSS with a gradually decreasing slope may be provided to the plurality of pixels PX during the subsequent blanking periods BLANK3_2 and BLANK3_3, such that a rapidly increasing gate cut-off voltage VSS may be provided to the plurality of pixels PX during the subsequent blanking period BLANK3_2 and then a gradually increasing gate cut-off voltage VSS may be provided to the plurality of pixels PX during the subsequent blanking period BLANK3_3.

[0100] In yet another embodiment, as Figure 16 As shown, the controller 400 may control the gate driver 300 to increase the gate cut-off voltage VSS in a convex-down shape according to the time length of the blanking period BLANK3 of the third frame period F3. For example, a constant gate cut-off voltage VSS may be provided to the plurality of pixels PX during the blanking period BLANK3_1 before a predetermined time is reached, and a gate cut-off voltage VSS with a gradually increasing slope may be provided to the plurality of pixels PX during the subsequent blanking periods BLANK3_2 and BLANK3_3, such that a gradually increasing gate cut-off voltage VSS may be provided to the plurality of pixels PX during the subsequent blanking period BLANK3_2 and then a rapidly increasing gate cut-off voltage VSS may be provided to the plurality of pixels PX during the subsequent blanking period BLANK3_3.

[0101] The method of setting the gate cut-off voltage VSS supplied to the plurality of pixels PX during the blank period by controlling the gate driver 300 through the controller 400 according to the inventive concept is not limited to the above. In another embodiment, for example, the controller 400 may control the data driver 200 to set the blank voltage supplied to the plurality of pixels PX during the blank period. Again, for example, the controller 400 may control the data driver 200 to gradually increase the blank voltage, increase the blank voltage in a stepped shape, increase the blank voltage in a convex-up shape, or increase the blank voltage in a convex-down shape.

[0102] Embodiments of the inventive concept may be applied to a display device and an electronic device including the display device. For example, the inventive concept may be applied to a cellular phone, a smart phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, a television, a computer display screen, a laptop computer or a notebook computer, a head-mounted display device, an MP3 player, etc.

[0103] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A display device, comprising: a display panel including a plurality of pixels; a data driver that provides a data voltage to the plurality of pixels through data lines during an active period of a frame period, and provides a blanking voltage to the plurality of pixels through the data lines during a blank period of the frame period; a gate driver that provides a gate-on voltage to the plurality of pixels through gate lines during the active period, and provides a gate-off voltage to the plurality of pixels through the gate lines during the blank period; and a controller that controls the data driver and the gate driver, wherein, when a time in the blank period reaches a predetermined time, the blanking voltage increases and the gate-off voltage increases.

2. The display device according to claim 1, wherein, the active period has a fixed time length, and the blank period has a variable time length.

3. The display device according to claim 1, wherein, the predetermined time is a time length of the blank period corresponding to a maximum frame rate within a variable frame rate range supported by the display device.

4. The display device according to claim 1, wherein, the gate-off voltage has a first negative value before reaching the predetermined time, and the gate-off voltage has a second negative value after the predetermined time, and wherein, an absolute value of the second negative value is less than an absolute value of the first negative value.

5. The display device according to claim 1, wherein, the gate-off voltage is constant after the predetermined time.

6. The display device according to claim 1, wherein, the gate-off voltage gradually increases as the time in the blank period increases after the predetermined time.

7. The display device according to claim 1, wherein, the blanking voltage is set to an average value of the data voltage provided to the plurality of pixels during the active period after the predetermined time.

8. The display device according to claim 1, wherein, the blanking voltage is set to a maximum value of the data voltage provided to the plurality of pixels during the active period after the predetermined time.

9. The display device according to claim 1, wherein, the blanking voltage is set to the same value as the data voltage corresponding to a maximum gray level after the predetermined time.

10. The display device according to claim 1, wherein, the blanking voltage is set for each of the data lines after the predetermined time.

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