Semiconductor device and method of forming the same

Abstract

Redistribution structures for semiconductor devices and methods of forming the same are provided. The semiconductor device includes a die sealed by an encapsulant, the die including a pad, and a connection electrically connected to the pad. The semiconductor device also includes a first via in physical contact with the connection. The first via is laterally offset from the connection by a first non-zero distance in a first direction. The first via has a tapered sidewall.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this increased density has been achieved by scaling down the dimensions of the components that make up these electronic circuits. As the dimensions of the components are scaled down, the number of components that can be formed on a given region increases. As the demand for smaller electronic devices increases, the demand for smaller and more creative semiconductor package technologies also increases. An example of such a package system is a package-on-package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices that are functionally enhanced and have a small footprint on a printed circuit board (PCB). SUMMARY

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a die sealed by a sealant, the die including a pad; a connection electrically connected to the pad; and a first via in physical contact with the connection, the first via laterally offset from the connection by a first non-zero distance in a first direction, the first via having a tapered sidewall.

[0004] Some embodiments of the present application provide a semiconductor device, comprising: a die embedded in a sealant, the die including a first pad, a second pad, and a third pad; a first connection physically connected to the first pad; a second connection physically connected to the second pad; a third connection physically connected to the third pad; and a redistribution structure physically connected to the first connection, the second connection, and the third connection, wherein a first via of the redistribution structure is physically connected to a top surface of the first connection, the first via laterally extends beyond an edge of the first connection in a first direction, the first via having a tapered sidewall.

[0005] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: attaching a die to a carrier substrate, the die including a connection; forming a sealant over the carrier substrate and along sidewalls of the die; and forming a redistribution structure over the die and the sealant, wherein forming the redistribution structure includes: forming a first redistribution layer, a first via of the first redistribution layer being in physical contact with the connection, the first via being laterally offset from the connection by a first non-zero distance in a first direction, the first via having a tapered sidewall. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, for the sake of brevity, various components have not been depicted in scaled form. Rather, the dimensions of various components have been arbitrarily expanded or reduced for the sake of discussion.

[0007] Figure 1 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0008] Figure 2 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0009] Figures 3 to 12 Top and cross-sectional views showing intermediate steps during a process for forming a package assembly are shown in accordance with some embodiments.

[0010] Figure 13 and Figure 14 A cross-sectional view of a device stack and implementation of formation is shown in accordance with some embodiments.

[0011] Figures 15 to 18 Top and cross-sectional views of a package assembly are shown in accordance with some embodiments.

[0012] Figure 19 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0013] Figures 20 to 23 Top and cross-sectional views of a package assembly are shown in accordance with some embodiments.

[0014] Figure 24 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0015] Figures 25 to 28 Top and cross-sectional views of a package assembly are shown in accordance with some embodiments.

[0016] Figure 29 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0017] Figure 30 A top view of an integrated circuit die is shown in accordance with some embodiments.

[0018] Figure 31 A top view of an integrated circuit die is shown in accordance with some embodiments.

[0019] Figures 32 to 35 Top and cross-sectional views of a package assembly are shown in accordance with some embodiments.

[0020] Figure 36 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0021] Figures 37 to 40 A top view and a cross-sectional view of a package assembly are shown, in accordance with some embodiments.

[0022] Figure 41 A cross-sectional view of a device stack is shown, in accordance with some embodiments.

[0023] Figures 42 to 45 A top view and a cross-sectional view of a package assembly are shown, in accordance with some embodiments.

[0024] Figure 46 A cross-sectional view of a device stack is shown, in accordance with some embodiments.

[0025] Figures 47 to 50 A top view and a cross-sectional view of a package assembly are shown, in accordance with some embodiments.

[0026] Figure 51 A cross-sectional view of a device stack is shown, in accordance with some embodiments.

[0027] Figure 52 A top view of an integrated circuit die is shown, in accordance with some embodiments.

[0028] Figure 53 A top view of an integrated circuit die is shown, in accordance with some embodiments.

[0029] Figure 54 A cross-sectional view of a package assembly is shown, in accordance with some embodiments.

[0030] Figure 55 A cross-sectional view of a device stack is shown, in accordance with some embodiments.

[0031] Figure 56 A cross-sectional view of a package assembly is shown, in accordance with some embodiments.

[0032] Figure 57 A cross-sectional view of a device stack is shown, in accordance with some embodiments.

[0033] Figure 58 A cross-sectional view of a package assembly is shown, in accordance with some embodiments.

[0034] Figure 59 A cross-sectional view of a device stack is shown, in accordance with some embodiments.

[0035] Figure 60 A cross-sectional view of a package assembly is shown, in accordance with some embodiments.

[0036] Figure 61 A cross-sectional view of a device stack is shown, in accordance with some embodiments.

[0037] Figure 62 A cross-sectional view of a package assembly is shown, in accordance with some embodiments.

[0038] Figure 63 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0039] Figure 64 A cross-sectional view of a package assembly is shown in accordance with some embodiments.

[0040] Figure 65 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0041] Figure 66 A cross-sectional view of a package assembly is shown in accordance with some embodiments.

[0042] Figure 67 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0043] Figure 68 A cross-sectional view of a package assembly is shown in accordance with some embodiments.

[0044] Figure 69 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0045] Figure 70 A cross-sectional view of a package assembly is shown in accordance with some embodiments.

[0046] Figure 71 A cross-sectional view of a device stack is shown in accordance with some embodiments.

[0047] Figure 72 is a flow diagram illustrating a method of forming a package in accordance with some embodiments.

[0048] Figure 73 is a flow diagram illustrating a method of forming a redistribution structure in accordance with some embodiments.

[0049] Figure 74 is a flow diagram illustrating a method of forming a redistribution structure in accordance with some embodiments.

[0050] Figure 75 is a flow diagram illustrating a method of forming a redistribution structure in accordance with some embodiments. DETAILED DESCRIPTION

[0051] The following disclosure provides a number of different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and second component are directly contacted forming, and can also include embodiments where additional components can be formed between the first component and second component such that the first component and second component can not be directly contacted. Furthermore, the application can be repeated with reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0052] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, or portion, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] Embodiments will be described with reference to embodiments in a particular context, namely, packages such as integrated fan-out (InFO) packages and methods of forming the same. Various embodiments presented herein allow a package to have an integrated circuit die with reduced size and pitch connections. Various embodiments presented herein also allow for an expanded die shift / rotation window by forming a redistribution structure over the integrated circuit die such that vias of the redistribution structure are laterally shifted with respect to and partially land on corresponding connections of the integrated circuit die.

[0054] Figure 1 A cross-sectional view of an integrated circuit die 10 is shown in accordance with some embodiments. The integrated circuit die 10 is to be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 10 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) unit, a static random access memory (SRAM) unit, etc.), a power management die (e.g., a power management integrated circuit (PMIC) unit), a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), or a combination thereof.

[0055] The integrated circuit die 10 can be formed in a wafer that can include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit die 10 can be processed according to applicable fabrication processes to form an integrated circuit. For example, the integrated circuit die 10 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or graded substrates, can also be used. The semiconductor substrate 52 has an active surface (e.g., an upwardly facing surface in Figure 1 ) that is sometimes referred to as the front side; and an inactive surface (e.g., a downwardly facing surface in Figure 1 ) that is sometimes referred to as the back side.

[0056] Devices (represented by a transistor) 54 can be formed at the front side of the semiconductor substrate 52. The devices 54 can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interlayer dielectric (ILD) 56 is over the front side of the semiconductor substrate 52. The ILD 56 surrounds and can cover the devices 54. The ILD 56 can include one or more dielectric layers formed from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., or combinations thereof.

[0057] Conductive plugs 58 extend through the ILD 56 to electrically and physically couple the devices 54. For example, when the devices 54 are transistors, the conductive plugs 58 can couple the gate and source / drain regions of the transistors. The conductive plugs 58 can be formed from tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or combinations thereof. An interconnect structure 60 is over the ILD 56 and the conductive plugs 58. The interconnect structure 60 interconnects the devices 54 to form an integrated circuit. The interconnect structure 60 can be formed from, for example, metallization patterns 60B in dielectric layers 60A over the ILD 56. The metallization patterns 60B include metal lines and vias formed in one or more low-k dielectric layers 60A. The metallization patterns 60B of the interconnect structure 60 are electrically coupled to the devices 54 through the conductive plugs 58. In some embodiments, the interconnect structure 60 can be formed from alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material, and can be formed by any suitable process, such as deposition, damascene, dual damascene, etc.

[0058] The integrated circuit die 10 also includes pads 62A and 62B, such as aluminum pads, for external connection thereto. The pads 62A and 62B are on the active side of the integrated circuit die 10, such as in and / or on the interconnect structure 60. In some embodiments, the width of the pads 62A is greater than the width of the pads 62B. In some embodiments, the pitch of the pads 62A is greater than the pitch of the pads 62B. One or more passivation films 64 are on the integrated circuit die 10, such as on portions of the interconnect structure 60 and the pads 62A and 62B. In some embodiments, the one or more passivation films 64 can include silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof. Openings extend through the passivation film 64 to the pads 62A and 62B.

[0059] Die connections 66A and 66B, such as conductive pillars (e.g., formed of a metal such as copper), extend through the openings in the passivation film 64 and are physically and electrically coupled to respective ones of the pads 62A and 62B. The die connections 66A and 66B can be formed by, for example, electroplating. The die connections 66A and 66B are electrically coupled to respective integrated circuits in the integrated circuit die 10. In some embodiments, the width Wl of the die connections 66A is greater than the width W2 of the die connections 66B. In some embodiments, the pitch PI of the die connections 66A is greater than the pitch P2 of the die connections 66B. In some embodiments, the die connections 66B have a higher density than the die connections 66A. Thus, the die connections 66B can also be referred to as high-density die connections, and the die connections 66A can also be referred to as low-density die connections. In some embodiments, the width Wl is between about 40 pm and about 70 pm. In some embodiments, the width W2 is between about 15 pm and about 25 pm. In some embodiments, the pitch PI is between about 70 pm and about 110 pm. In some embodiments, the pitch P2 is between about 19 pm and about 32 pm.

[0060] Optionally, solder regions (e.g., solder balls or solder bumps) can be disposed on the die connections 66A and 66B. The solder balls can be used to perform chip probe (CP) testing on the integrated circuit die 10. The CP testing can be performed on the integrated circuit die 10 to determine whether the integrated circuit die 10 is a known good die (KGD). Thus, only the integrated circuit dies 10 that are KGDs undergo subsequent processing and are packaged, while dies that do not pass the CP testing are not packaged. After testing, the solder regions can be removed in a subsequent processing step.

[0061] Insulation layer 68 can or can not be on the active side of integrated circuit die 10, such as on passivation film 64 and die connections 66A and 66B. Insulation layer 68 laterally seals die connections 66A and 66B, and insulation layer 68 is laterally co-terminal with integrated circuit die 10. In some embodiments, insulation layer 68 can bury die connections 66A and 66B, such that the topmost surface of insulation layer 68 is above the topmost surface of die connections 66A and 66B. In some embodiments in which solder regions are disposed on die connections 66A and 66B, insulation layer 68 can also bury the solder regions. Optionally, the solder regions can be removed prior to forming insulation layer 68.

[0062] Insulation layer 68 can be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, etc.; etc., or a combination thereof. Insulation layer 68 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, die connections 66A and 66A are exposed through insulation layer 68 during formation of integrated circuit die 10. In other embodiments, die connections 66A and 66B remain buried and exposed in subsequent processes that package integrated circuit die 10. Exposing die connections 66A and 66B can remove any solder regions that can be present on die connections 66A and 66B.

[0063] In some embodiments, integrated circuit die 10 is a stacked device that includes multiple semiconductor substrates. For example, integrated circuit die 10 can be a memory device such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc., that includes multiple memory dies. In such embodiments, integrated circuit die 10 includes multiple semiconductor substrates that are interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates can or can not have an interconnect structure.

[0064] Figure 2A cross-sectional view of an integrated circuit die 20 is shown in accordance with some embodiments. The integrated circuit die 20 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 20 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) unit, a static random access memory (SRAM) unit, etc.), a power management die (e.g., a power management integrated circuit (PMIC) unit), a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front end (AFE) die), etc., or a combination thereof. In some embodiments, the integrated circuit die 20 is similar to the integrated circuit die 10 (see Figure 1 ), where like components are labeled with like reference numerals, and the description of like components is not repeated here. In some embodiments, the integrated circuit die 20 can be formed using the process steps described above with reference to Figure 1 , and the description is not repeated here.

[0065] The integrated circuit die 20 includes pads 70, such as aluminum pads, for external connections thereto. The pads 70 are on the active side of the integrated circuit die 20, such as in and / or on the interconnect structure 60. In some embodiments, the pads 70 have a uniform width and a uniform pitch. In some embodiments, the width and pitch of the pads 70 are smaller than the width and pitch of the pads 62A (see Figure 1 ).

[0066] Die connections 72, such as conductive pillars (e.g., formed of a metal such as copper), extend through openings in the passivation film 64 and are physically and electrically coupled to respective ones of the pads 70. In some embodiments, the pads 70 can be formed using similar materials and methods as the pads 62A and 62B described above with reference to Figure 1 , and the description is not repeated here. In some embodiments, the die connections 72 have a uniform width W3 and a uniform pitch P3. In some embodiments, the width W3 and pitch P3 of the die connections 72 are smaller than the width Wl and pitch PI, respectively, of the die connections 66A (see Figure 1 ). Thus, the die connections 72 can also be referred to as high-density die connections. In some embodiments, the width W3 and pitch P3 of the die connections 72 are equal to the width W2 and pitch P2, respectively, of the die connections 66B (see Figure 1 ). In other embodiments, the width W3 and pitch P3 of the die connections 72 are different than the width W2 and pitch P2, respectively, of the die connections 66B (see Figure 1) different. In some embodiments, the width W3 is between about 40 pm and about 70 pm. In some embodiments, the pitch P3 is between about 70 pm and about 110 pm.

[0067] Figures 3 to 14 Top-down and cross-sectional views showing intermediate steps during a process for forming a package assembly 100 according to some embodiments are shown. A package region 100A of the package assembly 100 is shown. In some embodiments, the package assembly 100 includes multiple package regions (such as the package region 100A), and one or more integrated circuit dies (such as the integrated circuit dies 10 and 20 shown in Figure 1 and Figure 2 are packaged to form integrated circuit packages in each of the package regions. In some embodiments, the package assembly 100 is a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure.

[0068] In Figure 3 , a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 can be a wafer, such that multiple packages can be formed on the carrier substrate 102 at the same time.

[0069] The release layer 104 can be formed of a polymer-based material that can be removed from overlying structures to be formed in subsequent steps along with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-thermal conversion (LTHC) release coating. In other embodiments, the release layer 104 can be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 104 can be dispensed in liquid form and cured, can be a laminate film laminated onto the carrier substrate 102, or the like. The top surface of the release layer 104 can be horizontal and can have high planarity.

[0070] In some embodiments, an insulating layer 106 is formed over the release layer 104. In some embodiments, the insulating layer 106 can be formed using similar materials and methods as the passivation layer 64 described above with reference to Figure 1 , and are not repeated here. In other embodiments, the insulating layer 106 can be formed using similar materials and methods as the insulating layer 68 described above with reference to Figure 1 , and are not repeated here. In some embodiments, the insulating layer 106 can be omitted.

[0071] In Figure 4In some embodiments, vias 108 are formed over and extending away from insulating layer 106. As an example for forming vias 108, a seed layer (not shown) is formed over insulating layer 106. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In particular embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist (not shown) is formed over and patterned on the seed layer. The photoresist can be formed by spin coating, and can be exposed to light for patterning. The pattern of the photoresist corresponds to vias 108. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating, electroless plating, or the like. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, or the like. After the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and the conductive material form vias 108. In some embodiments, when insulating layer 106 is omitted, vias 108 are formed over release layer 104.

[0072] In Figure 5 In some embodiments, vias 108 are formed in a peripheral region of each of the package regions of package assembly 100, such as package region 100A, so that vias 108 surround an inner region of each of the package regions of package assembly 100. In the illustrated embodiment, two concentric rows of vias 108 are formed in package region 100A. In other embodiments, more than two rows of vias 108 can be formed in each of the package regions of package assembly 100, based on the functional requirements of package assembly 100.

[0073] In Figure 6In some embodiments, the integrated circuit dies 10 and 20 are adhered to the insulating layer 106 by an adhesive layer 110. In other embodiments, when the insulating layer 106 is omitted, the integrated circuit dies 10 and 20 are adhered to the release layer 104. The desired type and number of integrated circuit dies are adhered in each of the package regions of the package assembly 100, such as package region 100A. In the illustrated embodiment, one of the integrated circuit dies 10 and one of the integrated circuit dies 20 are adhered adjacent to each other in each of the package regions of the package assembly 100. The integrated circuit dies 10 can be logic devices, such as central processing units (CPUs), graphics processing units (GPUs), systems on a chip (SoCs), microcontrollers, etc. The integrated circuit dies 20 can be memory devices, such as dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, hybrid memory cube (HMC) modules, high bandwidth memory (HBM) modules, etc. In some embodiments, the integrated circuit dies 10 and 20 can be the same type of die, such as SoC dies. The integrated circuit dies 10 and 20 can be formed in a process at the same technology node, or can be formed in a process at different technology nodes. The integrated circuit dies 10 and 20 can have different sizes (e.g., different heights and / or surface areas), or can have the same size (e.g., the same height and / or surface area).

[0074] The adhesive layer 110 is formed on the backside of the integrated circuit dies 10 and 20 and adheres the integrated circuit dies 10 and 20 to the insulating layer 106. The adhesive layer 110 can include any suitable adhesive, epoxy, die attach film (DAF), etc. The adhesive layer 110 can be applied to the backside of the integrated circuit dies 10 and 20, over the surface of the carrier substrate 102 without utilizing the insulating layer 106, or to the top of the insulating layer 106. For example, the adhesive layer 110 can be applied to the backside of the integrated circuit dies 10 and 20 prior to singulation of the respective wafer into individual integrated circuit dies 10 and 20.

[0075] In Figure 7 The encapsulant 112 is formed over and around the various components. After formation, the encapsulant 112 encapsulates the through-vias 108 and the integrated circuit dies 10 and 20. The encapsulant 112 can be a molding compound, epoxy, etc. The encapsulant 112 can be applied by compression molding, transfer molding, etc., and can be formed over the carrier substrate 102 such that the through-vias 108 and / or the integrated circuit dies 10 and 20 are buried or covered. The encapsulant 112 is also formed in the gap regions between the integrated circuit dies 10 and the integrated circuit dies 20. The encapsulant 112 can be applied in a liquid or semi-liquid form and then subsequently cured.

[0076] In Figure 8In some embodiments, a planarization process is performed on the encapsulant 112 to expose the via 108, the die connections 66A and 66B of the integrated circuit die 10, and the die connections 72 of the integrated circuit die 20. The planarization process can also remove material of the via 108, the insulating layer 68, and / or the die connections 66A, 66B, and 72 until the die connections 66A, 66B, and 72 and the via 108 are exposed. Within process variation, after the planarization process, the top surface of the via 108, the die connections 66A, 66B, and 72, the insulating layer 68, and the encapsulant 112 are substantially coplanar or level. The planarization process can be, for example, chemical mechanical polishing (CMP), a lapping process, etc. In some embodiments, the planarization can be omitted, for example, if the via 108 and / or the die connections 66A, 66B, and 72 are already exposed.

[0077] In Figure 9 In some embodiments, a redistribution structure 114 is formed over the encapsulant 112, the via 108, and the integrated circuit dies 10 and 20. The redistribution structure 114 can also be referred to as a front side redistribution structure. The redistribution structure 114 includes insulating layers 116, 120, 124, and 128 and metallization patterns 118, 122, and 126. The metallization patterns can also be referred to as redistribution layers or redistribution lines. The redistribution structure 114 is shown as an example with three metallization patterns. More or fewer insulating layers and metallization patterns can be formed in the redistribution structure 114. If fewer insulating layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more insulating layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

[0078] In some embodiments, the formation of the redistribution structure 114 begins with depositing the insulating layer 116 over the encapsulant 112, the via 108, and the die connections 66A, 66B, and 72. In some embodiments, the insulating layer 116 is formed from a photosensitive material such as PBO, polyimide, BCB, etc., or a combination thereof, which can be patterned using a photomask. The insulating layer 116 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. The insulating layer 116 is then patterned. The patterning forms openings that expose the via 108 and portions of the die connections 66A, 66B, and 72. The patterning can be performed by an acceptable process such as by exposing and developing the insulating layer 116 if it is a photosensitive material, or by etching using, for example, anisotropic etching.

[0079] After the insulating layer 116 is formed, a metallization pattern 118 is formed. The metallization pattern 118 includes portions (such as conductive lines or traces 118B) on and extending along a major surface of the insulating layer 116. The metallization pattern 118 also includes portions (such as conductive vias 118A) extending through the insulating layer 116 to physically and electrically couple to the vias 108 and the connections 66A, 66B, and 72 of the integrated circuit dies 10 and 20.

[0080] As an example for forming the metallization pattern 118, a seed layer is formed over the insulating layer 116 and in openings extending through the insulating layer 116. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD or the like. A photoresist is then formed on and patterned on the seed layer. The photoresist can be formed by spin coating or the like, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 118. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating or the like. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum or the like. In some embodiments, the conductive material is formed in a conformal manner such that the conductive material partially fills the openings through the photoresist. The combination of the conductive material and the underlying portions of the seed layer form the metallization pattern 118. The portions of the photoresist and the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

[0081] After the metallization pattern 118 is formed, an insulating layer 120 is deposited on the metallization pattern 118 and the insulating layer 116. The insulating layer 120 can be formed using similar materials and methods as the insulating layer 116, and are not repeated here.

[0082] After the insulating layer 120 is formed, a metallization pattern 122 is formed. The metallization pattern 122 includes portions (such as conductive lines or traces 122B) on and extending along a major surface of the insulating layer 120. The metallization pattern 122 also includes portions (such as conductive vias 122A) extending through the insulating layer 120 to physically and electrically couple to the metallization pattern 118. The metallization pattern 122 can be formed using similar materials and methods as the metallization pattern 118, and are not repeated here.

[0083] After forming the metallization pattern 122, an insulating layer 124 is deposited over the metallization pattern 122 and the insulating layer 120. The insulating layer 124 can be formed using similar materials and methods as the insulating layer 116, and are not repeated here.

[0084] After forming the insulating layer 124, a metallization pattern 126 is formed. The metallization pattern 126 includes portions (such as conductive lines or traces 126B) on and extending along a major surface of the insulating layer 124. The metallization pattern 126 also includes portions (such as conductive vias 126A) extending through the insulating layer 124 to physically and electrically couple portions of the metallization pattern 122. The metallization pattern 126 can be formed using similar materials and methods as the metallization pattern 118, and are not repeated here.

[0085] After forming the metallization pattern 126, an insulating layer 128 is deposited over the metallization pattern 126 and the insulating layer 124. The insulating layer 128 can be formed using similar materials and methods as the insulating layer 116, and are not repeated here.

[0086] In some embodiments, the insulating layer 128 is the topmost insulating layer of the redistribution structure 114. As such, all of the metallization patterns (e.g., the metallization patterns 118, 122, and 126) of the redistribution structure 114 are disposed between the insulating layer 128 and the integrated circuit dies 10 and 20. Moreover, all of the intermediate insulating layers (e.g., the insulating layers 116, 120, and 124) of the redistribution structure 114 are disposed between the insulating layer 128 and the integrated circuit dies 10 and 20.

[0087] In some embodiments, the redistribution structure 114 is formed such that the vias of adjacent metallization patterns formed over the high-density die connections 66B and 72 are laterally shifted relative to one another such that the vias form a staggered or zigzag pattern. In the illustrated embodiment, the vias 122A are laterally shifted relative to corresponding ones of the vias 118A in a first direction (such as a direction extending from the integrated circuit die 20 to the integrated circuit die 10), and the vias 126A are laterally shifted relative to corresponding ones of the vias 122A in a second direction opposite the first direction (e.g., a direction extending from the integrated circuit die 10 to the integrated circuit die 20).

[0088] Additionally in Figure 9In the process of forming the redistribution structure 114, an under-bump metal (UBM) 130 is formed for external connection to the redistribution structure 114. The UBM 130 has bump portions extending on and along the main surface of the insulating layer 128, and via portions extending through the insulating layer 128 to be physically and electrically coupled to the metallization pattern 126. As a result, the UBM 130 is electrically coupled to integrated circuit dies 10 and 20 via the redistribution structure 114. The UBM 130 may be formed of the same material as the metallization pattern 126.

[0089] After the UBM 130 is formed, conductive connectors 132 are formed on the UBM 130. The conductive connectors 132 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, electroless nickel plating, electroless palladium immersion gold (ENEPIG) formed bumps, etc. The conductive connectors 132 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, the conductive connectors 132 are formed first by evaporation, electroplating, printing, solder transfer, solder ball placement to form a solder layer. Once the solder layer is structurally formed, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connectors 132 include metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal protective layer is formed on the top of the metal pillars. The metal protective layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or combinations thereof, and may be formed by a plating process.

[0090] Figure 10 Show Figure 9 The packaging component 100 has a region 134, which shows the interface between the redistribution structure 114 and the integrated circuit dies 10 and 20. Figure 11 A plan view of the integrated circuit die 10 is shown, which shows die connectors 66A and 66B and the corresponding through-hole 118A of the redistribution structure 114. Figure 12 A plan view of the integrated circuit die 20 is shown, illustrating the die connector 72 and the corresponding via 118A of the redistribution structure 114. (See reference) Figures 10 to 12 In some embodiments, the vias 118A of the metallized pattern 118 lie entirely on the corresponding low-density die connector 66A and partially on the corresponding high-density die connectors 66B and 72. In some embodiments, the partial landing of the vias 118A is caused by the displacement of the integrated circuit dies 10 and 20 during attachment to the insulating layer 106 (or, if the insulating layer 106 is omitted, attachment to the release layer 104) (see [link to relevant documentation]). Figure 6). In some embodiments, the portion of the via 118A is also caused by misalignment of the opening in the insulating layer 116 during patterning of the insulating layer 116. In some embodiments, the via 118A is laterally displaced relative to the corresponding die connections 66B and 72 in the first direction Dl. In the illustrated embodiment, the first direction Dl is parallel to the top faces of the integrated circuit dies 10 and 20, and extends from the integrated circuit die 20 to the integrated circuit die 10.

[0091] In some embodiments, the via 118A has a sloped sidewall. The sidewall of the via 118A forms an angle a with the top face of the corresponding one of the die connections 66B and 72. In some embodiments, the angle a is between about 70 degrees and about 89 degrees. The via 118A has a bottom width W4 at the top face of the corresponding one of the die connections 66B and 72. In some embodiments, the width W4 is between about 3 pm and about 15 pm. A portion of the via 118A extends beyond the edge of the corresponding one of the die connections 66B such that the sidewall of the via 118A is laterally spaced apart from the sidewall of the corresponding one of the die connections 66B by a distance XI. In some embodiments, the distance XI is greater than zero and less than or equal to 2 / 3 of the width W4. A portion of the via 118A extends beyond the edge of the corresponding one of the die connections 72 such that the sidewall of the via 118A is laterally spaced apart from the sidewall of the corresponding one of the die connections 72 by a distance X2. In some embodiments, the distance X2 is greater than zero and less than or equal to 2 / 3 of the width W4. In some embodiments, the distance XI is substantially equal to the distance X2. In other embodiments, the distance XI is different from the distance X2.

[0092] Figure 13 and Figure 14 Formation and implementation of a device stack 400 according to some embodiments is shown. The device stack is formed from the integrated circuit package formed in the package assembly 100. The device stack 400 can also be referred to as a package-on-package (PoP) structure.

[0093] In Figure 13 , the carrier substrate is debonded to separate (or "debond") the carrier substrate 102 (see Figure 9 ) from the package assembly 100. In some embodiments, debonding includes projecting light, such as a laser or UV light, on the release layer 104 (see Figure 9 ) so that the release layer 104 decomposes under the heat of the light and the carrier substrate 102 can be removed. After debonding the carrier substrate 102, the package assembly 100 is flipped and placed on a dicing tape 136.

[0094] After placing the package assembly 100 on the dicing tape 136, a conductive connection 138 is formed extending through the insulating layer 106 to contact the via 108. An opening is formed through the insulating layer 106 to expose a portion of the via 108. The opening can be formed, for example, using laser drilling, etching, etc. The conductive connection 138 is formed in the opening. In some embodiments, the conductive connection 138 includes a solder flux and is formed in a solder flux dipping process. In some embodiments, the conductive connection 138 includes a conductive paste, such as solder paste, silver paste, etc., and is dispensed in a printing process. In some embodiments, similar materials and methods described above with reference to the conductive connection 132 can be used to form the conductive connection 138, and are not repeated here. In other embodiments, when the insulating layer 106 is omitted, the process steps described above for patterning the insulating layer 106 are also omitted. Figure 9 The conductive connection 138 can be formed using similar materials and methods described above with reference to the conductive connection 132, and are not repeated here. In other embodiments, when the insulating layer 106 is omitted, the process steps described above for patterning the insulating layer 106 are also omitted.

[0095] Additionally in Figure 13 the package assembly 200 is coupled to the package assembly 100 such that one of the package assemblies 200 is coupled in each of the package regions of the package assembly 100, such as the package region 100A. The second package assembly 200 includes, for example, a substrate 202 and one or more stacked dies 210 (e.g., 210A and 210B) coupled to the substrate 202. Although a set of stacked dies 210 (210A and 210B) is shown, in other embodiments, multiple stacked dies 210 (each having one or more stacked dies) can be arranged side-by-side and coupled to a common surface of the substrate 202. The substrate 202 can be made of a semiconductor material, such as silicon, germanium, diamond, etc. In some embodiments, composite materials can also be used, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations thereof. Additionally, the substrate 202 can be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In one alternative embodiment, the substrate 202 is based on an insulating core, such as a fiberglass reinforced resin core. One example core material is fiberglass resin, such as FR4. Alternative materials for the core material include bismaleimide triazine (BT) resin or, alternatively, other printed circuit board (PCB) materials or thin films. A build-up film, such as Ajinomoto Build-up Film (ABF), or other build-up, can be used for the substrate 202.

[0096] The substrate 202 can include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, etc., can be used to produce the structural and functional requirements of the design of the package assembly 200. The devices can be formed using any suitable method.

[0097] The substrate 202 can also include a metallization layer (not shown) and conductive vias 208. The metallization layer can be formed over the active and passive devices and designed to connect the various devices to form functional circuits. The metallization layer can be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and can be formed by any suitable process such as deposition, damascene, dual damascene, etc. In some embodiments, the substrate 202 is substantially free of active and passive devices.

[0098] The substrate 202 can have bond pads 204 on a first side of the substrate 202 to couple to the stacked die 210 and bond pads 206 on a second side of the substrate 202 to couple to the conductive connections 138, the second side being opposite the first side of the substrate 202. In some embodiments, the bond pads 204 and 206 are formed by forming recesses (not shown) in a dielectric layer (not shown) on the first and second sides of the substrate 202. The recesses can be formed to allow the bond pads 204 and 206 to be embedded in the dielectric layer. In other embodiments, the recesses are omitted as the bond pads 204 and 206 can be formed on the dielectric layer. In some embodiments, the bond pads 204 and 206 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, etc., or a combination thereof. A conductive material of the bond pads 204 and 206 can be deposited over the thin seed layer. The conductive material can be formed by an electrochemical plating process, a chemical plating process, CVD, atomic layer deposition (ALD), PVD, etc., or a combination thereof. In an embodiment, the conductive material of the bond pads 204 and 206 is copper, tungsten, aluminum, silver, gold, etc., or a combination thereof.

[0099] In some embodiments, the bond pads 204 and the bond pads 206 are UBM including three layers of conductive material such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers such as an arrangement of chromium / copper-chromium alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold can be used to form the bond pads 204 and 206. Any suitable material or layer of material that can be used for the bond pads 204 and 206 is fully intended to be included within the scope of the present application. In some embodiments, the conductive vias 208 extend through the substrate 202 and couple at least one of the bond pads 204 to at least one of the bond pads 206.

[0100] In the illustrated embodiment, the stacked die 210 is coupled to the substrate 202 by wire bonds 212, although other connections such as conductive bumps can be used. In an embodiment, the stacked die 210 is a stacked memory die. For example, the stacked die 210 can be a memory die such as a low power (LP) double data rate (DDR) memory module such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, etc.

[0101] The stacked die 210 and wire bonds 212 can be encapsulated by an encapsulant 214. In some embodiments, the encapsulant 214 is a molding compound, a polymer, an epoxy, a silica filled material, etc., or a combination thereof. The encapsulant 214 can be molded on the stacked die 210 and wire bonds 212, for example, using compression molding. A curing process can be performed to cure the encapsulant 214. The curing process can be thermal curing, UV curing, etc., or a combination thereof. In some embodiments, the stacked die 210 and wire bonds 212 are buried in the encapsulant 214, and after the encapsulant 214 is cured, a planarization step, such as grinding, CMP, etc., is performed to remove excess portions of the encapsulant 214 and provide a substantially planar surface for the package assembly 200.

[0102] After the package assembly 200 is formed, the package assembly 200 is mechanically and electrically coupled to the package assembly 100 through the conductive connections 138 and the bond pads 206. In some embodiments, the stacked die 210 can be coupled to the integrated circuit dies 10 and 20 through the wire bonds 212, the bond pads 204 and 206, the conductive vias 208, the conductive connections 138, the vias 108, and the redistribution structure 114.

[0103] In some embodiments, a solder resist (not shown) is formed on the side of the substrate 202 opposite the stacked die 210. The conductive connections 138 can be disposed in openings in the solder resist to electrically and mechanically couple to conductive components (e.g., the bond pads 206) in the substrate 202. The solder resist can be used to protect areas of the substrate 202 from external damage. In some embodiments, the conductive connections 138 have an epoxy flux (not shown) formed thereon prior to reflow thereof, where at least some of the epoxy portion of the epoxy flux remains after the package assembly 200 is attached to the package assembly 100.

[0104] In some embodiments, an underfill (not shown) is formed between the package assembly 100 and the package assembly 200, which surrounds the conductive connections 138. The underfill can reduce stress and protect the joints resulting from reflow of the conductive connections 138. The underfill can be formed by a capillary flow process after the package assembly 200 is attached, or can be formed by an appropriate deposition method prior to attachment of the package assembly 200. In embodiments where an epoxy flux is formed, the epoxy flux can be used as the underfill.

[0105] Subsequently, a singulation process 216 is performed by sawing along the scribe regions (e.g., between adjacent package regions of the package assembly 100). The sawing singulates the package regions of the package assembly 100, such as the package region 100A, from one another. In some embodiments, the singulation process 216 includes sawing, etching, etc., or a combination thereof. The singulation process 216 results in the formation of singulated device stacks, such as the device stack 400. Each of the singulated device stacks includes one of the package assemblies 200 bonded to a corresponding singulated package assembly 100. In the illustrated embodiment, the singulation process 216 is performed after coupling the package assemblies 200 to the package assemblies 100. In other embodiments, the singulation process 216 is performed before coupling the package assemblies 200 to the package assemblies 100, such as after debonding and forming the conductive connections 138 (see Figure 9 ) of the carrier substrate 102.

[0106] In Figure 14 , the conductive connections 132 can be used to mount the device stack 400 to a substrate 300. The substrate 300 includes a substrate core 302 and a bond pad 304 over the substrate core 302. The substrate core 302 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Optionally, a composite material such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations thereof can also be used. Additionally, the substrate core 302 can be an SOI substrate. Typically, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In one optional embodiment, the substrate core 302 is based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternative materials for the core material include a bismaleimide triazine (BT) resin or optionally other PCB materials or thin films. A build-up film such as ABF or other laminate material can be used for the substrate core 302.

[0107] The substrate core 302 can include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations thereof, etc. can be used to produce the structural and functional requirements of the design of the device stack. The devices can be formed using any suitable method.

[0108] The substrate core 302 can also include a metallization layer and vias (not shown) in which the bond pad 304 is physically and / or electrically coupled to the metallization layer and vias. The metallization layer can be formed over the active and passive devices and designed to connect the various devices to form functional circuits. The metallization layer can be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias having layers of interconnecting conductive material and can be formed by any suitable process such as deposition, damascene, dual damascene, etc. In some embodiments, the substrate core 302 is substantially free of active and passive devices.

[0109] In some embodiments, the conductive connections 132 are reflowed to attach the device stack 400 to the bond pads 304 of the substrate 300. The conductive connections 132 electrically and / or physically couple the substrate 300, including the metallized layer in the substrate core 302, to the device stack 400. In some embodiments, a solder resist 306 is formed on the substrate core 302. The conductive connections 132 can be disposed in openings in the solder resist 306 to electrically and mechanically couple to the bond pads 304. The solder resist 306 can be used to protect areas of the substrate 300 from external damage.

[0110] The conductive connections 132 can have epoxy flux (not shown) formed thereon prior to their reflow, leaving at least some of the epoxy portion of the epoxy flux remaining after the device stack 400 is attached to the substrate 300. This remaining epoxy portion can act as an underfill to reduce stress and protect the joints resulting from reflowing the conductive connections 132. In some embodiments, an underfill 308 can be formed between the device stack 400 and the substrate 300 and around the conductive connections 132. The underfill 308 can be formed by a capillary flow process after the device stack 400 is attached, or can be formed by an appropriate deposition method prior to the device stack 400 being attached.

[0111] In some embodiments, a passive device (e.g., a surface mount device (SMD), not shown) can also be attached to the package assembly 100 (e.g., the UBM 130) or the substrate 300 (e.g., the bond pads 304). For example, the passive device can be bonded to the same surface of the package assembly 100 or the substrate 300 as the conductive connections 132. The passive device can be attached to an individual package assembly 100 prior to the device stack 400 being mounted on the substrate 300, or can be attached to the substrate 300 prior to or after the device stack 400 is mounted on the substrate 300.

[0112] In the illustrated embodiment, the package assembly 100 is implemented in a PoP structure. In other embodiments, the package assembly 100 can be implemented with other device stacks. For example, the package assembly 100 can also be implemented in a flip chip ball grid array (FCBGA) package. In such embodiments, the package assembly 100 is mounted to a substrate, such as the substrate 300, but the package assembly 200 is omitted. Optionally, a lid or heat sink can be attached to the package assembly 100.

[0113] Figures 15 to 18 A top view and a cross-sectional view of a package assembly 500 according to some embodiments is shown. Figure 15 A cross-sectional view of a package assembly 500 according to some embodiments is shown. Figure 16Region 504 of package assembly 100 is shown, which shows the interface between redistribution structure 502 and integrated circuit dies 10 and 20. Figure 17 A plan view of integrated circuit die 10 of package assembly 500 is shown, which shows die connections 66A and 66B and corresponding vias 118A of redistribution structure 502. Figure 18 A plan view of integrated circuit die 20 of package assembly 500 is shown, which shows die connections 72 and corresponding vias 118A of redistribution structure 502.

[0114] In Figure 15 package region 500A of package assembly 500 is shown. In some embodiments, package assembly 500 includes multiple package regions, such as package region 500A. Package assembly 500 can also be referred to as a wafer-level package structure, such as an InFO wafer-level package structure. Package assembly 500 is similar to package assembly 100 shown in Figure 9 , where like components are labeled with like reference numerals and the description of like components is not repeated here. In some embodiments, package assembly 500 can be formed using processing steps similar to the processing steps described above with reference to Figures 3 to 9 , and the description is not repeated here. In some embodiments, redistribution structure 502 includes insulating layers 116, 120, 124, and 128 and metallization patterns 118, 122, and 126, and can be formed in a similar manner as redistribution structure 114 described above with reference to Figure 9 , and the description is not repeated here.

[0115] In Figures 15 to 18 , vias 118A of redistribution structure 502 land fully on corresponding die connection 66A and partially on corresponding die connections 66B and 72. In some embodiments, the partial landing of vias 118A is due to the shift of integrated circuit dies 10 and 20 during the attachment of integrated circuit dies 10 and 20 to insulating layer 106. In some embodiments, the partial landing of vias 118A is also due to misalignment of openings in insulating layer 116 during patterning of insulating layer 116. In some embodiments, vias 118A are laterally shifted relative to corresponding die connections 66B and 72 in direction D2. In the embodiment shown, direction D2 is parallel to the top faces of integrated circuit dies 10 and 20 and extends from integrated circuit die 10 to integrated circuit die 20.

[0116] In some embodiments, the via 118A has a sloped sidewall. The sidewall of the via 118A forms an angle a with the top surface of the corresponding one of the die connections 66B and 72. In some embodiments, the angle a is between about 70 degrees and about 89 degrees. The via 118A has a width W4 at the top surface of the corresponding one of the die connections 66B and 72. In some embodiments, the width W4 is between about 3 pm and about 15 pm. A portion of the via 118A extends beyond the edge of the corresponding die connection 66B such that the sidewall of the via 118A is laterally spaced apart from the sidewall of the corresponding one of the die connections 66B by a distance X3. In some embodiments, the distance X3 is greater than zero and less than or equal to 2 / 3 of the width W4. A portion of the via 118A extends beyond the edge of the corresponding die connection 72 such that the sidewall of the via 118A is laterally spaced apart from the sidewall of the corresponding one of the die connections 72 by a distance X4. In some embodiments, the distance X4 is greater than zero and less than or equal to 2 / 3 of the width W4. In some embodiments, the distance X3 is substantially equal to the distance X4. In other embodiments, the distance X3 is different from the distance X4.

[0117] Figure 19 A cross-sectional view of a device stack 600 bonded to a substrate 300 is shown, in accordance with some embodiments. The device stack 600 is similar to the device stack 400 shown in Figure 14 where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 600 can be formed by performing the process steps described above with reference to the package assembly 500 shown in Figure 15 In some embodiments, the device stack 600 is bonded to the substrate 300 as described above with reference to the device stack 400 shown in Figure 13 and Figure 14 In some embodiments, the device stack 600 is bonded to the substrate 300 as described above with reference to the device stack 400 shown in Figure 14 In some embodiments, the device stack 600 is bonded to the substrate 300 as described above with reference to the device stack 400 shown in

[0118] Figures 20 to 23 A top view and cross-sectional views of a package assembly 700, in accordance with some embodiments, are shown. Figure 20 A cross-sectional view of a package assembly 700, in accordance with some embodiments, is shown. Figure 21 A region 704 of the package assembly 700 is shown, showing the interface between the redistribution structure 702 and the integrated circuit dies 10 and 20. Figure 22 A plan view of the integrated circuit die 10 of the package assembly 700 is shown, showing the die connections 66A and 66B and the corresponding vias 118A of the redistribution structure 702. Figure 23 A plan view of the integrated circuit die 20 of the package assembly 700 is shown, showing the die connections 72 and the corresponding vias 118A of the redistribution structure 702.

[0119] In some embodiments, the package assembly 700 is formed by performing the process steps described above with reference to the package assembly 500 shown in Figure 20The image shows a packaging region 700A of a packaging assembly 700. In some embodiments, the packaging assembly 700 includes multiple packaging regions (such as packaging region 700A). The packaging assembly 700 may also be referred to as a wafer-level packaging structure, such as an integrated fan-out (InFO) wafer-level packaging structure. The packaging assembly 700 is similar to... Figure 9 The encapsulation component 100 shown includes similar components labeled with similar reference numerals, and descriptions of such components are not repeated herein. In some embodiments, the same components referenced above may be used. Figures 3 to 9 The processing steps described are similar to those used to form the package assembly 700, and will not be repeated here. In some embodiments, the redistribution structure 702 includes insulating layers 116, 120, 124, and 128 and metallization patterns 118, 122, and 126, and may be referenced above. Figure 9 The redistribution structure 114 described is formed in a similar manner and will not be described again here.

[0120] exist Figures 20 to 23 In the redistribution structure 702, the through-hole 118A lies completely on the corresponding die connector 66A and partially on the corresponding die connectors 66B and 72. In some embodiments, the partial landing of the through-hole 118A is caused by displacement of the integrated circuit dies 10 and 20 during attachment to the insulating layer 106. In some embodiments, the partial landing of the through-hole 118A is also caused by misalignment of openings in the insulating layer 116 during patterning of the insulating layer 116. In some embodiments, the through-hole 118A is laterally displaced relative to the corresponding die connector 66B in direction D2. Direction D2 is parallel to the top surfaces of the integrated circuit dies 10 and 20 and extends from the integrated circuit die 10 to the integrated circuit die 20. In some embodiments, the through-hole 118A is laterally displaced relative to the corresponding die connector 72 in direction D1. Direction D1 is opposite to direction D2.

[0121] In some embodiments, through-hole 118A has inclined sidewalls. The sidewalls of through-hole 118A form an angle α with the top surfaces of the corresponding die connectors in die connectors 66B and 72. In some embodiments, angle α is between about 70 degrees and about 89 degrees. Through-hole 118A has a width W4 at the top surface of the corresponding die connector in die connectors 66B and 72. In some embodiments, width W4 is between about 3 μm and about 15 μm. A portion of through-hole 118A extends beyond the edge of the corresponding die connector 66B, such that the sidewalls of through-hole 118A are laterally spaced from the sidewalls of the corresponding die connectors in die connectors 66B by a distance X5. In some embodiments, distance X5 is greater than zero and less than or equal to 2 / 3 of width W4. A portion of through-hole 118A extends beyond the edge of the corresponding die connector 72, such that the sidewalls of through-hole 118A are laterally spaced from the sidewalls of the corresponding die connectors in die connectors 72 by a distance X6. In some embodiments, distance X6 is greater than zero and less than or equal to 2 / 3 of width W4. In some embodiments, distance X5 is substantially equal to distance X6. In other embodiments, distance X5 is different from distance X6.

[0122] Figure 24 A cross-sectional view is shown of a device stack 800 bonded to a substrate 300 according to some embodiments. The device stack 800 is similar to... Figure 14 The device stack 400 shown is illustrated, with similar components marked with similar reference numerals, and descriptions of such components are not repeated herein. In some embodiments, this can be achieved by... Figure 20 The encapsulation component 700 shown above performs the above reference. Figure 13 and Figure 14 The described process steps form the device stack 800. In some embodiments, the device stack 800 is as referenced above. Figure 14 As described, it is bonded to substrate 300.

[0123] Figures 25 to 28 A cross-sectional view of a packaged component 900 according to some embodiments is shown. Figure 25 A cross-sectional view of a packaged component 900 according to some embodiments is shown. Figure 26 The diagram shows region 904 of package assembly 900, which illustrates the interface between redistribution structure 902 and integrated circuit dies 10 and 20. Figure 27 A plan view of the integrated circuit die 10 of the package assembly 900 is shown, which shows die connectors 66A and 66B and the corresponding through-hole 118A of the redistribution structure 902. Figure 28 A plan view of the integrated circuit die 20 of the package assembly 900 is shown, which shows the die connector 72 and the corresponding through-hole 118A of the redistribution structure 902.

[0124] exist Figure 25The image shows a packaging region 900A of a packaging assembly 900. In some embodiments, the packaging assembly 900 includes multiple packaging regions (such as packaging region 900A). The packaging assembly 900 may also be referred to as a wafer-level packaging structure, such as an integrated fan-out (InFO) wafer-level packaging structure. The packaging assembly 900 is similar to... Figure 9 The encapsulation component 100 shown includes similar components labeled with similar reference numerals, and descriptions of such components are not repeated herein. In some embodiments, the same components referenced above may be used. Figures 3 to 9 The processing steps described are similar to those used to form the package assembly 900, and will not be repeated here. In some embodiments, the redistribution structure 902 includes insulating layers 116, 120, 124, and 128 and metallization patterns 118, 122, and 126, and may be referenced above. Figure 9 The redistribution structure 114 described is formed in a similar manner and will not be described again here.

[0125] exist Figures 25 to 28 In the redistribution structure 902, the via 118A lies entirely on the corresponding die connector 66A and partially on the corresponding die connectors 66B and 72. In some embodiments, the partial landing of the via 118A is caused by displacement of the integrated circuit dies 10 and 20 during attachment to the insulating layer 106. In some embodiments, the partial landing of the via 118A is also caused by misalignment of openings in the insulating layer 116 during patterning of the insulating layer 116. In some embodiments, the via 118A is laterally displaced relative to the corresponding die connector 66B in direction D1. Direction D1 is parallel to the top surfaces of the integrated circuit dies 10 and 20 and extends from the integrated circuit die 20 to the integrated circuit die 10. In some embodiments, the via 118A is laterally displaced relative to the corresponding die connector 72 in direction D2. Direction D2 is opposite to direction D1.

[0126] In some embodiments, the via 118A has a sloped sidewall. The sidewall of the via 118A forms an angle a with the top surface of the corresponding one of the die connections 66B and 72. In some embodiments, the angle a is between about 70 degrees and about 89 degrees. The via 118A has a width W4 at the top surface of the corresponding one of the die connections 66B and 72. In some embodiments, the width W4 is between about 3 pm and about 15 pm. A portion of the via 118A extends beyond the edge of the corresponding one of the die connections 66B such that the sidewall of the via 118A is laterally spaced apart from the sidewall of the corresponding one of the die connections 66B by a distance X7. In some embodiments, the distance X7 is greater than zero and less than or equal to 2 / 3 of the width W4. A portion of the via 118A extends beyond the edge of the corresponding one of the die connections 72 such that the sidewall of the via 118A is laterally spaced apart from the sidewall of the corresponding one of the die connections 72 by a distance X8. In some embodiments, the distance X8 is greater than zero and less than or equal to 2 / 3 of the width W4. In some embodiments, the distance X7 and the distance X8 are substantially equal. In other embodiments, the distance X7 and the distance X8 are different.

[0127] Figure 29 A cross-sectional view of a device stack 1000 bonded to a substrate 300 is shown in accordance with some embodiments. The device stack 1000 is similar to the device stack 400 shown in Figure 14 , where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 1000 can be formed by performing the process steps described above with reference to the package assembly 900 shown in Figure 25 . In some embodiments, the device stack 1000 is bonded to the substrate 300 as described above with reference to the device stack 400 shown in Figure 13 and Figure 14 . In some embodiments, the device stack 1000 is bonded to the substrate 300 as described above with reference to the device stack 400 shown in Figure 14 .

[0128] In the embodiments shown above with reference to Figure 11 , Figure 17 , Figure 22 and Figure 27 , each of the vias 118A is shifted in the same direction relative to the corresponding one of the die connections 66B of the integrated circuit die 10. In other embodiments, different ones of the vias 118A can be shifted in different directions relative to the corresponding ones of the die connections 66B of the integrated circuit die 10. In some embodiments, during the attachment of the integrated circuit die 10 to the insulating layer 106 (see Figure 6 ), rotation of the integrated circuit die 10 causes uneven shifting. Such embodiments are described in U.S. Patent Application No. 16 / 209, 1 10, filed December 4, 2018, entitled “METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES,” which is incorporated by reference in its entirety. Figure 30The diagram shows a plan view of an integrated circuit die 10, along with die connectors 66A and 66B and corresponding through-holes 118A. In the illustrated embodiment, the first through-hole 118A at the corner of the integrated circuit die 10 is shifted in direction D3, and the second through-hole 118A at the edge of the integrated circuit die 10 is shifted in direction D4, such that directions D3 and D4 are different.

[0129] In addition, as mentioned above Figure 12 , Figure 18 , Figure 23 and Figure 28 In the illustrated embodiment, each of the vias 118A is displaced in the same direction relative to a corresponding die connector in the die connector 72 of the integrated circuit die 20. In other embodiments, different vias in 118A may be displaced in different directions relative to corresponding dies in the die connector 72 of the integrated circuit die 20. In some embodiments, when attaching the integrated circuit die 20 to the insulating layer 106 (see...), Figure 6 During this process, the rotation of the integrated circuit die 20 causes uneven displacement. This embodiment... Figure 31 The diagram shows a plan view of an integrated circuit die 20, along with a die connector 72 and a corresponding through-hole 118A. In the illustrated embodiment, the first through-hole 118A at the first corner of the integrated circuit die 20 is shifted in direction D5, and the second through-hole 118A at the second corner of the integrated circuit die 20 is shifted in direction D6, such that directions D5 and D6 are different.

[0130] Figure 32 A cross-sectional view of a package assembly 1200 according to some embodiments is shown. Figure 32 The image shows a packaging region 1200A of a packaging assembly 1200. In some embodiments, the packaging assembly 1200 includes multiple packaging regions (such as packaging region 1200A). The packaging assembly 1200 may also be referred to as a wafer-level packaging structure, such as an integrated fan-out (InFO) wafer-level packaging structure. The packaging assembly 1200 is similar to... Figure 9 The encapsulation component 100 shown includes similar components labeled with similar reference numerals, and descriptions of such components are not repeated herein. In some embodiments, the same components referenced above may be used. Figures 3 to 9 The processing steps described are similar to those used to form the encapsulated component 1200, and will not be repeated here.

[0131] In some embodiments, the encapsulation assembly 1200 includes a redistribution structure 1202. The redistribution structure 1202 includes insulating layers 1204, 1208, 1212, and 1216, and metallization patterns 1206, 1210, and 1214. In some embodiments, the same as described above may be used. Figure 9Similar materials and methods described for forming the insulating layer 116 are used to form the insulating layers 1204, 1208, 1212, and 1216, and are not repeated here.

[0132] As an example for forming the metallization pattern 1206, a seed layer is formed over the insulating layer 1204 and in the openings extending through the insulating layer 1204. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using, for example, PVD. Then, photoresist is formed on and patterned on the seed layer. The photoresist can be formed by spin coating, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 1206. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. In some embodiments, the conductive material is formed in a non-conformal manner such that the conductive material completely fills the openings through the photoresist formed over the die connections 66B and 72. The combination of the conductive material and the underlying portions of the seed layer form the metallization pattern 1206. The photoresist and the portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. After the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. Similar materials and methods as the metallization pattern 1206 are used to form the metallization patterns 1210 and 1214, and are not repeated here.

[0133] In some embodiments, the redistribution structure 1202 is formed such that the vias of the metallization pattern formed over and in electrical contact with the high-density die connections 66B and 72 are vertically aligned. In the illustrated embodiment, the via 1206A of the metallization pattern 1206 is vertically aligned with the via 1210A of the metallization pattern 1210 and the via 1214A of the metallization pattern 1214.

[0134] Figure 33 A region 1218 of the package assembly 1200 is shown, which shows the interface between the redistribution structure 1202 and the integrated circuit dies 10 and 20. Figure 34 A plan view of the integrated circuit die 10 of the package assembly 1200 is shown, which shows the die connections 66A and 66B and the corresponding via 1206A of the redistribution structure 1202. Figure 35 A plan view of the integrated circuit die 20 of the package assembly 1200 is shown, which shows the die connections 72 and the corresponding via 1206A of the redistribution structure 1202.

[0135] Referring to Figures 33 to 35 In some embodiments, the via 1206A of the metallization pattern 1206 lands completely on the corresponding die connection 66A and partially lands on the corresponding die connections 66B and 72. In some embodiments, the partial landing of the via 1206A is due to a shift of the integrated circuit dies 10 and 20 during the attachment of the integrated circuit dies 10 and 20 to the insulating layer 106 (see Figure 32 ). In some embodiments, the partial landing of the via 1206A is also due to misalignment of the opening in the insulating layer 1204 during the patterning of the insulating layer 1204. In some embodiments, the via 1206A is laterally shifted relative to the corresponding die connections 66B and 72 in a direction Dl. In the illustrated embodiment, the first Dl is parallel to the top surface of the integrated circuit dies 10 and 20 and extends from the integrated circuit die 20 to the integrated circuit die 10.

[0136] In some embodiments, the via 1206A has a sloped sidewall. The sidewall of the via 1206A forms an angle β with the top surface of the corresponding one of the die connections 66B and 72. In some embodiments, the angle β is between about 70 degrees and about 89 degrees. The via 1206A has a width W5 at the top surface of the corresponding one of the die connections 66B and 72. In some embodiments, the width W5 is between about 3 μιη and about 15 μιη. The via 1206A extends partially beyond the edge of the corresponding die connection 66B such that the sidewall of the via 1206A is laterally spaced apart from the sidewall of the corresponding one of the die connections 66B by a distance X9. In some embodiments, the distance X9 is greater than zero and less than or equal to 2 / 3 of the width W5. The via 1206A extends partially beyond the edge of the corresponding die connection 72 such that the sidewall of the via 1206A is laterally spaced apart from the sidewall of the corresponding one of the die connections 72 by a distance XlO. In some embodiments, the distance XlO is greater than zero and less than or equal to 2 / 3 of the width W5. In some embodiments, the distance X9 and the distance XlO are substantially equal. In other embodiments, the distance X9 and the distance XlO are different.

[0137] Figure 36 A cross-sectional view of a device stack 1300 bonded to a substrate 300 is shown, in accordance with some embodiments. The device stack 1300 is similar to the device stack 400 shown in Figure 14 , where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 1300 can be formed by performing the above-described steps on the package assembly 1200 shown in Figure 32 . In some embodiments, the device stack 1300 can be formed by performing the above-described steps on the package assembly 1200 shown in Figure 13 and Figure 14The described process steps form the device stack 1300. In some embodiments, the device stack 1300 is as referenced above. Figure 14 As described, it is bonded to substrate 300.

[0138] Figures 37 to 40 A top view and a cross-sectional view of a packaged component 1400 according to some embodiments are shown. Figure 37 A cross-sectional view of a package assembly 1400 according to some embodiments is shown. Figure 38 The diagram shows region 1404 of package assembly 1400, which illustrates the interface between redistribution structure 1402 and integrated circuit dies 10 and 20. Figure 39 A plan view of the integrated circuit die 10 of the package assembly 1400 is shown, which shows die connectors 66A and 66B and the corresponding through-hole 1206A of the redistribution structure 1402. Figure 40 A plan view of the integrated circuit die 20 of the package assembly 1400 is shown, which shows the die connector 72 and the corresponding through-hole 1206A of the redistribution structure 1402.

[0139] exist Figure 37 The image shows a packaging region 1400A of a packaging assembly 1400. In some embodiments, the packaging assembly 1400 includes multiple packaging regions (such as packaging region 1400A). The packaging assembly 1400 may also be referred to as a wafer-level packaging structure, such as an integrated fan-out (InFO) wafer-level packaging structure. The packaging assembly 1400 is similar to... Figure 32 The encapsulation component 1200 shown includes similar components labeled with similar reference numerals, and descriptions of such components are not repeated herein. In some embodiments, the same components referenced above may be used. Figures 32 to 35 The processing steps described are similar to those used to form the package assembly 1400, and will not be repeated here. In some embodiments, the redistribution structure 1402 includes insulating layers 1204, 1208, 1212, and 1216, and metallization patterns 1206, 1210, and 1214, and may be referenced above. Figure 32 The redistribution structure 1202 described is formed in a similar manner.

[0140] exist Figures 37 to 40In some embodiments, the partial landing of via 1206A is due to misalignment of the openings in insulating layer 1204 during patterning of insulating layer 1204. In some embodiments, via 1206A is laterally displaced relative to the corresponding die connections 66B and 72 in direction D2. In the illustrated embodiment, direction D2 is parallel to the top faces of integrated circuit dies 10 and 20, and extends from integrated circuit die 10 to integrated circuit die 20.

[0141] In some embodiments, via 1206A has a sloped sidewall. The sidewall of via 1206A forms an angle β with the top face of the respective one of die connections 66B and 72. In some embodiments, angle β is between about 70 degrees and about 89 degrees. Via 1206A has a width W5 at the top face of the respective one of die connections 66B and 72. In some embodiments, width W5 is between about 3 pm and about 15 pm. A portion of via 1206A extends beyond the edge of the corresponding one of die connections 66B such that the sidewall of via 1206A is laterally spaced apart from the sidewall of the corresponding one of die connections 66B by a distance X11. In some embodiments, distance X11 is greater than zero and less than or equal to 2 / 3 of width W5. A portion of via 1206A extends beyond the edge of the corresponding one of die connections 72 such that the sidewall of via 1206A is laterally spaced apart from the sidewall of the corresponding one of die connections 72 by a distance X12. In some embodiments, distance X12 is greater than zero and less than or equal to 2 / 3 of width W5. In some embodiments, distance X11 and distance X12 are substantially equal. In other embodiments, distance X11 and distance X12 are different.

[0142] Figure 41 A cross-sectional view of a device stack 1500 bonded to a substrate 300 is shown, in accordance with some embodiments. Device stack 1500 is similar to device stack 1300 shown in Figure 36 device stack 1300 shown, where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, device stack 1500 can be formed by performing the process steps described above with reference to Figure 37 package assembly 1400 shown in FIG. 14A. In some embodiments, device stack 1500 is bonded to substrate 300 as described above with reference to Figure 13 and Figure 14 device stack 1300 shown in FIG. 13A. In some embodiments, device stack 1500 is bonded to substrate 300 as described above with reference to Figure 14 device stack 1300 shown in FIG. 13A. In some embodiments, device stack 1500 is bonded to substrate 300 as described above with reference to

[0143] Figures 42 to 45 A top view and a cross-sectional view of a package assembly 1600 are shown, in accordance with some embodiments. Figure 42 A cross-sectional view of a package assembly 1600 is shown, in accordance with some embodiments. Figure 43 A region 1604 of the package assembly 1600 is shown, showing the interface between the redistribution structure 1602 and the integrated circuit dies 10 and 20. Figure 44 A plan view of the integrated circuit die 10 of the package assembly 1600 is shown, showing the die connections 66A and 66B and the corresponding vias 1206A of the redistribution structure 1602. Figure 45 A plan view of the integrated circuit die 20 of the package assembly 1600 is shown, showing the die connections 72 and the corresponding vias 1206A of the redistribution structure 1602.

[0144] In Figure 42 A package region 1600A of the package assembly 1600 is shown. In some embodiments, the package assembly 1600 includes multiple package regions, such as the package region 1600A. The package assembly 1600 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 1600 is similar to the package assembly 1200 shown, where similar components are labeled with similar reference numbers, and the description of similar components is not repeated here. In some embodiments, the package assembly 1600 can be formed using processing steps similar to the processing steps described above with reference to the package assembly 1200, and the description is not repeated here. In some embodiments, the redistribution structure 1602 includes the insulating layers 1204, 1208, 1212, and 1216 and the metallization patterns 1206, 1210, and 1214, and can be formed in a similar manner as the redistribution structure 1202 described above with reference to the package assembly 1200. Figure 32 Figures 32 to 35 Figure 32

[0145] In Figures 42 to 45 ​​​In some embodiments, the via 1206A has a sloped sidewall. The sidewall of the via 1206A forms an angle β with the top surface of the respective one of the die connections 66B and 72. In some embodiments, the angle β is between about 70 degrees and about 89 degrees. The via 1206A has a width W5 at the top surface of the respective one of the die connections 66B and 72. In some embodiments, the width W5 is between about 3 μιη and about 15 μιη. The via 1206A extends partially beyond the edge of the respective one of the die connections 66B such that the sidewall of the via 1206A is laterally spaced apart from the sidewall of the respective one of the die connections 66B by a distance X13. In some embodiments, the distance X13 is greater than zero and less than or equal to 2 / 3 of the width W5. The via 1206A extends partially beyond the edge of the respective one of the die connections 72 such that the sidewall of the via 1206A is laterally spaced apart from the sidewall of the respective one of the die connections 72 by a distance X14. In some embodiments, the distance X14 is greater than zero and less than or equal to 2 / 3 of the width W5. In some embodiments, the distance X13 is substantially equal to the distance X14. In other embodiments, the distance X13 is different from the distance X14.

[0146] In some embodiments, the via 1206A has a sloped sidewall. The sidewall of the via 1206A forms an angle β with the top surface of the respective one of the die connections 66B and 72. In some embodiments, the angle β is between about 70 degrees and about 89 degrees. The via 1206A has a width W5 at the top surface of the respective one of the die connections 66B and 72. In some embodiments, the width W5 is between about 3 μιη and about 15 μιη. The via 1206A extends partially beyond the edge of the respective one of the die connections 66B such that the sidewall of the via 1206A is laterally spaced apart from the sidewall of the respective one of the die connections 66B by a distance X13. In some embodiments, the distance X13 is greater than zero and less than or equal to 2 / 3 of the width W5. The via 1206A extends partially beyond the edge of the respective one of the die connections 72 such that the sidewall of the via 1206A is laterally spaced apart from the sidewall of the respective one of the die connections 72 by a distance X14. In some embodiments, the distance X14 is greater than zero and less than or equal to 2 / 3 of the width W5. In some embodiments, the distance X13 is substantially equal to the distance X14. In other embodiments, the distance X13 is different from the distance X14. 14 In some embodiments, the distance X 14 is greater than zero and less than or equal to 2 / 3 of the width W5. In some embodiments, the distance X 13 is substantially equal to the distance X 14 In other embodiments, the distance X 13 is different from the distance X 14

[0147] Figure 46 A cross-sectional view of a device stack 1700 bonded to a substrate is shown, in accordance with some embodiments. The device stack 1700 is similar to the device stack 1300 shown, in which like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 1700 can be formed by performing the above-described processes on the package assembly 1600 shown in Figure 36 FIG. 16, in which like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 1700 can be formed by performing the above-described processes on the package assembly 1600 shown in Figure 42 FIG. 16, in which like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 1700 can be formed by performing the above-described processes on the package assembly 1600 shown in​Figure 13 and Figure 14 The process steps described above to form the device stack 1700. In some embodiments, the device stack 1700 is bonded to the substrate 300 as described above with reference to Figure 14 .

[0148] Figures 47 to 50 A top-down view and cross-sectional views of a package assembly 1800 are shown, in accordance with some embodiments. Figure 47 A cross-sectional view of the package assembly 1800 is shown, in accordance with some embodiments. Figure 48 A region 1804 of the package assembly 1800 is shown, showing the interface between the redistribution structure 1802 and the integrated circuit dies 10 and 20. Figure 49 A plan view of the integrated circuit die 10 of the package assembly 1800 is shown, showing the die connections 66A and 66B and the corresponding vias 1206A of the redistribution structure 1802. Figure 50 A plan view of the integrated circuit die 20 of the package assembly 1800 is shown, showing the die connections 72 and the corresponding vias 1206A of the redistribution structure 1802.

[0149] In Figure 47 , a package region 1800A of the package assembly 1800 is shown. In some embodiments, the package assembly 1800 includes multiple package regions, such as the package region 1800A. The package assembly 1800 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 1800 is similar to the package assembly 1200 shown above with reference to Figure 32 , where like components are labeled with like reference numbers, and the description of like components is not repeated here. In some embodiments, the package assembly 1800 can be formed using processing steps similar to the processing steps described above with reference to Figures 32 to 35 , and the description is not repeated here. In some embodiments, the redistribution structure 1802 includes the insulating layers 1204, 1208, 1212, and 1216 and the metallization patterns 1206, 1210, and 1214, and can be formed in a similar manner to the redistribution structure 1202 described above with reference to Figure 32 .

[0150] In Figures 47 to 50In some embodiments, the via 1206A is laterally displaced relative to the corresponding die connector 66B in a direction Dl. The direction Dl is parallel to the top surface of the integrated circuit dies 10 and 20 and extends from the integrated circuit die 20 to the integrated circuit die 10. In some embodiments, the via 1206A is laterally displaced relative to the corresponding die connector 72 in a direction D2. The direction D2 is opposite to the direction Dl.

[0151] In some embodiments, the via 1206A has a sloped sidewall. The sidewall of the via 1206A forms an angle β with the top surface of the respective one of the die connectors 66B and 72. In some embodiments, the angle β is between about 70 degrees and about 89 degrees. The via 1206A has a width W5 at the top surface of the respective one of the die connectors 66B and 72. In some embodiments, the width W5 is between about 3 μιη and about 15 μιη. The via 1206A extends partially beyond the edge of the corresponding die connector 66B such that the sidewall of the via 1206A is laterally spaced apart from the sidewall of the corresponding one of the die connectors 66B by a distance X 15 In some embodiments, the distance X 15 is greater than zero and less than or equal to 2 / 3 of the width W5. The via 1206A extends partially beyond the edge of the corresponding die connector 72 such that the sidewall of the via 1206A is laterally spaced apart from the sidewall of the corresponding one of the die connectors 72 by a distance X 16 In some embodiments, the distance X 16 is greater than zero and less than or equal to 2 / 3 of the width W5. In some embodiments, the distance X 15 is substantially equal to the distance X 16 In other embodiments, the distance X 15 is different from the distance X 16

[0152] Figure 51 A cross-sectional view of a device stack 1900 bonded to a substrate 300 is shown, in accordance with some embodiments. The device stack 1900 is similar to Figure 36 the device stack 1300 shown, where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 1300 can be formed by patterning the Figure 47 ​The encapsulation component 1800 shown above performs the above reference. Figure 13 and Figure 14 The described process steps form the device stack 1900. In some embodiments, the device stack 1900 is as referenced above. Figure 14 As described, it is bonded to substrate 300.

[0153] References above Figure 34 , Figure 39 , Figure 44 and Figure 49 In the illustrated embodiment, each of the vias 1206A is displaced in the same direction relative to the corresponding die connector 66B of the integrated circuit die 10. In other embodiments, different vias in 1206A may be displaced in different directions relative to the corresponding dies in the die connectors 66B of the integrated circuit die 10. In some embodiments, when attaching the integrated circuit die 10 to the insulating layer 106 (see...), Figure 6 During this process, the rotation of the integrated circuit die 10 causes uneven displacement. This embodiment... Figure 52 The diagram shows a plan view of an integrated circuit die 10, along with die connectors 66A and 66B and corresponding through-holes 1206A. In the illustrated embodiment, the first through-hole 1206A at the corner of the integrated circuit die 10 is shifted in direction D7, and the second through-hole 1206A at the edge of the integrated circuit die 10 is shifted in direction D8, such that directions D7 and D8 are different.

[0154] In addition, as mentioned above Figure 35 , Figure 40 , Figure 45 and Figure 50 In the illustrated embodiment, each of the vias 1206A is displaced in the same direction relative to a corresponding die connector in the die connector 72 of the integrated circuit die 20. In other embodiments, the different apertures in the vias 1206A of the redistribution structure 1202 may be displaced in different directions relative to corresponding die connectors in the die connector 72 of the integrated circuit die 20. In some embodiments, when attaching the integrated circuit die 20 to the insulating layer 106 (see...), Figure 6 During this process, the rotation of the integrated circuit die 20 causes uneven displacement. This embodiment... Figure 53 The diagram shows a plan view of an integrated circuit die 20, along with a die connector 72 and a corresponding through-hole 1206A. In the illustrated embodiment, the first through-hole 1206A at the first corner of the integrated circuit die 20 is shifted in direction D9, and the second through-hole 1206A at the second corner of the integrated circuit die 20 is shifted in direction D10, such that direction D10 is different from direction D9.

[0155] Figure 54 A cross-sectional view of a package assembly 2000 is shown, in accordance with some embodiments. In Figure 54 , a package region 2000A of the package assembly 2000 is shown. In some embodiments, the package assembly 2000 includes multiple package regions, such as the package region 2000A. The package assembly 2000 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 2000 is similar to the package assembly 100 shown in Figure 9 , where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 2000 can be formed using processing steps similar to the processing steps described above with reference to Figures 3 to 9 . The description of the processing steps is not repeated here.

[0156] In some embodiments, the package assembly 2000 includes a redistribution structure 2002. The redistribution structure 2002 includes a first sub-structure 2002A and a second sub-structure 2002B above the first sub-structure 2002A. The first sub-structure 2002A of the redistribution structure 2002 includes a portion of the redistribution structure 114 including the insulating layers 116 and 120 and the metallization patterns 118 (including the conductive lines 118B and the conductive vias 118A) and 122 (including the conductive lines 122B and the conductive vias 122A), and can be formed using the process steps described above with reference to Figure 9 . The second sub-structure 2002B of the redistribution structure 2002 includes the insulating layers 2004, 2008, and 2012 and the metallization patterns 2006 (including the conductive lines 2006B and the conductive vias 2006A) and 2010 (including the conductive lines 2010B and the conductive vias 2010A), and can be formed using the process steps described above with reference to Figure 32 . In some embodiments, the insulating layers 2004, 2008, and 2012 can be formed using similar materials and methods as the insulating layer 116 described above with reference to Figure 9 . In some embodiments, the metallization patterns 2006 and 2010 can be formed using similar materials and methods as the metallization pattern 1206 described above with reference to Figure 32 .

[0157] Figure 55 A cross-sectional view of a device stack 2100 bonded to a substrate 300, in accordance with some embodiments, is shown. The device stack 2100 is similar to the device stack 400 shown in Figure 14 , where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the device stack 2100 can be formed by performing the processing steps described above with reference to Figure 54 . In some embodiments, the device stack 2100 can be formed by performing the processing steps described above with reference to Figure 13 and Figure 14The process steps described above to form the device stack 2100 are used to form the package assembly 2200. In some embodiments, the package assembly 2200 is bonded to the substrate 300 as described above with reference to Figure 14 .

[0158] Figure 56 A cross-sectional view of a package assembly 2200 according to some embodiments is shown. In Figure 56 , a package region 2200A of the package assembly 2200 is shown. In some embodiments, the package assembly 2200 includes multiple package regions (such as the package region 2200A). The package assembly 2200 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 2200 is similar to the package assembly 500 shown above with reference to Figure 15 , where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, processing steps similar to the processing steps described above with reference to Figures 3 to 9 may be used to form the package assembly 2200, and the description is not repeated here.

[0159] In some embodiments, the package assembly 2200 includes a redistribution structure 2202. The redistribution structure 2202 includes a first sub-structure 2202A and a second sub-structure 2202B over the first sub-structure 2002A. The first sub-structure 2202A of the redistribution structure 2002 includes a portion of the redistribution structure 502 (see Figure 15 ) including the insulating layers 116 and 120 and the metallization patterns 118 (including the conductive lines 118B and the conductive vias 118A) and 122 (including the conductive lines 122B and the conductive vias 122A), and can be formed using the process steps described above with reference to Figure 15 . The second sub-structure 2202B of the redistribution structure 2202 includes the insulating layers 2004, 2008, and 2012 and the metallization patterns 2006 (including the conductive lines 2006B and the conductive vias 2006A) and 2010 (including the conductive lines 2010B and the conductive vias 2010A). In some embodiments, the insulating layers 2004, 2008, and 2012 can be formed using similar materials and methods as the insulating layers 116 described above with reference to Figure 9 . In some embodiments, the metallization patterns 2006 and 2010 can be formed using similar materials and methods as the metallization patterns 1206 described above with reference to Figure 32 .

[0160] Figure 57 A cross-sectional view of a device stack 2300 bonded to the substrate 300 according to some embodiments is shown. The device stack 2300 is similar to the device stack 2100 shown above with reference to Figure 19The device stack 600 shown includes similar components labeled with similar reference numerals, and descriptions of such components are not repeated herein. In some embodiments, this can be achieved by... Figure 56 The encapsulation component 2200 shown above performs the above reference. Figure 13 and Figure 14 The described process steps are used to form the device stack 2300. In some embodiments, the device stack 2300 is as referenced above. Figure 14 As described, it is bonded to substrate 300.

[0161] Figure 58 A cross-sectional view of a package assembly 2400 according to some embodiments is shown. Figure 58 The image shows a packaging region 2400A of a packaging assembly 2400. In some embodiments, the packaging assembly 2400 includes multiple packaging regions (such as packaging region 2400A). The packaging assembly 2400 may also be referred to as a wafer-level packaging structure, such as an integrated fan-out (InFO) wafer-level packaging structure. The packaging assembly 2400 is similar to... Figure 20 The encapsulation component 700 shown is illustrated, wherein similar components are labeled with similar reference numerals, and the description of similar components is not repeated herein. In some embodiments, the same as that referenced above may be used. Figures 3 to 9 The processing steps described are similar to those used to form the encapsulated component 2400, and will not be repeated here.

[0162] In some embodiments, the encapsulation component 2400 includes a redistribution structure 2402. The redistribution structure 2402 includes a first substructure 2402A and a second substructure 2402B above the first substructure 2402A. The first substructure 2402A of the redistribution structure 2402 includes a redistribution structure 702 (see...). Figure 20 The above reference includes insulating layers 116 and 120, and a portion of metallized patterns 118 (including conductive lines 118B and conductive vias 118A) and 122 (including conductive lines 122B and conductive vias 122A), and may be used with reference to the above reference. Figure 20 The process steps described above are used to form the redistribution structure 2402. The second substructure 2402B of the redistribution structure 2402 includes insulating layers 2004, 2008, and 2012, and metallization patterns 2006 (including conductive lines 2006B and conductive vias 2006A) and 2010 (including conductive lines 2010B and conductive vias 2010A). In some embodiments, the process steps described above can be used. Figure 9 The insulating layer 116 described uses materials and methods similar to those used to form insulating layers 2004, 2008, and 2012. In some embodiments, materials and methods similar to those referenced above can be used. Figure 32 The metallized pattern 1206 is described using similar materials and methods to form metallized patterns 2006 and 2010.

[0163] Figure 59 A cross-sectional view of a device stack 2500 bonded to a substrate 300 is shown, in accordance with some embodiments. The device stack 2500 is similar to the device stack 800 shown in Figure 24 , where like components are labeled with like reference numerals, and the description of like components is not repeated here. In some embodiments, the device stack 2500 can be formed by performing the process steps described above with reference to Figure 58 , to the package assembly 2400 shown in Figure 13 , and Figure 14 In some embodiments, the device stack 2500 is bonded to the substrate 300 as described above with reference to Figure 14 .

[0164] Figure 60 A cross-sectional view of a package assembly 2600 is shown, in accordance with some embodiments. In Figure 60 , a package region 2600A of the package assembly 2600 is shown. In some embodiments, the package assembly 2600 includes multiple package regions (such as the package region 2600A). The package assembly 2600 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 2600 is similar to the package assembly 900 shown in Figure 25 , where like components are labeled with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 2600 can be formed using process steps similar to the process steps described above with reference to Figures 3 to 9 , and the description is not repeated here.

[0165] In some embodiments, the package assembly 2600 includes a redistribution structure 2602. The redistribution structure 2602 includes a first sub-structure 2602A and a second sub-structure 2602B above the first sub-structure 2602A. The first sub-structure 2602A of the redistribution structure 2602 includes a portion of the redistribution structure 902 including the insulating layers 116 and 120 and the metallization patterns 118 (including the conductive lines 118B and the conductive vias 118A) and 122 (including the conductive lines 122B and the conductive vias 122A), and can be formed using the process steps described above with reference to Figure 25 . The second sub-structure 2602B of the redistribution structure 2602 includes the insulating layers 2004, 2008, and 2012 and the metallization patterns 2006 (including the conductive lines 2006B and the conductive vias 2006A) and 2010 (including the conductive lines 2010B and the conductive vias 2010A). In some embodiments, the insulating layers 2004, 2008, and 2012 can be formed using materials and methods similar to the insulating layers 116 described above with reference to Figure 9 , and the description is not repeated here. In some embodiments, the metallization patterns 2006 and 2010 can be formed using materials and methods similar to the metallization patterns 118 and 122 described above with reference to Figure 32The materials and methods described for forming the metallization pattern 1206 are similarly used to form the metallization patterns 2006 and 2010, and are not repeated here.

[0166] Figure 61 A cross-sectional view of a device stack 2700 bonded to a substrate 300 is shown, in accordance with some embodiments. The device stack 2700 is similar to the device stack 1000 shown in Figure 29 , where like components are labeled with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 2700 can be formed by performing the process steps described above with reference to Figure 60 to form the device stack 2700. In some embodiments, the device stack 2700 is bonded to the substrate 300 as described above with reference to Figure 13 and Figure 14 In some embodiments, the device stack 2700 is bonded to the substrate 300 as described above with reference to Figure 14 .

[0167] Figure 62 A cross-sectional view of a package assembly 2800 is shown, in accordance with some embodiments. In Figure 62 , a package region 2800A of the package assembly 2800 is shown. In some embodiments, the package assembly 2800 includes multiple package regions (such as the package region 2800A). The package assembly 2800 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 2800 is similar to the package assembly 1200 shown in Figure 32 , where like components are labeled with like reference numbers, and the description of like components is not repeated here. In some embodiments, the package assembly 2800 can be formed using processing steps similar to the processing steps described above with reference to Figure 32 and are not repeated here.

[0168] In some embodiments, the package assembly 2800 includes a redistribution structure 2802. The redistribution structure 2802 includes a first sub-structure 2802A and a second sub-structure 2802B over the first sub-structure 2802A. The first sub-structure 2802A of the redistribution structure 2802 includes a portion of the redistribution structure 1202 (see Figure 32 ) including the insulating layers 1204 and 1208 and the metallization patterns 1206 (including the conductive lines 1206B and the conductive vias 1206A) and 1210 (including the conductive lines 1210B and the conductive vias 1210A), and can use the processing steps described above with reference to Figure 32The second substructure 2802B of the redistribution structure 2802 includes insulating layers 2804, 2808, and 2812 and metallization patterns 2806 (including conductive lines 2806B and conductive vias 2806A) and 2810 (including conductive lines 2810B and conductive vias 2810A). In some embodiments, similar materials and methods as described above with reference to the insulating layers 116 can be used to form the insulating layers 2804, 2808, and 2812. In some embodiments, similar materials and methods as described above with reference to the metallization pattern 118 can be used to form the metallization patterns 2806 and 2810. Figure 9 The second substructure 2802B of the redistribution structure 2802 includes insulating layers 2804, 2808, and 2812 and metallization patterns 2806 (including conductive lines 2806B and conductive vias 2806A) and 2810 (including conductive lines 2810B and conductive vias 2810A). In some embodiments, similar materials and methods as described above with reference to the insulating layers 116 can be used to form the insulating layers 2804, 2808, and 2812. In some embodiments, similar materials and methods as described above with reference to the metallization pattern 118 can be used to form the metallization patterns 2806 and 2810. Figure 9 The second substructure 2802B of the redistribution structure 2802 includes insulating layers 2804, 2808, and 2812 and metallization patterns 2806 (including conductive lines 2806B and conductive vias 2806A) and 2810 (including conductive lines 2810B and conductive vias 2810A). In some embodiments, similar materials and methods as described above with reference to the insulating layers 116 can be used to form the insulating layers 2804, 2808, and 2812. In some embodiments, similar materials and methods as described above with reference to the metallization pattern 118 can be used to form the metallization patterns 2806 and 2810.

[0169] Figure 63 A cross-sectional view of a device stack 2900 bonded to a substrate 300 according to some embodiments is shown. The device stack 2900 is similar to the device stack 1300 shown in Figure 36 The device stack 1300 is shown, where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 2900 can be formed by performing the processing steps described above with reference to the device stack 1300 on the device stack 2800. Figure 62 The package assembly 2800 shown in Figure 13 and Figure 14 The device stack 2900 can be formed by performing the processing steps described above with reference to the device stack 1300. In some embodiments, the device stack 2900 is bonded to the substrate 300 as described above with reference to the device stack 1300. Figure 14 The device stack 2900 can be formed by performing the processing steps described above with reference to the device stack 1300. In some embodiments, the device stack 2900 is bonded to the substrate 300 as described above with reference to the device stack 1300.

[0170] Figure 64 A cross-sectional view of a package assembly 3000 according to some embodiments is shown. In Figure 64 A package region 3000A of the package assembly 3000 is shown in Figure 37 The package assembly 3000 is similar to the package assembly 1400 shown in Figure 37 The package assembly 3000 can be formed by performing processing steps similar to the processing steps described above with reference to the package assembly 1400, and the description is not repeated here.

[0171] In some embodiments, the package assembly 3000 includes a redistribution structure 3002. The redistribution structure 3002 includes a first substructure 3002A and a second substructure 3002B above the first substructure 3002A. The first substructure 3002A of the redistribution structure 3002 includes the redistribution structure 1402 (see Figure 37) including insulating layers 1204 and 1208 and portions of metallization patterns 1206 (including conductive lines 1206B and conductive vias 1206A) and 1210 (including conductive lines 1210B and conductive vias 1210A), and can use processing steps described above with reference to Figure 37 The second substructure 3002B of the redistribution structure 3002 includes insulating layers 2804, 2808, and 2812 and metallization patterns 2806 (including conductive lines 2806B and conductive vias 2806A) and 2810 (including conductive lines 2810B and conductive vias 2810A). In some embodiments, the insulating layers 2804, 2808, and 2812 can be formed using similar materials and methods as described above with reference to the insulating layers 116. Figure 9 The second substructure 3002B of the redistribution structure 3002 includes insulating layers 2804, 2808, and 2812 and metallization patterns 2806 (including conductive lines 2806B and conductive vias 2806A) and 2810 (including conductive lines 2810B and conductive vias 2810A). In some embodiments, the insulating layers 2804, 2808, and 2812 can be formed using similar materials and methods as described above with reference to the insulating layers 116. Figure 9 The metallization patterns 2806 and 2810 can be formed using similar materials and methods as described above with reference to the metallization pattern 118.

[0172] Figure 65 A cross-sectional view of a device stack 3100 bonded to a substrate 300 is shown, according to some embodiments. The device stack 3100 is similar to the device stack 1500 shown in Figure 41 the device stack 1500 shown in FIG. 15, where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the device stack 3100 can be formed by performing the processing steps described above with reference to the processing steps described above with reference to Figure 64 the package assembly 3000 shown in FIG. 30. In some embodiments, the device stack 3100 can be bonded to the substrate 300 as described above with reference to the device stack 1500 shown in FIG. 15. Figure 13 and Figure 14 The device stack 3100 can be formed using processing steps similar to the processing steps described above with reference to the processing steps described above with reference to Figure 14 the device stack 1500 shown in FIG. 15.

[0173] Figure 66 A cross-sectional view of a package assembly 3200 is shown, according to some embodiments. In Figure 66 the package assembly 3200 is shown in a package region 3200A. In some embodiments, the package assembly 3200 includes multiple package regions, such as the package region 3200A. The package assembly 3200 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 3200 is similar to the package assembly 1600 shown in Figure 42 the package assembly 1600 shown in FIG. 16, where like components are marked with like reference numbers, and the description of like components is not repeated here. In some embodiments, the package assembly 3200 can be formed using processing steps similar to the processing steps described above with reference to Figure 42 the processing steps described above with reference to the processing steps described above with reference to

[0174] In some embodiments, the encapsulation component 3200 includes a redistribution structure 3202. The redistribution structure 3202 includes a first substructure 3202A and a second substructure 3202B above the first substructure 3202A. The first substructure 3202A of the redistribution structure 3202 includes a redistribution structure 1602 (see...). Figure 42 The above reference includes insulating layers 1204 and 1208, and a portion of metallized patterns 1206 (including conductive lines 1206B and conductive vias 1206A) and 1210 (including conductive lines 1210B and conductive vias 1210A), and may be used with reference to the above reference. Figure 42 The process steps described above are used to form the redistribution structure 3202. The second substructure 3202B of the redistribution structure 3202 includes insulating layers 2804, 2808, and 2812, and metallization patterns 2806 (including conductive lines 2806B and conductive vias 2806A) and 2810 (including conductive lines 2810B and conductive vias 2810A). In some embodiments, the process steps described above can be used. Figure 9 The insulating layers 2804, 2808, and 2812 are formed using materials and methods similar to those described for insulating layer 116. In some embodiments, materials and methods similar to those referenced above may be used. Figure 9 The metallized pattern 118 is described using similar materials and methods to form metallized patterns 2806 and 2810.

[0175] Figure 67 A cross-sectional view is shown of a device stack 3300 bonded to a substrate 300 according to some embodiments. The device stack 3300 is similar to... Figure 46 The device stack 1700 shown is illustrated, with similar components marked with similar reference numerals, and descriptions of such components are not repeated herein. In some embodiments, this can be achieved by... Figure 66 The encapsulation component 3200 shown above performs the above reference. Figure 13 and Figure 14 The described process steps form the device stack 3300. In some embodiments, the device stack 3300 is as referenced above. Figure 14 As described, it is bonded to substrate 300.

[0176] Figure 68 A cross-sectional view of a package assembly 3400 according to some embodiments is shown. Figure 68 The image shows a packaging region 3400A of a packaging assembly 3400. In some embodiments, the packaging assembly 3400 includes multiple packaging regions (such as packaging region 3400A). The packaging assembly 3400 may also be referred to as a wafer-level packaging structure, such as an integrated fan-out (InFO) wafer-level packaging structure. The packaging assembly 3400 is similar to... Figure 47The package assembly 1800 is shown, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 1800 can be formed using the process steps described above with reference to Figure 47 The package assembly 3400 is formed using process steps similar to those described above with reference to

[0177] In some embodiments, the package assembly 3400 includes a redistribution structure 3402. The redistribution structure 3402 includes a first substructure 3402A and a second substructure 3402B over the first substructure 3402A. The first substructure 3402A of the redistribution structure 3202 includes a portion of the redistribution structure 1802 (see Figure 47 ) including the insulating layers 1204 and 1208 and the metallization patterns 1206 (including the conductive lines 1206B and the conductive vias 1206A) and 1210 (including the conductive lines 1210B and the conductive vias 1210A), and can be formed using the process steps described above with reference to Figure 47 The second substructure 3402B of the redistribution structure 3402 includes the insulating layers 2804, 2808, and 2812 and the metallization patterns 2806 (including the conductive lines 2806B and the conductive vias 2806A) and 2810 (including the conductive lines 2810B and the conductive vias 2810A). In some embodiments, the insulating layers 2804, 2808, and 2812 can be formed using materials and methods similar to the insulating layer 116 described above with reference to Figure 9 In some embodiments, the metallization patterns 2806 and 2810 can be formed using materials and methods similar to the metallization pattern 118 described above with reference to Figure 9

[0178] Figure 69 A cross-sectional view of a device stack 3500 bonded to a substrate 300 according to some embodiments is shown. The device stack 3500 is similar to Figure 51 The device stack 1900 is shown, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the device stack 3500 can be formed by performing the process steps described above with reference to Figure 68 the package assembly 3400 shown in Figure 13 and Figure 14 In some embodiments, the device stack 3500 is bonded to the substrate 300 as described above with reference to Figure 14

[0179] Figure 70 A cross-sectional view of a package assembly 3600 according to some embodiments is shown. In Figure 70 ​​In some embodiments, the package assembly 3600 includes a plurality of package regions (such as the package region 3600A). The package assembly 3600 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 3600 is similar to the package assembly 100 shown in FIG. 1, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 3600 can be formed using processing steps similar to those described above with reference to the package assembly 100, and the description is not repeated here. Figure 9 In some embodiments, the package assembly 3600 includes a plurality of package regions (such as the package region 3600A). The package assembly 3600 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 3600 is similar to the package assembly 100 shown in FIG. 1, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 3600 can be formed using processing steps similar to those described above with reference to the package assembly 100, and the description is not repeated here. Figures 3 to 9 In some embodiments, the package assembly 3600 includes a plurality of package regions (such as the package region 3600A). The package assembly 3600 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 3600 is similar to the package assembly 100 shown in FIG. 1, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 3600 can be formed using processing steps similar to those described above with reference to the package assembly 100, and the description is not repeated here.

[0180] In some embodiments, the package assembly 3600 includes a plurality of package regions (such as the package region 3600A). The package assembly 3600 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 3600 is similar to the package assembly 100 shown in FIG. 1, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 3600 can be formed using processing steps similar to those described above with reference to the package assembly 100, and the description is not repeated here. Figure 9 In some embodiments, the package assembly 3600 includes a plurality of package regions (such as the package region 3600A). The package assembly 3600 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 3600 is similar to the package assembly 100 shown in FIG. 1, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 3600 can be formed using processing steps similar to those described above with reference to the package assembly 100, and the description is not repeated here.

[0181] Figure 71 A cross-sectional view of a device stack 3700 bonded to a substrate 300 according to some embodiments is shown. The device stack 3700 is similar to the device stack 400 shown in FIG. 4, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the device stack 3700 can be formed by performing the process steps described above with reference to the package assembly 3600 shown in FIG. 36 on the package assembly 3600. Figure 14 In some embodiments, the package assembly 3600 includes a plurality of package regions (such as the package region 3600A). The package assembly 3600 can also be referred to as a wafer-level package structure, such as an integrated fan-out (InFO) wafer-level package structure. The package assembly 3600 is similar to the package assembly 100 shown in FIG. 1, where like components are marked with like reference numerals, and the description of like components is not repeated here. In some embodiments, the package assembly 3600 can be formed using processing steps similar to those described above with reference to the package assembly 100, and the description is not repeated here. Figure 70 In some embodiments, the device stack 3700 can be bonded to the substrate 300 as described above with reference to the device stack 400. Figure 13 In some embodiments, the device stack 3700 can be bonded to the substrate 300 as described above with reference to the device stack 400. Figure 14 In some embodiments, the device stack 3700 can be bonded to the substrate 300 as described above with reference to the device stack 400. Figure 14 In some embodiments, the device stack 3700 can be bonded to the substrate 300 as described above with reference to the device stack 400.

[0182] Figure 72 A flowchart showing a method 7200 of forming a package according to some embodiments is shown. The method 7200 starts at step 7202, where a plurality of electrically conductive columns are formed over a carrier substrate, as described above with reference to the method 7000. In step 7204, a first integrated circuit die and a second integrated circuit die are attached to the carrier substrate between adjacent electrically conductive columns, as described above with reference to the method 7000. Figures 3 to 5 In some embodiments, the device stack 3700 can be bonded to the substrate 300 as described above with reference to the device stack 400. Figure 6described above with reference to, for example, FIG. 7A, at step 7206. The first integrated circuit die, the second integrated circuit die, and the plurality of conductive pillars are sealed in a sealant, as described above with reference to, for example, FIG. 7A, at step 7206. Figure 7 and Figure 8 described above with reference to, for example, FIG. 7A, at step 7208. A redistribution structure is formed over the sealant, the first integrated circuit die, the second integrated circuit die, and the plurality of conductive pillars, as described above with reference to, for example, FIG. 7A, at step 7208. Figure 9 , Figure 15 , Figure 20 , Figure 25 , Figure 32 , Figure 37 , Figure 42 , Figure 47 , Figure 54 , Figure 56 , Figure 58 , Figure 60 , Figure 62 , Figure 64 , Figure 66 , Figure 68 or Figure 70 described above with reference to, for example, FIG. 7A, at step 7206. The first integrated circuit die, the second integrated circuit die, and the plurality of conductive pillars are sealed in a sealant, as described above with reference to, for example, FIG. 7A, at step 7206.

[0183] Figure 73 is a flowchart illustrating a method 7300 of forming a redistribution structure, according to some embodiments. The method 7300 begins with step 7302, in which a first insulating layer is formed over an integrated circuit die sealed in a sealant, where the integrated circuit die includes a die connector, as described above with reference to, for example, FIG. 7A. Figure 9 described above with reference to, for example, FIG. 7A, at step 7304. A first redistribution layer is formed over the first insulating layer, the first redistribution layer including a first via laterally displaced in a first direction relative to the die connector, as described above with reference to, for example, FIG. 7A, at step 7304. Figure 9 described above with reference to, for example, FIG. 7A, at step 7306. A second insulating layer is formed over the first redistribution layer, as described above with reference to, for example, FIG. 7A, at step 7306. Figure 9 described above with reference to, for example, FIG. 7A, at step 7308. A second redistribution layer is formed over the second insulating layer, the second redistribution layer including a second via laterally displaced in a second direction relative to the first via, as described above with reference to, for example, FIG. 7A, at step 7308. Figure 9 described above with reference to, for example, FIG. 7A, at step 7306. A second insulating layer is formed over the first redistribution layer, as described above with reference to, for example, FIG. 7A, at step 7306. Figure 9 described above with reference to, for example, FIG. 7A, at step 7312. A third redistribution layer is formed over the third insulating layer, the third redistribution layer including a third via laterally displaced in a third direction opposite the second direction relative to the second via, as described above with reference to, for example, FIG. 7A, at step 7312. Figure 9 described above with reference to, for example, FIG. 7A, at step 7306. A second insulating layer is formed over the first redistribution layer, as described above with reference to, for example, FIG. 7A, at step 7306.

[0184] Figure 74is a flowchart illustrating a method 7400 of forming a redistribution structure, according to some embodiments. The method 7400 begins with step 7402 in which a first insulating layer is formed over an integrated circuit die sealed in an encapsulant, where the integrated circuit die includes a die connector, as described above, for example, with reference to Figure 32 In step 7404, a first redistribution layer is formed over the first insulating layer, the first redistribution layer including a first via that is laterally displaced relative to the die connector in a first direction, as described above, for example, with reference to Figure 32 In step 7406, a second insulating layer is formed over the first redistribution layer, as described above, for example, with reference to Figure 32 In step 7408, a second redistribution layer is formed over the second insulating layer, the second redistribution layer including a second via that is directly over the first via, as described above, for example, with reference to Figure 32 In step 7410, a third insulating layer is formed over the second redistribution layer, as described above, for example, with reference to Figure 32 In step 7412, a third redistribution layer is formed over the third insulating layer, the third redistribution layer including a third via that is directly over the second via, as described above, for example, with reference to Figure 32

[0185] Figure 75 is a flowchart illustrating a method 7500 of forming a redistribution structure, according to some embodiments. The method 7500 begins with step 7502 in which a first substructure of a redistribution structure is formed over an integrated circuit die sealed in an encapsulant. In step 7504, a second substructure of the redistribution structure is formed over the first substructure of the redistribution structure. In some embodiments, step 7502 includes performing the method 7300 (see Figure 73 ) and step 7504 includes performing the method 7400 (see Figure 74 ), as described above, for example, with reference to Figure 54 In other embodiments, step 7502 includes performing the method 7400 (see Figure 74 ) and step 7504 includes performing the method 7300 (see Figure 73 ), as described above, for example, with reference to Figure 62

[0186] Other components and processes can also be included. For example, test structures can be included to facilitate verification testing of the 3D package or 3DIC device. The test structures can include, for example, test pads formed in the redistribution layers or on the substrate that allow the 3D package or 3DIC to be tested using probes and / or probe cards, etc. Verification testing can be performed on the intermediate structure as well as the final structure. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.​​

[0187] According to an embodiment, a semiconductor device includes a die sealed by an encapsulant, the die including a pad, a connection electrically connected to the pad, and a first via in physical contact with the connection, the first via laterally offset from the connection by a first non-zero distance in a first direction, the first via having a tapered sidewall. In an embodiment, the semiconductor device further includes a second via over and in physical contact with the first via, the second via laterally offset from the first via by a second non-zero distance in a second direction. In an embodiment, the second direction is the same as the first direction. In an embodiment, the second direction is opposite the first direction. In an embodiment, the semiconductor device further includes a third via over and in physical contact with the second via, the third via laterally offset from the second via by a third non-zero distance in a third direction opposite the second direction. In an embodiment, the semiconductor device further includes a second via directly over and in physical contact with the first via. In an embodiment, the semiconductor device further includes a third via directly over and in physical contact with the second via.

[0188] According to another embodiment, a semiconductor device includes a die embedded in an encapsulant, the die including a first pad, a second pad, and a third pad; a first connector physically connected to the first pad; a second connector physically connected to the second pad; a third connector physically connected to the third pad; and a redistribution structure physically connected to the first connector, the second connector, and the third connector, wherein a first via of the redistribution structure is physically connected to a top surface of the first connector, the first via laterally extends beyond an edge of the first connector in a first direction, the first via has a tapered sidewall. In an embodiment, a second via of the redistribution structure is over and physically connected to the first via, a vertical axis of the second via is laterally spaced apart from a vertical axis of the first via in a second direction, the vertical axis of the first via and the vertical axis of the second via are perpendicular to the top surface of the first connector. In an embodiment, a third via of the redistribution structure is over and physically connected to the second via, a vertical axis of the third via is laterally spaced apart from a vertical axis of the second via in a third direction opposite to the second direction, the vertical axis of the third via is perpendicular to the top surface of the first connector. In an embodiment, a fourth via of the redistribution structure is directly over and physically connected to the third via. In an embodiment, a second via of the redistribution structure is physically connected to a top surface of the second connector, the second via laterally extends beyond an edge of the second connector in a second direction. In an embodiment, the second direction is different from the first direction. In an embodiment, a second via of the redistribution structure is physically connected to a top surface of the third connector, the second via is entirely on the top surface of the third connector.

[0189] According to yet another embodiment, a method includes: attaching a die to a carrier substrate, the die including a connection; forming a sealant over the carrier substrate and along a sidewall of the die; and forming a redistribution structure over the die and the sealant, wherein forming the redistribution structure includes: forming a first redistribution layer, a first via of the first redistribution layer in physical contact with the connection, the first via laterally offset from the connection by a first non-zero distance in a first direction, the first via having a tapered sidewall. In an embodiment, forming the redistribution structure further includes: forming a second redistribution layer over the first redistribution layer, a second via of the second redistribution layer over and in physical contact with the first via, the second via laterally offset from the first via by a second non-zero distance in a second direction. In an embodiment, forming the redistribution structure further includes: forming a third redistribution layer over the second redistribution layer, a third via of the third redistribution layer over and in physical contact with the second via, the third via laterally offset from the second via by a third non-zero distance in a third direction opposite the second direction. In an embodiment, forming the redistribution structure further includes: forming a second redistribution layer over the first redistribution layer, a second via of the second redistribution layer directly over and in physical contact with the first via. In an embodiment, forming the redistribution structure further includes: forming a third redistribution layer over the second redistribution layer, a third via of the third redistribution layer directly over and in physical contact with the second via. In an embodiment, the method further includes: forming a conductive pillar over the carrier substrate prior to attaching the die to the carrier substrate.

[0190] The foregoing has outlined rather generally the features of several embodiments in accordance with this disclosure so that the skilled person can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: a die encapsulated by an encapsulant, the die including a first pad, a second pad, a third pad, and a fourth pad; a first connector electrically connected to the first pad; a second connector electrically connected to the second pad; a third connector electrically connected to the third pad; a fourth connector electrically connected to the fourth pad; and a first via in physical contact with the first connector, the first via laterally offset from the first connector by a first non-zero distance in a first direction, the first via having a tapered sidewall; a second via in physical contact with the second connector, the second via laterally offset from the second connector by a second non-zero distance in a second direction different from the first direction; a third via in physical contact with the third connector, the third via laterally offset from the third connector by a third non-zero distance in a third direction different from the first direction and the second direction; a fourth via in physical contact with the fourth connector, the fourth via falling entirely on the fourth connector.

2. The semiconductor device of claim 1, further comprising: a fifth via over the first via and in physical contact with the first via, the fifth via laterally offset from the first via by a fourth non-zero distance in a fourth direction.

3. The semiconductor device of claim 2, wherein, the fourth direction is the same as the first direction.

4. The semiconductor device of claim 2, wherein, the fourth direction is opposite the first direction.

5. The semiconductor device of claim 2, further comprising: a sixth via over the second via and in physical contact with the fifth via, the sixth via laterally offset from the fifth via by a fifth non-zero distance in a fifth direction opposite the fourth direction.

6. The semiconductor device of claim 1, further comprising a fifth via directly over the first via and in physical contact with the first via.

7. The semiconductor device of claim 6, further comprising a sixth via directly over the fifth via and in physical contact with the fifth via.

8. A semiconductor device comprising: a die embedded in an encapsulant, the die including a first pad, a second pad, a third pad, and a fourth pad; a first connector physically connected to the first pad; a second connector physically connected to the second pad; a third connector physically connected to the third pad; and a redistribution structure physically connected to the first connector, the second connector, and the third connector, wherein a first via of the redistribution structure is physically connected to a top surface of the first connector, the first via laterally extending beyond an edge of the first connector in a first direction, the first via having a tapered sidewall, wherein a second via of the redistribution structure is physically connected to a top surface of the second connector, the second via laterally extending beyond an edge of the second connector in a second direction different from the first direction, a third via of the redistribution structure is physically connected to a top surface of the third connector, the third via laterally extending beyond an edge of the third connector in a third direction different from the first direction and the second direction.

9. The semiconductor device of claim 8, wherein, A fourth via of the redistribution structure is over and physically connected to the first via, a vertical axis of the fourth via is laterally spaced apart from a vertical axis of the first via in a fourth direction, the vertical axis of the first via and the vertical axis of the fourth via are perpendicular to the top surface of the first connector.

10. The semiconductor device of claim 9, wherein, A fifth via of the redistribution structure is over and physically connected to the fourth via, a vertical axis of the fifth via is laterally spaced apart from a vertical axis of the fourth via in a fifth direction opposite to the fourth direction, the vertical axis of the fifth via is perpendicular to the top surface of the first connector.

11. The semiconductor device of claim 10, wherein, A sixth via of the redistribution structure is directly over and physically connected to the third via.

12. The semiconductor device of claim 8, further comprising: A fourth connector is physically connected to the fourth pad, wherein a fourth via of the redistribution structure is physically connected to a top surface of the fourth connector, the fourth via falls entirely on the top surface of the fourth connector.

13. The semiconductor device of claim 12, further comprising: A first conductive pillar and a second conductive pillar embedded in the encapsulant, the die is between the first conductive pillar and the second conductive pillar.

14. The semiconductor device of claim 8, wherein, The encapsulant comprises a molding compound, a polymer, an epoxy, a silicon oxide filler, or a combination thereof.

15. A method of forming a semiconductor device, comprising: attaching a die to a carrier substrate, the die comprising a first plurality of connectors and a second plurality of connectors; forming an encapsulant over the carrier substrate and along sidewalls of the die; and forming a redistribution structure over the die and the encapsulant, wherein forming the redistribution structure comprises: forming a first redistribution layer, a first plurality of vias of the first redistribution layer are in physical contact with the first plurality of connectors, and a second plurality of vias of the first redistribution layer fall entirely on the second plurality of connectors, the first plurality of vias are laterally offset from the first plurality of connectors by a first non-zero distance in a first direction respectively, the first plurality of vias have tapered sidewalls; forming a second redistribution layer over the first redistribution layer, wherein a third plurality of vias of the second redistribution layer are respectively over and vertically aligned with the first plurality of vias, a fourth via of the second redistribution layer is over and laterally offset from one of the second plurality of vias.

16. The method of claim 15, wherein, sidewalls of the first plurality of vias form an angle between 70 degrees and 89 degrees with a top surface of a respective connector of the first plurality of connectors.

17. The method of claim 16, wherein, forming the redistribution structure further comprises: forming a third redistribution layer over the second redistribution layer, one of a fifth plurality of vias of the third redistribution layer is over and in physical contact with and vertically aligned with one of the third plurality of vias.

18. The method of claim 15, wherein, the first plurality of vias have a width between 3 pm and about 15 pm at a top surface of a respective connector of the first plurality of connectors.

19. The method of claim 18, wherein, forming the redistribution structure further comprises: A third redistribution layer is formed over the second redistribution layer, one of a fifth plurality of vias of the third redistribution layer being directly over and in physical contact with the one of the third plurality of vias.

20. The method of claim 15, further comprising forming a conductive post over the carrier substrate prior to attaching the die to the carrier substrate.

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