Semiconductor device and method of forming an embedded die substrate

Abstract

Semiconductor devices and methods of forming embedded die substrates, and system-in-a-package modules having the same are disclosed. A semiconductor device has a first substrate. A first semiconductor component is disposed on a first surface of the first substrate. A second substrate includes a vertical interconnect structure on a first surface of the second substrate. A second semiconductor component is disposed on the first surface of the second substrate. The first semiconductor component or the second semiconductor component is a semiconductor package. The first substrate is disposed over the second substrate with the first semiconductor component and the second semiconductor component between the first substrate and the second substrate. A first encapsulant is deposited between the first substrate and the second substrate. A SiP sub-module is disposed over the first substrate or the second substrate opposite the encapsulant. A shield layer is formed over the SiP sub-module.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods of forming embedded die substrates (EDSs), and system-in-a-package (SiP) modules having the EDSs. BACKGROUND

[0002] Semiconductor devices are prevalent in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, opto-electronic generation, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor packages are often fabricated with several active semiconductor components, discrete passive components, and integrated passive devices (IPDs) packaged together into a single package system, also known as a system-in-a-package (SiP) module. SiP modules provide higher density and enhanced electrical functionality relative to traditional semiconductor packages.

[0004] Active and passive components are mounted to a substrate for structural support and electrical interconnection. In more advanced three-dimensional (3D) packages, semiconductor components are embedded into the substrate, sometimes referred to as embedded dies in substrate (EDS). In the case of EDS packages, semiconductor dies are embedded within multiple laminated layers during formation of the substrate. The semiconductor dies are then electrically connected to components on the top and bottom surfaces of the substrate through conductive vias and conductive traces of the substrate.

[0005] Manufacturing of EDSs requires formation of the substrate around the semiconductor dies, which limits the options available for the substrate. Additionally, manufacturing defects in the substrate result in not only loss of the substrate, but also otherwise good semiconductor dies. Conventional EDS packages have the additional problems of low yield, high cost, high warpage, and low design flexibility. Accordingly, there is a need for EDSs and methods of manufacturing that provide higher flexibility in substrate design and component selection, as well as increased manufacturing yield. SUMMARY

[0006] A method of making a semiconductor device is provided, comprising: providing a first substrate; disposing a first semiconductor component on a first surface of the first substrate; providing a second substrate, the second substrate comprising a vertical interconnect structure on a first surface thereof; disposing a second semiconductor component on a first surface of the second substrate; after disposing the first semiconductor component on the first surface of the first substrate and after disposing the second semiconductor component on the first surface of the second substrate, disposing the first substrate over the second substrate, wherein the first and second semiconductor components are between the first and second substrates, wherein a region of the first substrate over the second semiconductor component is free of semiconductor components mounted on the first substrate and a region of the second substrate over the first semiconductor component is free of semiconductor components mounted on the second substrate; and depositing a first encapsulant between the first and second substrates.

[0007] A method of making a semiconductor device is also provided, comprising: providing a first substrate; mounting a first semiconductor component to the first substrate; providing a second substrate; mounting a second semiconductor component to the second substrate; after mounting the first semiconductor component to the first substrate and mounting the second semiconductor component to the second substrate, disposing the second substrate over the first substrate, wherein the second semiconductor component is within a height of the first semiconductor component; and after disposing the second substrate over the first substrate, depositing a first encapsulant between the first and second substrates, over the first and second semiconductor components.

[0008] A method of making a semiconductor device is also provided, comprising: providing a first substrate, the first substrate comprising a first semiconductor die thereon; providing a second substrate, the second substrate comprising a second semiconductor die and a vertical interconnect structure thereon; disposing the first substrate over the second substrate, wherein the first semiconductor die is outside a footprint of the second semiconductor die and the vertical interconnect structure connects from the first substrate to the second substrate; and after disposing the first substrate over the second substrate, depositing a first encapsulant between the first and second substrates. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figures la-lc A semiconductor wafer is illustrated having multiple semiconductor dies separated by scribe lanes;

[0010] Figures 2a-2b Formation of a faceplate of a top substrate sub-module is illustrated;

[0011] Figures 3a-3bformation of a bottom substrate sub-module is illustrated;

[0012] Figures 4a-4c combining a top substrate sub-module and a bottom substrate sub-module into a single substrate with embedded semiconductor components is illustrated;

[0013] Figure 5 formation of an EDS from the combination of a top and bottom substrate sub-modules is illustrated;

[0014] Figures 6a-6d potential layout for components on a top and bottom substrate sub-module is illustrated;

[0015] Figures 7a-7c formation of an EDS with alternate interconnect structures is illustrated;

[0016] Figures 8a-8d formation of a top SiP sub-module for use by an EDS is illustrated;

[0017] Figure 9 SiP module with an EDS and a top SiP sub-module is illustrated;

[0018] Figure 10 mounting of a top SiP sub-module to an EDS with conductive micro-pillars through thermal compression is illustrated;

[0019] Figures 11a-11f formation of a bottom SiP sub-module for use by an EDS is illustrated;

[0020] Figure 12 SiP module with an EDS and both a top and bottom SiP sub-module is illustrated;

[0021] Figures 13a-13c formation of a top and bottom SiP sub-module directly on an EDS is illustrated;

[0022] Figures 14a-14b SiP module including an EDS with SiP sub-modules formed directly on the EDS is illustrated;

[0023] Figures 15a-15c SiP module with separately packaged semiconductor components mounted onto an EDS is illustrated;

[0024] Figures 16a-16c formation of an ESD with separately packaged semiconductor components embedded in the EDS is illustrated;

[0025] Figures 17a-17c electromagnetic interference (EMI) shielding options for an EDS with separately packaged semiconductor components is illustrated;

[0026] Figures 18a-18dadditional EMI shielding options for SiP modules made with EDS are illustrated; and

[0027] Figures 19a-19b a printed circuit board (PCB) with SiP modules mounted to the surface of the PCB is illustrated. DETAILED DESCRIPTION

[0028] The application is described in one or more embodiments in the following description with reference to the figures, in which like numbers represent the same or similar elements. While the application is described in terms of the best mode for achieving this application, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as can be included within the spirit and scope of the application, as defined by the appended claims and as supported by the following disclosure and drawings.

[0029] The term "semiconductor die" as used herein refers to both the singular and the plural of the word and can refer to both a single semiconductor device and multiple semiconductor devices. The term "semiconductor assembly" as used herein refers to both active devices formed from semiconductor dies and other active or passive components that can be used with semiconductor circuits.

[0030] Two complex manufacturing processes are generally used to manufacture semiconductor devices: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components electrically connected to form functional electrical circuitry. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as resistors, capacitors, and inductors, create a relationship between voltage and current that is necessary for the functioning of the electrical circuitry.

[0031] Back-end manufacturing refers to the process of cutting or singulating the finished wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. To singulate the semiconductor dies, the wafer is scribed and broken along a non-functional area of the wafer called a scribe line or street. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor dies are mounted to a packaging substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed on the semiconductor dies are then connected to contact pads within the package. Electrical connections can be made with conductive layers, bumps, pillars, conductive paste, or wire bonds. An encapsulant or other molding material is deposited on the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components.

[0032] Figure la A semiconductor wafer 100 is shown having a bulk substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by non-active, inter-die wafer area or streets 106. The streets 106 provide a cutting area to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0033] Figure lb A cross-sectional view of a portion of the semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110 containing analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed on the die and electrically interconnected according to the electrical design and function of the die. The circuitry can include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), application specific integrated circuit (ASIC), memory, or other signal processing circuitry. The semiconductor die 104 can also contain IPDs, such as inductors, capacitors, and resistors, formed in or on interconnect layers on the surface of the semiconductor die for RF signal processing. In some embodiments, the semiconductor die 104 includes multiple active surfaces having circuitry formed therein or thereon.

[0034] A conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition process. The conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive material. The conductive layer 112 functions as a contact pad that is electrically connected to the circuitry of the active surface 110.

[0035] The conductive bump material is deposited on the conductive layer 112 by using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, with optional flux solutions. For example, the bump material can be eutectic Sn / Pb, high lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 by using a suitable attachment or bonding process. In some embodiments, the bump material is reflowed by heating the material above its melting point, forming balls or bumps 114. In one embodiment, the bumps 114 are formed on an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. The bumps 114 can also be compression bonded or thermocompression bonded to the conductive layer 112. The bumps 114 represent one type of interconnect structure that can be formed on the conductive layer 112. Interconnect structures can also use wirebonds, conductive paste, stud bumps, microbumps, or other electrical interconnects.

[0036] In Figure lc The semiconductor wafer 100 is singulated into individual semiconductor dies 104 by sawing through the streets 106 using a saw blade or laser cutting tool 118. Prior to or after singulation, the individual semiconductor dies 104 can be inspected and electrically tested for identification of known good dies (KGD).

[0037] Figures 2a-2b A process of forming panels of top substrate submodules for assembly into a substrate with semiconductor dies 104 embedded in the substrate is illustrated. Figure 2a A cross-sectional view of a substrate 150 is shown that includes multiple regions for forming top substrate submodules 151 separated by streets 152. While only two regions for forming submodules 151 are shown, in other embodiments the substrate 150 is much larger with room to form hundreds or thousands of submodules 151 in parallel. The substrate 150 is formed from a bulk insulating material 153 with conductive layers 154 and 156 formed on both major surfaces of the insulating layer. In one embodiment, the insulating material 153 is a molded substrate. In some embodiments, the substrate 150 is formed by using multiple insulating layers 153 interleaved with multiple conductive layers, which allows for more complex signal routing. Portions of the conductive layers 154 and 156 are electrically common or electrically isolated, depending on the design and function of the SiP module being formed.

[0038] Conductive layers 154 and 156 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. A conductive via 158 extends through the insulating layer 153 to electrically connect portions of conductive layer 154 to portions of conductive layer 156. Conductive layers 154 and 156 provide horizontal electrical interconnections across substrate 150, while conductive via 158 provides vertical electrical interconnections through substrate 150. In one embodiment, conductive via 158 is formed by providing an opening through insulating layer 153 through etching, drilling, laser ablation, or another suitable process, followed by deposition or electroplating of conductive material into the opening. In some embodiments, as part of forming conductive layers 154 or 156, conductive material for conductive via 158 is deposited into the opening of insulating layer 153.

[0039] Substrate 150 can also be any suitable laminated insert, PCB, wafer form, strip insert, lead frame, or other type of substrate. Substrate 150 may include one or more layers of polytetrafluoroethylene (PTFE) prepreg (prepreg material), FR-4, FR-1, CEM-1, or CEM-3, having a combination of phenolic cotton paper, epoxy resin, resin, glass fabric, frosted glass, polyester, and other reinforcing fibers or fabrics. Insulating layer 153 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), alumina (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. The substrate 150 may also be a multilayer flexible laminate, ceramic, copper-clad laminate, glass, or semiconductor wafer, which includes an active surface containing one or more transistors, diodes, and other circuit elements for implementing analog or digital circuits.

[0040] Before mounting the semiconductor die and other components onto the substrate submodule, the top substrate submodule 151 can... Figure 2a The current stage, as seen in the image, is being tested. Figure 2b In this configuration, semiconductor die 104, along with discrete devices 160 and 162, is surface-mounted onto conductive layer 154. Semiconductor die 104 can be tested for KGD (Knock-down Die) before being mounted onto top substrate submodule 151 to avoid using a faulty die on a good substrate submodule, thus avoiding unnecessary waste of submodules. Additionally, top substrate submodule 151 can be tested before assembly, and submodules with manufacturing defects can be discarded without wasting KGD on a faulty substrate. In some embodiments, faulty or blank semiconductor dies 104 are disposed on faulty substrate submodule 151 to maintain uniform weight distribution across substrate 150 and help control warpage.

[0041] Figure 2b Each sub-module 151 is shown with two discrete devices 160 and 162, which can be inductors, capacitors, resistors, or other passive circuit components. Discrete devices 160 and 162 can also be devices with active functionality, such as power transistors, transient voltage suppression diodes, and the like. In other embodiments, any combination of active and passive devices can be provided on substrate 150 as desired for implementing the intended functionality of the final SiP module. In one embodiment, discrete devices 160 and 162 implement a bandpass filter or another radio frequency (RF) signal processing network. In another embodiment, discrete devices 160 and 162 filter a power signal to semiconductor die 104. Discrete devices 160 and 162 can implement any desired electrical functionality.

[0042] Discrete devices 160 and 162 are mechanically joined and electrically connected to conductive layer 154 by solder or solder paste 166. In one embodiment, solder paste 166 is printed onto substrate 150, reflowed with discrete devices 160 and 162 in physical contact, and then de-soldered. Semiconductor die 104 is mechanically joined and electrically connected to conductive layer 154 by conductive bumps 114. In some embodiments, bumps 114 and solder paste 166 are reflowed simultaneously for surface mounting all components in a single step. Area 151a indicates an area on sub-module 151 where active and passive components are located.

[0043] Figures 3a-3b A bottom substrate sub-module is formed. The process begins at Figure 3a where substrate 200 has locations for forming a plurality of bottom substrate sub-modules 201 separated by saw lanes 202. Substrate 200 is similar to substrate 150. Substrate 200 includes one or more insulating layers 203 and conductive layers 204 and 206 on opposite sides of the substrate. Portions of conductive layers 204 and 206 are electrically connected to each other via conductive vias 208 through substrate 200. Conductive posts 210 are formed on contact pads of conductive layer 204. Conductive posts 210 are formed by depositing one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material into openings of a masking layer. In other embodiments, conductive posts 210 are formed by another suitable metal deposition technique. Much like top substrate sub-module 151, bottom substrate sub-modules 201 can be tested prior to mounting components, and components can also be tested prior to mounting.

[0044] At Figure 3bIn this configuration, semiconductor dies 104 and discrete devices 160-162 are surface-mounted onto substrate 200 via solder paste 166 and conductive bumps 114 and are electrically connected to conductive layer 204. The semiconductor dies 104 and discrete devices 160-162 of the bottom substrate submodule 201 may be the same as or different from those of the top substrate submodule 151. In one embodiment, semiconductor die 104 is the same memory chip for both substrates 150 and 200 and is used in conjunction with a microprocessor provided at a later step. In another embodiment, one semiconductor die 104 on substrate 150 or 200 is a memory chip, while the other semiconductor die 104 is a microprocessor. Region 201a indicates the area on submodule 201 where active and passive components are located.

[0045] Figures 4a-4c The illustration shows the combination of substrate submodules 151 and 201 into an embedded die substrate (EDS). Figure 4a In this configuration, a substrate 150 having a top substrate submodule 151 is flipped and disposed on a substrate 200 having a bottom substrate submodule 201. In some embodiments, substrate 150, substrate 200, or both, may be singled out before the combination of the top and bottom substrate submodules. Components on the top substrate submodule 151 and the bottom substrate submodule 201 are confined within regions 151a and 201a, respectively. The layout of regions 151a and 201a is designed such that when the top substrate submodule 151 is flipped and mounted on the bottom substrate submodule 201, the components do not interfere with each other. That is, when one substrate submodule is flipped and aligned with the other submodule, all components of the two submodules are outside the space occupied by each other's components. Figure 4a As specified in the diagram, submodule 151 includes components only on the right half of the submodule, while submodule 201 includes components only on the left half. Other layouts are possible, as shown in the following reference. Figures 6a-6d The explanation given.

[0046] Although Figure 4a The illustration shows substrate 150 stacked on substrate 200, but in other embodiments substrate 200 may also be on top. In one embodiment, bottom substrate 150 or 200 is disposed on a carrier for physical support using optional double-sided strips, a heat release layer, a UV release layer, or other suitable interface layers. In some embodiments, top substrate 150 or 200 is singled out before being disposed on bottom substrate 150 or 200.

[0047] Figure 4bA top submount 151 is shown disposed on a bottom submount 201. The semiconductor dies 104 and discrete devices 160-162 on the top submount 151 extend within the height of the semiconductor dies and discrete devices on the bottom submount 201 without contacting the semiconductor dies and discrete devices on the bottom submount 201. Keeping the top and bottom submounts out of each other's footprint allows for a thinner substrate because the top and bottom submounts can occupy the same vertical area. However, in embodiments where design parameters allow, some or all of the components of the top submount 151 and bottom submount 201 can be directly on top of each other in the final device.

[0048] In Figure 4b the encapsulant or molding compound 220 is deposited between the substrates 150 and 200 and over the semiconductor dies 104 and discrete devices 160-162 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. The encapsulant 220 can be a polymer composite such as an epoxy, epoxy acrylate, or a polymer with or without fillers. The encapsulant 220 is non-conductive, provides structural support, and environmentally protects the semiconductor devices from external elements and contaminants. The encapsulant 220 flows under the semiconductor dies 104 between the conductive bumps 114 and under the discrete devices 160-162 between the solder paste 166 for completely filling the space between the substrates 150 and 200. The substrates 150 and 200 form a panel 224 with the encapsulant 220.

[0049] In Figure 4c the panel 224 is singulated into multiple embedded die substrates (EDSs) 230 by the substrates 150, 200, and the encapsulant 220. Figure 5 A completed EDS 230 is shown. In some embodiments, the panel 224 is not singulated into individual EDSs 230 until a later manufacturing stage, especially when additional components are mounted onto the substrates 150 or 200, as shown in various embodiments below. The discrete devices 160 and 162 are electrically coupled to the semiconductor dies 104 of the same substrate 150 or 200 through the conductive layers 154, 156, 204, and 206. The semiconductor dies 104 and discrete devices 160-162 of one substrate are electrically connected to components on the opposite substrate through the pillars 210. The discrete devices 160-162 are electrically connected to the semiconductor dies 104 to provide the desired passive functionality. Figure 5The EDS 230 in FIG. 1 constitutes a semiconductor package. The substrate 150 or the substrate 200 can be bumped opposite the encapsulant 220, and then the EDS 230 is mounted to a printed circuit board (PCB) or other substrate of an electronic device using the bumps. Additional active or passive devices can be mounted on top of the opposite substrate and sealed or left exposed in the final electronic device.

[0050] The EDS 230 is formed by placing the components on two separate substrates, placing the substrates on each other with the components between the substrates, and then depositing an encapsulant between the two substrates to cover the components. The method of forming the EDS 230 allows for flexible design of the substrates and components, increases yield, reduces cost, and helps control warpage during manufacturing. The substrate sub-modules 151 and 201 can be tested prior to mounting the semiconductor die 104, thereby reducing the number of scrap dies.

[0051] When the substrates are combined to make the EDS 230, the components on the substrates 150 and 200 are formed, mounted, or placed in areas outside of the footprint of each other. In the above embodiment, the components on the substrate 200 are formed on one half of the device, in area 201a of substrate 200a shown in FIG. 2. Figure 6a The components on the substrate 150 are formed in the other half of the device, in area 151a of substrate 150a shown in FIG. 1. Figure 6a Figures 6a-6d FIGS. 1-3 illustrate different embodiments of the substrates 150 and 200 when viewed from the top of the EDS 230, as indicated by lines 6a-6d in FIG. 6. Figure 5 When the substrates 150a and 200a are stacked, the areas 151a and 201a do not overlap. The components on the substrates 150 and 200 can be at the same vertical height because the components are horizontally in different locations. Each component on the substrates 150 and 200 can occupy as much as the entire height between the substrates 150 and 200 because the opposite substrate does not interfere with the components. Having such non-overlapping components on both substrates allows for taller components on the substrates and / or allows the substrates to be mounted closer to each other with shorter posts 210.

[0052] The components on the substrates 150 and 200 can be placed in any desired layout, and the layout on the substrates 150 and 200 need not be symmetrical. Figure 6b FIGS. 1-3 illustrate different embodiments of the substrates 150 and 200 when viewed from the top of the EDS 230, as indicated by lines 6a-6d in FIG. 6. Figure 6b ​In embodiments, more components, components with larger footprints, or both are disposed on substrate 200b within region 201b than in region 151b of substrate 150b. However, regions 151b and 201b remain non-overlapping, such that the components of the opposing substrates remain non-interfering with each other.

[0053] Figure 6c Regions 201c and 151c of substrates 200c and 150c, respectively, are shown that do not overlap each other, such as matching non-rectangular shapes. Figure 6d In embodiments, regions 201d and 151d are non-contiguous regions. Components can be disposed on substrates 150 and 200 in any desired pattern. In some embodiments, some components of the opposing substrates overlap, while others do not. For example, shorter components can be placed on top of each other, connected to their respective substrates 150 and 200, while other taller components are disposed in locations where the opposing substrate has no components. In one embodiment, semiconductor die 104 is back-grinded to a height that is less than half the distance between substrates 150 and 200, such that the two semiconductor dies will fit on top of each other when aligned between the substrates. Each of the substrates includes discrete components around the semiconductor die that are significantly taller than the die, and thus are disposed in non-overlapping regions around the semiconductor die.

[0054] Figures 7a-7c Options for vertical interconnect structures to electrically connect substrate 150 to substrate 200 are illustrated as an alternative to conductive posts 210. Figure 7a An EDS 234 is shown with conductive bumps 236 mounted to conductive layer 204 of substrate 200 instead of conductive posts 210. Conductive bumps 236 are reflowed or thermally compressed to attach the bumps to conductive layer 204. Substrate 150 is disposed on the bumps. The bumps are reflowed onto conductive layer 154 to physically and electrically connect substrate 150 to substrate 200. In other embodiments, bumps 236 are thermally compressed to substrate 150. Bumps 236 are similar to bumps 114.

[0055] Figure 7b An EDS 238 is illustrated in which conductive posts 210 are replaced by copper core solder balls (CCSB) 240-242. CCSB are formed by using a copper core 240 coated in solder 242. In some embodiments, solder 242 is electroplated onto copper core 240. In one embodiment, a layer of nickel is electroplated between solder 242 and copper core 240. CCSB 240-242 are used similarly to conductive bumps 236. CCSB provide improved resistance to electromigration, provide a more robust bump to maintain the offset between substrates 150 and 200, and increase the thermal conductivity between the substrates.

[0056] Figure 7c EDS 244 is illustrated that uses e-Bar or PCB units 246 for electrical interconnection between substrates 150 and 200. PCB units 246 include a core substrate 247 having conductive vias 248 formed through the core substrate. In some embodiments, contact pads are formed on the top and bottom surfaces of PCB units 246. Solder masks can be used on the contact pads. In some embodiments, PCB units 246 are mounted to substrate 200 by using solder or paste between vias 248 and conductive layer 204. Additional solder or paste can be used to connect substrate 150 to vias 248. In some embodiments, each PCB unit 246 extends between two adjacent devices 230 in panel 224, and Figure 4c In some embodiments, the singulated cut-through PCB units of panel 224 are singulated by sawing through the PCB units. Any of the previously described or below embodiments can be formed by using bumps 236, CCSBs 240-242, or PCB units 246 instead of conductive pillars 210.

[0057] Figures 8a-8d A process is illustrated that forms a panel of top SiP sub-modules for combination with EDS 230 into a system-in-a-package (SiP) module. Figure 8a A cross-sectional view of a substrate 250 is shown that includes a plurality of regions for forming top SiP sub-modules 251 that are separated by saw lanes 252. While only two regions for forming sub-modules 251 are shown, in other embodiments substrate 250 is much larger, having room to form hundreds or thousands of sub-modules 251 in parallel. Substrate 250 is formed from a bulk insulating material 253 with conductive layers 254 and 256 formed on both major surfaces of the insulating layer. Substrate 250 is generally similar to the descriptions above for substrates 150 and 200, although some characteristics can differ between the substrates.

[0058] In some embodiments, discrete devices 260, 262, and 264 are surface mounted to conductive layer 254. Figure 8b In some embodiments, discrete devices 260, 262, and 264 are surface mounted to conductive layer 254. Figure 8b Inductors 260, resistors 262, and capacitors 264 are shown mounted to substrate 250, although any combination of active and passive devices can be provided as desired to achieve the intended functionality of the SiP module. In one embodiment, discrete devices 260-264 implement a bandpass filter or another RF signal processing network. Discrete devices 260-264 are mechanically joined and electrically connected to conductive layer 254 by solder or paste 266. In one embodiment, paste 266 is printed onto substrate 250, reflowed with the discrete devices 260-264 in physical contact, and then de-soldered.

[0059] In Figure 8c sealant 270 is deposited with a thickness to completely cover the discrete devices 260-264. In other embodiments, active or passive components mounted on the substrate 250 can be kept exposed from the sealant 270 by using film assisted molding.

[0060] In Figure 8d sealant 270 is planarized by a grinder 272 to expose or create a new back surface 274 of the sealant 270. The grinder 272 planarizes the sealant 270 to form the surface 274. Alternatively, the sealant 270 is planarized by using chemical mechanical planarization (CMP), an etching process, or laser direct ablation (LDA). In some embodiments, the grinder 272 also planarizes some active or passive components disposed on the substrate 250 along with the sealant 270. Molding the sealant 270 to a greater thickness than necessary and then back grinding helps to control panel warpage. Sealing the substrate 250 and the discrete devices 260-264 creates a strip or panel 280 of top SiP sub-modules 251.

[0061] Figure 9 one of the top SiP sub-modules 251 is shown disposed on the EDS 230 to form a SiP module 276. The SiP sub-module 251 can be singulated from the panel 280 and disposed on a singulated EDS 230. In one embodiment, the singulated SiP sub-module 251 is disposed on the panel 224 before singulation into individual EDS 230. In another embodiment, the panel 280 is disposed on the panel 224 and the two panels are singulated together after the conductive bumps 282 are reflowed to physically and electrically connect the panels together. The conductive bumps 282 are reflowed between the EDS 230 and the top SiP sub-module 251 for mechanical joining and electrical interconnection between the substrate 250 and the substrate 150. The semiconductor die 104 is electrically connected to the discrete devices 260-264 through the conductive layers 204, 206, 154, 156, 254, and 256, the conductive vias 158, 208, and 258, the conductive pillars 210, and the conductive bumps 282. The semiconductor die 104 and the discrete devices 160, 162, 260, 262, and 264 are electrically coupled to the conductive bumps 284 through the substrates 150, 200, and 250, the conductive bumps 282, and the conductive pillars 210.

[0062] In other embodiments, the bumps 282 are thermocompression bonded. The thermocompression bonding can occur separately for each top SiP sub-module 251, or each top SiP sub-module can be thermocompression bonded to the panel 224 in groups at a time. The bumps 282 are formed similarly to the bumps 114 of the semiconductor die 104. The bumps 282 can be formed on the substrate 250 before or after singulating the panel 280 into the top SiP sub-modules 251, or can be formed on the substrate 150. The bumps 284 are formed on the conductive layer 206. The bumps 284 are applied in a similar manner to the bumps 114. In some embodiments, the bumps 284 are formed on the conductive layer 206 before singulating the panel 224 into the EDS 230. The bumps 284 are used to mount the SiP modules 276 to a larger substrate of an electronic device, such as Figures 19a-19b as shown in FIG. 1.

[0063] Figure 10 An alternative embodiment is illustrated in which the conductive bumps 282 are replaced with conductive micro-pillars 290. In one embodiment, the micro-pillars 290 are formed by electroplating copper or another suitable conductive material onto the contact pads of the conductive layer 256. A solder cap 292 is electroplated onto the micro-pillars 290. In one embodiment, the micro-pillars 290 and solder caps 292 are deposited into a common masking layer opening together with one another. An optional non-conductive film (NCF) or paste (NCP) 294 is disposed onto the substrate 150 to help thermocompression bond the solder caps 292 to the conductive layer 156. The solder caps 292 can alternatively be reflowed onto the conductive layer 156 with or without the NCP 294. The micro-pillars 290 can be used in the context of any of the embodiments described above or below in which the SiP sub-modules are mounted to the top or bottom of the EDS 230.

[0064] Figures 11a-11f A bottom SiP sub-module is illustrated. The process begins at Figure 11a where the substrate 300 has locations for forming a plurality of bottom SiP sub-modules 301 separated by saw streets 302, similar to the substrates 150, 200, and 250. The substrate 300 includes one or more insulating layers 303 and conductive layers 304 and 306 on opposite sides of the substrate. Portions of the conductive layers 304 and 306 are electrically connected to one another via conductive vias 308 through the substrate 300. Conductive pillars 310 are formed on contact pads of the conductive layer 304. The conductive pillars 310 are formed by depositing one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material into openings of a masking layer. In other embodiments, the conductive pillars 310 are formed by another suitable metal deposition technique. In some embodiments, conductive bumps 236, CCSB 240-242, or PCB units 246 are used instead of the conductive pillars 310.

[0065] In Figure 11b semiconductor die 104 and discrete device 312 are surface mounted to substrate 300 and electrically connected to conductive layer 304 by solder paste 314 and conductive bumps 114. Semiconductor die 104 can perform the same functions as semiconductor die 104 of EDS 230 or different functions. Figure 11c sealant 320 is shown deposited on substrate 300, conductive pillars 310, semiconductor die 104, and discrete device 312, similar to sealant 220. In Figure 11d In

[0066] In Figure 11e In

[0067] In Figure 11f In

[0068] Figure 12 SiP module 340 is illustrated with both top SiP sub-module 251 and bottom SiP sub-module 301 mounted to EDS 230. Top SiP sub-module 251 and EDS 230 are combined as described above with respect to Figure 9 and 10As discussed. In one embodiment, the bottom SiP panel 330, the EDS panel 224, and the top SiP panel 280 are all stacked together before singulation, with bumps 282 between the top panel and the EDS panel, and bumps 342 between the EDS panel and the bottom panel. The bumps 282 and 342 are simultaneously reflowed to mechanically and electrically connect all three panels before singulating any of the three panels. In other embodiments, the EDS panel 224 is flipped before or after attaching the top SiP sub-module 251. The SiP sub-module 301 is mounted to the substrate 200 after singulation of the panel 330, or the panel 330 can be mounted as a whole.

[0069] Bumps 344 are formed on the exposed ends of the posts 310 and extend into the recesses 332. The bumps 344 are applied in a similar manner as the bumps 114. In some embodiments, the bumps 344 are formed on the posts 310 before singulating the panel 330 into the bottom SiP sub-module 301. The bumps 344 provide similar functionality as the bumps 284 in Figure 9 The bumps 344 are used to mount the SiP module 340 to a substrate of a larger electronic device, thus incorporating the SiP module functionality into the electronic device.

[0070] Figures 13a-13c Figures 1 1-13 illustrate forming SiP modules in which the top and bottom SiP sub-modules are formed directly on the substrate of the EDS. In Figure 13a The top SiP panel 350 is formed based on the substrate 150 in Figure 2b The discrete devices 260-264 and the encapsulant 270 are provided in Figure 13a as in Figures 8a-8d but are placed directly onto the conductive layer 156 of the substrate 150 instead of onto a separate substrate 250. In Figure 13b The bottom SiP panel 360 is formed based on the substrate 200 from Figure 3b The conductive posts 310, semiconductor dies 104, discrete devices 312, encapsulant 320, and conductive bumps 344 are provided as in Figures 11a-11f but are placed directly onto the conductive layer 206 of the substrate 200 instead of onto a separate substrate 300. In Figure 13c The panels 350 and 360 are mounted together, with the substrates 150 and 200 connected by conductive posts 210 as in Figure 4a

[0071] The encapsulant 220 is deposited between the substrates 150 and 200, and then the panels 350 and 360 are singulated into a plurality of SiP modules 370 as in Figure 14a ​The SiP module 370 includes any desired combination of discrete components and semiconductor dies mounted on the top and bottom surfaces of the substrates 150 and 200. All components mounted to the substrates 150 and 200 are electrically connected to one another and to the bump 344 through the substrates and the conductive posts 210 and 310 for further system integration. Figure 14b An embodiment of a SiP module 380 is illustrated that is formed from a top SiP panel 350 as in Figure 13a but with a bottom substrate 200 as used in Figure 3b The bumps 284 are disposed on the conductive layer 206 as in Figure 9

[0072] Figures 15a-15c An embodiment of a SiP module 390 is illustrated that is formed from an EDS 230 using separately packaged semiconductor dies. Figure 15a The SiP module 390 is similar to the SiP module 340, but with a semiconductor package 392 in place of the bare semiconductor dies 104. The semiconductor dies 394 are bumped with conductive bumps 396 and encapsulated with an encapsulant 398 to form the package 392. In other embodiments, other types of semiconductor packages 392 are mounted on the substrate 300. The semiconductor package 392 can include a leadframe or substrate for the package. In various embodiments, any of the semiconductor dies disclosed herein can be replaced with a packaged die of any package type.

[0073] Figure 15b Two separate bottom SiP sub-modules 400 and 410 are illustrated disposed on the substrate 200 of the EDS 230. The bottom SiP sub-module 400 is similar to the bottom SiP sub-module 301 and includes the semiconductor dies 104, the discrete devices 312, and the conductive posts 310. The bottom SiP sub-module 410 is a separately packaged semiconductor die 412. The semiconductor die 412 is disposed on a substrate 414 using conductive bumps 416 and is molded within an encapsulant 418. Any other type of semiconductor package can be mounted to the conductive layer 206 of the substrate 200 adjacent to the bottom SiP sub-module 400 as the bottom SiP sub-module 410. The bottom SiP sub-module 410 can include other types of substrates or leadframes, or can be formed without a substrate as with the semiconductor package 392 in Figure 15a The bottom SiP sub-module 410 can include the conductive posts 310 or other vertical interconnect structures to allow connection through the bottom SiP sub-module 410 to the underlying substrate of a larger system as in Figures 19a-19b The bottom SiP sub-module 410 can also incorporate the discrete devices and any other features of the bottom SiP sub-module 400 or 301. ​

[0074] In Figure 15c , SiP module 420 includes a panel 350 from Figure 13a combined with substrate 200 in Figure 3b . Panel 350 is formed with conductive pillars 422 extending through encapsulant 170 and conductive bumps 424 on the pillars for subsequent system integration. Top SiP sub-module 426 includes discrete devices 428 and semiconductor package 431 mounted on substrate 430. Semiconductor package 431 is similar to semiconductor package 410 in Figure 15b . As illustrated, semiconductor package 431 includes semiconductor die 104 mounted on substrate 432, molded with encapsulant 434, and mounted to substrate 430 with conductive bumps 436. Other semiconductor package types are used in other embodiments. Figure 15c Semiconductor dies 104 in

[0075] Figures 16a-16c Illustrates forming an EDS where embedded components are molded prior to integration into the EDS. Figure 16a Illustrates substrate 150 with semiconductor dies 104 and discrete devices 160 and 162 mounted to the substrate. Semiconductor dies 104 and discrete devices 160-162 are molded in encapsulant prior to handling on substrate 150 to form semiconductor package 440. In one embodiment, semiconductor dies 104 and discrete devices 160-162 for multiple substrates 150 or 200 are disposed on a carrier, adjacent to each other, and encapsulated on the carrier to form a panel of packages 440. Conductive bumps 114 and solder 166 are disposed directly on the carrier and not completely covered by encapsulant. The encapsulated panel of semiconductor packages 440 is singulated into individual packages for use on substrate 150 or 200. Semiconductor package 440 is disposed on substrate 150 with bumps 114 and solder 166 on conductive layer 154.

[0076] A portion of the components disposed on substrate 150 or 200 can be packaged together while other discrete components or semiconductor dies are disposed outside the encapsulant. For illustration purposes, Figure 16a each component on substrate 150 encapsulated in package 440 is illustrated while Figure 16bA substrate 200 is illustrated with semiconductor dies 104 within semiconductor packages 442 and discrete devices 160-162 outside of the packages. In one embodiment, the same package configuration is used on both substrates 150 and 200. In other embodiments, any combination of semiconductor dies, semiconductor packages, and other components can be surface mounted to substrates 150 and 200. The semiconductor packages used on substrates 150 and 200 include any type of semiconductor package, and in some embodiments include a substrate or leadframe within the package.

[0077] In Figure 16c , substrates 150 and 200 are stacked face-to-face and sealed, as in Figures 4a-4b , to form EDS 446. EDS 446 can be singulated, as in Figure 4c , or left as a larger panel until additional SiP module components are added.

[0078] Figures 17a-17c Options for electromagnetic interference (EMI) shielding of a SiP module are illustrated with semiconductor packages between substrates 150 and 200. Figure 17a An EDS 450 is illustrated with semiconductor packages 440 and 442. Semiconductor package 442 includes a shielding layer 452 formed on the package. Semiconductor package 440 includes a shielding layer 454 formed on the package. In one embodiment, shielding layers 452 and 454 are applied during fabrication of packages 442 and 440. A panel of sealed components is singulated by the encapsulant but left on a carrier. Singulation removes the encapsulant material between each of the adjacent packages. A conductive material is electroplated on the top of the packages and into the space between the packages created by singulation. Electroplating is performed by CVD, PVD, electroless plating, or other suitable metal deposition process. Shielding layers 452 and 454 include one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. The devices are singulated through their shielding layers to finally separate each of the devices before mounting on substrates 150 and 200. In other embodiments, packages 440 and 442 are electroplated with shielding layers 452 and 454 after mounting on substrates 150 and 200 by using masking layers on other areas of the substrates.

[0079] Shielding layers 452 and 454 cover the top and side surfaces of packages 442 and 440, respectively. In some embodiments, shielding layers 452 and 454 are electrically connected to the conductive layer of the substrate to provide an electrical ground. Shielding layers 452 and 454 can be applied on any suitable type of semiconductor package used with substrates 150 and 200. Shielding layers 452 and 454 are formed by using any suitable process for forming a shielding layer on a semiconductor package. Shielding layers 452 and 454 reduce the amount of electromagnetic radiation that hits packages 442 and 440 that reaches semiconductor die 104 and other components within the package. EDS 450 can form the basis for any of the SiP modules disclosed herein.

[0080] Figure 17b SiP module 460 is illustrated that is fabricated based on EDS 446. Discrete devices 260-264 are mounted onto substrate 250 and molded with encapsulant 270. After discrete devices 260-264 and encapsulant 270 are added, shielding layer 462 is formed over the entire SiP module 460. In one embodiment, multiple SiP modules 460 are formed as a panel and singulated on a carrier. Shielding layer 462 is deposited on the panel after singulation, while the units remain on the carrier. Shielding layer 462 is generally similar to shielding layers 452 and 454, but is formed at the SiP module level rather than at the semiconductor package level.

[0081] Figure 17c SiP module 470 is illustrated that is formed with both shielding layers 452 and 454 from Figure 17a and shielding layer 462 from Figure 17b .

[0082] Figures 18a-18d Additional EMI shielding options for SiP modules with EDS substrates are illustrated. Figure 18a SiP module 480 is illustrated that has shielding layer 482 formed on top SiP sub-module 251. Top SiP sub-module 251 is formed as in Figures 8a-8d , and shielding layer 482 is formed on the panel of units after singulation. In some embodiments, conductive layer 254 or conductive layer 256 extends laterally to the edge of substrate 250 to contact shielding layer 482 and provide a ground connection.

[0083] Figure 18b SiP module 490 is shown that adds lower SiP sub-module 301 as in Figure 12 , where shielding layer 494 is formed over the lower SiP sub-module. Bottom SiP sub-module 301 is formed as shown in Figures 11a-11f . In Figure 11fThe faceplate is plated with a shield layer 494 after singulation in the

[0084] Figure 18c A SiP module 500 is illustrated that is formed by adding a shield layer 452 to the SiP module 350. Figure 14b A SiP module 370 is illustrated that is formed by adding a shield layer 462 to the SiP module 350. Figure 18d A SiP module 510 is illustrated that is formed by adding a shield layer 512 to the SiP module 370. The shield layers 502 and 512 are formed in a similar manner as the shield layers 452, 454, and 462 above. Figure 14a

[0085] Figures 19a-19b Electronic devices incorporating the SiP modules and EDS substrates described above are illustrated. Figure 19a A portion of the SiP module 380 from Figure 14b is mounted onto a PCB or other substrate 520 as part of an electronic device. The bumps 284 are reflowed onto a conductive layer 522 for physically attaching and electrically connecting the SiP module 380 to the PCB 520. Any of the SiP modules or EDS substrates described above can similarly be mounted onto the PCB 520 individually. In other embodiments, thermal compression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the SiP module 380 and the PCB 520.

[0086] The semiconductor die 104 is electrically coupled to the conductive layer 522 through the bumps 114, the substrates 200 and 150, the conductive posts 210, and the conductive bumps 284. The discrete devices 260-264 are coupled to the conductive layer 522 and the semiconductor die 104 through the substrate 150, the conductive posts 210, the substrate 200, and the conductive bumps 284.

[0087] Figure 19b An electronic device 524 is illustrated that includes a PCB 520 having a plurality of semiconductor packages mounted on a surface of the PCB, including the SiP module 380. The electronic device 524 can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

[0088] ​The electronic device 524 can be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 524 can be a subcomponent of a larger system. For example, the electronic device 524 can be part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. The electronic device 524 can also be a graphics card, a network interface card, or other signal processing card that is plugged into a computer. The semiconductor package can include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor dies or electrical components.

[0089] In Figure 19b The PCB 520 provides a general substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. In some embodiments, the PCB 520 is fabricated as an EDS according to the above description and includes active and passive components embedded within the PCB. Conductive signal traces 522 are formed on the surface of the PCB 520 or within layers of the PCB 520 by using evaporation, electrolytic plating, chemical plating, screen printing, or other suitable metal deposition processes. The signal traces 522 provide electrical communication between each of the semiconductor packages, the mounted components, and other external systems or components. The traces 522 also provide power and ground connections to each of the semiconductor packages as needed.

[0090] In some embodiments, the semiconductor device has two package levels. The first level package is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level package involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device can have only the first level package, in which the die is mechanically and electrically mounted directly to the PCB.

[0091] For illustrative purposes, several types of first level packages are shown on the PCB 520, including wire bond packages 526 and flip chips 528. In addition, several types of second level packages, including ball grid array (BGA) 530, bump chip carrier (BCC) 532, land grid array (LGA) 536, multi-chip module (MCM) 538, quad flat no-lead package (QFN) 540, embedded wafer level ball grid array (eWLB) 544, and wafer level chip scale package (WLCSP) 546 are shown mounted on the PCB 520 along with the SiP module 380. In one embodiment, the eWLB 544 is a fan-out wafer level package (Fo-WLP) and the WLCSP 546 is a fan-in wafer level package (Fi-WLP).

[0092] Semiconductor packages configured with any combination of the first and second hierarchical package styles, as well as any combination of other electronic components, can be connected to the PCB 520, depending on the needs of the system. In some embodiments, the electronic device 524 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because the semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less likely to malfunction and are less expensive to manufacture, resulting in lower costs for consumers.

[0093] While one or more embodiments of the application have been illustrated and described in detail, those skilled in the art will readily devise many modifications and variations that fall within the scope of the application as set forth in the claims.

Claims

1. A semiconductor device, comprising: First substrate; A first semiconductor component disposed on a first surface of the first substrate; A first solder bump is disposed between a first semiconductor component and a first substrate to mechanically bond the first semiconductor component and electrically connect it to the first substrate; A first sealant deposited on the first semiconductor component and extending into the first substrate; A first shielding layer formed on the first sealant and extending into the first substrate; A first discrete device is disposed on a first surface of a first substrate by a first solder paste disposed between the first discrete device and a first substrate, wherein the first discrete device is outside a first sealant. A second substrate is disposed on the first substrate; A second semiconductor component disposed on a first surface of a second substrate, wherein the first semiconductor component and the second semiconductor component are disposed between the first substrate and the second substrate, and wherein no semiconductor component on the first substrate is mounted in a region on the first surface of the first substrate above the second semiconductor component, and no semiconductor component on the second substrate is mounted in a region on the first surface of the second substrate above the first semiconductor component. A second solder bump is disposed between the second substrate and the second semiconductor component to mechanically bond the second semiconductor component and electrically connect it to the second substrate; A second discrete device is disposed on a first surface of a second substrate, wherein a second solder paste is disposed between the second discrete device and the second substrate; A second sealant is deposited on the second semiconductor assembly and the second discrete device and extends to the second substrate, wherein the second discrete device is sealed by the second sealant. A second shielding layer formed on the second sealant and extending into the second substrate; A first vertical interconnect structure extending from the first substrate to the second substrate, wherein the first vertical interconnect structure includes copper core solder balls (CCSB); A third sealant is deposited between the first substrate and the second substrate, wherein the third sealant extends between the first shielding layer and the second substrate, between the second shielding layer and the first substrate, and between the first discrete device and the first shielding layer, and wherein the third sealant physically contacts the first substrate, the second substrate, the first shielding layer, the second shielding layer and the first discrete device. A third semiconductor component is mounted on a second surface of the first substrate opposite to the first surface; A third solder bump is disposed between the third semiconductor component and the first substrate; A third discrete device disposed on the second surface of a first substrate, wherein a third solder paste is disposed between the third discrete device and the first substrate; A fourth sealant directly deposited on the second surface of the first substrate; A second vertical interconnect structure extending through the fourth sealant; A groove is formed into the fourth sealant around the second vertical interconnect structure; A fourth solder bump is disposed on the second vertical interconnect structure and into the groove; A discrete capacitor is mounted to a second surface of a second substrate opposite to the first surface, wherein the discrete capacitor is mounted between the discrete capacitor and the second substrate using a fourth solder paste. A discrete resistor is mounted to the second surface of the second substrate, wherein a fifth solder paste is disposed between the discrete resistor and the second substrate; Discrete inductors are mounted to the second surface of the second substrate by applying a sixth solder paste between the discrete inductors and the second substrate, wherein discrete capacitors, discrete resistors and discrete inductors implement a bandpass filter, and wherein only passive components are mounted to the second surface of the second substrate. A fifth sealant deposited on the second surface of the second substrate, on the discrete inductors, discrete capacitors, and discrete resistors; as well as A third shielding layer is formed on the fifth sealant, wherein the third shielding layer extends downward along the side surfaces of the fifth sealant, the second substrate, the third sealant, the first substrate and the fourth sealant; The first semiconductor component, the first discrete device, the second semiconductor component, the second discrete device, the third semiconductor component, the third discrete device, the discrete resistor, the discrete capacitor, and the discrete inductor are electrically connected to each other and are electrically connected to the fourth solder bump through the first substrate, the second substrate, the first vertical interconnect structure, and the second vertical interconnect structure.

2. The semiconductor device according to claim 1, wherein the first semiconductor component or the second semiconductor component is a semiconductor package.

3. A semiconductor device, comprising: First substrate; A first semiconductor component mounted on the first substrate; A first solder bump is disposed between a first substrate and a first semiconductor component to mechanically bond the first semiconductor component and electrically connect it to the first substrate; A second substrate is disposed on the first substrate; A second semiconductor component is mounted to the second substrate, wherein the second semiconductor component is within the height of the first semiconductor component; A second solder bump is disposed between the second substrate and the second semiconductor component to mechanically bond the second semiconductor component and electrically connect it to the second substrate; A first sealant is deposited between the first and second substrates, and on the first and second semiconductor components; A first vertical interconnect structure extending from the first substrate to the second substrate via the first sealant; A third semiconductor component is mounted on a first substrate opposite to the first semiconductor component; A third solder bump is disposed between the first substrate and the third semiconductor component to mechanically bond the third semiconductor component and electrically connect it to the first substrate; A second sealant is deposited on the first substrate and the third semiconductor component, opposite to the first sealant; A second vertical interconnect structure that extends through the second sealant and is exposed from the surface of the second sealant; A groove is formed in the surface of the second sealant around the second vertical interconnect structure, wherein the side surface of the second vertical interconnect structure is exposed in the groove; A fourth solder bump is disposed in the groove and above the second vertical interconnect structure for further system integration, wherein the fourth solder bump fills the groove; A discrete capacitor is mounted to a second substrate opposite to a second semiconductor component, wherein the discrete capacitor is mounted between the discrete capacitor and the second substrate with a first solder paste disposed therebetween. Discrete resistors are mounted onto a second substrate opposite to a second semiconductor assembly by applying a second solder paste between the discrete resistors and the second substrate. Discrete inductors are mounted to a second substrate opposite to a second semiconductor component by means of a third solder paste disposed between the discrete inductors and the second substrate, wherein the discrete capacitors, discrete resistors and discrete inductors implement a bandpass filter, and wherein only passive components are mounted to a second surface of the second substrate. as well as A third sealant deposited on the second substrate, discrete inductors, discrete capacitors, and discrete resistors; The first semiconductor component, the second semiconductor component, the third semiconductor component, the discrete capacitor, the discrete resistor and the discrete inductor are electrically connected to each other, and are electrically connected to the fourth solder bump through the first substrate, the second substrate, the first vertical interconnect structure and the second vertical interconnect structure.

4. The semiconductor device of claim 3, wherein the groove includes an inclined surface extending from the surface of the second sealant to the second vertical interconnect structure.

5. A semiconductor device, comprising: First substrate; Second substrate; A first semiconductor component disposed on the first substrate; A first solder bump is disposed between a first semiconductor component and a first substrate to mechanically bond the first semiconductor component and electrically connect it to the first substrate; A first sealant deposited on the first semiconductor component and extending into the first substrate; A shielding layer formed on a first sealant and a first semiconductor component, wherein the shielding layer extends to a conductive layer of a first substrate; A second sealant deposited between a first substrate and a second substrate, comprising a shielding layer disposed between the first sealant and the second substrate; as well as A third sealant is deposited directly on the first substrate, wherein the first substrate is disposed between the first sealant and the third sealant.

6. The semiconductor device of claim 5, further comprising a second semiconductor component disposed on the first substrate, opposite to the first semiconductor component, and within the third sealant.

7. The semiconductor device of claim 5 further includes a semiconductor package disposed on the second substrate and opposite to the first semiconductor component.

Images