Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device according to the present invention includes: a first plurality of all-around gate (GAA) devices, located in a first device region; and a second plurality of GAA devices, located in a second device region. Each of the first plurality of GAA devices includes: a first vertical stack of channel members extending along a first direction; and a first gate structure located above and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes: a second vertical stack of channel members extending along a second direction; and a second gate structure located above and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length, and each of the second plurality of GAA devices includes a second channel length that is less than the first channel length. Embodiments of the present invention also relate to methods for manufacturing semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors (also known as non-planar transistors) are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps the top and sidewalls of a "fin" of semiconductor material extending from a substrate). This configuration provides better control of the channel and greatly reduces SCE (specifically, by reducing subthreshold leakage (i.e., coupling between the source and drain of a FinFET in the "off" state)) compared to planar transistors. The gate structure of a GAA transistor may extend partially or entirely around the channel region to provide access to the channel region on two or more sides. The channel region of the GAA transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. In some embodiments, such a channel region includes a plurality of nanostructures stacked vertically (extending horizontally to provide a horizontally oriented channel). Such a GAA transistor can be referred to as a vertically stacked horizontal GAA (VGAA) transistor.

[0004] Different processes have been developed to obtain different GAA transistors with different threshold voltages in different device regions. The different voltages allow for staged activation of transistors in different device regions. It has been observed that these conventional processes may result in gate edge roughness and reduced process stability. Therefore, although conventional GAA devices are generally adequate for their intended purposes, they are not satisfactory in every respect. Summary of the invention

[0005] An embodiment of the present invention provides a semiconductor device, comprising: a first plurality of gate-all-around (GAA) devices, located in a first device region, wherein each of the first plurality of gate-all-around devices comprises: a first vertical stack of channel components, extending along a first direction, and a first gate structure, located above and around the first vertical stack of the channel components; and a second plurality of gate-all-around devices, located in a second device region, wherein each of the second plurality of gate-all-around devices comprises: a second vertical stack of channel components, extending along a second direction, and a second gate structure, located above and around the second vertical stack of the channel components, wherein each of the first plurality of gate-all-around devices comprises a first channel length, wherein each of the second plurality of gate-all-around devices comprises a second channel length that is less than the first channel length.

[0006] Another embodiment of the present invention provides a semiconductor device, comprising: a first plurality of all-around gate (GAA) devices, located in a first device region, wherein each of the plurality of first all-around gate devices comprises: a first vertical stack of channel members, extending along a first direction, a first gate top member, disposed above a topmost channel member of the first vertical stack of channel members, and a plurality of first lower gate members, disposed between two adjacent channel members of the first vertical stack of channel members; and a second plurality of all-around gate devices, located in a second device region, wherein each of the second plurality of all-around gate devices comprises: a second vertical stack of channel members, extending along a second direction, a second gate a top component disposed above a topmost channel component of a second vertical stack of channel components, and a plurality of second lower gate components disposed between two adjacent channel components of the second vertical stack of channel components, wherein the first gate top component comprises a first length along the first direction, wherein the second gate top component comprises a second length along the second direction, wherein the first length and the second length are the same, wherein each of the plurality of first lower gate components comprises a third length along the first direction, wherein each of the plurality of second lower gate components comprises a fourth length along the second direction, wherein the third length is greater than the fourth length.

[0007] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a layer stack including a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers on a substrate; forming a first plurality of fin elements from the layer stack in a first region of the substrate; forming a second plurality of fin elements from the layer stack in a second region of the substrate; forming a first plurality of dummy gate stacks above the first plurality of fin elements; forming a second plurality of dummy gate stacks above the second plurality of fin elements; depositing a spacer layer above the first plurality of dummy gate stacks and the second plurality of dummy gate stacks; selectively depositing a polymer layer above the spacer layer disposed above the first plurality of dummy gate stacks, while the spacer layer is disposed above the second plurality of dummy gate stacks not covered by the polymer layer; and etching the spacer layer above the first plurality of dummy gate stacks and the second plurality of dummy gate stacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1A , Figure 1B and Figure 1C Flowcharts collectively illustrate methods for forming a semiconductor device having multiple device regions according to one or more aspects of the present invention.

[0010] Figure 2 , Figure 3 , FIG. 4A to FIG. 4B , FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B , FIG. 8A to FIG. 8B , FIG. 9A to FIG. 9B , FIG. 10A to FIG. 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B , FIG. 14A to FIG. 14B , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and FIG. 22A to FIG. 22B According to one or more aspects of the present invention, Figures 1A to 1C A cross-sectional view of a workpiece during a manufacturing process. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] In addition, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or operating processes in addition to the orientation shown in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Further, when "about," "approximately," etc. are used to describe a number or a range of numbers, unless otherwise stated, the term is intended to cover numbers within + / -10% of the number. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0013] The present invention relates generally to multi-gate transistors and methods of fabrication, and more particularly to fabricating gate-all-around (GAA) transistors in different device regions of a semiconductor device.

[0014] Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of the channel region. These multi-gate devices may include p-type metal oxide semiconductor devices or n-type metal oxide semiconductor devices. Examples of multi-gate transistors include FinFETs because of their fin-type structures and all-around gate (GAA) devices. GAA devices include any device whose gate structure or part thereof is formed on the 4 sides of the channel region (e.g., the portion surrounding the channel region). Embodiments of the present invention may have channel regions configured as nanowire channels, strip channels, nanosheet channels, nanostructure channels, columnar channels, rod-shaped channels, and / or other suitable channel configurations. Devices according to the present invention may have one or more channel regions (e.g., nanowires, nanosheets, nanostructures) associated with a single continuous gate structure. However, those of ordinary skill will recognize that the teachings in the present invention may be applicable to a single channel (e.g., a single nanowire, a single nanosheet, a single nanostructure) or any number of channels. Those of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of the present invention.

[0015] As the proportion of the fin width in the FinFET decreases, the change in channel width may cause undesirable changes and mobility loss. GAA transistors are being studied as an alternative to FinFETs. In a GAA transistor, the gate of the transistor is formed around the entire channel so that the channel is surrounded or wrapped by the gate. The advantage of this transistor is that the electrostatic control of the gate over the channel is improved, which also alleviates the leakage current. GAA transistors include various spacers, such as internal spacers and gate spacers (also referred to as external spacers, top spacers or main spacers). The internal spacer is used to reduce capacitance and prevent leakage between the gate structure and the source / drain components. During the formation of the GAA transistor, the gate spacer is used as a mask during the formation of the source / drain trench. In the gate replacement process, after removing the dummy gate stack to make room for the metal gate stack, the gate spacer is used to maintain the integrity of the gate trench. The method according to the present invention is designed to manufacture GAA transistors with different threshold voltages to form gate spacers of different thicknesses in different regions.

[0016] exist Figures 1A to 1CA method 100 of forming a semiconductor device having multiple device regions of a multi-gate device is shown in FIG. As used herein, the term "multi-gate device" is used to describe a device (e.g., a semiconductor device) having at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, the multi-gate device may be referred to as a GAA device having gate material disposed on at least four sides of at least one channel of the device. The channel region may be referred to as a nanowire, nanosheet, nanostructure, channel member, semiconductor channel member, which, as used herein, include channel regions of various geometries (e.g., cylindrical, strip, sheet) and various sizes.

[0017] As with other method embodiments and exemplary devices discussed herein, it will be appreciated that Figure 2 , Figure 3 , FIG. 4A to FIG. 4B , FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B , FIG. 8A to FIG. 8B , FIG. 9A to FIG. 9B , FIG. 10A to FIG. 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B , FIG. 14A to FIG. 14B , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and FIG. 22A to FIG. 22B The various parts of the workpiece 200 shown in can be manufactured by a CMOS technology process flow, so only some processes are briefly described here. After completing the manufacturing process, the workpiece 200 will be manufactured into a semiconductor device 200. In this sense, in an appropriate context, the workpiece 200 can be referred to as a semiconductor device 200. In addition, the exemplary semiconductor device may include various other devices and components, such as other types of devices, including additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, SRAM and / or other logic circuits, etc., but are simplified for a better understanding of the inventive concepts of the present invention. In some embodiments, the exemplary device includes a plurality of semiconductor devices (e.g., transistors) that can be interconnected, including n-type GAA transistors, p-type GAA transistors, PFETs, NFETs, etc. In addition, it should be noted that the process steps of method 100 include reference Figure 2 , Figure 3 , FIG. 4A to FIG. 4B , FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B , FIG. 8A to FIG. 8B , FIG. 9A to FIG. 9B , FIG. 10A to FIG. 10B, FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B , FIG. 14A to FIG. 14B , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and FIG. 22A to FIG. 22B Any description given, such as the remainder of the method and the exemplary drawings provided in this disclosure, is merely exemplary and is not intended to limit what is specifically recited in the following claims.

[0018] refer to Figure 1A , Figure 2 and Figure 3 , the method 100 includes block 102, in which an epitaxial stack 204 is formed over a substrate 202. The epitaxial stack 204 includes first semiconductor layers 206 and second semiconductor layers 208 vertically stacked in an alternating configuration. Figure 2 200 is shown in FIG. The workpiece 200 includes a substrate 202, which may be a semiconductor substrate such as a silicon substrate. The substrate 202 may include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. As is known in the art, depending on the design requirements, the substrate 202 may include various doping configurations. For example, different doping profiles (e.g., n-well, p-well) may be formed on the substrate 202 in regions designed for different device types (e.g., n-type GAA transistors, p-type GAA transistors). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 may have isolation components between regions providing different device types. The substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. In addition, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon on insulator (SOI) structure, and / or may have other suitable enhancement components. In an embodiment of the method 100, an anti-punch-through (APT) implant is performed. For example, an APT implant may be performed in a region below a channel region of a device to prevent punch-through or unwanted diffusion.

[0019] The epitaxial stack 204 includes a first semiconductor layer 206 between a second semiconductor layer 208. The epitaxial stack 204 may also be referred to as a layer stack 204. Figure 2As shown, the first semiconductor layer 206 and the second semiconductor layer 208 are alternately and epitaxially deposited along the Z direction so that they are staggered. The components of the first semiconductor layer 206 and the second semiconductor layer 208 are different. In an embodiment, the first semiconductor layer 206 can be formed of silicon germanium (SiGe), and the second semiconductor layer 208 can be formed of silicon (Si). However, other embodiments are possible, including those that provide a first semiconductor component and a second semiconductor component with different oxidation rates and / or etching selectivities. For example, any one of the first semiconductor layer 206 and the second semiconductor layer 208 can include other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP or combinations thereof. As an example, the epitaxial growth of the layers of the epitaxial stack 204 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers such as the second semiconductor layer 208 include the same material as the substrate 202. In some embodiments, the first semiconductor layer 206 and the second semiconductor layer 208 are substantially dopant-free (i.e., have a thickness from about 0 cm to about 10 cm). -3 To about 1x10 17 cm -3 of extrinsic dopant concentration), for example, without intentional doping during the epitaxial growth process.

[0020] Note that Figure 2 As shown in other figures, three (3) layers of the first semiconductor layer 206 and three (3) layers of the second semiconductor layer 208 are arranged alternately, which is for illustrative purposes only and is not intended to limit the specific contents described in the claims. It is understood that any number of epitaxial layers can be formed in the epitaxial stack 204. The number of layers depends on the desired number of channel components of the device 200. In some embodiments, the number of the second semiconductor layer 208 is between 2 and 10.

[0021] In some embodiments, each first semiconductor layer 206 has a thickness in the range of about 2 nanometers (nm) to about 6nm, such as 3nm in a specific example. The thickness of the first semiconductor layer 206 can be substantially uniform. In some embodiments, each second semiconductor layer 208 has a thickness in the range of about 6nm to about 12nm, such as 9nm in a specific example. In some embodiments, the thickness of the second semiconductor layer 208 of the epitaxial stack 204 is substantially uniform. As described in more detail below, the second semiconductor layer 208 or a portion thereof can be used as a channel member of a subsequently formed multi-gate device, and the thickness is selected based on device performance considerations. The first semiconductor layer 206 in the channel region can eventually be removed, and the first semiconductor layer 206 is used to define the vertical distance between adjacent channel regions of the subsequently formed multi-gate device, and the thickness is selected based on device performance considerations. Therefore, the first semiconductor layer 206 can also be referred to as a sacrificial layer 206, and the second semiconductor layer 208 can also be referred to as a channel layer 208.

[0022] refer to Figure 1A , Figure 3 , Figure 4A , Figure 4B , Figure 5A and Figure 5B , the method 100 includes a block 104, in which a fin element 211 is formed from the epitaxial stack 204. Referring first to Figure 3 , a fin top hard mask layer 210 may be deposited over the workpiece 200. The fin top hard mask layer 210 may be a single layer or multiple layers. In some embodiments, the fin top hard mask layer 210 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbide, or a combination thereof. In embodiments where the fin top hard mask layer 210 is multiple layers, the fin top hard mask layer 210 may include a silicon oxide layer deposited on the epitaxial stack and a silicon nitride layer deposited on the silicon oxide layer. The fin top hard mask layer 210 is used in a patterning process to pattern the fin top hard mask layer 210 to form Figure 4A and Figure 4BThe fin element 211 shown. For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. The patterning process may be performed on the workpiece 200 until the fin element 211 extends from the substrate 202. In some embodiments, the patterning is also etched into the substrate 202 so that each fin element 211 includes a lower portion formed by the substrate 202 and an upper portion formed by the epitaxial stack 204. The upper portion includes each epitaxial layer of the epitaxial stack 204, including the sacrificial layer 206 and the channel layer 208. In some embodiments, the fin element 211 can be manufactured using a double patterning or multiple patterning process. Typically, a double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing for the production of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin elements 211 by etching the epitaxial stack 204. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. As shown in FIG. Figure 4A and Figure 4B As shown, the fin element 211 extends longitudinally along the X-direction.

[0023] Reference now Figure 5A and Figure 5B. After forming the fin elements 211, isolation features 212 are formed between adjacent fin elements 211. The isolation features 212 may also be referred to as shallow trench isolation (STI) features 212. As an example, in some embodiments, a dielectric layer is first deposited over the substrate 202, and the trenches between the fin elements 211 are filled with a dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and / or other suitable processes. Then, the deposited dielectric material is thinned, and the deposited dielectric material is planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed by a dry etching process, a wet etching process, and / or a combination thereof to form the STI features 212. After recessing, at least an upper portion of the fin element 211 is elevated above the STI feature 212. In some embodiments, the dielectric layer (and subsequently formed STI feature 212) may include a multi-layer structure, for example, with one or more liner layers.

[0024] In some embodiments not shown separately in the present invention, dielectric fins may also be formed at frame 104 of method 100. In an example process flow for forming dielectric fins, a slit extending parallel to the fin element 211 is formed in the dielectric material for the STI component 212, and then the dielectric fin material is deposited into the slit. The dielectric fin material is different from the dielectric material forming the STI component 212. This allows the dielectric layer for the STI component 212 to be selectively etched, leaving the dielectric fin raised above the STI component 212. In some embodiments, the dielectric fin material may include silicon nitride, silicon carbonitride, silicon carbide, aluminum oxide, zirconium oxide, or other suitable materials. In an embodiment in which dielectric fins are deployed, the dielectric fins are between the fin elements 211 and are used to separate the source / drain components of adjacent devices. Dielectric fins may also be referred to as pseudo fins or hybrid fins. In some optional embodiments, the upper portion of the dielectric fin may be removed during the gate cutting process and replaced by a reverse material component that may be different or similar to the dielectric fin. When formed, the dielectric fins limit the formation of epitaxial source / drain features and prevent undesirable merging between adjacent epitaxial source / drain features.

[0025] Still refer to Figure 1A , Fig. 6A , Figure 6B , Fig. 7A and Figure 7B, the method 100 includes block 106, where a dummy gate stack 220 is formed over the channel region 30 of the fin element 211. In some embodiments, a gate replacement process (or gate-last process) is employed, where the dummy gate stack 220 is used as a placeholder for a metal gate stack and is removed and replaced by a metal gate stack in a subsequent process. Other processes and configurations are possible. Now referring to Fig. 6A and Figure 6B . In order to form the dummy gate stack 220, a dummy dielectric layer 214 is first deposited on the workpiece 200 (including on the fin element 211) by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, or an ALD process. The dummy dielectric layer 214 may be formed of silicon oxide, silicon nitride, or other suitable dielectric materials. The dummy dielectric layer 214 may be used to prevent damage to the fin element 211 by subsequent processes (e.g., the formation of a dummy gate stack). Then, a dummy gate material layer 216 is deposited on the dummy dielectric layer 214. The dummy gate material layer 216 may be formed of polysilicon. For patterning purposes, a gate top hard mask 218 may be deposited on the dummy gate material layer 216. The gate top hard mask 218 may be a single layer or multiple layers, and may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride oxide, or a combination thereof. In the case where the gate top hard mask 218 is multi-layered, the gate top hard mask 218 includes a silicon oxide layer deposited on the dummy gate material layer 216 and a silicon nitride layer deposited on the silicon oxide layer. The gate top hard mask 218, the dummy gate material layer 216, and the dummy dielectric layer 214 are patterned by a patterning process, and the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography), and the photolithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods.

[0026] refer to Fig. 7A and Figure 7B , a dummy gate stack 220 is formed over the substrate 202 and at least partially disposed over the fin element 211. After patterning, the dummy gate material layer 216 is formed into a dummy electrode 216. The portion of the fin element 211 located below the dummy gate stack 220 is the channel region 30 of the fin element 211. The dummy gate stack 220 may also define a source / drain (S / D) region 40 adjacent to the channel region 30 and located on opposite sides of the channel region 30. Fig. 7AAs shown, each channel region 30 can be sandwiched between two source / drain regions 40 along the X direction. In some embodiments, after forming the dummy gate stack 220, the dummy dielectric layer 214 is removed from the source / drain region 40 of the fin element 211. That is, the dummy dielectric layer 214 not covered by the dummy electrode 216 is removed. The removal process may include wet etching, dry etching, and / or a combination thereof. The etching process is selected to selectively etch the dummy dielectric layer 214 without substantially etching the fin element 211, the gate top hard mask 218, and the dummy electrode 216. Fig. 7A As shown, the dummy gate stacks 220 are disposed at a uniform pitch P throughout the workpiece 200 .

[0027] refer to Figure 1A , Fig. 8A and Figure 8B , the method 100 includes a frame 108, wherein a gate spacer layer 221 is deposited over the substrate 202 (including over the dummy gate stack 220). In some embodiments, a spacer material for forming the gate spacer layer 221 is conformally deposited over the workpiece 200 (including over the top surface and sidewalls of the dummy gate stack 220). The term "conformally" may be used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The gate spacer layer 221 may have a single layer construction or include multiple layers. Fig. 8A and Figure 8B In some of the illustrated embodiments, the gate spacer layer 221 includes a single layer construction. The gate spacer layer 221 may include silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon oxycarbide, silicon carbon oxynitride, other suitable dielectric materials, or combinations thereof. The spacer material may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, or other suitable process. The spacer material is then etched back in an anisotropic etching process to form the gate spacer layer 221. The anisotropic etching process exposes portions of the fin element 211 that are adjacent to the dummy gate stack 220 and not covered by the dummy gate stack 220 (e.g., in the source / drain region 40). Although in Fig. 8A and Figure 8B Although not explicitly shown in the figure, the portion of the spacer material directly above the dummy gate stack 220 may be partially or completely removed by the anisotropic etching process, while the gate spacer layer 221 remains on the sidewalls of the dummy gate stack 220 .

[0028] refer to Figure 1A , Fig. 9A and Fig. 9B, method 100 includes frame 110, wherein a pattern layer 224 is selectively formed over the gate spacer layer 221 in the first region 10 while exposing the gate spacer layer 221 in the second region 20. In some embodiments, the pattern layer 224 can be formed of a dielectric material or a polymer material. For example, such a dielectric material can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbon, or other suitable dielectric materials. Such a polymer material can be a photoresist material or a polyimide. In some embodiments, the polymer material can include fluorine and fluorocarbon (CF x , x = 1, 2 or 3) functional groups in the form of fluorine and carbon or chlorocarbon compounds (CCl x , x=1, 2 or 3) functional groups. The pattern layer 224 may be deposited using a chemical vapor deposition (CVD) or spin coating process. The pattern layer 224 in the first region 10 provides additional etch resistance to the gate spacer layer 221 on the dummy gate stack 220 in the first region 10 compared to the unprotected / uncovered spacer layer 221 on the dummy gate stack 220 in the second region. As will be described below in conjunction with Fig. 12A and Fig. 12B As described, this additional etch resistance results in the first gate spacer layer 222 being thicker in the first region 10 and the second gate spacer layer 222 ′ being thinner in the second region 20 .

[0029] refer to Figure 1A , Fig. 10A and Fig. 10B, the method 100 includes block 112, in which a source / drain trench 227 or 227' is formed in the fin element 211 using the first gate spacer layer 222, the pattern layer 224, and the second gate spacer layer 222' as an etching mask. In some embodiments, the source / drain region 40 of the fin element 211 in the first region 10 is recessed to form the first source / drain trench 227, and the source / drain region 40 of the fin element 211 in the second region 20 is recessed to form the second source / drain trench 227'. Although not explicitly shown, the operation at block 112 can be performed using a photolithography process and at least one hard mask. For example, the dry etching process may employ an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. As described above in conjunction with block 110, the etching at block 112 etches and removes the pattern layer 224 before etching the first gate spacer layer 222. The use of the pattern layer 224 slows down the thinning of the gate spacer layer 221 in the first region 10, resulting in the first gate spacer layer 222 being thicker than the second gate spacer layer 222'. In some embodiments, the first gate spacer layer 222 has a first thickness T1, and the second gate spacer layer 222' has a second thickness T2. In some cases, the first thickness T1 is greater than the second thickness T2, and the difference therebetween is between about 0.5 nm and about 5 nm. Due to the thickness difference between the first gate spacer layer 222 and the second gate spacer layer 222' and the uniform pitch P on the workpiece 200, the first source / drain trench 227 in the first region 10 is narrower than the second source / drain trench 227' in the second region 20. The first source / drain trench 227 in the first region 10 has a first spacing S1 along the X direction, and the second source / drain trench 227' in the second region 20 has a second spacing S2 along the X direction. The second spacing S2 is greater than the first spacing S1. In some cases, the first spacing S1 is between about 10 nm and about 40 nm, and the second spacing S2 is between about 15 nm and about 45 nm. Fig. 10A and Fig. 10B In some embodiments shown, the upper portion of the fin element 211 is recessed to expose the sacrificial layer 206 and the channel layer 208. In some embodiments, at least a portion of the lower portion of the fin element 211 is also recessed. That is, the first source / drain trench 227 and the second source / drain trench 227' can extend below the bottommost sacrificial layer 206 in the first region 10 and the second region 20. At the end of the operations in block 112, the source / drain region 40 of the fin element 211 can become flush with or lower than the top surface of the STI feature 212.

[0030] exist Fig.11A , Fig. 11B , Fig. 12A and Fig. 12B 10 and 112 are shown in FIG. In these alternative embodiments, no pattern layer 224 is selectively deposited in the first region 10. Instead, after forming the gate spacer layer 221 over the workpiece 200 at block 108, the first source / drain trench 227 in the first region 10 and the second source / drain trench 227' in the second region 20 are formed separately. Fig.11A and Fig. 11B As shown, a first photoresist layer 226-1 is selectively deposited in the first region 10, and the fin element 211 in the second region 20 of the workpiece 200 is anisotropically etched in a first etch-back process to form a second source / drain trench 227'. Fig. 12A and Fig. 12B As shown, a second photoresist layer 226-2 is selectively deposited in the second region 20, and the fin element 211 in the first region 10 of the workpiece 200 is anisotropically etched in a second etch-back process to form a first source / drain trench 227. The parameters of the first etch-back process and the second etch-back process may be different, so that the first etch-back process etches the gate spacer layer 221 in the second region 20 faster than the second etch-back process etches the gate spacer layer in the first region 10. For example, the first etch-back process may include a different etchant, a lower process pressure, a higher bias voltage, a higher plasma density, a more reactive etchant, or a higher temperature than the second etch-back process.

[0031] refer to Figure 1A , Fig.13A and Fig. 13B The method 100 includes block 114, wherein the first semiconductor layer 206 in the fin elements 211 in the first region 10 and the second region 20 is recessed to form an inner spacer recess 228. Fig.13A and Fig. 13BIn some of the embodiments shown, the sacrificial layer 206 exposed in the first source / drain trench 227 and the second source / drain trench 227' is selectively and partially recessed to form an internal spacer recess 228, while the exposed channel layer 208 is substantially unetched. In embodiments where the channel layer 208 is substantially composed of Si and the sacrificial layer 206 is substantially composed of SiGe, the selective recessing of the sacrificial layer 206 may include a SiGe oxidation process followed by removal of the SiGe oxide. In those embodiments, the SiGe oxidation process may include the use of ozone. In some embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. In some embodiments, the selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. As Fig.13A and Fig. 13B As shown, the inner spacer recess 228 extends inwardly from the first source / drain trench 227 in the first region 10 or from the second source / drain trench 227' in the second region 20. In some embodiments, the selective wet etching process may include hydrogen fluoride (HF) or NH4OH etchant. Although the first gate spacer layer 222 in the first region 10 and the second gate spacer layer 222' in the second region 20 have different thicknesses, the inner spacer recess 228 has a substantially uniform size on the workpiece 200. That is, the inner spacer recess 228 in the first region 10 and the inner spacer recess 228 in the second region 20 extend inwardly into the sacrificial layer 206 by substantially equal amounts.

[0032] refer to Figure 1B , Fig.14A and Fig. 14B, the method 100 includes a block 116, in which an inner spacer 230 is formed in the inner spacer recess 228. In some embodiments, the inner spacer layer can be deposited over the workpiece 200 by CVD, PECVD, LPCVD, ALD, or other suitable methods. The inner spacer layer can be formed of aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, silicon oxide, silicon carbonitride, silicon carbon nitride, silicon oxycarbide, low-k material, other suitable metal oxides, or combinations thereof. In some embodiments, the inner spacer layer can be conformally deposited over the top surface of the gate top hard mask 218, the top surface and sidewalls of the first gate spacer layer 222, the top surface and sidewalls of the second gate spacer layer 222', and the portion of the substrate 202 exposed in the first source / drain trench 227 and the second source / drain trench 227'. Subsequently, the deposited inner spacer layer can be etched back to form the inner spacer 230 in the inner spacer recess 228. In the etch-back process, the inner spacer layer outside the inner spacer groove 228 is removed.

[0033] refer to Figure 1B and Fig.15 The method 100 includes a block 118 in which an epitaxial source / drain feature 232 is formed in the first source / drain trench 227 and the second source / drain trench 227'. Since the formation of the epitaxial source / drain feature 232 on the entire workpiece 200 is substantially the same, Fig.1520 . The formation of epitaxial source / drain features 232 in the first region 10 and the second region 20 is shown together in FIG. Although not shown separately in the figures of the present invention, the epitaxial source / drain features 232 may include n-type epitaxial source / drain features for n-type devices and p-type epitaxial source / drain features for p-type devices. In some embodiments, in the above or subsequent processes, n-type epitaxial source / drain features of n-type devices in the workpiece 200 may be formed together, and p-type epitaxial source / drain features of p-type devices in the workpiece 200 may be formed together. The epitaxial source / drain features 232 may be formed using a suitable epitaxial process, such as CVD deposition techniques (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. Exemplary n-type epitaxial source / drain features may include Si, GaAs, GaAsP, SiP, or other suitable materials. The n-type epitaxial source / drain components may be in-situ doped during the epitaxial process by introducing a doping substance including an n-type dopant such as phosphorus or arsenic and / or other suitable dopants (including combinations thereof). If the n-type epitaxial source / drain components are not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the n-type epitaxial source / drain components. Exemplary p-type epitaxial source / drain components may include Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or other suitable materials. The p-type epitaxial source / drain components may be in-situ doped during the epitaxial process by introducing a doping substance including a p-type dopant (such as boron or BF2) and / or other suitable dopants (including combinations thereof). If the p-type epitaxial source / drain components are not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the p-type epitaxial source / drain components.

[0034] refer to Figure 1B and Fig.16 The method 100 includes block 120, where an interlayer dielectric (ILD) layer 236 is formed over the epitaxial source / drain features 232. Since the formation of the ILD layer 236 is substantially the same across the workpiece 200, Fig.162 shows the formation of the ILD layer 236 in the first region 10 and the second region 20 together. In some embodiments, a contact etch stop layer (CESL) 234 is first deposited on the epitaxial source / drain features 232. In some examples, the CESL 234 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL 234 can be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. Then, the ILD layer 236 is deposited over the CESL 234. In some embodiments, the ILD layer 236 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or a doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boro-doped silicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 236 can be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 236, the workpiece 200 may be annealed to improve the integrity of the ILD layer 236. After deposition and annealing of the ILD layer 236, the workpiece 200 is planarized by, for example, a chemical mechanical polishing (CMP) process to form a flush top surface for further processing.

[0035] refer to Figure 1B and Fig.17 The method 100 includes block 122, where the dummy gate stack 220 is removed to form a gate trench 238. Since the removal of the dummy gate stack 220 is substantially the same across the workpiece 200, Fig.17 20. The removal of the dummy gate stack 220 in the first region 10 and the second region 20 is shown together in FIG. In the embodiment shown, the etching process completely removes the dummy gate stack 220 to expose the sacrificial layer 206 and the channel layer 208 in the channel region 30. The etching process may be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. The etching process may be selected so that the etching process is selective to the dummy gate stack 220 and does not substantially etch the CESL 234 and the ILD layer 236. Fig.17 In some embodiments shown, the dummy gate stack 220 and the dummy dielectric layer 214 are removed from the channel region 30 to expose the sacrificial region 206 and the channel layer 208 in the channel region 30 .

[0036] refer to Figure 1B and Fig.18 , the method 100 includes block 124, where the second semiconductor layer 208 in the channel region of the fin element 211 is released to form a channel member 239. Since the release of the second semiconductor layer 208 is substantially the same across the workpiece 200, Fig.1820. The release of the second semiconductor layer 208 in the first region 10 and the second region 20 is shown together. In the illustrated embodiment, the etching process selectively etches the first semiconductor layer 206 (i.e., the sacrificial layer 206) in the following manner: the second semiconductor layer 208 (i.e., the channel layer 208) is etched minimally or not, and in some embodiments, the first gate spacer layer 222, the second gate spacer layer 222' and / or the inner spacer 230 are etched minimally or not. Various etching parameters can be adjusted to achieve selective etching of the first semiconductor layer 206, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. For example, an etchant is selected for the etching process that etches the material of the first semiconductor layer 206 (in the illustrated embodiment, silicon) at a higher rate than the material of the second semiconductor layer 208 (in the illustrated embodiment, silicon) (i.e., the etchant has a high etching selectivity relative to the material of the first semiconductor layer 206). The etching process may be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, a dry etching process (such as an RIE process) utilizes a fluorine-containing gas (e.g., SF6) to selectively etch the first semiconductor layer 206 (i.e., the sacrificial layer 206). In some embodiments, the ratio of the fluorine-containing gas to the oxygen-containing gas (e.g., O2 or O3), the etching temperature, and / or the RF power may be adjusted to selectively etch silicon germanium or silicon. In some embodiments, a wet etching process utilizes an etching solution including ammonium hydroxide (NH4OH) and water (H2O) to selectively etch the first semiconductor layer 206 (i.e., the sacrificial layer 206). In some embodiments, a chemical vapor etching process using hydrochloric acid (HCl) selectively etches the first semiconductor layer 206 (i.e., the sacrificial layer 206). At the end of the operation at box 124, the channel layer 208 in the channel region 30 becomes suspended and may be referred to as a channel member 239. As will be described below in conjunction with Fig.22A and Fig. 22B Described in more detail, since the first gate spacer layer 222 in the first region 10 is thicker, the channel lengths of the channel members 239 in the first region 10 along the X direction may be greater than those in the second region 20 .

[0037] refer to Figure 1C and Fig.19 The method 100 includes a block 126 in which a gate dielectric layer 242 is formed around the channel member 239. Since the formation of the gate dielectric layer 242 is substantially the same across the workpiece 200, Fig.19, the formation of a gate dielectric layer 242 in the first region 10 and the second region 20 is shown together. In some embodiments, an interfacial layer 240 can be formed on the channel member 239 to provide adhesion between the channel member 239 and the gate dielectric layer 242. In some embodiments, the interfacial layer 240 may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer 240 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer 242 is deposited over and around the channel member 239 and may include one or more high-k dielectric materials. As used and described herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, which is, for example, greater than the dielectric constant of thermally oxidized silicon. Exemplary high-k dielectric materials for the gate dielectric layer 242 may include TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), other high-k dielectric materials, or combinations thereof. The gate dielectric layer 242 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0038] refer to Figure 1C and Fig. 20 The method 100 includes a block 128 in which a metal gate stack 244 is formed. Since the formation of the metal gate stack 244 is substantially the same across the workpiece 200, Fig. 20The formation of the metal gate stack 244 in the first region 10 and the second region 20 is shown together. Although not shown separately, the metal gate stack 244 may include one or more work function layers and one or more metal fill layers. In some embodiments, different work function layer stacks may be formed in the n-type device region and the p-type device region. In those embodiments, although the n-type device region and the p-type device region may share certain common work function layers, the n-type device region may include one or more work function layers that are not present in the p-type device region. Similarly, in optional embodiments, the p-type device region may include one or more work function layers that are not present in the n-type device region. The p-type work function layer includes any suitable p-type work function material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function materials, or combinations thereof. The N-type work function layer includes any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function materials, or combinations thereof. Note that the p-type work function layer is not limited to use in the p-type device region, and the n-type work function layer is not limited to use in the n-type device region. The p-type work function layer and the n-type work function layer can be applied in the n-type device region and the p-type device region to achieve the desired threshold voltage. In some embodiments, the metal gate stack 244 may include one or more metal fill layers. For example, a CVD process or a PVD process deposits one or more metal fill layers on the n-type work function layer and the p-type work function layer so that the metal fill layer fills any remaining portion of the gate trench 238. The metal fill layer may include a suitable conductive material, such as Al, W, and / or Cu. The metal fill layer may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof.

[0039] refer to Figure 1C and Fig.21 , the method 100 includes a block 130, in which the workpiece 200 is planarized to provide a flush surface. Since the planarization at block 130 is substantially the same across the workpiece 200, Fig.21 2 and 3 , planarization in the first region 10 and the second region 20 is shown together. In some embodiments, planarization is performed to remove excess interface layer 240, gate dielectric layer 242, and metal gate stack 244 on workpiece 200. For example, planarization may include a CMP process and may be performed until the top surface of ILD layer 236 is substantially planar with the top surface of metal gate stack 244.

[0040] Reference now Fig.22A and Fig. 22BAt the end of the operation at block 130, Fig.22A The first GAA transistor 250 shown may be formed in the first region 10 of the semiconductor device 200, and Fig. 22B The second GAA transistor 260 shown may be formed in the second region 20 of the semiconductor device 200. Fig.22A As shown, the first gate spacer layer 222 having a larger first thickness T1 produces a first channel member 239-1 having a first width W1 along the X direction. Due to the thicker first gate spacer layer 222, each metal gate stack 244 in the first region 10 includes a first gate top component 244A and a first lower gate component 244B disposed on the topmost channel member 239-1, and each first lower gate component 244B is sandwiched / disposed between two adjacent channel members 239-1. The first gate top component 244A includes a first gate length L1, and each first lower gate component 244B includes a second gate length L2. The epitaxial source / drain features 232 in the first region 10 have a second width W2. Because the dummy gate pitch P is uniform across the workpiece 200, P is equal to the sum of the first width W1 and the second width W2 in the first region 10. In some embodiments, P is between about 30 nm and about 60 nm; W1 is between about 16 nm and about 46 nm; W2 is between about 9 nm and about 40 nm; L1 is between about 5 nm and about 20 nm; and L2 is between about 6 nm and about 30 nm. Fig. 22B As shown, the second gate spacer layer 222' having a smaller second thickness T2 produces a second channel member 239-2 having a third width W3 along the X direction. Each metal gate stack 244 in the second region 20 includes a second gate top component 244C and a second lower gate component 244D disposed on the topmost channel member 239-2, and each second lower gate component 244D is sandwiched / disposed between two adjacent channel members 239-2. The second gate top component 244C includes a third gate length L3, and each second lower gate component 244D includes a fourth gate length L4. The epitaxial source / drain component 232 in the second region 20 has a fourth width W4. Because the pseudo gate pitch P is uniform across the workpiece 200, P is equal to the sum of the third width W3 and the fourth width W4 in the second region 20. In some embodiments, P is between about 30 nm and about 60 nm; W3 is between about 15 nm and about 45 nm; W4 is between about 10 nm and about 40 nm; L3 is between about 5 nm and about 20 nm; and L4 is between about 5 nm and about 20 nm. Fig. 22B In the illustrated embodiment, the third gate length L3 is substantially the same as the fourth gate length L4.

[0041] It can be seen that, except for the first gate top component 244A, the first GAA transistor 250 is characterized by a second gate length L2. The second GAA transistor 260 is characterized by a third gate length L3. Fig.22A and Fig. 22B In the illustrated embodiment, the second gate length L2 may be greater than the third gate length L3, and their difference is between about 1 nm and about 10 nm. It has been observed that the leakage current of the GAA transistor may decrease with the gate length, and the threshold voltage of the GAA transistor may increase with the leakage current of the GAA transistor. Since the second gate length L2 of the first GAA transistor 250 is greater than the third gate length L3 of the second GAA transistor 260, the first GAA transistor 250 has a lower leakage current and a higher threshold voltage than the second GAA transistor 260. In some cases, the first GAA transistor 250 has a first threshold voltage (VT1), and the second GAA transistor 260 has a second threshold voltage (VT2). By adopting the first GAA transistor 250 in the first region 10 and the second GAA transistor 260 in the second region 20, the semiconductor device 200 according to the present invention may include GAA transistors having different threshold voltages-a first threshold voltage (VT1) and a second threshold voltage (VT2).

[0042] refer to Figure 1C , method 100 includes box 132, in which further processes are performed. Manufacturing can continue to continue manufacturing semiconductor device 200. For example, various contacts can be formed to facilitate operation of the GAA transistor in semiconductor device 200. For example, one or more ILD layers and / or CESL layers similar to ILD layer 236 can be formed above substrate 202 (specifically above ILD layer 236 and metal gate stack 244). Contacts can then be formed in ILD layer 236 and / or an ILD layer disposed above ILD layer 236. For example, the contacts are electrically and / or physically coupled to the metal gate stack 244, respectively, and the contacts are electrically and / or physically coupled to the source / drain regions of the GAA transistor, respectively. Because the epitaxial source / drain features 232 in the first region 10 are narrower than those in the second region 20 (along the X direction, as shown in FIG. 2 ), the epitaxial source / drain features 232 in the first region 10 are narrower than those in the second region 20 (along the X direction, as shown in FIG. 2 ). Fig.22A and Fig. 22BAs shown), the source / drain contacts of the first GAA transistor 250 in the first region 10 can be narrower than the source / drain contacts of the second GAA transistor 260 in the second region 20. The contacts include conductive materials such as aluminum, aluminum alloys (e.g., aluminum / silicon / copper alloys), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, other suitable metals, or combinations thereof. In some embodiments, a metal silicide layer can be formed at the interface between the epitaxial source / drain features 232 and the source / drain contacts. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, the ILD layer and contacts disposed above the ILD layer 236 (e.g., extending through the ILD layer 236 and / or other ILD layers) are part of a multi-layer interconnect (MLI) structure.

[0043] In one exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes: a first plurality of all-around gate (GAA) devices, located in a first device region; and a second plurality of GAA devices, located in a second device region. Each of the first plurality of GAA devices includes: a first vertical stack of channel members, extending along a first direction; and a first gate structure, located above and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes: a second vertical stack of channel members, extending along a second direction; and a second gate structure, located above and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length, and each of the second plurality of GAA devices includes a second channel length that is less than the first channel length.

[0044] In some embodiments, each of the first gate structures includes: a first gate top component disposed above the topmost channel component of the first vertical stack of channel components; and a plurality of first lower gate components disposed between two adjacent channel components of the first vertical stack of channel components. Each of the second gate structures includes: a second gate top component disposed above the topmost channel component of the second vertical stack of channel components; and a plurality of second lower gate components disposed between two adjacent channel components of the second vertical stack of channel components. The first gate top component includes a first length along a first direction, the second gate top component includes a second length along a second direction, and the first length and the second length are substantially the same. In some embodiments, each of the plurality of first lower gate components includes a third length along the first direction, each of the plurality of second lower gate components includes a fourth length along the second direction, and the third length is greater than the fourth length. In some embodiments, the fourth length is substantially the same as the first length. In some embodiments, the third length is between about 6nm and about 30nm, and the fourth length is between about 5nm and about 20nm. In some embodiments, each of the first plurality of GAA devices further comprises a first gate spacer disposed along the first gate top component, and each of the second plurality of GAA devices further comprises a second gate spacer disposed along the second gate top component. In these embodiments, the first gate spacer comprises a first thickness, and the second gate spacer comprises a second thickness that is less than the first thickness. In some cases, the difference between the first thickness and the second thickness is between about 0.5 nm and about 5 nm. In some cases, the first plurality of GAA devices comprises a first gate pitch, and the second plurality of GAA devices comprises a second gate pitch that is the same as the first gate pitch. In some embodiments, each of the first plurality of GAA devices comprises a first source / drain component, each of the second plurality of GAA devices comprises a second source / drain component, and the thickness of the first source / drain component along the first direction is less than the thickness of the second source / drain component. In some embodiments, each of the first plurality of GAA devices comprises a first threshold voltage, and each of the second plurality of GAA devices comprises a second threshold voltage that is less than the first threshold voltage.

[0045] In another exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes: a first plurality of all-around gate (GAA) devices, located in a first device region; and a second plurality of GAA devices, located in a second device region. Each of the plurality of first GAA devices includes a first vertical stack of channel members, extending along a first direction; a first gate top component, disposed above the topmost channel member of the first vertical stack of channel members; and a plurality of first lower gate components, disposed between two adjacent channel members of the first vertical stack of channel members. Each of the second plurality of GAA devices includes: a second vertical stack of channel members, extending along a second direction; a second gate top component, disposed above the topmost channel member of the second vertical stack of channel members; and a plurality of second lower gate components, disposed between two adjacent channel members of the second vertical stack of channel members. The first gate top component includes a first length along the first direction, and the second gate top component includes a second length along the second direction, wherein the first length and the second length are substantially the same. In some embodiments, each of the plurality of first lower gate components includes a third length along the first direction, and each of the plurality of second lower gate components includes a fourth length along the second direction. The third length is greater than the fourth length.

[0046] In some embodiments, the fourth length is substantially the same as the first length. In some embodiments, each of the first plurality of GAA devices further comprises a first gate spacer disposed along the first gate top component, and each of the second plurality of GAA devices further comprises a second gate spacer disposed along the second gate top component. The first gate spacer comprises a first thickness, and the second gate spacer comprises a second thickness less than the first thickness. In some embodiments. The first plurality of GAA devices comprises a first gate pitch, and the second plurality of GAA devices comprises a second gate pitch that is the same as the first gate pitch. In some embodiments, each of the first plurality of GAA devices comprises a first source / drain component, each of the second plurality of GAA devices comprises a second source / drain component, and the thickness of the first source / drain component along the first direction is less than the thickness of the second source / drain component.

[0047] In yet another exemplary aspect, the present invention is directed to a method of manufacturing a semiconductor device. The method includes forming a layer stack including a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers on a substrate, forming a first plurality of fin elements from the layer stack in a first region of the substrate, forming a second plurality of fin elements from the layer stack in a second region of the substrate, forming a first plurality of dummy gate stacks over the first plurality of fin elements, forming a second plurality of dummy gate stacks over the second plurality of fin elements, depositing a spacer layer over the first plurality of dummy gate stacks and the second plurality of dummy gate stacks, selectively depositing a polymer layer over the spacer layer disposed over the first plurality of dummy gate stacks, while the spacer layer is disposed over the second plurality of dummy gate stacks not covered by the polymer layer, and etching the spacer layer over the first plurality of dummy gate stacks and the second plurality of dummy gate stacks.

[0048] In some embodiments, the polymer layer includes carbon and fluorine. In some embodiments, the etching of the spacer layer includes forming a first spacer layer above the first plurality of dummy gate stacks, and forming a second spacer layer above the second plurality of dummy gate stacks. The first spacer layer includes a first thickness, and the second spacer layer includes a second thickness. The first thickness is greater than the second thickness. In some cases, the difference between the first thickness and the second thickness is between 0.5nm and approximately 5nm. In some embodiments, the method may also include forming a first plurality of source / drain trenches in the first region to expose sidewalls of the first plurality of fin elements, forming a second plurality of source / drain trenches in the second region to expose sidewalls of the second plurality of fin elements, and partially etching a plurality of second semiconductor layers in the first plurality of fin elements and the second plurality of fin elements to form internal spacer grooves.

[0049] The present invention summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that this equivalent configuration is not directed away from the spirit and scope of the present invention, and in the case of not directed away from the spirit and scope of the present invention, they can make multiple changes, replacements and changes herein.

Claims

1. A semiconductor device, comprising: A first plurality of all-around gate devices are located in a first device region, wherein each of the first plurality of all-around gate devices comprises: a first vertical stack of channel members, each channel member of the first vertical stack of channel members extending lengthwise along a first direction, and a first gate structure over and around a first vertical stack of channel members, wherein the first gate structure includes a first gate top component disposed over a topmost channel member of the first vertical stack of channel members; and A second plurality of all-around gate devices are located in the second device region, wherein each of the second plurality of all-around gate devices comprises: a second vertical stack of channel members, each channel member of the second vertical stack of channel members extending lengthwise along the first direction, and a second gate structure over and around a second vertical stack of channel members, wherein the second gate structure includes a second gate top component disposed over a topmost channel member of the second vertical stack of channel members, wherein each of the first plurality of all-around gate devices comprises a first channel length, wherein each of the second plurality of all-around gate devices comprises a second channel length that is less than the first channel length, Each of the first plurality of all-around gate devices further comprises a first gate spacer disposed along the first gate top component, and each of the second plurality of all-around gate devices further comprises a second gate spacer disposed along the second gate top component, wherein the first gate spacer comprises a first thickness measured at a height along the first direction, wherein the second gate spacer comprises a second thickness measured at the height along the first direction, and the second thickness is less than the first thickness, Wherein, each of the first gate structures further comprises: a plurality of first lower gate components disposed between two adjacent channel members of the first vertical stack of channel members, Wherein, each of the second gate structures further comprises: a plurality of second lower gate components disposed between two adjacent channel members of the second vertical stack of channel members, wherein each of the plurality of first lower gate components comprises a third length along the first direction, and each of the plurality of second lower gate components comprises a fourth length along the first direction, The third length is greater than the fourth length, and a pitch between adjacent full-all-around gate devices in the first plurality of full-all-around gate devices is equal to a pitch between adjacent full-all-around gate devices in the second plurality of full-all-around gate devices.

2. The semiconductor device according to claim 1, in, The first gate top component comprises a first length along the first direction, wherein the second gate top component comprises a second length along the first direction, The first length and the second length are the same.

3. The semiconductor device according to claim 2, in, The pitch is between 30 nm and 60 nm.

4. The semiconductor device according to claim 3, wherein: The fourth length is the same as the first length.

5. The semiconductor device according to claim 3, in, The third length is between 6 nm and 30 nm, Wherein, the fourth length is between 5 nm and 20 nm.

6. The semiconductor device according to claim 1, in, Each of the first plurality of gate-all-around devices further comprises a first plurality of internal spacer features interleaved with the first vertical stack of channel members, each of the second plurality of gate-all-around devices further comprises a second plurality of internal spacer features interleaved with the second vertical stack of channel members, Wherein a thickness of the first plurality of inner spacer components along the first direction is the same as a thickness of the second plurality of inner spacer components along the first direction.

7. The semiconductor device according to claim 6, wherein: A difference between the first thickness and the second thickness is between 0.5 nm and 5 nm.

8. The semiconductor device according to claim 1, in, The first plurality of gate-all-around devices comprises a first gate pitch, The second plurality of all-around gate devices include a second gate pitch that is the same as the first gate pitch.

9. The semiconductor device according to claim 1, in, Each of the first plurality of gate-all-around devices comprises a first source / drain feature, wherein each of the second plurality of all-around gate devices comprises a second source / drain feature, Wherein, a thickness of the first source / drain component along the first direction is smaller than a thickness of the second source / drain component.

10. The semiconductor device according to claim 1, in, Each of the first plurality of gate-all-around devices comprises a first threshold voltage, Wherein, each of the second plurality of gate-all-around devices comprises a second threshold voltage that is less than the first threshold voltage.

11. A semiconductor device comprising: A first plurality of all-around gate devices are located in a first device region, wherein each of the first plurality of all-around gate devices comprises: a first vertical stack of channel members, each channel member of the first vertical stack of channel members extending lengthwise along a first direction, a first gate top member disposed above a topmost channel member of a first vertical stack of channel members, and a plurality of first lower gate features disposed between two adjacent channel members of a first vertical stack of channel members; and A second plurality of all-around gate devices are located in the second device region, wherein each of the second plurality of all-around gate devices comprises: a second vertical stack of channel members, each channel member of the second vertical stack of channel members extending lengthwise along the first direction, a second gate top member disposed above a topmost channel member of a second vertical stack of channel members, and a plurality of second lower gate components disposed between two adjacent channel members of the second vertical stack of channel members, wherein the first gate top component comprises a first length along the first direction, wherein the second gate top component comprises a second length along the first direction, wherein the first length and the second length are the same, wherein each of the plurality of first lower gate components comprises a third length along the first direction, wherein each of the plurality of second lower gate components comprises a fourth length along the first direction, wherein the third length is greater than the fourth length, Each of the first plurality of all-around gate devices further comprises a first gate spacer disposed along the first gate top component, and each of the second plurality of all-around gate devices further comprises a second gate spacer disposed along the second gate top component, wherein the first gate spacer comprises a first thickness measured at a height along the first direction, wherein the second gate spacer comprises a second thickness measured at the height along the first direction, and the second thickness is less than the first thickness, Wherein, a pitch between adjacent full-all-around gate devices in the first plurality of full-all-around gate devices is equal to a pitch between adjacent full-all-around gate devices in the second plurality of full-all-around gate devices.

12. The semiconductor device according to claim 11, wherein The fourth length is the same as the first length.

13. The semiconductor device according to claim 11, wherein The first length is between 5 nm and 20 nm, and the third length is between 6 nm and 30 nm.

14. The semiconductor device according to claim 11, in, The first plurality of gate-all-around devices comprises a first gate pitch, The second plurality of all-around gate devices include a second gate pitch that is the same as the first gate pitch.

15. The semiconductor device according to claim 11, in, Each of the first plurality of gate-all-around devices comprises a first source / drain feature, wherein each of the second plurality of all-around gate devices comprises a second source / drain feature, Wherein, a thickness of the first source / drain component along the first direction is smaller than a thickness of the second source / drain component.

16. A method for manufacturing a semiconductor device, comprising: forming a layer stack including a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers on a substrate; forming a first plurality of fin elements extending lengthwise along a first direction from the layer stack in a first region of the substrate; forming a second plurality of fin elements extending lengthwise along the first direction from the layer stack in a second region of the substrate; forming a first plurality of dummy gate stacks over the first plurality of fin elements; forming a second plurality of dummy gate stacks over the second plurality of fin elements; depositing a spacer layer over the first plurality of dummy gate stacks and the second plurality of dummy gate stacks; selectively depositing a polymer layer over the spacer layer disposed over the first plurality of dummy gate stacks while the spacer layer is disposed over the second plurality of dummy gate stacks not covered by the polymer layer; as well as Etching the spacer layer over the first plurality of dummy gate stacks and the second plurality of dummy gate stacks, wherein the etching of the spacer layer comprises: forming a first spacer layer over the first plurality of dummy gate stacks; and forming a second spacer layer over the second plurality of dummy gate stacks, wherein the first spacer layer comprises a first thickness measured at a height along the first direction, and the second spacer layer comprises a second thickness measured at the height along the first direction, wherein the first thickness is greater than the second thickness; removing the first plurality of dummy gate stacks and the second plurality of dummy gate stacks; releasing the plurality of first semiconductor layers in the channel regions of the first plurality of fin elements to form a plurality of first channel components, and releasing the plurality of first semiconductor layers in the channel regions of the second plurality of fin elements to form a plurality of second channel components; forming a first gate structure over and around each of the plurality of first channel members, forming a second gate structure over and around each of the plurality of second channel members, wherein the first gate structure further comprises a plurality of first lower gate components disposed between two adjacent channel components of each of the plurality of first channel components, wherein the second gate structure further comprises a plurality of second lower gate components disposed between two adjacent channel components of each of the plurality of second channel components, wherein a length of each of the plurality of first lower gate components along the first direction is greater than a length of each of the plurality of second lower gate components along the first direction, Wherein, a pitch between adjacent gate structures of the first gate structure is equal to a pitch between adjacent gate structures of the second gate structure.

17. The method according to claim 16, wherein: The polymer layer includes carbon and fluorine.

18. The method according to claim 16, wherein: The polymer layer is deposited using a chemical vapor deposition or spin coating process.

19. The method according to claim 16, wherein: A difference between the first thickness and the second thickness is between 0.5 nm and 5 nm.

20. The method of claim 16, further comprising: forming a first plurality of source / drain trenches in the first region to expose sidewalls of the first plurality of fin elements; forming a second plurality of source / drain trenches in the second region to expose sidewalls of the second plurality of fin elements; as well as The plurality of second semiconductor layers in the first plurality of fin elements and the second plurality of fin elements are partially etched to form inner spacer recesses.

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