Semiconductor device and method of forming the same

Abstract

A semiconductor device includes: a first multi-gate field-effect transistor (FET) disposed above a substrate, the first multi-gate FET including a first active region; and a second multi-gate FET disposed above the first multi-gate FET, the second multi-gate FET including a second active region. The first and second active regions are not fully projected along a vertical direction perpendicular to the substrate. Embodiments of the present invention also provide a method for forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming the same. Background Technology

[0002] As the semiconductor industry relentlessly pursues higher device density, higher performance, and lower costs, challenges arising from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field-effect transistors (FETs), including FinFETs and gate-all-around (GAA) FETs. In a typical FinFET, the gate electrode is located adjacent to the three sides of the channel region, with a gate dielectric layer interposed in between. Complementary FETs (CFETs) typically consist of a bottom FET disposed above the substrate and a top FET disposed above the bottom FET. The gate structure, including the gate dielectric layer and the gate electrode layer, is typically formed around the channel regions of the bottom and top FETs. Typically, the bottom FET is a first conductivity type (e.g., n-type) FET, while the top FET is a second conductivity type (e.g., p-type) different from the first conductivity type, and vice versa. Summary of the Invention

[0003] According to one aspect of the present invention, a semiconductor device is provided, comprising: a first multi-gate field-effect transistor (FET) disposed above a substrate, the first multi-gate field-effect transistor including a first active region extending on a first horizontal plane; and a second multi-gate field-effect transistor disposed above the first multi-gate field-effect transistor, the second multi-gate field-effect transistor including a second active region extending on a second horizontal plane parallel to the first horizontal plane; wherein, when viewed from a vertical direction perpendicular to the first horizontal plane, the first active region and the second active region do not completely overlap.

[0004] According to another aspect of the present invention, a semiconductor device is provided, comprising: a substrate; a first multi-gate field-effect transistor disposed above the substrate, the first multi-gate field-effect transistor including a first active region extending on a first horizontal plane parallel to the substrate and having a first projection of the first active region on the substrate; and a second multi-gate field-effect transistor disposed above the first multi-gate field-effect transistor, the second multi-gate field-effect transistor including a second active region extending on a second horizontal plane parallel to the substrate and having a second projection of the second active region on the substrate; wherein the first projection and the second projection do not completely overlap.

[0005] According to another aspect of the present invention, a method for forming a semiconductor device is provided, comprising: forming a first multi-gate field-effect transistor disposed above a substrate, the first multi-gate field-effect transistor including a first active region extending on a first horizontal plane; and forming a second multi-gate field-effect transistor disposed above the first multi-gate field-effect transistor, the second multi-gate field-effect transistor including a second active region extending on a second horizontal plane parallel to the first horizontal plane; wherein, when viewed from a vertical direction perpendicular to the first horizontal plane, the first active region and the second active region do not completely overlap. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1A This is a perspective view illustrating an example of a CFET according to some embodiments;

[0008] Figure 1B It is shown according to some embodiments Figure 1A The cross-sectional view of the example CFET is shown below;

[0009] Figure 1C It is shown according to some embodiments Figure 1A Another cross-sectional view of the example CFET shown;

[0010] Figure 2 This is a layout diagram illustrating an example of a CFET according to some embodiments;

[0011] Figure 3A This is a perspective view illustrating an example of a CFET according to some embodiments;

[0012] Figure 3B It is shown according to some embodiments Figure 3A The cross-sectional view of the example CFET is shown below;

[0013] Figure 4 This is a flowchart illustrating an example of a method for forming a CFET according to some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0015] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] As transistor sizes shrink, wiring congestion can become a challenge. Specifically, the bottom FET in a complementary FET (CFET) has fewer wiring paths compared to the top FET. Poor internal wiring capabilities can result in a larger chip area.

[0017] This invention discloses an example CFET with partially overlapping active regions when viewed from above. Specifically, when viewed from above, the top active region of the top FET and the bottom active region of the bottom FET do not completely overlap. Because the active region of the bottom FET is not completely covered by the active region of the top FET when viewed from above, more wiring flexibility can be created for the bottom FET. Thus, the example CFET can improve internal wiring capability and potentially reduce chip area.

[0018] Figure 1A , Figure 1B ,and Figure 1C An example of a CFET100 according to some embodiments is shown. Specifically, Figure 1A This is a perspective view showing a portion of the example CFET100. Figure 1B It corresponds to Figure 1A A cross-sectional view of line X1-X1. Figure 1C It corresponds to Figure 1A A cross-sectional view of line X2-X2.

[0019] like Figure 1A As shown, example CFET100 includes at least a bottom FET110 and a top FET120. In some embodiments, the bottom FET110 is a bottom multi-gate FET. In some embodiments, the top FET120 is a top multi-gate FET. In some embodiments, both the bottom FET110 and the top FET120 are FinFETs. In some embodiments, both the bottom FET110 and the top FET120 are GAAFETs.

[0020] The bottom FET110 is located on the substrate 190 ( Figure 1B Above (shown). The bottom FET 110 includes at least a first active region 111, two metal contact regions 112, and a gate region (i.e., a polysilicon region) 113. For example, the bottom FET 110 may include, among other things, a first active region 111, metal contact regions 112a, metal contact regions 112b, and a gate region 113a. In this embodiment, the first active region 111 is disposed on a first horizontal plane 101. The first horizontal plane 101 is located in an XY plane perpendicular to the vertical direction (Z). The first active region 111 may define an active region in which a transistor can be constructed. In this embodiment, the first active region 111 is a first conductivity type (e.g., n-type). It should be noted that the first active region 111 may be a second conductivity type (e.g., p-type). In this embodiment, metal contact regions 112a and 112b are disposed above the first active region 111. One of the metal contact regions 112a and 112b can be used as the source of the bottom FET 110, and the other can be used as the drain of the bottom FET 110. In one example, metal contact region 112a can be used as the source of the bottom FET 110, and metal contact region 112b can be used as the drain of the bottom FET 110. Source and drain contacts can be further disposed above metal contact regions 112a and 112b to form the source and drain terminals of the bottom FET 110. In this embodiment, gate region 113a is located between metal contact regions 112a and 112b. Gate region 113a is adjacent to a plurality (e.g., three or four) sides of the first active region 111. Gate region 113a can be used as the gate of the bottom FET 110. Gate electrode can be further disposed around gate region 113a to form the gate terminal of the bottom FET 110. It should be noted that the bottom FET 110 may include another combination of components. For example, the bottom FET 110 may include, among other things, a first active region 111, a metal contact region 112b, a metal contact region 112c, and a gate region 113b.

[0021] On the other hand, the top FET 120 is disposed above the bottom FET 110. The top FET 120 includes at least a second active region 121, two metal contact regions 122, and a gate region (i.e., a polysilicon region) 123. For example, the top FET 120 may include, among other things, a second active region 121, metal contact regions 122a, metal contact regions 122b, and a gate region 123a. In this embodiment, the second active region 121 is disposed on a second horizontal plane 102. The second horizontal plane 102 is located in an XY plane perpendicular to the vertical direction (Z). The second horizontal plane 102 is located above the first horizontal plane 101. The second active region 121 may define an active region in which a transistor can be constructed. In this embodiment, the second active region 121 is a second conductivity type (e.g., p-type). It should be noted that the second active region 121 may be a first conductivity type (e.g., n-type). In this embodiment, metal contact regions 122a and 122b are disposed above the second active region 121. One of the metal contact regions 122a and 122b can be used as the source of the top FET 120, and the other can be used as the drain of the top FET 120. In one example, metal contact region 122a can be used as the source of the top FET 120, and metal contact region 122b can be used as the drain of the top FET 120. Source and drain contacts can be further disposed above metal contact regions 122a and 122b to form the source and drain terminals of the top FET 120. In this embodiment, gate region 123a is located between metal contact regions 122a and 122b. Gate region 123a is adjacent to multiple (e.g., three or four) sides of the second active region 121. Gate region 123a can be used as the gate of the top FET 120. It should be noted that in this embodiment, gate region 123a and gate region 113a can be identical. In other words, gate regions 113a / 123a are connected rather than separated. A gate electrode may be further disposed around gate region 123a to form the gate terminal of top FET 120. It should be noted that top FET 120 may include another combination of components. For example, top FET 120 may include, among other things, a second active region 121, a metal contact region 122b, a metal contact region 122c, and a gate region 123b. It should be noted that in this embodiment, gate region 123b and gate region 123a may be identical. In other words, gate regions 113b / 123b are connected rather than separated.

[0022] like Figure 1A As shown, multiple wires 131 are disposed above the top FET 120. Multiple wires 131 are disposed on a third horizontal plane 103. The third horizontal plane 103 is located in an XY plane perpendicular to the vertical direction (Z). The third horizontal plane 103 is located above the second horizontal plane 102.

[0023] In some embodiments, the multiple conductors 131 are metal traces 131, collectively referred to as metal zero (MO) layers. It should be noted that different numbers of metal traces 131 can be used as needed, as can various arrangements of the metal traces 131. The metal traces 131 can be used to electrically connect different terminals of the bottom FET 110 and the top FET 120 as needed. For example, one of the metal traces 131 can be electrically connected to the drain terminal of the bottom FET 110 (e.g., disposed above the metal contact area 112b).

[0024] like Figure 1A As shown, for example, when viewed from the vertical direction (Z), that is, when viewed from above, the first active region 111 and the second active region 121 do not completely overlap. In other words, the projection of the second active region 121 onto the first horizontal plane 101 does not completely overlap with the first active region 111. Figure 1A In the example shown, the second active region 121 has a projection 121' on the first horizontal plane 101. The projection 121' of the second active region 121 does not completely overlap with the first active region 111. In some embodiments, the projection 121' of the second active region 121 partially overlaps with the first active region 111. In some embodiments, the projection 121' of the second active region 121 does not overlap with the first active region 111 at all. In some embodiments, the area of ​​the first active region 111 is larger than the area of ​​the second active region 121. In some embodiments, the area of ​​the first active region 111 is equal to the area of ​​the second active region 121. In an embodiment, the area of ​​the first active region 111 is smaller than the area of ​​the second active region 121.

[0025] Figure 1B and Figure 1C The cross-sectional view further shows Figure 1A The example CFET100 is shown. (As shown) Figure 1B As shown in the cross-sectional view, the first active region 111 of the bottom FET 110 is disposed above the substrate 190 and on a first horizontal plane 101. The second active region 121 of the top FET 120 is disposed on a second horizontal plane 102 above the first horizontal plane 101. Multiple conductors 131 (e.g., multiple metal traces 131) are disposed on a third plane 103 above the second horizontal plane 102. The second active region 121 has a projection 121' on the first horizontal plane 101. When viewed along the X direction, for example from above, the projection 121' of the second active region 121 on the first horizontal plane 101 does not completely overlap with the first active region 111. Along the vertical direction (Z), the second active region 121 is not located between at least a portion of the first active region 111 (in this example, the entire first active region 111) and the multiple conductors 131. This allows for greater wiring flexibility for the bottom FET 110.

[0026] like Figure 1C As shown in the cross-sectional view, in the first horizontal plane 101, the bottom FET 110 may include, among other things, a first active region 111 and gate regions 113a adjacent to at least two sides of the first active region 111. A second active region 121 has a projection 121' on the first horizontal plane 101. The projection 121' of the second active region 121 on the first horizontal plane 101 does not completely overlap with the first active region 111. This allows for greater wiring flexibility for the bottom FET 110, as explained above.

[0027] Figure 2 An example layout of the CFET200 according to some embodiments is shown. Figure 2 This is a top view of example CFET 200. As shown, example CFET 200 includes at least a bottom FET 210 and a top FET 220. The bottom FET 210 is disposed above a substrate (not shown for clarity). The bottom FET 210 includes at least a first active region 211, two metal contact regions 212, and a gate region (i.e., a polysilicon region) 213c. In this embodiment, the first active region 211 is disposed on a first horizontal plane. The first horizontal plane is located in an XY plane perpendicular to the vertical direction (Z). The first active region 211 may define an active region in which a transistor can be constructed. In this embodiment, the first active region 211 is a first conductivity type (e.g., n-type). It should be noted that in other examples, the first active region 211 may be a second conductivity type (e.g., p-type). In this embodiment, metal contact regions 212a and 212b are disposed above the first active region 211. One of the metal contact regions 212a and 212b can be used as the source of the bottom FET 210, and the other can be used as the drain of the bottom FET 210. In one example, metal contact region 212a can be used as the source of the bottom FET 210, and metal contact region 212b can be used as the drain of the bottom FET 210. Source and drain contacts can be further disposed above metal contact regions 212a and 212b to form the source and drain terminals of the bottom FET 210. In this embodiment, gate region 213c is located between metal contact regions 212a and 212b. Gate region 213c is adjacent to a plurality (e.g., three or four) sides of the first active region 211. Gate region 213c can be used as the gate of the bottom FET 210. Gate electrode can be further disposed around gate region 213c to form the gate terminal of the bottom FET 210. It should be noted that other gate regions 213a, 213b, 213d, and 213e are parallel to gate region 213c and can be used as gates for other semiconductor devices (e.g., other CFETs) not shown for clarity.

[0028] On the other hand, the top FET 220 is disposed above the bottom FET 210. The top FET 220 includes at least a second active region 221, two metal contact regions 222, and a gate region (i.e., a polysilicon region) 223c. In this embodiment, the second active region 221 is disposed on a second horizontal plane. The second horizontal plane is located in an XY plane perpendicular to the vertical direction (Z). The second horizontal plane is located above the first horizontal plane. The second active region 221 may define an active region in which a transistor can be constructed. In this embodiment, the second active region 221 is a second conductivity type (e.g., p-type). It should be noted that in other examples, the second active region 221 may be a first conductivity type (e.g., n-type). In this embodiment, metal contact regions 222a and 222b are disposed above the second active region 221. One of the metal contact regions 222a and 222b may be used as the source of the top FET 220, and the other may be used as the drain of the top FET 220. In one example, metal contact region 222a can be used as the source of the top FET 220, while metal contact region 222b can be used as the drain of the top FET 220. Source and drain contacts can be further disposed above metal contact regions 222a and 222b to form the source and drain terminals of the top FET 220. In this embodiment, gate region 223c is located between metal contact regions 222a and 222b. Gate region 223c is adjacent to multiple (e.g., three or four) sides of the second active region 221. Gate region 223c can be used as the gate of the top FET 220. It should be noted that in this embodiment, gate region 223c and gate region 213c can be identical. In other words, gate regions 213c / 223c are connected rather than separated. A gate electrode can be further disposed around gate region 223c to form the gate terminal of the top FET 220.

[0029] Multiple conductors 231 are disposed above the top FET 220. Multiple conductors 231 are disposed on a third horizontal plane. The third horizontal plane lies in an XY plane perpendicular to the vertical direction (Z). The third horizontal plane is located above the second horizontal plane 102. In some embodiments, the multiple conductors 231 are metal traces 231, collectively referred to as the MO layer. It should be noted that different numbers of metal traces 231 can be used as needed, as can various arrangements of the metal traces 231. The metal traces 231 can be used to electrically connect to different terminals of the bottom FET 210 and the top FET 220 as needed. For example, metal trace 131 can be used to electrically connect to the drain terminal of the bottom FET 110 (e.g., disposed above the metal contact area 112b).

[0030] When viewed from the vertical direction (Z), the first active region 211 and the second active region 221 do not completely overlap. Specifically, when... Figure 2As shown, when viewed from above, the projection of the second active region 221 onto the first horizontal plane does not completely overlap with the first active region 211. The portion of the first active region 211 that does not overlap with the projection of the second active region 221 onto the first horizontal plane has a rectangular shape, with a length L1 along the X direction and a length L2 along the Y direction. Due to the non-overlapping portion, when viewed from the vertical direction (Z), the first active region 211 and the second active region 221 do not completely overlap. Therefore, when viewed from the vertical direction (Z), metal contact areas 212a and 222a do not completely overlap, and when viewed from the vertical direction (Z), metal contact areas 212b and 222b do not completely overlap.

[0031] Along the vertical direction (Z), the second active region 221 is not located between at least a portion of the first active region 211 (a rectangular portion in this example) and the conductor 231d. Similarly, the metal contact region 222a is not located between at least a portion of the metal contact region 212a and the conductors 231d and 231e, while the metal contact region 222b is not located between at least a portion of the metal contact region 212b and the conductors 231d and 231e. For example, the conductor 231e can be electrically connected downwards along the vertical direction (Z) to the metal contact region 212a (via source / drain contacts not shown for clarity) without passing through the metal contact region 222a. This allows for greater wiring flexibility for the bottom FET 110.

[0032] Figure 3A and 3B An example of a CFET300 according to some embodiments is shown. Specifically, Figure 3A This is a perspective view of the CFET300. Figure 3B It corresponds to Figure 3A A cross-sectional view of line X3-X3.

[0033] like Figure 3AAs shown, example CFET 300 includes at least a bottom FET 310 and a top FET 320. The bottom FET 310 is disposed above a substrate (not shown for clarity). The bottom FET 310 includes at least a first active region 311, two metal contact regions 312, and a gate region (i.e., a polysilicon region) 313. In this embodiment, the first active region 311 is disposed on a first horizontal plane 301. The first horizontal plane 301 is located on an XY plane perpendicular to the vertical direction (Z). The first active region 311 may define an active region in which a transistor can be constructed. In this embodiment, the first active region 311 is a first conductivity type (e.g., n-type). It should be noted that in other examples, the first active region 311 may be a second conductivity type (e.g., p-type). In this embodiment, metal contact regions 312a and 312b are disposed above the first active region 311. One of the metal contact regions 312a and 312b can be used as the source of the bottom FET 310, and the other can be used as the drain of the bottom FET 310. In one example, metal contact region 312a can be used as the source of the bottom FET 310, and metal contact region 312b can be used as the drain of the bottom FET 310. Source and drain contacts can be further disposed above metal contact regions 312a and 312b to form the source and drain terminals of the bottom FET 310. In this embodiment, gate region 313 is located between metal contact regions 312a and 312b. Gate region 313 is adjacent to a plurality (e.g., three or four) sides of the first active region 311. Gate region 313 can be used as the gate of the bottom FET 310. Gate electrode can be further disposed around gate region 313 to form the gate terminal of the bottom FET 310.

[0034] On the other hand, the top FET 320 is disposed above the bottom FET 310. The top FET 320 includes at least a second active region 321, two metal contact regions 322, and a gate region (i.e., a polysilicon region) 323. In this embodiment, the second active region 321 is disposed on a second horizontal plane 302. The second plane is located in an XY plane perpendicular to the vertical direction (Z). The second horizontal plane 302 is located above the first horizontal plane 301. The second active region 321 may define an active region in which a transistor can be constructed. In this embodiment, the second active region 321 is a second conductivity type (e.g., p-type). It should be noted that in other examples, the second active region 321 may be a first conductivity type (e.g., n-type). In this embodiment, metal contact regions 322a and 322b are disposed above the second active region 321. One of the metal contact regions 322a and 322b may be used as the source of the top FET 320, and the other may be used as the drain of the top FET 320. In one example, metal contact region 322a can be used as the source of the top FET 320, and metal contact region 322b can be used as the drain of the top FET 320. Source and drain contacts can be further disposed above metal contact regions 322a and 322b to form the source and drain terminals of the top FET 320. In this embodiment, gate region 323 is located between metal contact regions 322a and 322b. Gate region 323 is adjacent to multiple (e.g., three or four) sides of the second active region 321. Gate region 323 can be used as the gate of the top FET 320. It should be noted that in this embodiment, gate region 323 and gate region 313 are separated rather than connected. Gate electrodes can be further disposed around gate region 323 to form the gate terminal of the top FET 320.

[0035] Multiple conductors (not shown for clarity) may be disposed above the top FET 320. Multiple conductors are disposed on a third plane (not shown for clarity) located in the XY plane and above the second horizontal plane 302. In some embodiments, the multiple conductors are metallic traces, collectively referred to as the M0 layer.

[0036] like Figure 3A As shown, the reference plane 304 is a YZ plane perpendicular to the horizontal direction (X). The first active region 311 has a distance D relative to the reference plane 304 along the X direction. B The second active region 321 has a distance D along the X direction relative to the reference plane 304. T The first active region 311 has a width W along the X direction. B The second active region 321 has a width W along the X direction. T Reference Figure 3B Detailed discussion of D B D T WB and W T The relationship between them.

[0037] like Figure 3B As shown, in the first horizontal plane 301, the bottom FET 310 may include, among other things, a first active region 311 and gate regions 313 adjacent to at least two sides of the first active region 311. A second active region 321 has a projection 321' on the first horizontal plane 301. The projection 321' of the second active region 321 on the first horizontal plane 301 does not completely overlap with the first active region 311. In other words, when viewed from the vertical direction (Z), the projections 321' of the first active region 311 and the second active region 321 do not completely overlap. Along the vertical direction (Z), the second active region 321 is not located between at least a portion of the first active region 311 (in this example, portion 311a of the first active region 311 comprising two portions 311a and 311b) and multiple wires. This allows for greater wiring flexibility for the bottom FET 110, as explained above.

[0038] Additionally, in some embodiments, the distance D B It can be less than the distance D T In some embodiments, distance D B It can be related to distance D T Same. In some embodiments, distance D B It can be greater than the distance D T In some embodiments, the width W B It can be smaller than the width W T In some embodiments, the width W B Can be used with width W T Same. In some embodiments, the width W B It can be larger than the width W T In other words, D B With D T The relationship between W and B With W T Various combinations of relationships are within the scope of this invention.

[0039] Figure 4 It is shown that it is used to form such as Figure 1A The flowchart illustrates an example of a method 400 for a semiconductor device, such as an example CFET100. In step 402, an element such as... is formed above the substrate. Figure 1A The bottom FET 110 shown is a first multi-gate FET. The first multi-gate FET includes a first active region extending on a first horizontal plane. In step 404, a region such as [missing information] is formed above the first multi-gate FET. Figure 1AThe second multi-gate FET of the top FET120 is shown. The second multi-gate FET includes a second active region extending on a second horizontal plane parallel to the first horizontal plane. When viewed from a vertical direction perpendicular to the first horizontal plane, the first active region and the second active region do not completely overlap.

[0040] According to some disclosed embodiments, a semiconductor device can be provided. The semiconductor device includes: a first multi-gate field-effect transistor (FET) disposed above a substrate, the first multi-gate FET including a first active region extending on a first horizontal plane; and a second multi-gate FET disposed above the first multi-gate FET, the second multi-gate FET including a second active region extending on a second horizontal plane parallel to the first horizontal plane. When viewed from a vertical direction perpendicular to the first horizontal plane, the first active region and the second active region do not completely overlap.

[0041] In the aforementioned semiconductor device, the first active region and the second active region have different conductivity types.

[0042] In the aforementioned semiconductor device, the first projection of the second active region onto the first horizontal plane partially overlaps with the first active region.

[0043] In the aforementioned semiconductor device, the first projection of the second active region onto the first horizontal plane does not overlap with the first active region.

[0044] In the aforementioned semiconductor device, the first area of ​​the first active region is smaller than the second area of ​​the second active region.

[0045] In the above-mentioned semiconductor device, the first area of ​​the first active region is equal to the second area of ​​the second active region.

[0046] In the aforementioned semiconductor device, the first area of ​​the first active region is larger than the second area of ​​the second active region.

[0047] In the above-described semiconductor device, the first multi-gate field-effect transistor further includes a first metal contact region disposed above the first active region and a second metal contact region disposed above the first active region; and the second multi-gate field-effect transistor further includes a third metal contact region disposed above the second active region and a fourth metal contact region disposed above the second active region; wherein, when viewed from the vertical direction, the first metal contact region and the third metal contact region do not completely overlap, and when viewed from the vertical direction, the first metal contact region and the fourth metal contact region do not completely overlap.

[0048] In the aforementioned semiconductor device, when viewed from a vertical direction, the second metal contact and the third metal contact area do not completely overlap, and when viewed from a vertical direction, the second metal contact area and the fourth metal contact area do not completely overlap.

[0049] In the above-described semiconductor device, the first multi-gate field-effect transistor further includes a first gate region adjacent to a plurality of sides of the first active region, and the second multi-gate field-effect transistor further includes a second gate region adjacent to a plurality of sides of the second active region.

[0050] In the semiconductor device described above, the first gate region and the second gate region are separated.

[0051] In the above semiconductor device, the first gate region and the second gate region are connected.

[0052] In the above-mentioned semiconductor device, the first width of the first active region is equal to the second width of the second active region.

[0053] In the aforementioned semiconductor device, the first width of the first active region is different from the second width of the second active region.

[0054] According to some disclosed embodiments, a semiconductor device can be provided. The semiconductor device includes: a substrate; a first multi-gate FET disposed above the substrate, the first multi-gate FET including a first active region extending on a first horizontal plane parallel to the substrate and having a first projection of the first active region on the substrate; and a second multi-gate FET disposed above the first multi-gate FET, the second multi-gate FET including a second active region extending on a second horizontal plane parallel to the substrate and having a second projection of the second active region on the substrate. The first projection and the second projection do not completely overlap.

[0055] In the aforementioned semiconductor device, the first projection and the second projection do not overlap.

[0056] In the aforementioned semiconductor device, the first projection and the second projection partially overlap.

[0057] According to a further disclosed embodiment, a method for forming a semiconductor device can be provided. The method includes: forming a first multi-gate FET disposed above a substrate, the first multi-gate FET including a first active region extending on a first horizontal plane; and forming a second multi-gate FET disposed above the first multi-gate FET, the second multi-gate FET including a second active region extending on a second horizontal plane parallel to the first horizontal plane. When viewed from a vertical direction perpendicular to the first horizontal plane, the first active region and the second active region do not completely overlap.

[0058] In the above method, the first active region and the second active region have different conductivity types.

[0059] In the above method, the first projection of the second active region onto the first horizontal plane partially overlaps with the first active region.

[0060] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: A first multi-gate field-effect transistor is disposed above a substrate, and the first multi-gate field-effect transistor includes a first active region extending on a first horizontal plane; as well as A second multi-gate field-effect transistor is disposed above the first multi-gate field-effect transistor, and the second multi-gate field-effect transistor includes a second active region extending on a second horizontal plane parallel to the first horizontal plane; Specifically, when viewed from a vertical direction perpendicular to the first horizontal plane, the first active region and the second active region do not completely overlap. The first multi-gate field-effect transistor further includes a first metal contact region disposed above the first active region and a second metal contact region disposed above the first active region; and the second multi-gate field-effect transistor further includes a third metal contact region disposed above the second active region and a fourth metal contact region disposed above the second active region; wherein, when viewed vertically, the projections of the first metal contact region and the third metal contact region onto the first horizontal plane do not completely overlap along a direction perpendicular to the extension direction of the first active region, and when viewed vertically, the projections of the first metal contact region and the fourth metal contact region onto the first horizontal plane do not completely overlap along a direction perpendicular to the extension direction of the first active region, the first metal contact region and the third metal contact region partially overlap, the first metal contact region and the fourth metal contact region do not overlap, the second metal contact region and the third metal contact region do not overlap, and the second metal contact region and the fourth metal contact region partially overlap. The first projection of the second active region onto the first horizontal plane partially overlaps with the first active region.

2. The semiconductor device according to claim 1, wherein, The first active region and the second active region have different conductivity types.

3. The semiconductor device according to claim 1, wherein, The first active region is of type n.

4. The semiconductor device according to claim 1, wherein, The second active region is p-type.

5. The semiconductor device according to claim 1, wherein, The first area of ​​the first active region is smaller than the second area of ​​the second active region.

6. The semiconductor device according to claim 1, wherein, The first area of ​​the first active region is equal to the second area of ​​the second active region.

7. The semiconductor device according to claim 1, wherein, The first area of ​​the first active region is greater than the second area of ​​the second active region.

8. The semiconductor device according to claim 1, wherein, The area of ​​the first active region is larger than the area of ​​the second active region.

9. The semiconductor device according to claim 1, wherein, The portion of the first active region that does not overlap with the first projection of the second active region onto the first horizontal plane has a rectangular shape.

10. The semiconductor device according to claim 1, wherein, The first multi-gate field-effect transistor further includes a first gate region adjacent to a plurality of sides of the first active region, and the second multi-gate field-effect transistor further includes a second gate region adjacent to a plurality of sides of the second active region.

11. The semiconductor device according to claim 10, wherein, The first gate region and the second gate region are separated.

12. The semiconductor device according to claim 10, wherein, The first gate region and the second gate region are connected.

13. The semiconductor device according to claim 1, wherein, The first width of the first active region is equal to the second width of the second active region.

14. The semiconductor device according to claim 1, wherein, The first width of the first active region is different from the second width of the second active region.

15. A semiconductor device, comprising: Substrate; A first multi-gate field-effect transistor is disposed above the substrate. The first multi-gate field-effect transistor includes a first active region extending on a first horizontal plane parallel to the substrate and having a first projection of the first active region on the substrate. as well as A second multi-gate field-effect transistor is disposed above the first multi-gate field-effect transistor. The second multi-gate field-effect transistor includes a second active region extending on a second horizontal plane parallel to the substrate and having a second projection of the second active region on the substrate. Wherein, the first projection and the second projection do not completely overlap. The first multi-gate field-effect transistor further includes a first metal contact region disposed above the first active region and a second metal contact region disposed above the first active region; and the second multi-gate field-effect transistor further includes a third metal contact region disposed above the second active region and a fourth metal contact region disposed above the second active region; wherein, when viewed vertically, the projections of the first metal contact region and the third metal contact region onto the first horizontal plane do not completely overlap along a direction perpendicular to the extension direction of the first active region, and when viewed vertically, the projections of the first metal contact region and the fourth metal contact region onto the first horizontal plane do not completely overlap along a direction perpendicular to the extension direction of the first active region, the first metal contact region and the third metal contact region partially overlap, the first metal contact region and the fourth metal contact region do not overlap, the second metal contact region and the third metal contact region do not overlap, and the second metal contact region and the fourth metal contact region partially overlap. The first projection and the second projection partially overlap.

16. The semiconductor device according to claim 15, wherein, The first active region is of type n.

17. The semiconductor device according to claim 15, wherein, The second active region is p-type.

18. A method for forming a semiconductor device, comprising: A first multi-gate field-effect transistor is formed above a substrate, the first multi-gate field-effect transistor including a first active region extending on a first horizontal plane; as well as A second multi-gate field-effect transistor is formed above the first multi-gate field-effect transistor, the second multi-gate field-effect transistor including a second active region extending on a second horizontal plane parallel to the first horizontal plane; wherein, when viewed from a vertical direction perpendicular to the first horizontal plane, the first active region and the second active region do not completely overlap. The first multi-gate field-effect transistor further includes a first metal contact region disposed above the first active region and a second metal contact region disposed above the first active region; and the second multi-gate field-effect transistor further includes a third metal contact region disposed above the second active region and a fourth metal contact region disposed above the second active region; wherein, when viewed vertically, the projections of the first metal contact region and the third metal contact region onto the first horizontal plane do not completely overlap along a direction perpendicular to the extension direction of the first active region, and when viewed vertically, the projections of the first metal contact region and the fourth metal contact region onto the first horizontal plane do not completely overlap along a direction perpendicular to the extension direction of the first active region, the first metal contact region and the third metal contact region partially overlap, the first metal contact region and the fourth metal contact region do not overlap, the second metal contact region and the third metal contact region do not overlap, and the second metal contact region and the fourth metal contact region partially overlap. The first projection of the second active region onto the first horizontal plane partially overlaps with the first active region.

19. The method according to claim 18, wherein, The first active region and the second active region have different conductivity types.

20. The method according to claim 18, wherein, The first active region is n-type, and the second active region is p-type.

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