TFT array substrate, display panel and electronic equipment

Abstract

The disclosed embodiments provide a TFT array substrate, a display panel, and an electronic device. The TFT array substrate includes: multiple GOA models, one GOA model is used to drive a row of pixels; each GOA model includes multiple pairs of TFT units, each TFT unit in each pair of TFT units includes multiple TFTs, and the three electrodes of the multiple TFTs constitute the three-electrode routing of the TFT unit, and the three electrodes are gate, source, and drain; wherein the shape and size of the three-electrode routing layout of the first TFT unit and the second TFT unit in each pair of TFT units are the same, and one or two electrodes of the electrode routing with the same signal in the three-electrode routing of the first TFT unit and the second TFT unit are configured as a shared routing. The disclosed embodiments configure one or two electrodes of the electrode routing with the same signal in each pair of TFT units in each GOA model as a shared routing, thereby reducing the space occupied by the GOA layout area.

Description

Technical Field

[0001] The present disclosure relates to the field of displays, and in particular to a TFT array substrate, a display panel, and an electronic device. Background Art

[0002] For new products, THO6090 (Temperature (60°C) Humidity (90%) Operation) is a key evaluation criterion. This involves operating the screen in a harsh environment of high temperature and humidity, and evaluating how long the screen can display normally. The longer the normal display duration, the better. The current factory minimum standard is 1000 hours or longer. Abnormal THO display occurs because, over time, moisture intrudes into the seal in the GOA (Gate on Array) area, corroding the signal lines. This causes the CLK signal line under the seal to short-circuit, resulting in abnormal screen display. Currently, many oxide products struggle to meet this minimum standard, delaying mass production and reducing customer satisfaction.

[0003] To ensure that Oxide products meet THO test standards, the factory currently employs various methods. One approach involves increasing the distance between the outer edge of the seal in the GOA area and the product's CLK signal line. However, this increases the product's bezel, which contradicts the market trend toward narrower bezels. Therefore, to meet the required distance between the seal and the CLK signal line, thereby resolving THO display issues and aligning with market trends, reducing the GOA layout space is a critical issue that needs to be addressed.

[0004] At present, the GOA model of Oxide products (that is, the GOA that drives a row of pixels) adopts two groups of noise-reducing TFT (ThinFilm Transistor) units A and B to work alternately to extend the product life. The shape and size of group A and group B must be completely consistent to avoid defects when working alternately. Each TFT unit is composed of multiple TFTs accumulated, and the TFT unit is rectangular, resulting in a large space occupied by the GOA layout area, which is not conducive to achieving a narrow frame. Summary of the Invention

[0005] In view of this, the embodiments of the present disclosure propose a TFT array substrate, a display panel and an electronic device to solve the following problems in the prior art: the GOA model of the Oxide product adopts two groups of noise reduction TFT units A and B to work alternately to extend the product life. Each TFT unit is composed of multiple TFTs accumulated, and the TFT unit is rectangular, resulting in a large space occupied by the GOA layout area, which is not conducive to achieving a narrow frame.

[0006] On the one hand, an embodiment of the present disclosure proposes a TFT array substrate, comprising: multiple GOA models, one GOA model is used to drive a row of pixels; each of the GOA models includes multiple pairs of TFT units, each of the TFT units in each pair of TFT units includes multiple TFTs, and the three electrodes of the multiple TFTs constitute the three-electrode routing of the TFT unit, and the three electrodes are gate, source and drain; wherein, the shape and size of the three-electrode routing in the first TFT unit and the second TFT unit of each pair of TFT units are the same, and one or two electrodes of the electrode routing with the same signal in the three-electrode routing of the first TFT unit and the second TFT unit are configured as a common routing.

[0007] In some embodiments, when the number of the electrode traces having the same signal is two and the electrode traces include a source trace and / or a drain trace, the source trace and / or the drain trace are configured as a common trace.

[0008] In some embodiments, when the number of the electrode routing having the same signal is one and the electrode routing is not the gate routing, the source routing or the drain routing is configured as a shared routing.

[0009] In some embodiments, when the first TFT unit and the second TFT unit have the same source signal and drain signal, the source wiring of the first TFT unit and the second TFT unit are configured as a common wiring.

[0010] In some embodiments, when the first TFT unit and the second TFT unit have the same source signal and drain signal, the drain wiring of the first TFT unit and the second TFT unit are configured as a common wiring.

[0011] In some embodiments, when the first TFT unit and the second TFT unit have the same gate signal and source signal, the source wiring of the first TFT unit and the second TFT unit are configured as a common wiring, and the gate wiring is configured as a common wiring.

[0012] In some embodiments, when the first TFT unit and the second TFT unit have the same gate signal and drain signal, the drain wiring of the first TFT unit and the second TFT unit are configured as a common wiring, and the gate wiring is configured as a common wiring.

[0013] On the other hand, an embodiment of the present disclosure provides a display panel, which at least includes: a TFT array substrate as described in any embodiment of the present disclosure.

[0014] On the other hand, an embodiment of the present disclosure provides an electronic device, comprising at least: the display panel described in any embodiment of the present disclosure.

[0015] The disclosed embodiment improves two identical TFT units when setting the GOA model. The common routing is determined by determining the electrode routing with the same signal in the three-pole routing of the two TFT units. Then, during wiring, one or both of the electrode routings with the same signal in each pair of TFT units in each GOA model are configured as common routings, thereby saving the area occupied by the electrode routing with the same signal, thereby reducing the space occupied by the GOA layout area and freeing up more space for narrow-frame design. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 Schematic diagram of the layout of the GOA model provided by the existing technology Figure 1 ;

[0018] Figure 2 Schematic diagram of the layout of the GOA model provided by the existing technology Figure 2 ;

[0019] Figure 3 A schematic structural diagram of a TFT array substrate provided in an embodiment of the present disclosure;

[0020] Figure 4 Schematic diagram of the layout of the GOA model provided by the existing technology Figure 3 ;

[0021] Figure 5 Schematic diagram of the layout of the GOA model provided in the embodiment of the present disclosure Figure 1 ;

[0022] Figure 6 Schematic diagram of the layout of the GOA model provided in the embodiment of the present disclosure Figure 2 ;

[0023] Figure 7 Schematic diagram of the layout of the GOA model provided by the existing technology Figure 4 ;

[0024] Figure 8 Schematic diagram of the layout of the GOA model provided in the embodiment of the present disclosure Figure 3 .

[0025] Reference numerals:

[0026] 1-GOA model, 11-first TFT unit, 12-second TFT unit. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0029] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0030] A GOA model may include multiple pairs of TFT units. The shape and size of the triode wiring layout of the first TFT unit and the second TFT unit in each pair of TFT units are the same. The shape and size of the triode wiring layout of each pair of TFT units in a GOA model can be different, or of course, the same, and this is not limited here. In the following content, for the sake of clarity, the embodiments of the present disclosure are generally illustrated by taking a GOA model including only one pair of TFT units as an example. In specific implementation, the layout of each pair of TFT units can be configured in accordance with the embodiments of the present disclosure.

[0031] In the GOA model, the shapes and sizes of TFT units in groups A and B must be identical, effectively forming a pair. This prevents defects during alternating operation. Because A and B are working in alternating groups, at least one of the three signal sets—source (S), drain (D), and gate (G)—of the noise-reduction TFT units in groups A and B will differ, while the remaining two or one signal set will be identical. Figure 1 and Figure 2 There are two noise reduction TFT units commonly used in the current GOA model, Figure 1 It is the layout of TFT units of group A and B with the same gate signal and source signal. Figure 2 It is the layout of the A and B groups of TFT units with the same source and drain signals.

[0032] Based on the above figures, it can be seen that the existing TFT array substrate occupies a large area when the GOA model is laid out. Therefore, the embodiment of the present disclosure provides a TFT array substrate, the structure of which is shown in FIG. Figure 3 Shown, including:

[0033] Multiple GOA models 1, one GOA model 1 is used to drive a row of pixels; each GOA model 1 includes multiple pairs of TFT units, each TFT unit in each pair of TFT units includes multiple TFTs, and the three electrodes of the multiple TFTs constitute the three-electrode routing of the TFT unit, and the three electrodes are the gate, source and drain; wherein, the shape and size of the three-electrode routing layout in the first TFT unit 11 and the second TFT unit 12 of each pair of TFT units are the same, and one or two electrodes of the electrode routing with the same signal in the three-electrode routing of the first TFT unit and the second TFT unit are configured as a shared routing.

[0034] The disclosed embodiment improves two identical TFT units when setting the GOA model. The common routing is determined by determining the electrode routing with the same signal in the three-pole routing of the two TFT units. Then, during wiring, one or both of the electrode routings with the same signal in each pair of TFT units in each GOA model are configured as common routings, thereby saving the area occupied by the electrode routing with the same signal, thereby reducing the space occupied by the GOA layout area and freeing up more space for narrow-frame design.

[0035] above Figure 3 Only one pair of TFT units in a GOA model is illustrated. The other pairs of TFT units also adopt a shared routing design. The specific configuration of which electrode routing is the shared routing can be based on the electrode routing of the same signal in each pair of TFT units. This will not be described in detail here.

[0036] For the GOA model, its three-level routing is in different layers, namely the gate layer, insulating layer, oxide layer, and source and drain layer, respectively. It can be seen that the source routing and drain routing are distributed in one layer, and the gate routing is in a separate layer. The gate routing changes with the overall wiring of the source routing and drain routing. Therefore, in the specific implementation, it is mainly necessary to determine which level or which two poles the electrode routing with the same signal is.

[0037] For example, when there are two electrode traces with the same signal, and the electrode traces include a source trace and / or a drain trace, the two electrode traces with the same signal include at least one trace in a source / drain layer. Therefore, the source trace and / or the drain trace can be configured as a shared trace. If the two electrode traces with the same signal are a source trace and a drain trace, both the source trace and the drain trace can be configured as a shared trace.

[0038] Specifically, when the first TFT unit and the second TFT unit have the same source signal and drain signal, all or part of the source lines of the first TFT unit and the second TFT unit can be configured as a common line, all or part of the drain lines of the first TFT unit and the second TFT unit can be configured as a common line, and all or part of the source lines and drain lines of the first TFT unit and the second TFT unit can be configured as a common line.

[0039] When the first TFT unit and the second TFT unit have the same gate signal and source signal, the source routing of the first TFT unit and the second TFT unit can be configured as a shared routing, and the gate routing can be configured as a shared routing; when the first TFT unit and the second TFT unit have the same gate signal and drain signal, the drain routing of the first TFT unit and the second TFT unit can be configured as a shared routing, and the gate routing can be configured as a shared routing. Since the gate routing configured as a shared routing is located on a layer other than the source layer, the routing of the gate routing can be configured accordingly with the routing of the source and drain layers.

[0040] For another example, when the number of electrode traces with the same signal is one and the electrode trace is not a gate trace, it means that the electrode traces with the same signal can be arranged as common traces, and therefore, the source trace or the drain trace can be configured as a common trace.

[0041] The above process will be further described below with reference to the accompanying drawings.

[0042] The disclosed embodiments provide a GOA layout method for achieving a narrow bezel of a panel (display panel): that is, without increasing additional development costs and processes, by sharing one or two of the gate, source, and drain electrodes of the two groups of noise reduction TFT units A and B (i.e., the first TFT unit and the second TFT unit) in the GOA, the GOA layout space is reduced, and the saved space is used to meet the distance requirements between the seal glue and the CLK signal line, solve the THO abnormal display problem that occurs frequently in the factory, or further reduce the product bezel, meet customer needs, and greatly improve customer satisfaction.

[0043] like Figure 4 and Figure 5 As shown, for the noise reduction TFT units of groups A and B with the same gate signal and source signal, Figure 4 This is a schematic diagram of the GOA model layout in the prior art. Figure 5 This is a schematic diagram of the GOA model layout of an embodiment of the present disclosure. In the embodiment of the present disclosure, the source wiring and gate wiring of the two groups A and B TFT units are directly shared. Figure 4 The area occupied by the layout shown is approximately 1151.4um 2 ,and Figure 5 The layout shown occupies an area of ​​approximately 732.45um 2 , reduced by about 36%, effectively reducing the GOA typesetting space.

[0044] In principle, for Figure 4 For example, when the noise reduction TFT unit of group A is working and group B is not working, that is, channel 1 is working, assuming that its gate voltage is VG, and the source and drain voltages are VS and VD1 respectively; channel 2 is not working, but since the gate and source signals of groups A and B are the same, its gate voltage is still VG, the source voltage is still VS, and its drain signal is VD2 (0 signal). If using Figure 5 By comparing the layout of the noise reduction TFT units in Group A and Group B, we find that when the noise reduction TFT units in Group A are operating and Group B is not operating, the gate, source, and drain voltages of Channel 1 are VG, VS, and VD1, respectively; the gate, source, and drain voltages of Channel 2 remain VG, VS, and VD2, respectively. The principle analysis when Group A is not operating and Group B is operating is similar, so I won't elaborate on it here. This shows that the environment of each channel in Groups A and B remains unchanged, and does not affect the TFT characteristics or operation.

[0045] like Figure 1 and Figure 6 As shown, it can be applied to 17.3-inch UHD products, which use A and B groups of noise reduction TFT units with the same gate signal and source signal. Figure 1 This is a schematic diagram of the GOA model layout in the prior art. Figure 6This is a schematic diagram of the GOA model layout of an embodiment of the present disclosure. In the embodiment of the present disclosure, the adjacent source wirings and gate wirings of the two groups of noise reduction units A and B are directly shared. Figure 1 The area occupied by the layout shown is approximately 3399.4um 2 ,and Figure 6 The layout area occupied by the typesetting is about 2439.45um 2 , reduced by about 26%, effectively reducing the GOA typesetting space.

[0046] like Figure 7 and Figure 8 As shown, for the noise reduction TFT units of groups A and B with the same source signal and drain signal, Figure 7 This is a schematic diagram of the GOA model layout in the prior art. Figure 8 This is a schematic diagram of the GOA model layout of an embodiment of the present disclosure. The embodiment of the present disclosure directly shares some source wiring of the two groups A and B of noise reduction units. Figure 7 The area occupied by the layout shown is approximately 17255.5um 2 ,and Figure 8 The layout area is about 13647.4um 2 , reduced by about 22%, effectively reducing the GOA typesetting space.

[0047] Although the source wiring and the drain wiring are distinguished by different lines in the various drawings of the embodiments of the present disclosure, in actual operation, the source wiring and the drain wiring can be completely opposite to the embodiments of the present disclosure, which is not limited here.

[0048] The embodiment of the present disclosure further provides a display panel, which at least includes any one of the TFT array substrates in the above embodiments. The embodiment of the present disclosure further provides an electronic device, which at least includes the display panel in the above embodiments.

[0049] Furthermore, although exemplary embodiments have been described herein, the scope includes any and all embodiments based on the present disclosure with equivalent elements, modifications, omissions, combinations (e.g., solutions that intersect various embodiments), adaptations, or changes. The elements in the claims are to be interpreted broadly based on the language employed in the claims and are not limited to the examples described in this specification or during the prosecution of this application, which examples are to be interpreted as non-exclusive. Therefore, this specification and examples are intended to be considered as examples only, with the true scope and spirit being indicated by the following claims and the full scope of their equivalents.

[0050] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more schemes thereof) can be used in combination with each other. For example, a person of ordinary skill in the art may use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features can be grouped together to simplify the present disclosure. This should not be interpreted as an intention that a disclosed feature that is not required to be protected is necessary for any claim. On the contrary, the subject matter of the present disclosure may be less than all the features of a specific disclosed embodiment. Thus, the following claims are incorporated into the specific embodiments as examples or embodiments, wherein each claim is independently a separate embodiment, and it is considered that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

[0051] The above describes in detail multiple embodiments of the present disclosure, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concepts of the present disclosure, and these variations and modifications should all fall within the scope of protection claimed by the present disclosure.

Claims

1. A TFT array substrate, characterized in that: include: Multiple GOA models, one GOA model is used to drive a row of pixels; Each of the GOA models includes multiple pairs of TFT units, each of the TFT units in each pair includes multiple TFTs, and the three electrodes of the multiple TFTs constitute the three-electrode wiring of each TFT unit, and the three electrodes are gate, source and drain; the source wiring and the drain wiring are distributed in one layer, and the gate wiring is in a single layer, wherein, The shape and size of the three-electrode wiring layout of the first TFT unit and the second TFT unit of each pair of TFT units are the same, and one or two electrodes of the electrode wiring with the same signal in the three-electrode wiring of the first TFT unit and the second TFT unit are configured as a common wiring; When the first TFT unit and the second TFT unit have the same source signal and drain signal, the source wiring of the first TFT unit and the second TFT unit are configured as a common wiring.

2. A display panel, characterized in that: At least: The TFT array substrate according to claim 1.

3. An electronic device, characterized in that: At least: The display panel according to claim 2.

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