Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same are provided. The semiconductor device includes: a first logic die including a first through hole; an image sensor die hybridly bonded to the first logic die; and a second logic die bonded to the first logic die. The front side of the first logic die faces the front side of the image sensor die. The front side of the second logic die faces the back side of the first logic die. The second logic die includes a first conductive pad electrically coupled to the first through hole.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to the repeated reduction in the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there has been a demand for packaging technologies for smaller and more creative semiconductor dies. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device, comprising: a first logic die including a first through hole; an image sensor die hybridly bonded to the first logic die, with the front side of the first logic die facing the front side of the image sensor die; and a second logic die bonded to the first logic die, with the front side of the second logic die facing the back side of the first logic die, the second logic die including a first conductive pad electrically coupled to the first through hole.

[0004] Another embodiment of the present invention provides a semiconductor device, including: a first logic die, the front side of the first logic die including a first insulating layer and a first conductive pad, and the back side of the first logic die including a second insulating layer and a second conductive pad; an image sensor die bonded to the first logic die, the front side of the image sensor die including a third insulating layer and a third conductive pad, the third conductive pad being in physical contact with the first conductive pad, and the third insulating layer being in physical contact with the first insulating layer; and a second logic die bonded to the first logic die, the front side of the second logic die including a fourth insulating layer and a fourth conductive pad, and the fourth insulating layer facing the second insulating layer.

[0005] Another embodiment of the present invention provides a method for forming a semiconductor device, comprising: bonding a logic wafer to an image sensor wafer, the front side of the logic wafer comprising a first conductive pad, the front side of the image sensor wafer comprising a second conductive pad, wherein bonding the logic wafer to the image sensor wafer comprises directly bonding the first conductive pad to the second conductive pad; forming a first redistribution structure on the back side of the logic wafer; and bonding a logic die to the first redistribution structure, the front side of the logic die comprising a third conductive pad, wherein the third conductive pad is electrically coupled to the first redistribution structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0008] Figure 2 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0009] Figure 3 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0010] Figure 4 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0011] Figures 5 to 18 Cross-sectional views are shown of intermediate steps during a process of forming a package in accordance with some embodiments.

[0012] Fig.19 A cross-sectional view of a package is shown in accordance with some embodiments.

[0013] Fig. 20 A cross-sectional view of a package is shown in accordance with some embodiments.

[0014] Fig.21 A cross-sectional view of a package is shown in accordance with some embodiments.

[0015] Figure 22 to Figure 27 Cross-sectional views are shown of intermediate steps during a process of forming a package in accordance with some embodiments.

[0016] Fig.28 A cross-sectional view of a package is shown in accordance with some embodiments.

[0017] Fig.29A cross-sectional view of a package is shown in accordance with some embodiments.

[0018] Fig.30 A cross-sectional view of a package is shown in accordance with some embodiments.

[0019] Figure 31 to Figure 36 Cross-sectional views are shown of intermediate steps during a process of forming a package in accordance with some embodiments.

[0020] Fig.37 A cross-sectional view of a package is shown in accordance with some embodiments.

[0021] Figures 38 to 43 Cross-sectional views are shown of intermediate steps during a process of forming a package in accordance with some embodiments.

[0022] Fig.44 A cross-sectional view of a package is shown in accordance with some embodiments.

[0023] Fig.45 A cross-sectional view of a package is shown in accordance with some embodiments.

[0024] Fig.46 A cross-sectional view of a package is shown in accordance with some embodiments.

[0025] Fig.47 is a flow chart illustrating a method of forming a package according to some embodiments. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0028] The embodiments will be described with respect to embodiments in a specific context, namely, packages such as multi-layer stacked image sensor packages and methods of forming the same. The various embodiments presented herein allow for the formation of packages for edge artificial intelligence (AI) applications (such as self-driving cars), which may require fast processing speeds. Embodiments such as those disclosed herein integrate logic dies and / or memory (e.g., (one or more) DRAM chips) within a multi-layer stacked image sensor package for processing image information, thereby increasing processing speeds to meet the functional and processing speed requirements of edge AI applications.

[0029] Figure 1 A cross-sectional view of an integrated circuit die 10 according to some embodiments is shown. The integrated circuit die 10 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 10 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof.

[0030] The integrated circuit die 10 may be formed in a wafer that may include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 10 may be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 10 includes a substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. The substrate 52 has an active surface (e.g., at Figure 1 The surface facing upward in the middle), sometimes called the front side, and the passive surface (e.g. Figure 1 The downward-facing surface of the middle part of the body is sometimes called the posterior side.

[0031] Devices (represented by transistors) 54 may be formed at the front surface of substrate 52. Devices 54 may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, inductors, etc., or combinations thereof. Interlayer dielectric (ILD) 56 is located above the front surface of substrate 52. ILD 56 surrounds and may cover device 54. ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and may be formed using spin coating, lamination, atomic layer deposition (ALD), chemical vapor deposition (CVD), etc.

[0032] Conductive plug 58 extends through ILD 56 to electrically and physically couple device 54. For example, when device 54 is a transistor, conductive plug 58 can couple the gate and source / drain regions of the transistor. Conductive plug 58 can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof. Interconnect structure 60 is located above ILD 56 and conductive plug 58. Interconnect structure 60 interconnects device 54 to form an integrated circuit. Interconnect structure 60 can be formed by, for example, a metallization pattern in a dielectric layer on ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. In some embodiments, interconnect structure 60 can be formed by alternating layers of dielectric (e.g., low-k dielectric material) and conductive (e.g., copper) materials, with vias interconnecting the layers of conductive material, and can be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). The metallization pattern of interconnect structure 60 is electrically coupled to device 54 through conductive plug 58.

[0033] The integrated circuit die 10 also includes a pad 62, such as an aluminum pad, for connection to the outside. The pad 62 is located on the active side of the integrated circuit die 10, such as in and / or on the interconnect structure 60. An insulating layer 64 is located on the integrated circuit die 10 so that the pad 62 is embedded in the insulating layer 64. The insulating layer 64 may also be referred to as a passivation layer. In some embodiments, the insulating layer 64 may include one or more layers of silicon oxide, silicon nitride, silicon oxynitride, etc. or a combination thereof, and may be formed using ALD, CVD, etc. In some embodiments, the pad 62 and the insulating layer 64 may be formed by forming and patterning a conductive material over the interconnect structure 60 to form the pad 62, forming an insulating material of the insulating layer 64 over the interconnect structure 60 and the pad 62, and planarizing the insulating material to expose the pad 62.

[0034] In other embodiments, pad 62 and insulating layer 64 may be formed by forming an insulating material of insulating layer 64 on interconnect structure 60, patterning the insulating material to form an opening for pad 62, depositing a conductive material of pad 62 in the opening, and planarizing the conductive material to remove a portion of the conductive material that overfills the opening. The portion of the conductive material remaining in the opening forms pad 62. In some embodiments, the planarization process may include chemical mechanical polishing (CMP), grinding, etching, a combination thereof, and the like. In some embodiments, within the process variation of the planarization process, the top surface of insulating layer 64 and the top surface of pad 62 are substantially flush or substantially coplanar.

[0035] In some embodiments, a chip probe (CP) test is performed on the integrated circuit die 10. The CP test can be performed on the integrated circuit die 10 to determine whether the integrated circuit die 10 is a known good die (KGD). Therefore, only the integrated circuit die 10 of the KGD is subsequently processed and packaged, while the die that fails the CP test is not packaged.

[0036] In some embodiments, the integrated circuit die 10 is a stacked device including a plurality of substrates 52. For example, the integrated circuit die 10 may be a memory device such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc., including a plurality of memory dies. In such embodiments, the integrated circuit die 10 includes a plurality of substrates 52 interconnected by through substrate vias (TSVs) (not shown). Each substrate 52 may have (or may not have) an interconnect structure 60.

[0037] Figure 2 2 shows a cross-sectional view of an integrated circuit die 20 according to some embodiments. The integrated circuit die 20 will be packaged in subsequent processing to form an integrated circuit package. In some embodiments, the integrated circuit die 20 is similar to the integrated circuit die 10 (see Figure 1), wherein similar components are labeled with similar reference numerals, and the description of similar components is not repeated here. In some embodiments, the above reference numerals may be used. Figure 1 The process steps described above are used to form the integrated circuit die 20, and are not repeated here. In the illustrated embodiment, the integrated circuit die 20 includes TSVs 66 extending through the substrate 52. In some embodiments, the TSVs 66 may include a suitable conductive material, such as copper or the like.

[0038] Figure 3 1 shows a cross-sectional view of an integrated circuit die 30 according to some embodiments. The integrated circuit die 30 will be packaged in subsequent processing to form an integrated circuit package. In some embodiments, the integrated circuit die 30 is similar to the integrated circuit die 10 (see Figure 1 ), wherein similar components are labeled with similar reference numerals, and the description of similar components is not repeated here. In some embodiments, the above reference numerals may be used. Figure 1 The integrated circuit die 30 is formed by the process steps described above and will not be repeated here.

[0039] In the illustrated embodiment, insulating layer 64 is located on integrated circuit die 30, such as on portions of interconnect structure 60 and pads 62. Openings extend through insulating layer 64 to pads 62. Under bump metallization (UBM) 68 extends through the openings in insulating layer 64 and is physically and electrically coupled to corresponding pads 62. UBM 68 may be formed of one or more suitable conductive materials.

[0040] After forming UBM 68, a conductive connector 70 is formed on UBM 68. Conductive connector 70 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating chemical palladium immersion gold technology (ENEPIG), etc. Conductive connector 70 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, conductive connector 70 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow may be performed to shape the material into a desired bump shape. In another embodiment, conductive connector 70 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process.

[0041] Figure 44 shows a cross-sectional view of an integrated circuit die 40 according to some embodiments. The integrated circuit die 40 will be packaged in subsequent processing to form an integrated circuit package. In some embodiments, the integrated circuit die 40 is similar to the integrated circuit die 30 (see Figure 3 ), wherein similar components are labeled with similar reference numerals, and the description of similar components is not repeated here. In some embodiments, the above reference numerals may be used. Figure 1 and Figure 3 The process steps described above are used to form the integrated circuit die 40, and are not repeated here. In the illustrated embodiment, the integrated circuit die 40 includes TSVs 66 extending through the substrate 52. In some embodiments, the TSVs 66 may include a suitable conductive material, such as copper or the like.

[0042] Figures 5 to 18 Cross-sectional views are shown of intermediate steps during a process of forming package 1000 , in accordance with some embodiments. Figure 5 1 shows a cross-sectional view of a die region 100A of a wafer 100 according to some embodiments. Wafer 100 may also be referred to as a logic wafer. In some embodiments, wafer 100 includes a plurality of die regions (such as die region 100A). In some embodiments, wafer 100 includes substrate 102. Figure 1 Substrate 102 is formed by using materials and methods similar to those described for substrate 52 and will not be described again herein. Substrate 102 has an active surface (e.g., Figure 5 The surface facing upward in the middle), sometimes called the front side, and the passive surface (e.g. Figure 5 In some embodiments, TSV 104 is formed in substrate 102. In some embodiments, TSV 104 may include a suitable conductive material, such as copper, etc. TSV 104 extends from the front side of substrate 102 toward the back side of substrate 102.

[0043] Devices (represented by transistors) 106 may be formed at the front surface of substrate 102. Device 106 may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, an inductor, etc., or a combination thereof. ILD 108 is located above the front surface of substrate 102. ILD 108 surrounds and may cover device 106. The same reference numerals as above may be used. Figure 1 ILD 108 is formed using similar materials and methods as described for ILD 56 , and will not be described again herein.

[0044] Conductive plug 110 extends through ILD 108 to electrically and physically couple device 106. For example, when device 106 is a transistor, conductive plug 110 may couple the gate and source / drain regions of the transistor. Figure 1 Conductive plug 110 is formed using similar materials and methods as described for conductive plug 58 , and will not be described again herein.

[0045] An interconnect structure 112 is located above the ILD 108 and the conductive plugs 110. The interconnect structure 112 interconnects the devices 106 to form an integrated circuit. The interconnect structure 112 may be formed, for example, by a metallization pattern in a dielectric layer on the ILD 108. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The same techniques as those described above may be used. Figure 1 Interconnect structure 112 is formed using similar materials and methods as described for interconnect structure 60 and will not be described again herein.

[0046] In some embodiments, wafer 100 further includes an insulating layer 116 and pads 114 embedded in insulating layer 116. Figure 1 The pad 114 is formed using materials and methods similar to those described for the pad 62 and will not be described again herein. Figure 1 Insulation layer 116 is formed using similar materials and methods as described for insulation layer 64 and will not be described again. In some embodiments, within the process variation of the planarization process, the top surface of insulation layer 116 and the top surface of pad 114 are substantially flush or substantially coplanar.

[0047] Figure 6 2 shows a cross-sectional view of a die region 200A of a wafer 200 according to some embodiments. Wafer 200 may also be referred to as an image sensor wafer. In some embodiments, wafer 200 includes a plurality of die regions (such as die region 200A). In some embodiments, wafer 200 includes substrate 202. Figure 1 Substrate 202 is formed by using materials and methods similar to those described for substrate 52, and will not be described again herein. Substrate 202 has an active surface (e.g., Figure 6 the upward-facing surface in the Figure 6 The downward-facing surface of the middle part of the body is sometimes called the posterior side.

[0048] A plurality of photosensitive pixels 218 are formed at the front surface (upper surface) of the substrate 202. The photosensitive pixels 218 include corresponding photosensitive devices (not shown), which may be formed, for example, by implanting appropriate impurity ions into the substrate 202. The photosensitive device is configured to convert an optical signal (e.g., photons) into an electrical signal, and may be a PN junction photodiode, a PNP phototransistor, an NPN phototransistor, etc. For example, the photosensitive device may include an n-type implanted region formed within a p-type semiconductor layer (e.g., at least a portion of the substrate 202). In such an embodiment, the p-type substrate may isolate and reduce electrical crosstalk between adjacent photosensitive regions of the photosensitive pixels 218. In an embodiment, the photosensitive pixels 218 extend from the front surface of the substrate 202 toward the rear surface of the substrate 202, and form an array of photosensitive pixels. In some embodiments, the photosensitive pixels 218 form a two-dimensional rectangular array when viewed from the top. In some embodiments, each photosensitive pixel 218 may also include a transfer gate transistor (not shown) and a floating diffusion capacitor (not shown). In each photosensitive pixel 218, a first source / drain region of a corresponding transfer-gate transistor is electrically coupled to a corresponding photosensitive device, and a second source / drain region of the corresponding transfer-gate transistor is electrically coupled to a corresponding floating diffusion capacitor.

[0049] In some embodiments, an isolation region 220 is formed in the substrate 202 between adjacent photosensitive pixels 218 to prevent electrical crosstalk between the photosensitive pixels 218. In some embodiments, the isolation region 220 may include a shallow trench isolation (STI) structure. In some embodiments, the STI structure may be formed by patterning the front surface of the substrate 202 to form a trench in the substrate 202 and filling the trench with a suitable dielectric material to form the STI structure. In some embodiments, the substrate 202 is patterned using a suitable photolithography and etching process. In other embodiments, the isolation region 220 may include various doped regions formed using a suitable implantation process.

[0050] A device (represented by a transistor) 206 may be formed at the front surface of the substrate 202. The device 206 may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, an inductor, etc., or a combination thereof. An ILD 208 is located above the front surface of the substrate 202. The ILD 208 surrounds and may cover the device 206. The same reference numerals as above may be used. Figure 1 ILD 208 is formed using similar materials and methods as described for ILD 56 , and will not be described again here.

[0051] Conductive plug 210 extends through ILD 208 to electrically and physically couple device 206. For example, when device 206 is a transistor, conductive plug 210 may couple the gate and source / drain regions of the transistor. Figure 1Conductive plug 210 is formed using similar materials and methods as described for conductive plug 58 , and will not be described again herein.

[0052] An interconnect structure 212 is located above the ILD 208 and the conductive plug 210. The interconnect structure 212 interconnects the devices 206 to form an integrated circuit. The interconnect structure 212 may be formed, for example, by a metallization pattern in a dielectric layer on the ILD 208. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The same reference numerals as above may be used. Figure 1 Interconnect structure 212 is formed using similar materials and methods as described for interconnect structure 60 and will not be described again herein.

[0053] In some embodiments, the wafer 200 further includes an insulating layer 216 and a pad 214 embedded in the insulating layer 216. Figure 1 The pad 214 is formed by using materials and methods similar to those of the pad 62 described above. The description will not be repeated here. Figure 1 Insulation layer 216 is formed using similar materials and methods as described for insulation layer 64 and will not be described again. In some embodiments, within the process variation of the planarization process, the top surface of insulation layer 216 and the top surface of pad 214 are substantially flush or substantially coplanar.

[0054] Figure 7 Wafer 100 is shown bonded to wafer 200. In some embodiments, wafer 100 is bonded to wafer 200 using a hybrid bonding method. The hybrid bonding method includes directly bonding pads 114 of wafer 100 to corresponding pads 214 of wafer 200, and directly bonding insulating layer 116 of wafer 100 to insulating layer 216 of wafer 200. In some embodiments, wafer 100 is bonded to wafer 200 such that a die region (such as die region 100A) of wafer 100 is bonded to a corresponding die region (such as die region 200A) of wafer 200.

[0055] Figure 8 A thinning process is shown performed on the back side of the substrate 102 of the wafer 100. In some embodiments, the thinning process includes CMP, grinding, etching, combinations thereof, etc. The thinning process removes portions of the substrate 102 and exposes the TSVs 104 formed in the substrate 102. In some embodiments, within process variations of the thinning process, the back surface of the substrate 102 and the exposed surface of the TSVs 104 are substantially flush or substantially coplanar.

[0056] Figures 9 to 14It is shown that a wafer-level package structure 3000 is formed on the back side of the wafer 100. The wafer-level package structure 3000 may also be referred to as a wafer-level integrated fan-out (InFO) structure. The wafer-level package structure 3000 includes a plurality of die regions, such as a die region 3000A. The die region 3000A of the wafer-level package structure 3000 corresponds to the die region 100A of the wafer 100 and the die region 200A of the wafer 200.

[0057] Fig. 9 An insulating layer 304 and pads 306 are shown formed on the back side of wafer 100. Figure 1 The pad 306 is formed by using materials and methods similar to those described for the pad 62 and will not be described again herein. Figure 1 Insulating layer 304 is formed by using materials and methods similar to those described for insulating layer 64, and will not be described again herein. In some embodiments, within the process variation of the planarization process, the top surface of insulating layer 304 and the top surface of pad 306 are substantially flush or substantially coplanar. In some embodiments, insulating layer 304 and pad 306 form a redistribution structure 302. In the embodiment shown, redistribution structure 302 includes a single conductive layer and a single insulating layer. In other embodiments, redistribution structure 302 may include multiple conductive layers and multiple insulating layers.

[0058] Fig.10 It is shown that a through hole 308 is formed above the pad 306 of the redistribution structure 302. As an example of forming a through hole 308, a seed layer (not shown) is formed above the insulating layer 304 and the pad 306. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer located above the titanium layer. The seed layer can be formed using, for example, PVD. A photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating, etc., and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to a conductive through hole. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. The portion of the photoresist and the seed layer on which the conductive material is not formed is removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portion of the seed layer and the conductive material form a via 308.

[0059] exist Fig.11In the embodiment shown, a plurality of integrated circuit dies 10 (e.g., a first integrated circuit die 10A and a second integrated circuit die 10B) are bonded to the back side of the wafer 100. The desired type and number of integrated circuit dies 10 are bonded in each die-level region. In the illustrated embodiment, the first integrated circuit die 10A and the second integrated circuit die 10B are bonded adjacent to each other. The first integrated circuit die 10A may be a logic device such as a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), a microcontroller, etc. In some embodiments, the first integrated circuit die 10A may include an integrated circuit configured for edge AI applications.

[0060] The second integrated circuit die 10B may be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. In some embodiments, the integrated circuit dies 10A and 10B may be dies of the same type, such as SoC dies. The first integrated circuit die 10A and the second integrated circuit die 10B may be formed in a process of the same technology node, or may be formed in a process of different technology nodes. For example, the first integrated circuit die 10A may have a more advanced process node than the second integrated circuit die 10B. The integrated circuit dies 10A and 10B may have different sizes (e.g., different heights and / or surface areas), or may have the same size (e.g., the same height and / or surface area).

[0061] In some embodiments, the integrated circuit dies 10A and 10B are bonded to the insulating layer 304 and the pads 306 of the redistribution structure 302 using a hybrid bonding method. The hybrid bonding method includes directly bonding the pads 62 of the integrated circuit dies 10A and 10B to the corresponding pads 306 of the redistribution structure 302, and directly bonding the insulating layer 64 of the integrated circuit dies 10A and 10B to the insulating layer 304 of the redistribution structure 302.

[0062] exist Fig.12 In the embodiment of the present invention, an encapsulant 310 is formed on and around the integrated circuit dies 10A and 10B and the through-hole 308. The encapsulant 310 may be a molding compound, an epoxy resin, etc. The encapsulant 310 may be applied by compression molding, transfer molding, etc., and the encapsulant 310 may be formed over the bonded wafers 100 and 200 so that the integrated circuit dies 10A and 10B and the through-hole 308 are buried or covered. The encapsulant 310 may be applied in a liquid or semi-liquid form and then subsequently cured.

[0063] exist Fig.13In the embodiment shown, after the planarization process is performed, the backside surfaces of the integrated circuit dies 10A and 10B are covered by the encapsulant 310. In other embodiments, after the planarization process is performed, the backsides of the integrated circuit dies 10A and 10B are exposed. Within the process variation of the planarization process, the top surface of the encapsulant 310 and the top surface of the through hole 308 are substantially coplanar. The planarization process may include CMP, grinding, etching, combinations thereof, and the like. In some embodiments, for example, if the through hole 308 is already exposed, the planarization may be omitted.

[0064] exist Fig.14 In the embodiment of the present invention, a redistribution structure 312 is formed over the encapsulant 310, the integrated circuit dies 10A and 10B, and the through-hole 308. The redistribution structure 312 includes insulating layers 314, 318, 322, and 326; and metallization patterns 316, 320, and 324. The metallization patterns may also be referred to as redistribution layers or redistribution lines. As an example with three layers of metallization patterns, a redistribution structure 312 is shown. More or fewer insulating layers and metallization patterns may be formed in the redistribution structure 312. If fewer insulating layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more insulating layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0065] In some embodiments, insulating layer 314 is deposited on encapsulant 120, integrated circuit dies 10A and 10B, and vias 308. In some embodiments, insulating layer 314 is formed of a photosensitive material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., and insulating layer 314 can be patterned using a photolithographic mask. Insulating layer 314 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. In other embodiments, insulating layer 314 can include non-photosensitive materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be formed by ALD, CVD, etc., or a combination thereof. Insulating layer 314 is then patterned. Patterning forms openings in insulating layer 314, which expose portions of vias 308. Patterning can be performed by an acceptable process, such as by exposing insulating layer 314 and developing it when insulating layer 314 is a photosensitive material, or by etching using, for example, anisotropic etching when insulating layer 314 is a non-photosensitive material.

[0066] Then form metallization pattern 316.Metallization pattern 316 includes conductive elements extending along the main surface of insulating layer 314 and extending through insulating layer 314 to be physically and electrically coupled to through hole 308.As an example of forming metallization pattern 316, a seed layer is formed above insulating layer 314 and in an opening extending through insulating layer 314.In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials.In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer.The seed layer can be formed using, for example, PVD.Then, a photoresist is formed on the seed layer and the photoresist is patterned.The photoresist can be formed by spin coating, etc., and the photoresist can be exposed to light for patterning.The pattern of the photoresist corresponds to metallization pattern 316.The patterning forms an opening through the photoresist to expose the seed layer.Then a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer.The conductive material can be formed by plating such as electroplating, chemical plating, etc. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the portion of the underlying seed layer forms the metallization pattern 316. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet or dry etching.

[0067] After forming the metallization pattern 316, an insulating layer 318 is deposited on the metallization pattern 316 and the insulating layer 314. The insulating layer 318 may be formed using similar materials and methods as the insulating layer 314.

[0068] The metallization pattern 320 is then formed. The metallization pattern 320 includes a portion located on the main surface of the insulating layer 318 and extending along the main surface of the insulating layer 318. The metallization pattern 320 also includes a portion extending through the insulating layer 318 to be physically and electrically coupled to the metallization pattern 316. The metallization pattern 320 can be formed using materials and methods similar to the metallization pattern 316. In some embodiments, the metallization pattern 320 has a different size than the metallization pattern 316. For example, the wires and / or vias of the metallization pattern 320 can be wider or thicker than the wires and / or vias of the metallization pattern 316. In addition, the metallization pattern 320 can be formed with a larger pitch than the metallization pattern 316.

[0069] After forming the metallization pattern 320, an insulating layer 322 is deposited on the metallization pattern 320 and the insulating layer 318. The insulating layer 322 may be formed using similar materials and methods as the insulating layer 314.

[0070] Then, a metallization pattern 324 is formed. The metallization pattern 324 includes a portion located on and extending along the main surface of the insulating layer 322. The metallization pattern 324 also includes a portion extending through the insulating layer 322 to be physically and electrically coupled to the metallization pattern 320. The metallization pattern 324 can be formed using materials and methods similar to the metallization pattern 316. The metallization pattern 324 is the topmost metallization pattern of the redistribution structure 312. Therefore, all the intermediate metallization patterns (e.g., metallization patterns 316 and 320) of the redistribution structure 312 are disposed between the metallization pattern 324 and the sealant 310. In some embodiments, the metallization pattern 324 has a different size from the metallization patterns 316 and 320. For example, the wires and / or vias of the metallization pattern 324 can be wider or thicker than the wires and / or vias of the metallization patterns 316 and 320. In addition, the metallization pattern 324 can be formed to have a larger pitch than the metallization patterns 316 and 320.

[0071] After forming the metallization pattern 324, an insulating layer 326 is deposited on the metallization pattern 324 and the insulating layer 322. The insulating layer 326 may be formed using similar materials and methods as the insulating layer 314. The insulating layer 326 is the topmost insulating layer of the redistribution structure 312. Therefore, all metallization patterns of the redistribution structure 312 (e.g., the metallization patterns 316, 320, and 324) are disposed between the insulating layer 326 and the sealant 310. In addition, all intermediate insulating layers of the redistribution structure 312 (e.g., the insulating layers 314, 318, 322) are disposed between the insulating layer 326 and the sealant 310.

[0072] Further in Fig.14 In the embodiment of the present invention, after forming the redistribution structure 312, the UBM 328 is formed for external connection to the redistribution structure 312. The UBM 328 has a bump portion located on and extending along the main surface of the insulating layer 326, and has a via portion extending through the insulating layer 326 to be physically and electrically coupled to the metallization pattern 324. As a result, the UBM 328 is electrically coupled to the via 308 and the integrated circuit dies 10A and 10B through the redistribution structure 312. The UBM 328 is formed of the same material as the metallization pattern 324. In some embodiments, the UBM 328 has a different size than the metallization patterns 316, 320, and 324.

[0073] After forming the UBM 328, a conductive connector 330 is formed on the UBM 328. The conductive connector 330 may be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a micro bump, a bump formed by electroless nickel electroless palladium immersion gold (ENEPIG), etc. The conductive connector 330 may be formed by using the same method as in the above reference. Figure 3Conductive connector 330 is formed using similar materials and methods as described for conductive connector 70 and will not be described again herein.

[0074] exist Fig.15 In Fig.14 The stacked wafer-level structure is flipped over and attached to a carrier substrate 332 using an adhesive 334. The carrier substrate 332 may be a glass carrier substrate, a ceramic carrier substrate, or the like. Subsequently, a thinning process is performed on the back side of the substrate 202 of the wafer 200. In some embodiments, the thinning process includes CMP, grinding, etching, a combination thereof, or the like. The thinning process removes a portion of the substrate 202 and reduces the distance between the back side surface of the substrate 202 and the photosensitive pixels 218.

[0075] exist Fig.16 , color filter 336 is formed over the backside surface of substrate 202 of wafer 200. In some embodiments, color filter 336 is aligned with photosensitive pixel 218. Color filter 336 can be used to allow light of specific wavelengths to pass through while reflecting other wavelengths, thereby allowing the image sensor to determine the color of light received by photosensitive pixel 218. Color filter 336 can vary, such as red, green, and blue filters for Bayer pattern. Other combinations, such as cyan, yellow, and magenta, can also be used. The number of different colors of color filter 336 can also vary. Color filter 336 can include a polymer material or resin, such as polymethyl methacrylate (PMMA), polyglycidyl methacrylate (PGMA), etc., including color pigments. In some embodiments, a reflective guide layer (not shown) is formed along the sidewalls of color filter 336. The reflective guide layer is formed of a metal or other high refractive index material capable of reflecting light, such as copper, aluminum, tantalum nitride, titanium nitride, tungsten, silicon nitride, etc., or a combination thereof.

[0076] Further in Fig.16 In the embodiment of the present invention, a dam structure 338 is formed over the backside surface of the substrate 202 of the wafer 200, and the dam structure 338 surrounds the color filter 336. In some embodiments, the dam structure 338 has an annular structure in a plan view. In some embodiments, the annular structure can be a ring, a square annular structure, etc. The dam structure 338 may include epoxy resin, silicone resin, etc. or a combination thereof. In some embodiments, the dam structure 338 is disposed in the die area 200A of the wafer 200. Subsequently, a cover 340 is attached to the dam structure 338. The cover 340 may include a transparent material such as glass. In some embodiments, the cover 340 is attached to the dam structure 338 using an adhesive (not shown).

[0077] exist Fig.17 In Fig.16 The stacked wafer-level structure is formed from a carrier substrate 332 (see Fig.16) are debonded and placed on a dicing tape 342. Subsequently, a singulation process 344 is performed by sawing along a scribe line region (e.g., between adjacent die regions of a stacked wafer-level structure). Sawing separates the die regions from the stacked wafer-level structure and forms a plurality of packages 1000. Each package 1000 includes a die region 100A of a wafer 100, a die region 200A of a wafer 200, and a die region 3000A of a wafer-level package structure 3000.

[0078] exist Fig.18 , the package 1000 is mounted to the package substrate 400 using the conductive connector 330. In some embodiments, the package substrate 400 includes a substrate core 402 and a bonding pad 404 located above the substrate core 402. The substrate core 402 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Optionally, compounds such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, etc. and combinations thereof can also be used. In addition, the substrate core 402 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an optional embodiment, the substrate core 402 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternative materials for the core material include bismaleimide triazine (BT) resin, or optionally other printed circuit board (PCB) materials or films. A deposited film such as ABF or other stack may be used for the substrate core 402 .

[0079] The substrate core 402 may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations thereof may be used to generate the structural and functional requirements for the design of the resulting device. Any suitable method may be used to form the device.

[0080] The substrate core 402 may also include metallization layers and vias (not shown), wherein the bonding pads 404 are physically and / or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectrics (e.g., low-k dielectric materials) and conductive materials (e.g., copper) and vias interconnecting the conductive material layers, and may be formed by any suitable process (e.g., deposition, inlay, dual inlay, etc.). In some embodiments, the substrate core 402 is substantially free of active and passive devices.

[0081] In some embodiments, the conductive connectors 330 are reflowed to attach the package 1000 to the bonding pads 404. The conductive connectors 330 electrically and / or physically couple the package substrate 400 (including the metallization layers in the substrate core 402) to the package 1000. In some embodiments, a solder resist 406 is formed on the substrate core 402. The conductive connectors 330 can be disposed in openings in the solder resist 406 to electrically and mechanically couple to the bonding pads 404. The solder resist 406 can be used to protect areas of the substrate core 402 from external damage.

[0082] In some embodiments, an underfill 408 may be formed between the package 1000 and the package substrate 400 and around the conductive connector 330. The underfill 408 may be formed by a capillary flow process after attaching the package 1000 to the package substrate 400, or may be formed by a suitable deposition method before attaching the package 1000 to the package substrate 400.

[0083] In some embodiments, passive devices (e.g., surface mount devices (SMDs), not shown) may also be attached to package 1000 (e.g., to UBM 328) or package substrate 400 (e.g., to bonding pads 404). For example, the passive devices may be bonded to the same surface of package 1000 or package substrate 400 as conductive connectors 330. The passive devices may be attached to package 1000 before package 1000 is mounted on package substrate 400, or may be attached to package substrate 400 before or after package 1000 is mounted on package substrate 400.

[0084] Fig.19 FIG. 4 shows a cross-sectional view of a package 1100 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 1100 is similar to Fig.18 The package 1000 shown in FIG. 1 is a package 1000 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated herein. Figures 5 to 18 The process steps described in the foregoing are used to form the package 1100, and the description is not repeated here. The die area 3100A of the package 1100 is similar to the die area 3000A of the package 1000, except that within the process variation, the lower surface of the encapsulant 310 of the die area 3100A is substantially flush with the lower surface of the through hole and the back side surface of the integrated circuit die 10A and 10B. In the embodiment shown, the insulating layer 314 of the redistribution structure 312 is in physical contact with the back side surface of the integrated circuit die 10A and 10B. In some embodiments, the encapsulant 310 is planarized so that the back side surfaces of the integrated circuit die 10A and 10B are also exposed in addition to the through hole 308.

[0085] Fig. 20 FIG. 4 shows a cross-sectional view of a package 1200 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 1200 is similar to Fig.18 The package 1000 shown in FIG. 1 is a package 1000 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated herein. Figures 5 to 18 The package 1200 is formed by the process steps described above and will not be described again herein. The die area 3200A of the package 1200 is similar to the die area 3000A of the package 1000, except that the integrated circuit die 30 (see FIG. Figure 3 ) instead of the integrated circuit die 10. In the illustrated embodiment, the integrated circuit die 30 (such as the first integrated circuit die 30A and the second integrated circuit die 30B) are bonded to the back side of the die area 100A adjacent to each other. The integrated circuit dies 30A and 30B are bonded to the pads 306 of the redistribution structure 302 using conductive connectors 70. The first integrated circuit die 30A can be a logic device such as a CPU, GPU, SoC, microcontroller, etc. In some embodiments, the first integrated circuit die 30A can include an integrated circuit configured for edge AI applications.

[0086] The second integrated circuit chip 30B may be a memory device such as a DRAM die, an SRAM die, an HMC module, a high bandwidth memory HBM module, etc. In some embodiments, the integrated circuit chips 30A and 30B may be the same type of die, such as a SoC die. The first integrated circuit die 30A and the second integrated circuit die 30B may be formed in a process of the same technology node, or may be formed in a process of different technology nodes. For example, the first integrated circuit die 30A may have a more advanced process node than the second integrated circuit die 30B. The integrated circuit dies 30A and 30B may have different sizes (e.g., different heights and / or surface areas), or may have the same size (e.g., the same height and / or surface area).

[0087] Fig.21 FIG. 1 shows a cross-sectional view of a package 1300 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 1300 is similar to Fig. 20 The package 1200 shown in FIG. 1 is a package 1200 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated here. In some embodiments, the above reference numerals may be used. Figures 5 to 18 and Fig. 20The package 1300 is formed by the process steps described in the foregoing, and the description is not repeated here. The die area 3300A of the package 1300 is similar to the die area 3200A of the package 1200, except that within the process variation, the lower surface of the encapsulant 310 of the die area 3300A is substantially flush with the lower surface of the through hole 308 and the back side surface of the integrated circuit die 30A and 30B. In the embodiment shown, the insulating layer 314 of the redistribution structure 312 is in physical contact with the back side surface of the integrated circuit die 30A and 30B. In some embodiments, the encapsulant 310 is planarized so that the back side surface of the integrated circuit die 30A and 30B is also exposed in addition to the through hole 308.

[0088] Figure 22 to Figure 27 1400 is a cross-sectional view showing an intermediate step during a process of forming package 1400 according to some embodiments. Figure 22 to Figure 27 Some of the components and process steps described may be similar to those in the above reference Figures 5 to 18 The components and process steps described are similar, and the descriptions of similar components and process steps are not repeated here. Figure 22 to Figure 24 FIG. 3 shows a wafer-level package structure 3400 formed on the back side of the wafer 100 after the wafer 100 is bonded to the wafer 200. Figure 7 The wafer 100 is bonded to the wafer 200 , and the description is not repeated here.

[0089] exist Fig. 22 In some embodiments, the backside surface of the wafer 100 is thinned to expose the TSV 104, and a redistribution structure 302 including an insulating layer 304 and a pad 306 is formed on the backside of the wafer 100. Figure 8 The back side surface of the thinned wafer 100 is not repeatedly described here. In some embodiments, as described above with reference to Fig. 9 The redistribution structure 302 is formed and will not be described again herein. Subsequently, the plurality of integrated circuit dies 10 (e.g., the first integrated circuit die 10A and the second integrated circuit die 10B) are bonded to the back side of the wafer 100 using the insulating layer 304 and the pads 306 of the redistribution structure 302. In some embodiments, as described above with reference to Fig.11 The first integrated circuit die 10A and the second integrated circuit die 10B are bonded to the back side of the wafer 100 and will not be described again herein.

[0090] exist Fig.23 In, as mentioned above Fig.12 As described above, encapsulant 310 is formed on and around integrated circuit dies 10A and 10B, and description thereof will not be repeated herein.

[0091] exist Fig.24In the embodiment of the present invention, a planarization process is performed on the encapsulant 310 to expose the backside surfaces of the integrated circuit dies 10A and 10B. The planarization process can also remove portions of the backsides of the integrated circuit dies 10A and 10B. Within the process variation of the planarization process, the top surface of the encapsulant 310 and the backside surfaces of the integrated circuit dies 10A and 10B are substantially coplanar or substantially flush. The planarization process can include CMP, grinding, etching, combinations thereof, and the like.

[0092] exist Fig.25 In Fig.24 The stacked wafer-level structure is flipped over and attached to a carrier substrate 332 using adhesive 334. Subsequently, as described above with reference to Fig.15 As described above, a thinning process is performed on the back side of the substrate 202 of the wafer 200, and the description is not repeated here. After the thinning process is performed, as described above with reference to Fig.16 As described above, a color filter 336 is formed over the backside surface of the substrate 202 of the wafer 200, and the description is not repeated here. Fig.16 As described above, the dam structure 338 is formed over the backside surface of the substrate 202 of the wafer 200 and around the color filter 336, and the description is not repeated here. Fig.16 As described above, the cover 340 is attached to the dam structure 338, and the description is not repeated here. In some embodiments, the pad 346 is formed on the back side of the substrate 202 of the wafer 200. In some embodiments, the pad 346 is disposed outside the dam structure 338 but within the die area 200A of the wafer 200. The pad 346 may include the same as described above with reference to Figure 1 The pads 346 may be used to couple the resulting package to external devices.

[0093] exist Fig.26 In Fig.25 The stacked wafer-level structure is formed from a carrier substrate 332 (see Fig.25 ) are debonded and placed on a dicing tape 342. Subsequently, a singulation process 344 is performed by sawing along the scribe line area (e.g., between adjacent die areas of the stacked wafer-level structure). Sawing separates the die areas from the stacked wafer-level structure and forms packages 1400. Each package 1400 includes the die area 100A of the wafer 100, the die area 200A of the wafer 200, and the die area 3400A of the wafer-level package structure 3400.

[0094] exist Fig. 27, package 1400 is attached to package substrate 400 using adhesive 350. In some embodiments, package 1400 is electrically coupled to package substrate 400 by coupling pads 346 of package 1400 to bonding pads 404 of package substrate 400 using wire connectors 348. In some embodiments, wire connectors 348 are bonded to pads 346 and 404 using thermocompression bonding, ultrasonic bonding, thermosonic bonding, or the like.

[0095] Fig.28 FIG. 4 shows a cross-sectional view of a package 1500 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 1500 is similar to Fig. 27 The package 1400 shown in FIG. 1 is a package 1400 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated here. In some embodiments, the above reference numerals may be used. Figure 22 to Figure 27 Package 1500 is formed by the process steps described above and will not be repeated here. The die area 3500A of package 1500 is similar to the die area 3400A of package 1400, except that a portion of the encapsulant 310 is interposed between the adhesive 350 and the back side of the integrated circuit dies 10A and 10B. In such an embodiment, the encapsulant 310 is planarized so that the back side of the integrated circuit dies 10A and 10B is not exposed after the planarization process is performed.

[0096] Fig.29 FIG. 1 shows a cross-sectional view of a package 1600 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 1600 is similar to Fig. 27 The package 1400 shown in FIG. 1 is a package 1400 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated here. In some embodiments, the above reference numerals may be used. Figure 22 to Figure 27 The process steps described above are used to form the package 1600, and the description is not repeated here. The die area 3600A of the package 1600 is similar to the die area 3400A of the package 1400, except that the integrated circuit die 30 (see Figure 3 ) instead of the integrated circuit die 10. In the illustrated embodiment, the integrated circuit die 30 (such as the first integrated circuit die 30A and the second integrated circuit die 30B) are bonded to the back side of the die area 100A adjacent to each other. The integrated circuit dies 30A and 30B are bonded to the pads 306 of the redistribution structure 302 using conductive connectors 70. The first integrated circuit die 30A can be a logic device such as a CPU, GPU, SoC, microcontroller, etc. In some embodiments, the first integrated circuit die 30A can include an integrated circuit configured for edge AI applications.

[0097] The second integrated circuit die 30B may be a memory device such as a DRAM die, an SRAM die, an HMC module, a high bandwidth memory HBM module, etc. In some embodiments, the integrated circuit chips 30A and 30B may be the same type of die, such as a SoC die. The first integrated circuit die 30A and the second integrated circuit die 30B may be formed in a process of the same technology node, or may be formed in a process of different technology nodes. For example, the first integrated circuit die 30A may have a more advanced process node than the second integrated circuit die 30B. The integrated circuit dies 30A and 30B may have different sizes (e.g., different heights and / or surface areas), or may have the same size (e.g., the same height and / or surface area).

[0098] Fig.30 FIG. 1 shows a cross-sectional view of a package 1700 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 1700 is similar to FIG. Fig.29 The package 1600 shown in FIG. 1 is a package 1600 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated here. In some embodiments, the above reference numerals may be used. Figure 22 to Figure 27 and Fig.29 The process steps described above are used to form package 1700, and will not be repeated here. The die area 3700A of package 1700 is similar to the die area 3600A of package 1600 (see Fig.29 ), except that a portion of encapsulant 310 is interposed between adhesive 350 and the backside of integrated circuit dies 30A and 30B. In such an embodiment, encapsulant 310 is planarized so that the backside of integrated circuit dies 30A and 30B is not exposed after the planarization process is performed.

[0099] Figure 31 to Figure 36 18 is a cross-sectional view showing an intermediate step during a process of forming package 1800 according to some embodiments. Figure 31 to Figure 36 Some of the components and process steps described may be similar to those in the above reference Figures 5 to 18 The components and process steps described are similar, and the description of similar components and process steps will not be repeated here. Figure 31 to Figure 33 1 and 2. The wafer level package structure 3800 is shown formed on the back side of the wafer 100 after the wafer 100 is bonded to the wafer 200. The wafer level package structure 3800 may also be referred to as a wafer level integrated fan-out (InFO) structure. The wafer 100 may be formed as described above with reference to FIG. Figure 7 The bonding to wafer 200 is described above and will not be repeated here.

[0100] exist Fig.31In the embodiment, the back side of the wafer 100 is thinned to expose the TSV 104, and after thinning, a redistribution structure 302 including an insulating layer 304 and a pad 306 is formed on the back side of the wafer 100. In some embodiments, as described above with reference to Figure 8 The back side of the thinned wafer 100 is not described again here. In some embodiments, as described above with reference to Fig. 9 The redistribution structure 302 is formed and will not be described again here.

[0101] Subsequently, a plurality of integrated circuit dies 20 (see Figure 2 ) (such as a first integrated circuit die 20A and a second integrated circuit die 20B) are bonded to the back side of the wafer 100. A desired type and number of integrated circuit dies 20 are bonded in each die area (such as die area 100A) of the wafer 100. In the illustrated embodiment, the first integrated circuit die 20A and the second integrated circuit die 20B are bonded adjacent to each other. The first integrated circuit die 20A may be a logic device, such as a CPU, a GPU, a SoC, a microcontroller, etc. In some embodiments, the first integrated circuit die 20A may include an integrated circuit configured for edge AI applications.

[0102] The second integrated circuit die 20B can be a memory device, such as a DRAM die, an SRAM die, an HMC module, an HBM module, etc. In some embodiments, the integrated circuit chips 20A and 20B can be the same type of die, such as a SoC die. The first integrated circuit die 20A and the second integrated circuit die 20B can be formed in a process of the same technology node, or can be formed in a process of different technology nodes. For example, the first integrated circuit die 20A can have a more advanced process node than the second integrated circuit die 20B. The integrated circuit dies 20A and 20B can have different sizes (e.g., different heights and / or surface areas), or can have the same size (e.g., the same height and / or surface area).

[0103] In some embodiments, a hybrid bonding method is used to bond the integrated circuit dies 20A and 20B to the insulating layer 304 and the pads 306 of the redistribution structure 302. The hybrid bonding method includes directly bonding the pads 62 of the integrated circuit dies 20A and 20B to the corresponding pads 306 of the redistribution structure 302, and directly bonding the insulating layer 64 of the integrated circuit dies 20A and 20B to the insulating layer 304 of the redistribution structure 302.

[0104] exist Fig.32 In, as mentioned above Fig.12As described above, a sealant 310 is formed on and around the integrated circuit dies 20A and 20B, and the description is not repeated here. Subsequently, a planarization process is performed on the sealant 310 to expose the rear side surface of the integrated circuit dies 20A and 20B. The planarization process also exposes the TSV 66 of the integrated circuit dies 20A and 20B. The planarization process can also remove parts of the rear side of the integrated circuit dies 20A and 20B and parts of the TSV 66. Within the process variation of the planarization process, the top surface of the sealant 310, the rear side surface of the integrated circuit dies 20A and 20B are substantially coplanar or substantially flush with the exposed surface of the TSV 66. The planarization process may include CMP, grinding, etching, combinations thereof, and the like.

[0105] exist Fig.33 In the embodiment, a redistribution structure 502 is formed over the encapsulant 310 and the integrated circuit dies 20A and 20B. The redistribution structure 502 includes insulating layers 504, 508, 512, and 516; and metallization patterns 506, 510, and 514. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The redistribution structure 502 is shown as an example having three layers of metallization patterns. More or fewer insulating layers and metallization patterns may be formed in the redistribution structure 502. The same reference numerals as above may be used. Fig.14 The redistribution structure 502 is formed using materials and methods similar to those described above for the redistribution structure 312 and will not be described again herein. Fig.14 Insulating layers 504, 508, 512, and 516 are formed using materials and methods similar to those described for insulating layer 314, and are not described again herein. Fig.14 The metallization patterns 506, 510 and 514 are formed by using similar materials and methods as described in the metallization pattern 316, and are not described again here. Fig.14 As described above, the UBM 328 and the corresponding conductive connector 330 are formed over the redistribution structure 502 , and the description thereof will not be repeated herein.

[0106] exist Fig.34 In Fig.33 The stacked wafer-level structure is flipped over and attached to a carrier substrate 332 using adhesive 334. Subsequently, as described above with reference to Fig.15 As described above, a thinning process is performed on the back side of the substrate 202 of the wafer 200, and the description is not repeated here. After the thinning process is performed, as described above with reference to Fig.16 As described above, color filter 336 is formed over the back side of substrate 202 of wafer 200, and will not be described again here. Fig.16As described above, the dam structure 338 is formed over the backside surface of the substrate 202 of the wafer 200 and around the color filter 336, and the description is not repeated here. Fig.16 As described above, the cover 340 is attached to the dam structure 338, and the description is not repeated here.

[0107] exist Fig.35 In Fig.34 The stacked wafer-level structure is formed from a carrier substrate 332 (see Fig.34 ) are debonded and placed on a dicing tape 342. Subsequently, a singulation process 344 is performed by sawing along a scribe line region (e.g., between adjacent die regions of a stacked wafer-level structure). Sawing separates the die regions from the stacked wafer-level structure and forms packages 1800. Each package 1800 includes a die region 100A of a wafer 100, a die region 200A of a wafer 200, and a die region 3800A of a wafer-level package structure 3800.

[0108] exist Fig.36 In, as mentioned above Fig.18 As described above, the package 1800 is attached to the package substrate 400 using the connector 330. Subsequently, as described above with reference to Fig.18 As described above, the underfill 408 is formed between the package 1800 and the package substrate 400 and around the conductive connection 330 .

[0109] Fig.37 FIG. 1 shows a cross-sectional view of a package 1900 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 1900 is similar to Fig.36 The package 1800 shown in FIG. 1 is a package 1800 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated here. In some embodiments, the above reference numerals may be used. Figure 31 to Figure 36 The process steps described above are used to form the package 1900, and the description is not repeated here. The die area 3900A of the package 1900 is similar to the die area 3800A of the package 1800, except that the integrated circuit die 40 (see Figure 4 ) instead of the integrated circuit die 10. In the illustrated embodiment, the integrated circuit die 40 (such as the first integrated circuit die 40A and the second integrated circuit die 40B) are bonded to the back side of the die area 100A adjacent to each other. The integrated circuit dies 40A and 40B are bonded to the pads 306 of the redistribution structure 302 using conductive connectors 70. The first integrated circuit die 40A can be a logic device such as a CPU, GPU, SoC, microcontroller, etc. In some embodiments, the first integrated circuit die 40A can include an integrated circuit configured for edge AI applications.

[0110] The second integrated circuit die 40B may be a memory device such as a DRAM die, an SRAM die, an HMC module, a high bandwidth memory HBM module, etc. In some embodiments, the integrated circuit dies 40A and 40B may be the same type of die, such as a SoC die. The first integrated circuit die 40A and the second integrated circuit die 40B may be formed in a process of the same technology node, or may be formed in a process of different technology nodes. For example, the first integrated circuit die 40A may have a more advanced process node than the second integrated circuit die 40B. The integrated circuit dies 40A and 40B may have different sizes (e.g., different heights and / or surface areas), or may have the same size (e.g., the same height and / or surface area).

[0111] Figures 38 to 43 2000 is a cross-sectional view showing an intermediate step during a process of forming package 2000 according to some embodiments. Figure 33 to Figure 43 Some of the components and process steps described may be similar to those in the above reference Figures 5 to 18 The components and process steps described are similar, and the descriptions of similar components and process steps are not repeated here. Figures 38 to 40 1 and 2. The wafer-level package structure 4000 is shown formed on the back side of the wafer 100 after the wafer 100 is bonded to the wafer 200. The wafer-level package structure 4000 may also be referred to as a wafer-level integrated fan-out (InFO) structure. The wafer 100 may be formed as described above with reference to FIG. Figure 7 The ground is bonded to the wafer 200 and will not be described again here.

[0112] exist Fig.38 In the embodiment, the back side of the wafer 100 is thinned to expose the TSV 104, and a redistribution structure 302 including an insulating layer 304 and a pad 306 is formed on the back side of the wafer 100 after thinning. Figure 8 The back side surface of the thinned wafer 100 is not repeatedly described here. In some embodiments, as described above with reference to Fig. 9 The redistribution structure 302 is formed, and the description is not repeated here. After the redistribution structure 302 is formed, as described above with reference to Fig.10 As described above, the through hole 308 is formed above the pad 306 of the redistribution structure 302 , and the description thereof will not be repeated herein.

[0113] Subsequently, a plurality of die stacks (such as die stack 606 including integrated circuit dies 10 and 20) are bonded to the back side of wafer 100. Integrated circuit die 20 may be a logic device, such as a CPU, GPU, SoC, microcontroller, etc. In some embodiments, integrated circuit die 20 may include an integrated circuit configured for edge AI applications. Integrated circuit die 10 may be a memory device such as a DRAM die, an SRAM die, an HMC module, an HBM module, etc. Integrated circuit die 10 and integrated circuit die 20 may be formed in a process of the same technology node, or may be formed in a process of different technology nodes. For example, integrated circuit die 20 may have a more advanced process node than integrated circuit die 10. Integrated circuit dies 10 and 20 may have different sizes (e.g., different heights and / or surface areas), or may have the same size (e.g., the same height and / or surface area).

[0114] In some embodiments, the die stack 606 is formed by bonding the integrated circuit die 10 to the integrated circuit die 20. In some embodiments, the insulating layer 604 and the pad 602 are formed on the back side of the integrated circuit die 20. Figure 1 The insulating layer 604 and the pad 602 are formed by materials and methods similar to those described above for the insulating layer 64 and the pad 62, and are not described again herein. A hybrid bonding method may be used to bond the integrated circuit die 10 to the integrated circuit die 20. The hybrid bonding method includes directly bonding the pad 62 of the integrated circuit die 10 to the corresponding pad 602 of the integrated circuit die 20, and directly bonding the insulating layer 64 of the integrated circuit die 10 to the insulating layer 604 of the integrated circuit die 20.

[0115] After forming the die stack 606, a hybrid bonding method is used to attach the die stack 606 to the back side of the wafer 100. The hybrid bonding method includes directly bonding the pads 62 of the integrated circuit die 20 to the corresponding pads 306 of the redistribution structure 302, and directly bonding the insulating layer 64 of the integrated circuit die 20 to the insulating layer 304 of the redistribution structure 302.

[0116] exist Fig.39 In, as mentioned above Fig.12 As mentioned above, encapsulant 310 is formed on and around die stack 606 and through-hole 308 , and description thereof will not be repeated herein.

[0117] exist Fig.40In some embodiments, after performing the planarization process, a portion of the encapsulant 310 covers the back side of the integrated circuit die 10. The planarization process may also remove a portion of the through hole 308. Within the process variation of the planarization process, the top surface of the encapsulant 310 and the exposed surface of the through hole 308 are substantially coplanar or substantially flush. The planarization process may include CMP, grinding, etching, combinations thereof, etc. After performing the planarization process, as described above with reference to Fig.14 As described above, a redistribution structure 312 is formed over the sealant 310 and the through hole 308, and the description is not repeated here. After the redistribution structure 312 is formed, as described above with reference to Fig.14 As described above, the UBM 328 and the corresponding conductive connector 330 are formed over the redistribution structure 312 , and the description thereof will not be repeated herein.

[0118] exist Fig.41 In Fig.40 The stacked wafer-level structure is flipped over and attached to a carrier substrate 332 using adhesive 334. Subsequently, as described above with reference to Fig.15 As described above, a thinning process is performed on the back side of the substrate 202 of the wafer 200, and the description is not repeated here. After the thinning process is performed, as described above with reference to Fig.16 As described above, color filter 336 is formed over the back side of substrate 202 of wafer 200, and will not be described again here. Fig.16 As described above, the dam structure 338 is formed over the backside surface of the substrate 202 of the wafer 200 and around the color filter 336, and the description is not repeated here. Fig.16 As described above, the cover 340 is attached to the dam structure 338, and the description is not repeated here.

[0119] exist Fig.42 In Fig.41 The stacked wafer-level structure is formed from a carrier substrate 332 (see Fig.41 ) are debonded and placed on a dicing tape 342. Subsequently, a singulation process 344 is performed by sawing along a scribe line region (e.g., between adjacent die regions of a stacked wafer-level structure). Sawing separates the die regions from the stacked wafer-level structure and forms packages 2000. Each package 2000 includes the die region 100A of the wafer 100, the die region 200A of the wafer 200, and the die region 4000A of the wafer-level package structure 4000.

[0120] exist Fig.43 In, as mentioned above Fig.18 As described above, the package 2000 is attached to the package substrate 400 using the conductive connector 330. Subsequently, as described above with reference to Fig.18As described above, the underfill 408 is formed between the package 2000 and the package substrate 400 and around the conductive connection 330 .

[0121] Fig.44 FIG. 4 shows a cross-sectional view of a package 2100 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 2100 is similar to FIG. Fig.43 The package 2000 shown in FIG. 1 is a package 2000 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated herein. Figures 38 to 43 The package 2100 is formed by the process steps described in the foregoing, and the description is not repeated here. The die area 4100A of the package 2100 is similar to the die area 4000A of the package 2000, except that the lower surface of the encapsulant 310 of the die area 4100A is substantially coplanar or substantially flush with the lower surface of the through-hole 308 and the backside surface of the integrated circuit die 10 of the die stack 606. In the illustrated embodiment, the insulating layer 314 of the redistribution structure 312 is in physical contact with the backside surface of the integrated circuit die 10. The encapsulant 310 is planarized so that the backside surface of the integrated circuit die 10 is also exposed in addition to the through-hole 308.

[0122] Fig.45 FIG. 4 shows a cross-sectional view of a package 2200 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 2200 is similar to Fig.43 The package 2000 shown in FIG. 1 is a package 2000 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated herein. Figures 38 to 43 The process steps described above are used to form package 2200, and will not be repeated here. The die area 4200A of package 2200 is similar to the die area 4000A of package 2000, except that die stack 608 is packaged instead of die stack 606. Die stack 608 includes a die stack bonded to integrated circuit die 40 (see FIG. 1 ). Figure 4 ) of the integrated circuit die 10 (see Figure 1 ). In some embodiments, using the above reference Fig.38 The hybrid bonding method described herein bonds the integrated circuit die 10 to the integrated circuit die 40 and is not described again herein. The die stack 608 is bonded to the pad 306 of the redistribution structure 302 using the conductive connector 70 of the integrated circuit die 40. The integrated circuit die 40 may be a logic device such as a CPU, a GPU, a SoC, a microcontroller, etc. In some embodiments, the integrated circuit die 40 may include an integrated circuit configured for edge AI applications.

[0123] The integrated circuit die 10 may be a memory device such as a DRAM die, an SRAM die, an HMC module, a high bandwidth memory HBM module, etc. In some embodiments, the integrated circuit dies 10 and 40 may be the same type of die, such as an SoC die. The integrated circuit die 10 and the integrated circuit die 40 may be formed in a process of the same technology node, or may be formed in a process of different technology nodes. For example, the integrated circuit die 40 may have a more advanced process node than the integrated circuit die 10. The integrated circuit dies 10 and 40 may have different sizes (e.g., different heights and / or surface areas), or may have the same size (e.g., the same height and / or surface area).

[0124] Fig.46 FIG. 4 shows a cross-sectional view of a package 2300 bonded to a package substrate 400 according to some embodiments. In some embodiments, the package 2300 is similar to Fig.45 The package 2200 shown in FIG. 1 is a package 2200 in which similar components are labeled with similar reference numerals, and detailed descriptions of similar components are not repeated here. In some embodiments, the above reference numerals may be used. Figures 38 to 43 and Fig.45 The package 2300 is formed by the process steps described in the above description, and will not be repeated here. The die area 4300A of the package 2300 is similar to the die area 4200A of the package 2200, except that the lower surface of the encapsulant 310 of the die area 4300A is substantially coplanar or substantially flush with the lower surface of the through-hole 308 and the backside surface of the integrated circuit die 10 of the die stack 608. In the illustrated embodiment, the insulating layer 314 of the redistribution structure 312 is in physical contact with the backside surface of the integrated circuit die 10. In such an embodiment, the encapsulant 310 is planarized so that the backside surface of the integrated circuit die 10 is also exposed in addition to the through-hole 308.

[0125] Fig.47 4700 is a flowchart illustrating a method 4700 of forming a package according to some embodiments. The method 4700 begins at step 4701, wherein as described above with reference to Figure 7 As described above, a logic wafer (such as Figure 7 Wafer 100 is shown bonded to an image sensor wafer such as Figure 7 In step 4703, as described above with reference to the wafer 200 shown in FIG. Fig. 9 As described above, a first redistribution structure (such as Fig. 9 In step 4705, as described above with reference to Fig.10 The first conductive pillar (such as Fig.10 The through hole 308 shown) and the second conductive pillar (such as Fig.10In step 4707, as described above with reference to Fig.11 The first integrated circuit die (such as Fig.11 The integrated circuit die 10A shown) and a second integrated circuit die (such as Fig.11 In some embodiments, the first integrated circuit die 10B is bonded to the first redistribution structure. In some embodiments, the first integrated circuit die is a logic die. In some embodiments, a hybrid bonding method is used to bond the first integrated circuit die and the second integrated circuit die to the first redistribution structure. In other embodiments, a conductive connector is used to bond the first integrated circuit die and the second integrated circuit die to the first redistribution structure. In other embodiments, the first integrated circuit die and the second integrated circuit die are bonded to the first redistribution structure so that the first integrated circuit die and the second integrated circuit die form a die stack above the first redistribution structure. In step 4709, as described above with reference to Fig.12 The first integrated circuit die and the second integrated circuit die are sealed in a sealant (such as Fig.12 In step 4711, as described above with reference to Fig.14 The second redistribution structure (such as a first integrated circuit die and a second integrated circuit die) is formed over the encapsulant, the first integrated circuit die and the second integrated circuit die, and the first conductive pillar and the second conductive pillar. Fig.14 In step 4713, as described above with reference to Fig.16 As described above, color filters (such as Fig.16 In step 4715, as described above with reference to the color filter 336. Fig.16 As described above, a dam structure (such as Fig.16 In step 4717, as described above with reference to the dam structure 338 shown in FIG. Fig.16 As described above, the cover (such as Fig.16 In other embodiments, the cover 340 shown in FIG. 4 is attached to the dam structure above the color filter. In other embodiments, step 4705 can be omitted. In other embodiments, steps 4705 and 4711 can be omitted.

[0126] Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows the 3D package or 3DIC to be tested using a probe and / or a probe card. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0127] According to an embodiment, a semiconductor device includes: a first logic die including a first through-hole; an image sensor die hybridly bonded to the first logic die, the front side of the first logic die facing the front side of the image sensor die; and a second logic die bonded to the first logic die, the front side of the second logic die facing the back side of the first logic die, the second logic die including a first conductive pad electrically coupled to the first through-hole. In an embodiment, the second logic die is hybrid bonded to the first logic die. In an embodiment, the second logic die is bonded to the first logic die using a plurality of first connectors. In an embodiment, the semiconductor device also includes a memory die bonded to the first logic die, the front side of the memory die facing the back side of the first logic die. In an embodiment, the memory die is hybrid bonded to the first logic die. In an embodiment, the memory die is bonded to the first logic die using a plurality of second connectors. In an embodiment, the semiconductor device also includes a memory die hybrid bonded to the second logic die, the front side of the memory die facing the back side of the second logic die.

[0128] According to another embodiment, a semiconductor device includes: a first logic die, the front side of the first logic die includes a first insulating layer and a first conductive pad, the back side of the first logic die includes a second insulating layer and a second conductive pad; an image sensor die bonded to the first logic die, the front side of the image sensor die includes a third insulating layer and a third conductive pad, the third conductive pad is in physical contact with the first conductive pad, and the third insulating layer is in physical contact with the first insulating layer; and a second logic die bonded to the first logic die, the front side of the second logic die includes a fourth insulating layer and a fourth conductive pad, and the fourth insulating layer faces the second insulating layer. In an embodiment, the second insulating layer is in physical contact with the fourth insulating layer, and the second conductive pad is in physical contact with the fourth conductive pad. In an embodiment, the semiconductor device further includes a conductive connector that electrically and mechanically couples the second conductive pad to the fourth conductive pad. In an embodiment, the semiconductor device further includes an encapsulant extending along a sidewall of the second logic die. In an embodiment, the semiconductor device further includes a through hole extending through the encapsulant adjacent to the second logic die. In an embodiment, the semiconductor device further includes a redistribution structure electrically coupled to the via, the second logic die being interposed between the redistribution structure and the first logic die. In an embodiment, a portion of the encapsulant is interposed between the second logic die and the redistribution structure.

[0129] According to yet another embodiment, a method includes bonding a logic wafer to an image sensor wafer. The front side of the logic wafer includes a first conductive pad. The front side of the image sensor wafer includes a second conductive pad. Bonding the logic wafer to the image sensor wafer includes bonding the first conductive pad directly to the second conductive pad. A first redistribution structure is formed on the back side of the logic wafer. Bonding the logic die to the first redistribution structure. The front side of the logic die includes a third conductive pad. The third conductive pad is electrically coupled to the first redistribution structure. In an embodiment, bonding the logic die to the first redistribution structure includes bonding the third conductive pad of the logic die directly to a fourth conductive pad of the first redistribution structure. In an embodiment, bonding the logic die to the first redistribution structure includes electrically and mechanically coupling the third conductive pad of the logic die to the fourth conductive pad of the first redistribution structure using a conductive connector. In an embodiment, the method also includes forming an encapsulant on the first redistribution structure and around the logic die. In an embodiment, the method also includes forming a second redistribution structure in electrical contact with the first redistribution structure, with the logic die being between the first redistribution structure and the second redistribution structure. In an embodiment, the method further includes forming a conductive pillar over the first redistribution structure before bonding the logic die to the first redistribution structure, the conductive pillar electrically coupling the first redistribution structure to the second redistribution structure.

[0130] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a first logic die including a first through-via; an image sensor die hybrid-bonded to the first logic die, the front side of the first logic die facing the front side of the image sensor die; as well as a second logic die bonded to the first logic die, the front side of the second logic die facing the back side of the first logic die, the second logic die comprising a first conductive pad electrically coupled to the first through-via; an encapsulant extending along a sidewall of the second logic die, a first surface of the encapsulant being spaced from the first logic die by a distance greater than a distance between the first surface of the encapsulant and a back side of the second logic die, the first surface of the encapsulant and the back side of the second logic die facing away from the first logic die; A redistribution structure is located on the first surface of the sealant, the second logic die is between the first logic die and the redistribution structure, a portion of the sealant is between the back side of the second logic die and the redistribution structure, and the back side of the second logic die faces the redistribution structure.

2. The semiconductor device according to claim 1, wherein The second logic die is hybrid bonded to the first logic die.

3. The semiconductor device according to claim 1, wherein The second logic die is bonded to the first logic die using a plurality of first connectors.

4. The semiconductor device according to claim 1, further comprising: A memory die bonded to the first logic die, the front side of the memory die facing the back side of the first logic die.

5. The semiconductor device according to claim 4, wherein: The memory die is hybrid bonded to the first logic die.

6. The semiconductor device according to claim 4, wherein: The memory die is bonded to the first logic die using a plurality of second connectors. 7 . The semiconductor device of claim 1 , further comprising a memory die hybrid-bonded to the second logic die, a front side of the memory die facing a back side of the second logic die.

8. A semiconductor device comprising: a first logic die, the front side of the first logic die comprising a first insulating layer and a first conductive pad, the back side of the first logic die comprising a second insulating layer and a second conductive pad; an image sensor die bonded to the first logic die, the front side of the image sensor die comprising a third insulating layer and a third conductive pad, the third conductive pad being in physical contact with the first conductive pad, and the third insulating layer being in physical contact with the first insulating layer; as well as a second logic die bonded to the first logic die, the front side of the second logic die comprising a fourth insulating layer and a fourth conductive pad, the back side of the second logic die comprising a fifth insulating layer and a fifth conductive pad, the fourth insulating layer facing the second insulating layer; a memory die connected to a second logic die, the memory die having a width smaller than a width of the first logic die, the front side of the memory die comprising a sixth insulating layer and a sixth conductive pad, the sixth conductive pad being in physical contact with the fifth conductive pad, and the sixth insulating layer being in physical contact with the fifth insulating layer; an encapsulant extending along sidewalls of the second logic die and along sidewalls of the memory die, a portion of the encapsulant extending along and in physical contact with a back side of the memory die, the back side of the memory die being relative to a front side of the memory die, the combined height of the second logic die and the memory die being less than a height of the encapsulant.

9. The semiconductor device according to claim 8, wherein: The second insulating layer is in physical contact with the fourth insulating layer, and wherein the second conductive pad is in physical contact with the fourth conductive pad.

10. The semiconductor device according to claim 8, further comprising: A conductive connector electrically and mechanically couples the second conductive pad to the fourth conductive pad.

11. The semiconductor device according to claim 8, wherein The second logic die includes a through via that is in physical contact with the fifth conductive pad. 12 . The semiconductor device of claim 11 , further comprising a via extending through the encapsulant adjacent the second logic die.

13. The semiconductor device according to claim 12, further comprising: A redistribution structure is electrically coupled to the through-via, the second logic die being interposed between the redistribution structure and the first logic die.

14. The semiconductor device according to claim 13, wherein: A portion of the encapsulant is between the second logic die and the redistribution structure.

15. A method of forming a semiconductor device, comprising: Bonding a logic wafer to an image sensor wafer, the front side of the logic wafer comprising a first conductive pad, the front side of the image sensor wafer comprising a second conductive pad, wherein bonding the logic wafer to the image sensor wafer comprises bonding the first conductive pad directly to the second conductive pad; forming a first redistribution structure on a back side of the logic wafer; and bonding a die stack to the first redistribution structure, the die stack comprising: a logic die, a front side of the logic die comprising a third conductive pad, wherein the third conductive pad is electrically coupled to the first redistribution structure, and a back side of the logic die comprising a fourth conductive pad; and a memory die bonded to the logic die, a front side of the memory die comprising a fifth conductive pad, the fifth conductive pad being in physical contact with the fourth conductive pad; and An encapsulant is formed on the first redistribution structure and around the die stack, a portion of the encapsulant extending along and in physical contact with a back side of the memory die, the back side of the memory die being relative to a front side of the memory die, and a total height of the logic die and the memory die being less than a height of the encapsulant.

16. The method according to claim 15, wherein: Bonding the die stack to the first redistribution structure includes bonding the third conductive pad of the logic die directly to a sixth conductive pad of the first redistribution structure.

17. The method according to claim 15, wherein: Bonding the die stack to the first redistribution structure includes electrically and mechanically coupling the third conductive pad of the logic die to a sixth conductive pad of the first redistribution structure using a conductive connector.

18. The method according to claim 15, further comprising: A second redistribution structure is formed in electrical contact with the first redistribution structure, with the die stack interposed between the first redistribution structure and the second redistribution structure.

19. The method according to claim 18, further comprising: Before bonding the logic die to the first redistribution structure, a conductive pillar is formed over the first redistribution structure, the conductive pillar electrically coupling the first redistribution structure to the second redistribution structure.

20. The method according to claim 19, wherein: The third height of the conductive pillar is greater than the first height of the die stack.

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