An IEGT device with high latch-up resistance

Abstract

The present invention discloses an IEGT device with high anti-latch capability, wherein a P-type base region and a gate are arranged at intervals above an N-type drift layer, a floating P region is arranged between the gates, a P-channel MOSFET tube is arranged in the floating P region, and a P+ type base region is arranged on one side of the surface of the other P-type base regions except the P-type base region provided with the P-channel MOSFET tube, and an N+ type emitter region is arranged on the other side, and an emitter connected to the n+ type emitter region is arranged above the N+ type emitter region; an N-type buffer region is arranged below the N-type drift layer, the P-type collector region is arranged below the N-type buffer region, and a collector is connected below the P-type collector region. The present invention improves anti-latch capability by adding a P-channel MOSFET as a hole shunt in the floating P region to bypass the hole current to reduce the high hole density.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to an IEGT device with high anti-latch capability. Background Art

[0002] Today, power inverter systems employing IGBTs and IEGTs are used in many applications. Especially in the context of battery-powered electric vehicles, the improvement of IEGT devices and the reduction of power losses are becoming increasingly important. The most serious problem in power converter applications is catastrophic failure in the case of simultaneous application of high current, high voltage, and high temperature. Generally speaking, in IGBT and IEGT applications, the latch-up phenomenon of the built-in thyristor leads to catastrophic failure, which is the most serious problem in IGBT and IEGT applications.

[0003] The reason for the latching phenomenon of the IEGT device is that there is a parasitic thyristor in the IEGT device, that is, an NPNP structure. During the normal operation of the device, it is not desirable to turn on the parasitic thyristor. If the parasitic thyristor is in the on state, the gate of the IEGT device will lose control of the current. However, during the operation of the IEGT, if the hole current flowing under the emitter is too large, the PN junction of the emitter and the base region will be forward biased, that is, the emitter begins to inject electrons into the base region, and the base region begins to inject holes into the source. At this time, the parasitic thyristor is turned on, that is, the IGBT device is in a latched state.

[0004] Figure 1 shows a cross-sectional view of a conventional IEGT, Figure 2 The current flow in the IEGT during turn-on is shown, and it is clear that the lateral hole flow comes from the adjacent floating p-region. The high hole current flows through the p- and p+ regions below the n+ emitter region, and the resistance of the p- region below the n+ emitter region produces a voltage drop that forward biases the junction between the n+ and p- regions. When the forward bias is sufficient to promote the injection of electrons from the n+ emitter region, the parasitic thyristor is triggered, resulting in a latch-up failure.

[0005] Therefore, how to improve the anti-latch capability of IEGT devices is a technical problem that needs to be solved urgently. Summary of the invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and provide an IEGT device with high anti-latch capability, by adding a P-channel MOSFET in a floating P region as a hole shunt to bypass the hole current to reduce the high hole density and improve the anti-latch capability.

[0007] To solve the above technical problems, the present invention provides an IEGT device with high anti-latch capability, comprising: an emitter, an N+ type emitter region, a gate, a floating P region, a P type base region, a P+ type base region, a P channel MOSFET tube, an N-type drift layer, an N-type buffer region, a P-type collector region, and a collector;

[0008] The P-type base region and the gate are arranged above the N-type drift layer, the floating P region is arranged between the gates, the P-channel MOSFET is arranged in the floating P region, and the P+-type base region is arranged on one side of the surface of the other P-type base regions except the P-type base region where the P-channel MOSFET is arranged, and the N+-type emitter region is arranged on the other side, and the emitter connected to the N+-type emitter region is arranged above the N+-type emitter region;

[0009] The N-type buffer region is disposed below the N-type drift layer, the P-type collector region is disposed below the N-type buffer region, and the collector is connected below the P-type collector region.

[0010] Optionally, the P-channel MOSFET is turned off during the on-period of the IEGT device, and turned on during the off-period of the IEGT device.

[0011] Optionally, the N+ type emitter region is arranged vertically.

[0012] Optionally, the vertical N+ type emitter region is formed using CVD PSG lateral diffusion technology.

[0013] Optionally, an inverted P+ type base region is arranged below the P+ type base region and the N+ type emitter region.

[0014] Optionally, the reverse P+ type base region is implanted using high voltage ions.

[0015] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: the present invention increases a P-channel MOSFET in the floating P region as a hole shunt to bypass the hole current to reduce the high hole density and improve the anti-latch capability, and sets a vertical N+ type emitter region to shorten the length of the N+ type emitter region, increases an inverted P+ type base region below the N+ type emitter region to reduce the parasitic resistance of the P region, and further improves the anti-latch capability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is the cross section of IEGT in the prior art;

[0017] Figure 2 It is the current flow direction when the IEGT is turned on in the prior art;

[0018] Figure 3The IEGT structure with a hole shunt of the present invention;

[0019] FIG4 shows the current flow direction of the IEGT device of the present invention when it is turned on and off: (1) is the current flow direction when it is turned on, and (2) is the current flow direction when it is turned off;

[0020] Figure 5 The process flow of the IEGT device of the present invention;

[0021] Figure 6 To increase the cross-sectional device structure of the reverse P+ region;

[0022] Figure 7 For along Figure 6 Line A-A' shows the detailed doping profile applied to the reverse P+ region. DETAILED DESCRIPTION

[0023] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0024] In the description of the patent of the present invention, it should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the listed elements but also other elements not explicitly listed.

[0025] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] Figure 2 The current flow when the existing IEGT is turned on is shown. Figure 2It can be seen that the hole current is concentrated from the p region to the adjacent active cell, resulting in an increase in the voltage drop in the p region below the n+ emitter region. Rb1 and Rb2 are used to represent the parasitic resistors through which the hole current flows. When the voltage drop exceeds the built-in voltage Vbi of the p-n+ junction between the n+ emitter and the p base region, the parasitic thyristor latches, resulting in catastrophic failure of the IEGT. And the smaller the length of the n+ emitter region, the larger the latch current. In order to prevent the latching of the parasitic thyristor (i.e., improve the anti-latch capability), the technical solutions that can be used include adding a hole shunt (p-channel MOSFET), reducing the length of the n+ emitter and the p-region resistance.

[0028] An IEGT device with high anti-latch capability of the present invention, see Figure 3 As shown, it includes: an emitter, an N+ type emitter region, a gate, a floating P region, a P type base region, a P+ type base region, a P channel MOSFET tube, an N-type drift layer, an N-type buffer region, a P-type collector region, and a collector;

[0029] The P-type base region and the gate are arranged above the N-type drift layer, the floating P region is arranged between the gates, the p-type MOSFET is arranged in the floating P region, the P-type base region other than the P-type base region where the P-channel MOSFET is arranged has the P+-type base region on one side and the N+-type emitter region on the other side, and the emitter connected to the N+-type emitter region is arranged above the N+-type emitter region;

[0030] The N-type buffer region is disposed below the N-type drift layer, the P-type collector region is disposed below the N-type buffer region, and the collector is connected below the P-type collector region.

[0031] The P-channel MOSFET tube is used as a hole bypass and hole shunt, and is arranged in the floating P region between the active channel gate. The relatively wide floating P region can provide hole bypass without sacrificing any performance. During the conduction period of the IEGT device, Figure 3 The additional P-channel MOSFET in the floating P region is turned off, as shown in Figure 4 (1). During the turn-off period of the IEGT device, the additional P-channel MOSFET in the floating P region can be turned on, and the P-channel MOSFET will provide a hole bypass, as shown in Figure 4 (2). During the turn-off period, the presence of the hole bypass can achieve a lower hole current density under the n+ emitter region of the active cell.

[0032] Furthermore, the N+ type emitter region is vertically arranged. Figure 6The structure is shown formed and results in a very short N+ type emitter region length using a vertical structure that applies a new processing technique using lateral diffusion from a solid source CVD PSG. Figure 6 The completed cross-sectional device structure is shown along with the N+ emitter and the inverted P+ region underneath the P+ region. Figure 7 Shown along Figure 6 Lines A–A’ in Figure 4 apply a detailed doping profile in the reverse P+ region and achieve a lower resistance below the N+ emitter region.

[0033] Compared with traditional IGBT and IEGT, the new N+ emitter structure transformed from a lateral N+ emitter to a vertical N+ emitter has great advantages in reducing the length of the N+ emitter and the parasitic resistance under the N+ emitter. The solid source diffusion and self-aligned electrode contact method formed by CVD-PSG are used. The cross-sectional view is shown in Figure 6 As shown, it can be clearly seen that the quasi-vertical n+ emitter region is formed using lateral diffusion of CVD PSG, and tapered etching is used to form PSG and BPSG with tilted angles, and it enables self-aligned electrode contact.

[0034] Furthermore, an inverted P+ base region using high voltage ion implantation is arranged below the P+ base region and the N+ emitter region. The application of this technology leads to a significant reduction in the parasitic resistance of the P base region below the N+ emitter region.

[0035] Figure 5 The method for constructing the IEGT device of the present invention is shown. Figure 5 Represents the following sequence of process steps,

[0036] (a) Si3N4 is deposited by chemical vapor deposition (CVD), followed by photolithography and etching;

[0037] (b) Local oxidation SiO2 growth;

[0038] (c) Oxide etching using RIE (reactive ion etching technology) and shallow Si etching using CDE (chemical dry etching technology);

[0039] (d) Si channel etching using RIE and H2 annealing to obtain soft corners at the top and bottom of the channel;

[0040] (e) Sacrificial SiO2 growth, etching out SiO2, forming a gate oxide layer, and then doped polysilicon deposition;

[0041] (f) Etching of polysilicon and gate SiO2 until the designed depth is about 1 μm below the silicon surface;

[0042] (g) PSG (phosphosilicate glass), BPSG (boron phosphosilicate glass) and Si3N4 deposition;

[0043] (h) Si3N4 RIE etching without any photolithography process;

[0044] (i) PSG and BPSG are processed by tapered dry etching with gradually changing etching rates, followed by BPSG reflow process for n+ type emitter diffusion, and dry etching to remove residual oxide in the contact area. Al-Si-Cu electrodes are deposited by sputtering.

[0045] The IEGT device of the present invention was tested and the hole shunt as a P-channel MOSFET was arranged in the floating P region, which improved the withstand voltage performance of RBSOA (reverse bias safe operating area) by about 35%. In the FBSOA (forward bias safe operating area) and SCSOA (short circuit safe operating area) tests, shortening the N+ emitter length and reducing the parasitic resistance of the P region under the N+ emitter can improve by about 30%. In the FBSOA and SCSOA tests, the reverse diffused p+ base region was improved by 25%. In general, the improvement of the SOA test is 25-35% higher than that of traditional IGBT and IEGT.

[0046] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An IEGT device with high anti-latch capability, characterized in that: include: Emitter, N+ type emitter region, gate, floating P region, P type base region, P+ type base region, P channel MOSFET tube, N- type drift layer, N- type buffer region, P- type collector region, and collector; The P-type base region and the gate are arranged above the N-type drift layer, the floating P region is arranged between the gates, the P-channel MOSFET is arranged in the floating P region, the P-type base region other than the P-type base region where the P-channel MOSFET is arranged has the P+-type base region on one side and the N+-type emitter region on the other side, and the emitter connected to the N+-type emitter region is arranged above the N+-type emitter region; The N-type buffer is disposed below the N-type drift layer, the P-type collector region is disposed below the N-type buffer, and the collector is connected below the P-type collector region. The P-channel MOSFET is turned off during the on-period of the IEGT device and turned on during the off-period of the IEGT device. The N+ type emitter region is vertically arranged, and the vertical N+ type emitter region is formed using the lateral diffusion technology of CVD PSG to reduce the length of the N+ type emitter region and the parasitic resistance under the N+ type emitter region. The lateral diffusion technology of CVD PSG is: phosphosilicate glass and borophosphosilicate glass are subjected to conical dry etching with a changed etching rate, and then the borophosphosilicate glass reflow process is used to form the N+ type emitter region.

2. The IEGT device with high anti-latch capability according to claim 1, characterized in that: An inverted P+ type base region is arranged below the P+ type base region and the N+ type emitter region.

3. The IEGT device with high anti-latch capability according to claim 2, characterized in that: The reverse P+ type base region is implanted using high voltage ions.

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