semiconductor devices

Abstract

The present invention provides a semiconductor device comprising a plurality of gate trench portions electrically connected to a gate electrode and a plurality of dummy trench portions electrically connected to an emitter electrode, the semiconductor device comprising: a first trench group comprising a gate trench portion and two dummy trench portions adjacent to the gate trench portion and adjacent to each other; and a second trench group comprising two gate trench portions adjacent to each other.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, in trench-gate IGBTs (Insulated Gate Bipolar Transistors) or vertical MOSFETs (metal-oxide-semiconductor field effect transistors), a structure in which dummy trench portions are provided at a certain ratio relative to the gate trench portion has been repeatedly employed (for example, see Patent Documents 1 and 2).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2015 / 162811

[0006] Patent Document 2: International Publication No. 2017 / 033315 Summary of the Invention

[0007] Technical issues

[0008] Suppresses noise generation during switching of semiconductor devices.

[0009] Technical Solution

[0010] In a first embodiment of the present invention, a semiconductor device is provided, comprising a plurality of gate trench portions electrically connected to a gate electrode and a plurality of dummy trench portions electrically connected to an emitter electrode, the semiconductor device comprising: a first trench group including a gate trench portion and two dummy trench portions arranged adjacent to the gate trench portion and adjacent to each other; and a second trench group including two gate trench portions adjacent to each other.

[0011] The second trench group may include three or more consecutively adjacent dummy trench portions.

[0012] The second trench group may have a configuration including two gate trench portions adjacent to each other and four dummy trench portions continuously adjacent to each other, with the two gate trench portions being adjacent to the four dummy trench portions.

[0013] The first trench group and the second trench group are adjacent to each other.

[0014] The semiconductor device may include: a plurality of the first trench groups; and a plurality of the second trench groups. The ratio of the number of the plurality of first trench groups to the number of the plurality of second trench groups may be 1:1.

[0015] A semiconductor device may include: an emitter region of a first conductivity type; a base region of a second conductivity type having a polarity different from that of the first conductivity type; a drift region of the first conductivity type, which is arranged below the base region and has a lower doping concentration than that of the emitter region; and an accumulation region of the first conductivity type, which is arranged between the base region and the drift region and has a higher doping concentration than that of the drift region.

[0016] A semiconductor device may include a mesa portion sandwiched between at least two of a plurality of gate trenches or a plurality of dummy trenches, the mesa portion including an emitter region of a first conductivity type and a base region of a second conductivity type having a polarity different from the first conductivity type. The base region and the emitter region may be alternately arranged in the extending direction of the trench portion in contact with the mesa portion.

[0017] A semiconductor device may include a mesa portion sandwiched between at least two of a plurality of gate trenches or a plurality of dummy trenches, the mesa portion including an emitter region of a first conductivity type and a base region of a second conductivity type having a polarity different from the first conductivity type. The two emitter regions may extend in contact with the trench portion, sandwiching the base region, and the trench portion may be in contact with the mesa portion.

[0018] It should be noted that the above summary of the invention does not list all the features of the present invention, and sub-combinations of these features may also constitute other inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1A FIG. 1 is an example of a cross-sectional view of the semiconductor device 100 according to the embodiment.

[0020] Figure 1B FIG. 1 is another example of a cross-sectional view of the semiconductor device 100 according to the embodiment.

[0021] Figure 1C This is an example of a circuit diagram of the semiconductor assembly 150 .

[0022] Figure 1D 1 is a diagram comparing the electrostatic capacitance Cies of the first trench group 110 and the second trench group 120 .

[0023] Figure 2A 2 is a cross-sectional view of a semiconductor device 200 according to Comparative Example 1.

[0024] Figure 2B 1 is a diagram showing changes in the current Iak and the voltage Vak of the semiconductor device 200 with respect to time t.

[0025] Figure 3A 3 is a cross-sectional view of a semiconductor device 300 according to Comparative Example 2.

[0026] Figure 3B3 is a diagram showing changes in the current Iak and the voltage Vak of the semiconductor device 300 with respect to time t.

[0027] Figure 4 1 is a diagram showing changes in the current Iak and the voltage Vak of the semiconductor device 100 with respect to time t.

[0028] Figure 5 1 is an example of a plan view of the mesa portion 60 of the semiconductor device 100 .

[0029] Figure 6 1 is another example of a plan view of the mesa portion 60 of the semiconductor device 100 .

[0030] Explanation of symbols

[0031] 10···semiconductor substrate, 12···emitter region, 14···base region, 16···accumulation region, 18···drift region, 22···collector region, 30···dummy trench portion, 32···dummy insulating film, 34···dummy conductive portion, 40···gate trench portion, 42···gate insulating film, 44···gate conductive portion, 50···gate electrode, 52···emitter electrode, 54···conductor, 55···Conductor, 56···Interlayer insulating film, 60···Mesa portion, 62···Mesa portion, 64···Mesa portion, 78···Semiconductor chip, 80···Lower arm portion, 82···Upper arm portion, 100···Semiconductor device, 110···First trench group, 120···Second trench group, 150···Semiconductor assembly, 200···Semiconductor device, 300···Semiconductor device DETAILED DESCRIPTION

[0032] Hereinafter, the present invention will be described by way of the embodiments of the invention. However, the following embodiments do not limit the invention as claimed. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical solution of the invention.

[0033] In this specification, one side parallel to the depth direction of a semiconductor substrate is referred to as "upper" or "front," and the other side is referred to as "lower" or "back." Of the two main surfaces of a substrate, layer, or other component, one is referred to as the upper surface, and the other as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the orientation of a semiconductor device when mounted on a substrate, etc.

[0034] In this specification, technical matters are sometimes described using the rectangular coordinate axes of the X-axis, Y-axis, and Z-axis. In this specification, the plane parallel to the top surface of the semiconductor substrate is referred to as the XY plane, and the depth direction of the semiconductor substrate is referred to as the Z-axis. The XYZ plane is a right-handed system. Note that in this specification, viewing the semiconductor substrate from the Z-axis direction is referred to as a top view.

[0035] In each embodiment, although an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type, the first conductivity type may be set to P type and the second conductivity type may be set to N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are opposite in polarity.

[0036] In this specification, the term "doping concentration" refers to the concentration of the donor- or acceptor-type impurities. In this specification, the difference between the concentrations of the donor and acceptor is sometimes referred to as the doping concentration. Additionally, the peak value of the doping concentration distribution in a doped region is sometimes referred to as the doping concentration in that doped region.

[0037] In this specification, layers or regions prefixed with N or P indicate that electrons or holes are majority carriers, respectively. In addition, + and - marked on N or P indicate that the impurity concentration is higher or lower than that of layers or regions not marked with + or -, respectively.

[0038] Figure 1A This is an example of a cross-sectional view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 can be an IGBT or a vertical MOSFET. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 in this embodiment includes a trench group comprising dummy trenches 30 and gate trenches 40, and mesas serving as dopant diffusion regions between the trench groups. The trench groups in this embodiment include a first trench group 110 and a second trench group 120.

[0039] The dummy trench portion 30 includes a dummy insulating film 32 and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52 and is set to an emitter potential Ve. The emitter potential Ve can be set to a ground potential.

[0040] The gate trench portion 40 includes a gate insulating film 42 and a gate conductive portion 44. The gate conductive portion 44 is electrically connected to the gate electrode 50 and is set to a gate potential Vg. As an example, the gate potential Vg may be a potential higher than the emitter potential Ve.

[0041] The mesa portion of the semiconductor substrate 10 of this example includes a mesa portion 60, a mesa portion 62, and a mesa portion 64. The mesa portion 60 is a region sandwiched between the gate trenches 40 on the front surface of the semiconductor substrate 10. The mesa portion 62 is a region sandwiched between the gate trenches 40 and the dummy trenches 30 on the front surface of the semiconductor substrate 10. The mesa portion 64 is a region sandwiched between the dummy trenches 30 on the front surface of the semiconductor substrate 10.

[0042] The mesa portions 60, 62, and 64 of the semiconductor substrate 10 have, from the upper surface side, an emitter region 12 of the first conductivity type, a base region 14 of the second conductivity type, and a drift region 18 of the first conductivity type and a collector region 22 of the second conductivity type provided below the base region 14. If the semiconductor device 100 is a vertical MOSFET rather than an IGBT, the semiconductor substrate 10 does not have the collector region 22.

[0043] The mesa portion 60, the mesa portion 62, and the mesa portion 64 of this embodiment have a first conductivity type accumulation region 16 provided between the base region 14 and the drift region 18. By providing the accumulation region 16, the IE effect (Injection Enhancement effect) of carriers into the base region 14 can be improved. Figure 1B As shown in another example of the cross-sectional view of the semiconductor device 100 according to the embodiment of FIG. 1 , the accumulation region 16 may be omitted.

[0044] The emitter region 12 is a region of the first conductivity type provided on the front surface side of the semiconductor substrate 10. As an example, the emitter region 12 has an N+ type polarity.

[0045] The base region 14 is a region of the second conductivity type provided in contact with the lower portion of the emitter region 12. For example, the base region 14 has a P-type polarity. The base region 14 may be exposed on the front surface of the semiconductor substrate 10. When the gate conductive portion 44 is set to the gate potential Vg, electrons in the base region 14 are attracted toward the gate trench 40. An N-type channel is formed in the region of the base region 14 in contact with the gate trench 40, allowing the device to be driven as a transistor.

[0046] A conductor 54 is disposed on the upper surface of the emitter region 12 and is connected to the emitter electrode 52. An interlayer insulating film 56 is disposed on the upper surface of the gate conductive portion 44. The interlayer insulating film 56 insulates the conductor 54 from the gate conductive portion 44.

[0047] Conductor 55 is provided on the lower surface of semiconductor substrate 10 and can be connected to an external electrode. If semiconductor device 100 is an IGBT, conductor 55 is provided on the lower surface of collector region 22 and can be connected to a collector electrode.

[0048] The first trench group 110 includes one gate trench portion 40 and a plurality of continuously adjacent dummy trench portions 30. The first trench group 110 may be a 1G2E trench group including one gate trench portion 40 and two dummy trench portions 30 adjacent to and adjacent to the gate trench portion 40. In the first trench group 110, when a gate potential Vg is applied to the gate conductive portion 44, the electrostatic capacitance Cies between the mesa portion 62 sandwiched between the dummy trench portion 30 and the gate trench portion 40 and the gate conductive portion 44 is charged. The entire electrostatic capacitance Cies, which is proportional to the surface area of the gate trench portion 40, is charged, and the electrostatic capacitance Cies to be charged is larger.

[0049] The second trench group 120 includes two gate trench portions 40 adjacent to each other and a plurality of dummy trench portions 30. In the second trench group 120, the two gate trench portions 40 are adjacent to the plurality of dummy trench portions 30. The second trench group 120 may include three or more consecutively adjacent dummy trench portions.

[0050] In particular, the second trench group 120 may include four dummy trench sections 30 disposed adjacent to two adjacent gate trench sections 40. In the second trench group 120, when there are four dummy trench sections 30, this is referred to as a 2G4E trench group. When the first trench group 110 is a 1G2E trench group and the second trench group 120 is a 2G4E trench group, characteristics such as withstand voltage in each region are ensured to be the same.

[0051] The region of the semiconductor substrate 10 including the second trench group 120 has mesa portions 60 between adjacent gate trench portions 40. A gate potential Vg is applied to both the gate conductive portions 44 in the trench portions adjacent to the mesa portions 60. Therefore, a potential difference is easily generated between the gate conductive portions 44 and the mesa portions 60. That is, in the second trench group 120, the electrostatic capacitance Cies between the gate conductive portions 44 and the emitter region 12 during conduction is smaller than the electrostatic capacitance Cies of the first trench group 110.

[0052] The semiconductor device 100 includes a plurality of first trench groups 110 and a plurality of second trench groups 120. By adjusting the ratio of the number of the plurality of first trench groups 110 to the number of the plurality of second trench groups, the electrostatic capacitance Cies can be adjusted, and the slope dV / dt of the potential V that changes during switching of the semiconductor device 100 with respect to time t can be adjusted.

[0053] Characteristics such as the breakdown voltage and switching characteristics of the semiconductor device 100 depend on the ratio of the number of dummy trench portions 30 to the number of gate trench portions 40. When the first trench group 110 is a 1G2E trench group, by configuring the second trench group 120 as a 2G4E trench group, the gradient dV / dt of the potential V with respect to time t can be adjusted while ensuring the overall performance of the semiconductor device 100.

[0054] The plurality of first trench groups 110 and the plurality of second trench groups 120 are arranged at a predetermined ratio. As an example, the ratio of the plurality of first trench groups 110 to the plurality of second trench groups 120 can be 1:1. When the ratio of the plurality of first trench groups 110 to the plurality of second trench groups 120 is 1:1, dV / dt can be reduced across the entire voltage range during switching of the semiconductor device 100. The ratio of the plurality of first trench groups 110 to the plurality of second trench groups 120 is not limited to 1:1 and can also be 1:3 to 3:1.

[0055] In this example, a plurality of first trench groups 110 and a plurality of second trench groups 120 are arranged alternately. That is, semiconductor device 100 includes a structure in which first trench groups 110 and second trench groups 120 are adjacent to each other. The first trench groups 110 and second trench groups 120 can be arranged in a predetermined arrangement ratio and are not limited to being arranged alternately.

[0056] Figure 1C This is an example of a circuit diagram of a semiconductor assembly 150. By connecting three semiconductor assemblies 150 in parallel, a three-phase AC inverter circuit having three-phase drive currents U, V, and W can be formed as part of an onboard unit that drives a vehicle motor.

[0057] The case of phase U will be described. Two semiconductor chips 78 are connected in series in the semiconductor assembly 150. The semiconductor device 100 can be formed of circuit elements including the semiconductor chips 78.

[0058] Among the semiconductor chips in semiconductor assembly 150, semiconductor chip 78-2 can constitute lower arm portion 80. On the other hand, among the semiconductor chips in semiconductor assembly 150, semiconductor chip 78-1 can constitute upper arm portion 82. Furthermore, a pair of lower arm portion 80 and upper arm portion 82 included in semiconductor assembly 150 can constitute a bridge arm.

[0059] In the lower arm portion 80 , the emitter electrode of the semiconductor chip 78 - 2 can be electrically connected to the input terminal N1, and the collector electrode of the semiconductor chip 78 - 2 can be electrically connected to the output terminal U. In the upper arm portion 82 , the emitter electrode of the semiconductor chip 78 - 1 can be electrically connected to the output terminal U, and the collector electrode of the semiconductor chip 78 - 1 can be electrically connected to the input terminal P1. The lower arm portion 80 and the upper arm portion 82 can be alternately switched on and off by a signal input to the control electrode pad of the semiconductor chip 78 .

[0060] The input terminal P1 can be connected to the positive electrode of an external power supply. The input terminal N1 can be connected to the negative electrode of an external power supply. The output terminals U, V, and W can be connected to a load, respectively.

[0061] In the semiconductor module, semiconductor chip 78 may be an RC-IGBT semiconductor chip. In an RC-IGBT semiconductor chip, an IGBT and a freewheeling diode (FWD) are integrally formed. In an RC-IGBT semiconductor chip, the IGBT and FWD may be connected in reverse parallel. Semiconductor chip 78 may include a combination of a transistor, such as a MOSFET or an IGBT, and a diode. Semiconductor device 100 may be semiconductor chip 78.

[0062] The relationship between the semiconductor chip 78-1 and the semiconductor chip 78-2 is referred to as a relationship in which the semiconductor chips are arranged as opposing arms. When the transistor portion arranged in the semiconductor chip 78-2 is turned on, a reverse recovery current flows through the diode portion of the semiconductor chip 78-1 arranged in the opposing arm.

[0063] When the reverse recovery current varies significantly over time, the absolute value of the radiation noise generated by the diode portion of semiconductor chip 78-1 also increases. In this case, a large surge current flows into the transistor portion of semiconductor chip 78-2. For example, in a high-voltage 1200V IGBT module, high-frequency switching at 30 to 40 MHz generates significant radiation noise during reverse recovery.

[0064] Therefore, the smaller the temporal change dV / dt of the voltage when the transistor portion of semiconductor assembly 150 is on, the smaller the radiation noise, improving circuit protection and circuit reliability. In semiconductor device 100, by using both first trench group 110 and second trench group 120, which are provided at a predetermined ratio on the front surface of semiconductor substrate 10, dV / dt can be reduced over a wide range from low voltage to high voltage during switching operation.

[0065] Figure 1D1 is a diagram comparing the electrostatic capacitance Cies of the first trench group 110 and the second trench group 120. The electrostatic capacitance Cies of the first trench group 110 is larger than the electrostatic capacitance Cies of the second trench group 120.

[0066] When the semiconductor device 100 is turned on, the electrostatic capacitance Cies on the low-voltage side becomes a reference for determining the driving speed of the semiconductor device 100. During the switching operation of the semiconductor device 100, the capacitance of the electrostatic capacitance Cies decreases at a time point on the high-voltage side just before the gate-emitter voltage stabilizes. In other words, in the high-voltage area, the number of dummy trench portions 30 arranged in series has a greater impact than that of adjacent gate trench portions 40. Since the number of dummy trench portions 30 arranged in series also has a significant impact on the performance of the semiconductor device 100, the number of dummy trench portions 30 arranged in series can be determined based on the desired performance of the semiconductor device 100.

[0067] Figure 2A 1 is an example of a cross-sectional view of a semiconductor device 200 according to Comparative Example 1. The semiconductor device 200 includes the first trench group 110 and does not include the second trench group 120 .

[0068] In semiconductor device 200, first trench groups 110 are repeatedly provided. In the configuration of repeated first trench groups 110, trenches on both sides adjacent to a single gate trench 40 serve as dummy trenches 30. That is, the opposing area between gate trench 40 and dummy trench 30 is large.

[0069] Since the facing area between the gate trench portion 40 and the dummy trench portion 30 is large, the electrostatic capacitance Cies for driving the switching element increases. Therefore, when the first trench group 110 is driven, dV / dt decreases on the low voltage side during on-state operation.

[0070] Figure 2B This graph shows the changes in current Iak and voltage Vak of semiconductor device 200 over time t. It also shows the temporal changes in current Iak flowing between the anode (a) and cathode (k) of a diode portion of another semiconductor device 200, which is provided in an arm opposing the chip included in semiconductor device 200, and voltage Vak between the anode and cathode, when semiconductor device 200 switches.

[0071] When a voltage is gradually applied to the gate conductive portion 44, the voltage Vak flowing between the opposing arms of the IGBT increases, the current Iak decreases, and then stabilizes at a constant value. The gradient dV / dt of the voltage Vak changes with time.

[0072] In the first trench group 110 , the change dV / dt of the voltage Vak relative to time t at the start of switching is small. On the other hand, the change dV / dt of the voltage Vak relative to time t before the voltage Vak reaches a high voltage and stabilizes is large.

[0073] When dV / dt is large, the absolute value of the voltage change noise also increases. In the semiconductor device 200 having the first trench group 110, the dV / dt value is larger than that of the semiconductor device 100 at a high voltage and before the voltage stabilizes.

[0074] Figure 3A 3 is a cross-sectional view of a semiconductor device 300 according to Comparative Example 2. The semiconductor substrate 10 of the semiconductor device 300 includes the second trench group 120 and does not include the first trench group 110 .

[0075] The semiconductor device 300 is repeatedly provided with a second trench group 120. In particular, the semiconductor device 300 is repeatedly provided with a 2G4E trench group. In the second trench group 120, both the mesa portion 60 adjacent to each other in the gate trench portion 40 and the trench portion adjacent to the mesa portion 60 are set to the gate potential Vg. This increases the potential difference between the gate conductive portion 44 and the mesa portion 60, making it easier to form an N-type channel in the base region 14. This corresponds to a situation where the electrostatic capacitance Cies between the gate conductive portion 44 and the emitter region 12 is small when the semiconductor device 300 is driven.

[0076] Figure 3B This diagram shows the changes in current Iak and voltage Vak over time t in semiconductor device 300. It also shows the temporal changes in current Iak and voltage Vak flowing through a diode portion of another semiconductor device 300, which is a chip provided in an arm opposing a chip included in semiconductor device 300, when semiconductor device 300 switches.

[0077] When a voltage is gradually applied to the gate conductive portion 44, similar to the semiconductor device 200, the voltage Vak flowing between the opposing arms of the IGBT increases, while the current Iak decreases, and then stabilizes at a constant value. The semiconductor device 300 having the second trench group 120 has a larger dV / dt on the low-voltage side and a smaller dV / dt on the high-voltage side compared to the semiconductor device 200 having only the first trench group 110.

[0078] Since the electrostatic capacitance Cies of semiconductor device 300 is small, the dV / dt at low voltage during on-state operation increases. On the other hand, when the device stabilizes at a high voltage after driving, the dV / dt value decreases due to the difference in electrostatic capacitance Cies, because of the presence of mesa portions 62 between dummy trench 30 and gate trench 40, and mesa portions 60 between gate trenches 40.

[0079] Figure 4 1 is a diagram showing changes in the current Iak and the voltage Vak of the semiconductor device 100 with respect to time t, and shows the time change of the voltage Vak when the semiconductor device 100 is turned on.

[0080] The semiconductor device 100 has characteristics that combine the low-voltage characteristics of the semiconductor device 200 and the high-voltage characteristics of the semiconductor device 300. That is, the dV / dt value is small on both the low-voltage side and the high-voltage side.

[0081] Since the dV / dt of the semiconductor device 100 is small, the absolute value of the noise generated by the voltage Vak and the current Iak is also small in the semiconductor device 100. Therefore, in the semiconductor device 100, the elements can be adequately protected and a highly reliable circuit can be formed.

[0082] Figure 5 This is an example of a top view of mesa portion 60 of semiconductor device 100. This example shows the configuration of mesa portion 60 sandwiched between gate trenches 40. Mesa portion 62 and mesa portion 64 may have the same configuration. That is, the mesa portion sandwiched between at least two of the plurality of gate trenches 40 and the plurality of dummy trenches 30 may have the same configuration.

[0083] In this example, base regions 14 and emitter regions 12 are alternately arranged in the extending direction of two gate trenches 40 in contact with mesas 60. When semiconductor device 100 is an IGBT, the configuration of mesas 60 on the upper surface of semiconductor substrate 10 suppresses IGBT latch-up.

[0084] Figure 6 This is another example of a top view of mesa portion 60 of semiconductor device 100. This example shows the configuration of mesa portion 60 sandwiched between gate trenches 40. Mesa portion 62 and mesa portion 64 may have the same configuration. That is, mesa portions sandwiched between at least two of the plurality of gate trenches 40 and the plurality of dummy trenches 30 may have the same configuration.

[0085] The emitter region 12 of this example extends in contact with two gate trenches 40, and the two gate trenches 40 are in contact with the mesa portion 60. The emitter region 12 is arranged so as to sandwich the base region 14. The structure of the mesa portion 60 of this example is referred to as a base structure.

[0086] While the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, embodiments incorporating such modifications or improvements are also encompassed within the technical scope of the present invention.

[0087] It should be noted that the order in which actions, processes, steps, and stages, etc., of the devices, systems, programs, and methods described in the claims, specifications, and drawings may be executed in any order, unless otherwise expressly stated, such as "before" or "before," and unless the results of previous processing are used in subsequent processing. Even if the action flow in the claims, specifications, and drawings is described using phrases such as "first" or "next" for convenience, it does not necessarily mean that the actions must be executed in that order.

Claims

1. A semiconductor device, characterized in that: A plurality of gate trench portions electrically connected to the gate electrode and a plurality of dummy trench portions electrically connected to the emitter electrode are provided. The semiconductor device comprises: a first trench group including only one gate trench portion that is not adjacent to any other gate trench portion, and two dummy trench portions that are disposed adjacent to the only one gate trench portion and are adjacent to each other; as well as a second trench group including two gate trench portions adjacent to each other among the plurality of gate trench portions; The first trench group and the second trench group are repeatedly arranged at a predetermined ratio.

2. The semiconductor device according to claim 1, wherein The second trench group includes three or more consecutively adjacent dummy trench portions.

3. The semiconductor device according to claim 1, wherein The second groove group has four consecutive adjacent dummy groove portions. The two gate trench portions are adjacent to the four dummy trench portions.

4. The semiconductor device according to claim 2, wherein The second groove group has four consecutive adjacent dummy groove portions. The two gate trench portions are adjacent to the four dummy trench portions.

5. The semiconductor device according to any one of claims 1 to 4, wherein The first trench group and the second trench group are adjacent to each other.

6. The semiconductor device according to any one of claims 1 to 4, wherein: The ratio of the number of the plurality of first trench groups to the number of the plurality of second trench groups is 1:

1.

7. The semiconductor device according to any one of claims 1 to 4, wherein: The semiconductor device comprises: an emitter region of a first conductivity type; a base region of a second conductivity type having a polarity different from that of the first conductivity type; a drift region of a first conductivity type, which is disposed below the base region and has a lower doping concentration than that of the emitter region; as well as An accumulation region of the first conductivity type is provided between the base region and the drift region and has a higher doping concentration than that of the drift region.

8. The semiconductor device according to any one of claims 1 to 4, wherein: The semiconductor device includes a mesa portion, The mesa portion is sandwiched by at least two of the plurality of gate trench portions and the plurality of dummy trench portions, The table portion has: an emitter region of a first conductivity type; and As a base region of a second conductivity type having a polarity different from the first conductivity type, The base regions and the emitter regions are alternately arranged in an extending direction of a gate trench portion or a dummy trench portion that is in contact with the mesa portion.

9. The semiconductor device according to any one of claims 1 to 4, wherein: The semiconductor device includes a mesa portion, The mesa portion is sandwiched by at least two of the plurality of gate trench portions and the plurality of dummy trench portions, The table portion has: an emitter region of a first conductivity type; and As a base region of a second conductivity type having a polarity different from the first conductivity type, The two emitter regions extend in contact with a gate trench portion or a dummy trench portion in contact with the mesa portion and sandwich the base region.

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