Waveform Generator

Abstract

Embodiments of the present disclosure relate to waveform generators. A waveform generator includes a system control unit and a signal channel controlled by the system control unit, the signal channel being configured to provide a drive signal to drive a corresponding transducer of a transducer array. Each signal channel includes a sequential access memory having rows, wherein each row contains an instruction word configured to generate a corresponding step size of a waveform to be generated. The memory output of the sequential access memory is defined by an output row located at a fixed position. The waveform to be generated is defined by a block of instruction words. Each signal channel also includes an internal control unit, which is configured to sequentially move the contents of the sequential access memory based on the instruction word currently at the memory output so as to provide a sequence of instruction words at the output row.

Description

[0001] Priority claim

[0002] This patent application claims the benefit of priority from Italian Patent Application No. 102020000004231, filed on February 28, 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The invention relates to a waveform generator. Background Art

[0004] As is well known, many applications involve the use of waveform generators to drive transducer arrays. For example, in ultrasound imaging systems, linear or two-dimensional arrays of piezoelectric transducers are alternately used to generate ultrasound beams and receive echoes generated by the interaction of the beams with the target under study. During the beamforming phase, the transducers are driven by digital waveform generators and analog pulse generators. The waveform is typically defined by a sequence of discrete values, such as two or more independent voltage values. For example, by utilizing beamforming techniques, multiple groups of transducers or a single transducer (channel) can be driven separately to improve control over the characteristics of the ultrasound beam. The precisely controlled delay of the drive signal received by the transducer can be critical because the phase difference directly determines the constructive or destructive interference and the characteristics of the beam.

[0005] In order to meet the increasing demands in terms of accuracy and resolution, it is usually necessary to speed up the system clock as well as the frequency, and up to 200MHz (and 5ns time resolution) has been achieved. In addition to resolution, flexibility is also considered so that several waveforms can be provided for different purposes and investigations. Specific waveform generators are proposed to achieve the requirements of resolution and flexibility. The first type of waveform generator is based on a finite state machine, which defines a sequence of states according to voltage levels. A time counter and a pulse counter allow the determination of the appropriate duration of the pulse and the total length of the sequence (number of pulses). Although such a waveform generator can effectively achieve high resolution, only a relatively limited range of simple waveforms can be obtained.

[0006] In another known waveform generator, the parameters of the waveform are stored in an array of volatile or non-volatile memory in the form of successive voltage levels and corresponding durations, which define the states of the waveform generator. The memory array can be scanned (e.g., row by row), and the waveform generated based on the retrieved voltage levels and durations. In order to reduce the memory usage when generating a repeating sequence, an address manager can be provided. The address manager allows the repetition of the state sequence (voltage levels and associated durations), so it can be stored only once instead of the desired number of repetitions.

[0007] Waveform generators based on memory arrays are more flexible and yield greater freedom in designing waveforms. However, these generators are subject to limitations related to the aspect ratio and size of the memory array. In applications where a relatively large number of channels and a corresponding number of waveform generators need to be driven independently, such as ultrasonic inspection, signal routing can be a critical issue due to the arrangement of the contact pins of the memory array and the number and length of the connecting wires reaching each contact pin. In addition, waveform generators use several small blocks of memory, such as flash memory, typically one block per channel. However, the area occupancy efficiency of the memory blocks is very low because each block requires dedicated circuitry, including row and column decoders, sense amplifiers, and reference generators.

[0008] There is a need in the art to provide a waveform generator that allows the above-mentioned limitations to be overcome or at least attenuated. Summary of the invention

[0009] In an embodiment, the waveform generator comprises: a system control unit; and a plurality of channels controlled by the system control unit and configured to provide a corresponding plurality of drive signals, wherein each drive signal is configured to drive a respective transducer of the transducer array.

[0010] Each channel includes: a sequential access memory having a plurality of rows, wherein each row stores an instruction word configured to generate a corresponding step size of a waveform, and a memory output defined by an output row located at a fixed position, wherein the waveform is defined by a block of instruction words; and an internal control unit configured to sequentially shift the contents of the sequential access memory based on the instruction word currently at the memory output to provide a sequence of instruction words at the output row.

[0011] In an embodiment, an electronic system comprises: a transducer array configured to generate a wave in response to a drive signal; and a waveform generator (as described above) configured to generate the drive signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a better understanding of the invention, some embodiments thereof will now be described purely by way of non-limiting example and with reference to the accompanying drawings, in which:

[0013] Figure 1 is a simplified block diagram of an electronic system;

[0014] Figure 2 yes Figure 1 A more detailed block diagram of a portion of an electronic system including a waveform generator according to one embodiment;

[0015] Figure 3 yes Figure 2 A more detailed block diagram of a portion of a waveform generator;

[0016] Figure 4 Shown in Figure 2 Examples of waveforms used in the waveform generator of

[0017] Figures 5A-5C Shows the limit Figure 1 A corresponding example of an instruction for the step size of a waveform used in a waveform generator;

[0018] Figure 6 A simplified block that is a portion of a waveform generator according to another embodiment;

[0019] Fig. 7A Is limited to loading in Figure 2 A schematic diagram of an example of an instruction block for a waveform in a sequential access memory of a waveform generator;

[0020] Figure 7B Shows Fig. 7A The waveform of

[0021] Fig. 8A Is limited to loading in Figure 2 A schematic diagram of another example of an instruction block for sequentially accessing a waveform in a memory of a waveform generator;

[0022] Figure 8B Shows Fig. 8A The waveform of

[0023] Fig.9A Is limited to loading in Figure 2 A schematic diagram of another example of an instruction block for sequentially accessing a waveform in a memory of a waveform generator; and

[0024] Fig. 9B Shows Fig.9A waveform. DETAILED DESCRIPTION

[0025] exist Figure 1 An ultrasound investigation device according to an embodiment is illustrated in FIG. 1 and designated as a whole by the number 1. The ultrasound investigation device 1 can be used, for example, in medical sonography or in ultrasound inspection of mechanical parts. However, the invention is not limited to ultrasound applications and can be advantageously utilized in any case involving waveform generators, in particular for driving multiple transducers with synchronized waveforms.

[0026] The ultrasonic investigation device 1 includes a waveform generator 100 and a transducer unit 101. The ultrasonic investigation device 1 may also include a processing unit 102, a storage unit 103, a communication device 104 for remote communication (e.g., wired or wireless communication through a computer network), an input device 105, and a display 106. In one embodiment, the waveform generator 100 and the transducer unit 101 may be integrated in an inspection head and remotely connected to the remaining components of the ultrasonic investigation device 1. The processing unit 102, the storage unit 103, the communication device 104, the input device 105, and the display 106 may be integrated in a dedicated structure, integrated in a personal computer, a laptop computer, a tablet computer, or a smart phone.

[0027] like Figure 2 As shown, the waveform generator 100 includes a system control unit 2, a plurality of channels 3.1, ..., 3.N and a corresponding plurality of drivers 4.1, ..., 4.N, which are fed by the corresponding channels 3.1, ..., 3.N. The transducer unit 101 includes an array of ultrasonic transducers 5.1, ..., 5.N coupled to the corresponding drivers 4.1, ..., 4.N, N being the number of channels and ultrasonic transducers (in one example, N=128). The ultrasonic transducers 5.1, ..., 5.N may include, for example, piezoelectric transducers arranged in a linear array or a two-dimensional array. Each ultrasonic transducer 5.1, ..., 5.N is driven by the corresponding channel 3.1, ..., 3.N through the corresponding driver 4.1, ..., 4.N. The driver 4.1, ..., 4.N may be an analog pulse generator that converts a low voltage discrete signal into an analog waveform for the corresponding ultrasonic transducer 5.1, ..., 5.N. The system control unit 2 and the channels 3.1, ..., 3.N receive a common system clock CK.

[0028] The system control unit 2 comprises a serial interface 6, a beamforming module 7, an upload register 8 and a mask module 9. The beamforming module 7 provides start commands ST1, ..., STN to the channels 3.1, ..., 3.N, which are synchronized to create a controlled interference of the pressure waves generated by the individual ultrasonic transducers 5.1, ..., 5.N, thereby determining the beam characteristics, such as the propagation direction and shape of the beam front.

[0029] Through the serial interface 6, the parameters of the waveform to be generated can be stored in the upload register 8 and then uploaded to the channels 3.1, ..., 3.N. The parameters of the waveform can be defined offline with the assistance of a waveform design tool. The mask module 9 allows the parameters to be sent to multiple selected channels 3.1, ..., 3.N simultaneously, thus allowing the parameters to be uploaded in parallel.

[0030] Figure 3One of the channels 3.1, ..., 3.N is shown in detail, which will be identified as 3.K and will be referred to herein, since all channels 3.1, ..., 3.N are structurally identical to one another.

[0031] Channel 3.K includes a bidirectional, cyclic, two-dimensional shift register 10, a state inverter module 11 and an internal control unit 12. The two-dimensional shift register 10 in turn includes a plurality of bidirectional, cyclic, one-dimensional shift registers 13, all of which have the same size and are configured to operate in parallel so that the contents of all one-dimensional shift registers 13 can be shifted in either direction at the same time. For example, a single shift command SH can be provided to a common shift input 13a to be provided to each cyclic shift register 13. The shift command SH has a first logic value (e.g., forward shift) and a second logic value (e.g., reverse shift), the first logic value causing the contents of all one-dimensional shift registers 13 to shift in a first direction, and the second logic value causing the contents of all one-dimensional shift registers 13 to shift in a second direction opposite to the first direction. Another logic value can be used to keep the contents of all one-dimensional shift registers 13 unchanged (e.g., no shift). For convenience, in the following first direction and second direction, they will be referred to as forward direction and reverse direction, respectively, or simply forward and reverse.

[0032] Therefore, the two-dimensional shift register 10 defines a matrix, having as many rows as the number of bits of each one-dimensional shift register 13 and as many columns as the number of one-dimensional shift registers 13. Note that the one-dimensional shift registers 13 are logically adjacent to each other, meaning that the bits at the same position in different one-dimensional shift registers 13 form the rows of the two-dimensional shift register 10. However, the one-dimensional shift registers 13 do not need to be physically adjacent to each other. Typically, the shift register includes a plurality of cascaded bistable circuits, which have a common clock and are configured to respond to a forward shift command (or a corresponding reverse shift command) so that the state of each bistable circuit is transmitted to the next (or previous) bistable circuit in the cascade. To define a matrix for the two-dimensional shift register 10, the individual bistable circuits of the logically adjacent one-dimensional shift registers 13 do not have to be physically close to each other. On the contrary, it is sufficient to define the position of the bit (bistable circuit) in each one-dimensional shift register 13 and keep the position consistent during processing. One of the rows of the two-dimensional shift register 10 is provided with a physical connection to the outside and defines a register output 10a.

[0033] The contents of the two-dimensional shift register 10 can be shifted row by row. Each row defines a register word W and contains information about the waveform to be generated. The waveform is generated as a sequence of steps or states, each step or state having a corresponding one of a plurality of state logic values ​​and a corresponding duration, which can advantageously be expressed as a number of clock cycles. The state logic value includes a plurality of values ​​V1, ..., VM. In one example (see Figure 4 ), the state logic value may include a low state value V1, a clamped or intermediate logic value V2, and a high state value V3. The waveform is stored in the two-dimensional shift register 10 as a block of corresponding continuous words W, including at least the corresponding state logic value, the corresponding duration and possible additional information and / or instructions for processing. In each step, a word W in the position corresponding to the register output 10a is read out, and a portion of the waveform is generated based on the information contained in the word W, as described in detail below.

[0034] In one embodiment, each word W includes at least a first field or instruction field FI, for example, 7 bits (one bit of each of the seven one-dimensional shift registers 13, not necessarily adjacent to each other), a second field or mode field FM, for example, 1 bit (one bit of another one-dimensional shift register 13) and a third field or status field FS, for example, two bits of an adjacent one-dimensional shift register 13 (one bit of each of the other two one-dimensional shift registers 13, not necessarily adjacent to each other).

[0035] The instruction field FI contains information about the action to be taken. Specifically, the instruction field FI may contain:

[0036] - Initialization string IS( Figure 5A ) defines an enable code EN to selectively enable and disable the repetition of the overall symmetric waveform pattern, a symmetry type code E / O to selectively define whether the overall symmetry is even or odd, and an overall repetition number RO, RO defines how many times the overall step sequence is to be repeated;

[0037] - the duration D of the current step, for example, based on the number of clock cycles of the symmetrical part of the waveform and the number of local repetitions RL ( FIG. 5 b ) (if any); and

[0038] - the duration D of the current step (Fig. 5c), for example expressed in the number of clock cycles.

[0039] However, the waveform need not be symmetrical or contain symmetrical portions.

[0040] The mode field FM includes a mode flag M having a logic value defining a standard operating mode and a start / repeat mode. In the standard operating mode, the shift direction of the two-dimensional shift register 10 is maintained, whether it is forward (main) or reverse (inversion), and in the start / repeat mode, the shift direction is reversed from forward to reverse, or from reverse to forward. The mode flag M pair of the subsequent word W of the start / repeat mode is set to define the delimiter of the step sequence to be repeated in the waveform. The internal control unit 12 can be configured to identify the first and each odd symmetric reception mode flag M, setting the start / repeat mode to the beginning of the step sequence to be repeated; and the second and each even symmetric reception mode flag M, setting the start / repeat mode to the end of the step sequence to be repeated. As an alternative, the mode flag M can also have a separate logic value to identify the beginning and end of the step sequence to be repeated.

[0041] The state field FS contains state logic values ​​V1, ..., VM, which represent the corresponding levels of the waveform to be generated. The state field FS may also contain a dedicated start code (e.g., a logic value not used for the state logic values ​​V1, ..., VM), which identifies the starting row of the word block W defining the waveform. The state field FS defining the starting row of the block of waveforms may contain a waveform identification tag WFTAG.

[0042] The sequential upload input 10b of the two-dimensional shift register 10 is coupled to the system control unit 2 via a mask module 9 for waveform parameter upload. Advantageously, blocks of words W defining respective steps of one or more waveforms are loaded sequentially row by row, e.g. shifted in the main direction in each iteration of the process.

[0043] Reference Figure 3 , the internal control unit 12 includes a control module 15, a time counter 16, a shift reverse counter 17 and a shift command generator 18. In one embodiment, the control module 15 may be a finite state machine.

[0044] The control module 15 receives each word W read at the register output 10 a of the two-dimensional shift register 10 and performs an action based on the content of the word W received.

[0045] The way in which the instruction field FI is interpreted by the control module 15 is determined by the contents of the mode field FM and the status field FS.

[0046] The mode flag M in the mode field FM determines the standard operating mode or the start / repeat operating mode. In the standard operating mode, the content of the instruction field FI is interpreted as the duration of the current step of the waveform being generated. In the start / repeat mode, the content of the instruction field FI is interpreted as the initialization string IS or the local repetition number RL depending on the content of the status field FS.

[0047] In start / repeat mode, the content of instruction field FI is interpreted as an initialization string for the presence of a start code in status field FS and a local repetition number RL for the presence of any other state logic value V1, ..., VM in status field FS.

[0048] In one embodiment, the control module 15 is configured to perform the following actions:

[0049] 1) receiving a system instruction containing a reference tag TR identifying a waveform to be generated and shifting a two-dimensional shift register 10 until a row containing a word W with a matching waveform identification tag WT (WFTAG) in the status field FS is shifted to the register output 10a; starting to generate the selected waveform;

[0050] 2) in response to word W, initialize the time counter 16 by means of the mode field FM, set the standard operating mode, and increase the time counter 16 at each clock cycle until the duration D of the instruction field FI of the received word W is reached;

[0051] 3) shifting the contents of the two-dimensional shift register 10 each time a waveform step defined in the corresponding word W is completed;

[0052] 4) initializing a shift reverse counter 17 in response to a word W having a mode flag M which sets the start / repeat mode of operation and causes a reversal of the shift direction (e.g., a mode flag M identifying the end of a sequence to be repeated); and incrementing the shift reverse counter 17 each time a repetition of a step sequence is completed between corresponding delimiters, until a local repetition number RL is reached contained in the instruction field FI of the word W initiating the repetition sequence (e.g., the criterion for incrementing may be a mode flag M identifying that the start of a sequence to be repeated is received and the shift direction is reversed; or that the direction is reversed every second);

[0053] 5) terminating the execution of the waveform upon receiving a new word W containing an initialization string IS and a waveform identification tag WT of a subsequent waveform; and

[0054] 6) If the enable code EN in the start word W of the waveform being executed is capable of repeating the overall symmetrical waveform pattern, then the entire block of word W defining the waveform is repeated; as described below, the state inverter module 11 is set to even symmetry or odd symmetry repetition symmetry based on the symmetry type code E / O.

[0055] The shift command generator 18 is controlled by the control module 15 and is configured to provide a forward shift command SF, a backward shift command SB, and a no-shift command SN which maintains a current state of the two-dimensional shift register 10 .

[0056] The state inverter module 11 receives the word W (or at least the state logic values ​​V1, ..., VM) corresponding to the waveform step currently to be executed from the register output 10a, and has a normal operation mode, in which the state logic values ​​V1, ..., VM are transmitted unchanged to the drivers 4.1, ..., 4.N, and an inverse operation mode, in which the state logic values ​​V1, ..., VM are inverted before being transmitted to the drivers 4.1, ..., 4.N. In one embodiment, the state logic values ​​V1, ..., VM are sorted from V1 to VM (e.g., lowest and highest), respectively, and the inverse state logic values ​​(here indicated by V1', ..., VM') are obtained from the state logic values ​​V1, ..., VM as follows:

[0057] VK'=V(MK) where K=1, 2, ..., M

[0058] When the enable code EN in the starting word W of the waveform being executed enables the repetition of the overall symmetrical waveform pattern, and the entire block of word W has been executed, the state inverter module 11 is set to normal operating mode or reverse operating mode based on the symmetry type code E / O and the word block W using the state logic value V1, ..., VM (normal operating mode) or the reverse state logic value, here represented by V1', ..., VM' (reverse operating mode) from the last row to the first row.

[0059] An arbitrary waveform can be defined, loaded into the two-dimensional shift register 10, and then generated.

[0060] exist Figure 6 In one embodiment shown in the figure, the two-dimensional shift registers (2DSR) 10 of channels 3.1, ..., 3.N are connected in series with each other, and the word blocks W defining the waveform can be sequentially shifted between consecutive channels 3.1, ..., 3.N. This feature can be very useful in ultrasonic imaging devices that implement sliding windows, and also allows scan testing. In circuits that combine logic networks and memory elements (such as flip-flops or shift registers), scan testing is used to check the correct operation of the logic network. To this end, a known state is loaded in the memory element, a processing step (or a sequence of processing steps) is executed, and the output is compared with the expected result. Continuously connecting memory elements in the form of shift registers helps to load known states and read processed outputs, because the structure that allows the scan test to be implemented is the same as the structure that implements the main function. Similarly, the two-dimensional shift registers 10 of channels 3.1, ..., 3.N are connected in series to form a global shift register, so that scan testing can be performed on the logic components of the waveform generator 100.

[0061] The repetition of the sequence allows for a compressed waveform representation with a sequence of steps that are symmetrical in the corresponding state logic values ​​V1, ..., VM and duration relative to a step of the sequence, with the first part of the sequence also being repeated at the end of the sequence. For example, a step sequence such as (ABCBA)BC allows for a compressed representation. The portion of the sequence in brackets is symmetrical relative to the step size C, and the underlined portion is repeated at the end of the sequence.

[0062] Fig. 7A and 7B An example of a waveform (labeled as WT=WFTAG1) is shown, including a plurality of steps, each step having a corresponding one of three state logic values ​​V1, V2, V3, and a respective duration expressed in the number of clock cycles. Specifically, Fig. 7A The contents for a portion of a two-dimensional array 10 are illustrated, and Figure 7B Successive steps in time are shown. For convenience, the step lengths are identified here as ABCBABCDEF and indicated in the auxiliary columns, however, the step lengths do not need to be included in the two-dimensional shift register 10. The row marked S1 contains a start word W, which has a waveform identification tag WT of the current waveform and overall parameters for initializing the control module 15. Thereafter, the control module 15 executes the steps A, B and sends a forward shift command to the two-dimensional shift register 10. The first occurrence of the mode flag M defining the start / repeat mode is ignored.

[0063] At step C, the second receiving mode flag M defining the start / repeat mode is interpreted by the control module 15 as a delimiter of the sequence to be repeated, and the shift direction is reversed from the main (forward) to the reverse (reverse). The waveform portion defined in the word of step C is executed, the shift reverse counter 17 is initialized, and the local number of repetitions RL can be stored in an auxiliary register, not shown here. Then, a reverse shift command is provided to the two-dimensional shift register 10, and step B is executed. The shift direction remains unchanged until another delimiter is reached. In the exemplary sequence, this is represented by the mode flag M of step A. Once the waveform portion defined in the word of step A is executed, the shift direction is reversed from the reverse (reverse) to the main (forward) and the shift reverse counter 17 is incremented. Then, steps B and C are executed again. If the content of the shift reverse counter 17 matches the local number of repetitions RL stored (or directly obtained from the instruction field FI of the word W at step C) in the auxiliary register, the shift direction is maintained, and steps D, E and F are executed in sequence. Otherwise, if the content of the shift reverse counter 17 has not reached the local repetition number RL, the shift direction is changed again from main (forward) to reverse (reverse). Steps B, A, B, C are repeated until the content of the shift reverse counter 17 equals the local repetition number RL.

[0064] When the last step of the sequence (F in the example) has been executed, the content of the two-dimensional shift register 10 is shifted again in the main direction and the first step of the next block defining the next waveform is moved to the register output 10a. The word of the new block is interpreted by the control module 15 as a stop command and the generation of the current waveform is terminated.

[0065] Fig. 8A and 8B Another example of a waveform is shown (labeled WT=WFTAG2), including Fig. 7A and 7B The same step length sequence ABCBABCDEF as the sequence of waveform WFTAG1, in addition, there is an overall repetition instruction with even symmetry. The instruction is provided in the instruction field FI of the start word W of the start line marked S2, namely by the enable code EN (e.g., true), the symmetry type code E / O (e.g., even symmetry) and the corresponding value of the overall repetition number RO (e.g., 1). In this case, when the last row of the block defining the current waveform WFTAG2 is reached, for Fig. 7A and 7B The partial repetition of waveform WFTAG1 is reversed. At this stage, the overall step sequence (including the partial repetition) is executed as FEDCBABCBA in the reverse direction.

[0066] Fig.9A and 9B Another waveform example (labeled WT=WFTAG3) is shown, including Fig. 7A and 7B The sequence of waveform WFTAG1 is the same as the step sequence ABCBABCDEF, with the addition of an overall repetition instruction of odd symmetry. The instruction is provided in the instruction field FI of the start word W in the start line marked S2, namely by the corresponding values ​​of the enable code EN (e.g., true), the symmetry type code E / O (e.g., odd symmetry) and the overall repetition number RO (e.g., 1). In this case, for Fig. 8A and 8B The waveform WFTAG2 of the state inverter module 11 is reversed, and the shift direction is reversed. In addition, the state inverter module 11 is set to the reverse operation mode, whereby the state logic values ​​V1, V2, V3 are reversed before being transmitted to the driver 4.1, ..., 4.N. Accordingly, the driver 4.1, ..., 4.N receives the reverse state V1'=V3, V2'=V2, V3'=V1.

[0067] The sequence of steps defining the waveform typically includes a periodic or repeating portion. The waveform generator according to the present invention advantageously provides a compressed waveform representation and storage, thereby allowing a considerable saving in required memory. Fig. 7A , 7BAs shown in the examples of 8A, 8B and 9A, 9B, the waveform generator is capable of executing a forward sequence, a forward and reverse sequence, and a forward and reverse sequence with a reverse state without the need for additional memory.

[0068] Furthermore, the waveform generator according to the present invention can generate almost any type of waveform.

[0069] Another important advantage of the present invention is that a two-dimensional shift register consisting of a plurality of one-dimensional shift registers operating in parallel is used to replace a conventional random access memory such as a flash memory. In contrast to conventional random access memories, shift registers have no predefined requirements for shape and aspect ratio. Shift registers are basically composed of cascaded bistable circuits, and once series connection is achieved, there are actually no other position requirements for a single bistable circuit. In addition, a single input row and a single output row are sufficient to operate the two-dimensional shift register. Flexible design and a small number of connections make it easier to route signals, and the number of channels and corresponding transducers can be significantly increased. More independent channels and transducers allow more information to be received and a more complete inspection to be performed. In the case of a two-dimensional array of transducers, a three-dimensional image can be produced.

[0070] Furthermore, the shift register does not require addressing circuitry or a read / write interface. On the one hand, silicon area can be further saved, and, on the other hand, the control logic can be very simple, making the shift register intrinsically fast in responding to commands. In particular, no address decoding is required, which introduces some delays, and three command lines or two command lines with logic gates are sufficient to provide all the required commands (forward shift command SF, reverse shift command SB and no shift command SN). This allows a very fine time resolution, in the order of 5ns, as well as a relatively precise spatial (depth) resolution.

[0071] Finally, it is evident that modifications and variations may be made to the waveform generator described, without departing from the scope of the present invention, as defined in the appended claims.

Claims

1. A waveform generator, comprising: System control unit; as well as a plurality of channels controlled by the system control unit and configured to provide a corresponding plurality of drive signals, wherein each drive signal is configured to drive a corresponding transducer of the transducer array; Each channel includes: a sequential access memory having a plurality of rows, wherein each row stores instruction words configured to generate a corresponding step size of a waveform, and a memory output defined by output rows located at fixed positions, wherein the waveform is defined by a block of instruction words; as well as an internal control unit configured to sequentially shift the instruction words of the sequential access memory based on the instruction words currently at the output of the memory, thereby providing a sequence of instruction words at the output row; wherein the instruction word contains a local sequence delimiter of a sequence of instruction words to be repeated, and wherein the internal control unit is configured to reverse a shift direction of the sequential access memory in response to the local sequence delimiter and a reverse condition; and The instruction word in which the local sequence delimiter is contained also contains repetition information defining the number of repetitions to be performed on the corresponding word sequence to be repeated.

2. The waveform generator of claim 1 , wherein the sequential access memory comprises a two-dimensional shift register formed by the plurality of rows, the plurality of rows being configured to selectively shift row-wise in one of a first direction and a second direction, wherein the second direction is opposite to the first direction.

3. The waveform generator of claim 2, wherein the internal control unit is configured to shift the sequential access memory based on the content of the instruction word currently at the memory output.

4. The waveform generator of claim 1 , wherein the sequential access memory comprises a plurality of bidirectional, circular, one-dimensional shift registers forming columns of the sequential access memory, wherein the bidirectional, circular, one-dimensional shift registers all have the same size and are configured to operate in parallel.

5. The waveform generator of claim 4 , wherein the bidirectional, circular, one-dimensional shift registers are configured to simultaneously receive a single shift command, the shift command having a first logic value and a second logic value, wherein the first logic value causes the contents of all of the bidirectional, circular, one-dimensional shift registers to shift in a first direction, and the second logic value causes the contents of all of the bidirectional, circular, one-dimensional shift registers to shift in a second direction, wherein the second direction is opposite to the first direction.

6. The waveform generator of claim 5, wherein the internal control unit is configured to shift all of the bidirectional, circular, one-dimensional shift registers based on the contents of the instruction word currently at the memory output.

7. The waveform generator of claim 1, wherein the instruction word contains a duration and state value of a corresponding drive signal defining a corresponding step size of the waveform to be generated.

8. The waveform generator of claim 1, wherein a starting instruction word of a block of instruction words defining the waveform contains an identification tag identifying the waveform.

9. The waveform generator of claim 8, wherein the sequential access memory comprises a plurality of instruction word blocks, each instruction word block defining a corresponding waveform and having a corresponding one of the starting instruction words, and wherein the internal control unit is configured to stop executing a current instruction word block defining a current waveform upon receiving the starting instruction word of a subsequent instruction word block.

10. The waveform generator of claim 9, wherein the internal control unit is configured to receive a reference tag from the system control unit and sequentially shift the sequential access memory until one of the start instruction words containing an identification tag matching the received reference tag is shifted to the memory output.

11. The waveform generator of claim 10, wherein each start instruction word comprises an enable code, a symmetry type code, and an overall repetition count, wherein the enable code is used to selectively enable and disable repetition of the overall symmetric waveform pattern, the symmetry type code selectively defines whether the overall symmetry is even symmetry or odd symmetry, and the overall repetition count defines how many times the overall step sequence is to be repeated; and wherein, The internal control unit is configured to receive the starting instruction word of the current waveform and is configured to repeat the same number of times as the overall number of repetitions in the starting instruction word. If the enable code in the starting instruction word enables repetition of the overall symmetrical waveform pattern, the entire instruction word block defines the current waveform.

12. The waveform generator of claim 11 , wherein each channel comprises a state inverter module configured to receive the drive signal from the memory output and having a normal operation mode and a reverse operation mode, in which the drive signal is transmitted unchanged and in which the drive signal is reversed before being transmitted; and wherein based on the enable code in the start instruction word, the internal control unit is configured to be in one of the normal operation mode and the reverse operation mode.

13. The waveform generator of claim 1, wherein the sequential access memory has a sequential upload input, and the system control unit is configured to sequentially upload instruction word blocks defining the corresponding waveform into the sequential access memory through the sequential upload input.

14. An electronic system comprising: a transducer array configured to generate a wave in response to a drive signal; as well as a waveform generator configured to generate the drive signal, wherein the waveform generator comprises: a system control unit; and a plurality of channels controlled by the system control unit and configured to provide a corresponding plurality of drive signals, wherein each drive signal is configured to drive a corresponding transducer of the transducer array; Each channel includes: a sequential access memory having a plurality of rows, wherein each row stores instruction words configured to generate a corresponding step size of a waveform, and a memory output defined by output rows located at fixed positions, wherein the waveform is defined by a block of instruction words; and an internal control unit configured to sequentially shift the instruction words of the sequential access memory based on the instruction words currently at the output of the memory, thereby providing a sequence of instruction words at the output row; wherein the instruction word contains a local sequence delimiter of a sequence of instruction words to be repeated, and wherein the internal control unit is configured to reverse a shift direction of the sequential access memory in response to the local sequence delimiter and a reverse condition; and The instruction word in which the local sequence delimiter is contained also contains repetition information defining the number of repetitions to be performed on the corresponding word sequence to be repeated.

15. The system of claim 14, wherein the transducer comprises a piezoelectric transducer.

16. A waveform generator channel circuit configured to generate a drive signal, comprising: a sequential access memory having a plurality of rows, wherein each row stores instruction words configured to generate a corresponding step size of a waveform, and a memory output defined by output rows located at fixed positions, wherein the waveform is defined by the blocks of instruction words; as well as an internal control unit configured to sequentially shift the instruction words of the sequential access memory based on the instruction words currently at the output of the memory, thereby providing a sequence of instruction words at the output row; wherein the instruction word contains a local sequence delimiter of a sequence of instruction words to be repeated, and wherein the internal control unit is configured to reverse a shift direction of the sequential access memory in response to the local sequence delimiter and a reverse condition; and The instruction word in which the local sequence delimiter is contained also contains repetition information defining the number of repetitions to be performed on the corresponding word sequence to be repeated.

17. The waveform generator channel circuit of claim 16, wherein the sequential access memory comprises a two-dimensional shift register formed by the plurality of rows, the plurality of rows being configured to selectively shift row by row in one of a first direction and a second direction, wherein the second direction is opposite to the first direction.

18. The waveform generator channel circuit of claim 17, wherein the internal control unit is configured to shift the sequential access memory based on the contents of the instruction word currently at the memory output.

19. The waveform generator channel circuit of claim 16, wherein the sequential access memory comprises a plurality of bidirectional, circular, one-dimensional shift registers forming columns of the sequential access memory, wherein the bidirectional, circular, one-dimensional shift registers all have the same size and are configured to operate in parallel.

20. The waveform generator channel circuit of claim 19, wherein the bidirectional, circular, one-dimensional shift registers are configured to simultaneously receive a single shift command, the shift command having a first logic value that causes the contents of all of the bidirectional, circular, one-dimensional shift registers to shift in a first direction, and a second logic value that causes the contents of all of the bidirectional, circular, one-dimensional shift registers to shift in a second direction, wherein the second direction is opposite to the first direction.

21. The waveform generator channel circuit of claim 20, wherein the internal control unit is configured to shift all of the bidirectional, circular, one-dimensional shift registers based on the contents of the instruction word currently at the memory output.

22. The waveform generator channel circuit of claim 16, wherein the instruction word contains a duration and state value of a corresponding drive signal defining a corresponding step size of the waveform to be generated.

23. The waveform generator channel circuit of claim 16, wherein a starting instruction word of a block of instruction words defining the waveform includes an identification tag identifying the waveform.

24. The waveform generator channel circuit of claim 23, wherein the sequential access memory comprises a plurality of instruction word blocks, each instruction word block defining a respective waveform and having a respective one of the starting instruction words, and wherein, The internal control unit is configured to stop executing a current instruction word block defining a current waveform upon receiving the start instruction word of a subsequent instruction word block.

25. The waveform generator channel circuit of claim 24, wherein the internal control unit is configured to receive a reference tag from a system control unit and sequentially shift the sequential access memory until one of the start instruction words containing an identification tag matching the received reference tag is shifted to the memory output.

26. The waveform generator channel circuit of claim 25, wherein each start instruction word comprises an enable code, a symmetry type code, and an overall repetition count, wherein the enable code is used to selectively enable and disable repetition of the overall symmetric waveform pattern, the symmetry type code alternatively defines whether the overall symmetry is even symmetry or odd symmetry, and the overall repetition count defines how many times the overall step sequence is to be repeated; and wherein, The internal control unit is configured to receive the starting instruction word of the current waveform and is configured to repeat the same number of times as the overall number of repetitions in the starting instruction word. If the enable code in the starting instruction word enables repetition of the overall symmetrical waveform pattern, the entire instruction word block defines the current waveform.

27. The waveform generator channel circuit of claim 26 , wherein each channel comprises a state inverter module configured to receive the drive signal from the memory output and having a normal operation mode and a reverse operation mode, wherein the drive signal is transmitted unchanged in the normal operation mode and the drive signal is reversed before being transmitted in the reverse operation mode; and wherein based on the enable code in the start instruction word, the internal control unit is configured to be in one of the normal operation mode and the reverse operation mode.

28. The waveform generator channel circuit of claim 16, wherein the sequential access memory has a sequential upload input, through which instruction word blocks defining corresponding waveforms are sequentially uploaded into the sequential access memory.

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